Re: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Krzysztof Kozlowski]

On 20.10.2015 17:17, Pavel Fedin wrote:
>  Hello!
> 
>>>  Pin controller is needed in order to configure multi-functional pins 
>>> correctly.
>>
>> Are there any obstacles for upstreaming it?
> 
>  I don't know. The last post on this topic is from March, 2015:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330862.html. 
> Patch 0003 has been acked-by, and nothing more since
> that.
>  Actually, only 0002 and 0003 of this series are needed for the pin 
> controller. 0001 has been accepted
> (27284129522e7e2a5b89e80bd44ea3345f79c9e8).

I see that all objections were solved and I already reviewed all of the
patches. This was sent before I started collecting patches as
co-maintainer so all it is needed now is to rebase and resend with
collected tags.

I'll try to find them in my archives and apply.

Really, if you have anything waiting then just resend/ping. Things
changed since May this year :) .

Best regards,
Krzysztof

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[PATCH v2 0/9] Add tune support of Mediatek MMC driver

[Chaotian Jing]

Change in v2:
Drop the 400mhz and use assigned-clock-parents to instead
Split the original tune patch to several independent patches
Re-write the mmc_send_tuning()
Fix GPD checksum error
Move the HS400 setting to ops->prepare_hs400_tuning()   
Modify SD driving settings

Change in v1:
Add DT bindings for eMMC hardware reset
Add pinctrl of data strobe pin for HS400 mode
Modify eMMC driving settings
Add 400mhz source clock for HS400 mode
Add eMMC HS200/HS400 mode support
Add SD SDR50/SDR104 mode support
Add implement of tune function with CMD19/CMD21

Chaotian Jing (9):
  mmc: core: Add DT bindings for eMMC hardware reset support
  mmc: dt-bindings: update Mediatek MMC bindings
  mmc: mediatek: make cmd_ints_mask to const
  mmc: mediatek: change the argument "ddr" to "timing"
  mmc: mediatek: fix got GPD checksum error interrupt when data transfer
  mmc: mediatek: add implement of ops->hw_reset()
  mmc: mmc: extend the mmc_send_tuning()
  mmc: mediatek: add HS400 support
  arm64: dts: mediatek: add HS200/HS400/SDR50/SDR104 support

 Documentation/devicetree/bindings/mmc/mmc.txt|   1 +
 Documentation/devicetree/bindings/mmc/mtk-sd.txt |  11 +-
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts  |  27 ++-
 drivers/mmc/core/host.c  |   2 +
 drivers/mmc/core/mmc_ops.c   |   8 +-
 drivers/mmc/host/dw_mmc-exynos.c |   4 +-
 drivers/mmc/host/dw_mmc.c|   2 +-
 drivers/mmc/host/dw_mmc.h|   2 +-
 drivers/mmc/host/mtk-sd.c| 296 ---
 drivers/mmc/host/sdhci-esdhc-imx.c   |   6 +-
 drivers/mmc/host/sdhci-msm.c |   2 +-
 drivers/mmc/host/sdhci-sirf.c|   2 +-
 include/linux/mmc/core.h |   2 +-
 13 files changed, 314 insertions(+), 51 deletions(-)

-- 
1.8.1.1.dirty

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[PATCH v2 1/9] mmc: core: Add DT bindings for eMMC hardware reset support

[Chaotian Jing]

Sometime only need set MMC_CAP_HW_RESET for one of MMC hosts,
So set it in device tree is better.

Signed-off-by: Chaotian Jing 
---
 Documentation/devicetree/bindings/mmc/mmc.txt | 1 +
 drivers/mmc/core/host.c   | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt 
b/Documentation/devicetree/bindings/mmc/mmc.txt
index 0384fc3..f693baf 100644
--- a/Documentation/devicetree/bindings/mmc/mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc.txt
@@ -37,6 +37,7 @@ Optional properties:
 - sd-uhs-sdr104: SD UHS SDR104 speed is supported
 - sd-uhs-ddr50: SD UHS DDR50 speed is supported
 - cap-power-off-card: powering off the card is safe
+- cap-mmc-hw-reset: eMMC hardware reset is supported
 - cap-sdio-irq: enable SDIO IRQ signalling on this interface
 - full-pwr-cycle: full power cycle of the card is supported
 - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index abd933b..04fdc2f 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -507,6 +507,8 @@ int mmc_of_parse(struct mmc_host *host)
host->caps |= MMC_CAP_UHS_DDR50;
if (of_property_read_bool(np, "cap-power-off-card"))
host->caps |= MMC_CAP_POWER_OFF_CARD;
+   if (of_property_read_bool(np, "cap-mmc-hw-reset"))
+   host->caps |= MMC_CAP_HW_RESET;
if (of_property_read_bool(np, "cap-sdio-irq"))
host->caps |= MMC_CAP_SDIO_IRQ;
if (of_property_read_bool(np, "full-pwr-cycle"))
-- 
1.8.1.1.dirty

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[PATCH v2 3/9] mmc: mediatek: make cmd_ints_mask to const

[Chaotian Jing]

cmd_ints_mask and data_ints_mask are constant value,
so make it to const

Signed-off-by: Chaotian Jing 
---
 drivers/mmc/host/mtk-sd.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index b2e89d3..8b3e15d 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -353,7 +353,10 @@ static void msdc_reset_hw(struct msdc_host *host)
 static void msdc_cmd_next(struct msdc_host *host,
struct mmc_request *mrq, struct mmc_command *cmd);
 
-static u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
+static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
+   MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
+   MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
+static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
 
@@ -725,10 +728,7 @@ static bool msdc_cmd_done(struct msdc_host *host, int 
events,
if (done)
return true;
 
-   sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY |
-   MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO |
-   MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR |
-   MSDC_INTEN_ACMDTMO);
+   sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
 
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136) {
@@ -818,10 +818,7 @@ static void msdc_start_command(struct msdc_host *host,
rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
mod_delayed_work(system_wq, >req_timeout, DAT_TIMEOUT);
 
-   sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CMDRDY |
-   MSDC_INTEN_RSPCRCERR | MSDC_INTEN_CMDTMO |
-   MSDC_INTEN_ACMDRDY | MSDC_INTEN_ACMDCRCERR |
-   MSDC_INTEN_ACMDTMO);
+   sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
writel(cmd->arg, host->base + SDC_ARG);
writel(rawcmd, host->base + SDC_CMD);
 }
-- 
1.8.1.1.dirty

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[PATCH v2 4/9] mmc: mediatek: change the argument "ddr" to "timing"

[Chaotian Jing]

use the ios->timing directly is better
It can reflect current timing and do settings by timing

Signed-off-by: Chaotian Jing 
---
 drivers/mmc/host/mtk-sd.c | 20 
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 8b3e15d..c877ded 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -297,7 +297,7 @@ struct msdc_host {
u32 mclk;   /* mmc subsystem clock frequency */
u32 src_clk_freq;   /* source clock frequency */
u32 sclk;   /* SD/MS bus clock frequency */
-   bool ddr;
+   unsigned char timing;
bool vqmmc_enabled;
struct msdc_save_para save_para; /* used when gate HCLK */
 };
@@ -488,7 +488,7 @@ static void msdc_ungate_clock(struct msdc_host *host)
cpu_relax();
 }
 
-static void msdc_set_mclk(struct msdc_host *host, int ddr, u32 hz)
+static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
 {
u32 mode;
u32 flags;
@@ -504,7 +504,8 @@ static void msdc_set_mclk(struct msdc_host *host, int ddr, 
u32 hz)
 
flags = readl(host->base + MSDC_INTEN);
sdr_clr_bits(host->base + MSDC_INTEN, flags);
-   if (ddr) { /* may need to modify later */
+   if (timing == MMC_TIMING_UHS_DDR50 ||
+   timing == MMC_TIMING_MMC_DDR52) {
mode = 0x2; /* ddr mode and use divisor */
if (hz >= (host->src_clk_freq >> 2)) {
div = 0; /* mean div = 1/4 */
@@ -535,12 +536,12 @@ static void msdc_set_mclk(struct msdc_host *host, int 
ddr, u32 hz)
cpu_relax();
host->sclk = sclk;
host->mclk = hz;
-   host->ddr = ddr;
+   host->timing = timing;
/* need because clk changed. */
msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
sdr_set_bits(host->base + MSDC_INTEN, flags);
 
-   dev_dbg(host->dev, "sclk: %d, ddr: %d\n", host->sclk, ddr);
+   dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
 }
 
 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
@@ -1158,14 +1159,9 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, 
struct mmc_ios *ios)
 {
struct msdc_host *host = mmc_priv(mmc);
int ret;
-   u32 ddr = 0;
 
pm_runtime_get_sync(host->dev);
 
-   if (ios->timing == MMC_TIMING_UHS_DDR50 ||
-   ios->timing == MMC_TIMING_MMC_DDR52)
-   ddr = 1;
-
msdc_set_buswidth(host, ios->bus_width);
 
/* Suspend/Resume will do power off/on */
@@ -1202,8 +1198,8 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct 
mmc_ios *ios)
break;
}
 
-   if (host->mclk != ios->clock || host->ddr != ddr)
-   msdc_set_mclk(host, ddr, ios->clock);
+   if (host->mclk != ios->clock || host->timing != ios->timing)
+   msdc_set_mclk(host, ios->timing, ios->clock);
 
 end:
pm_runtime_mark_last_busy(host->dev);
-- 
1.8.1.1.dirty

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[PATCH v2 2/9] mmc: dt-bindings: update Mediatek MMC bindings

[Chaotian Jing]

Add 400Mhz clock source for HS400 mode

Signed-off-by: Chaotian Jing 
---
 Documentation/devicetree/bindings/mmc/mtk-sd.txt | 11 ++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt 
b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index a1adfa4..0120c7f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -17,6 +17,11 @@ Required properties:
 - vmmc-supply: power to the Core
 - vqmmc-supply: power to the IO
 
+Optional properties:
+- assigned-clocks: PLL of the source clock
+- assigned-clock-parents: parent of source clock, used for HS400 mode to get 
400Mhz source clock
+- hs400-ds-delay: HS400 DS delay setting
+
 Examples:
 mmc0: mmc@1123 {
compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
@@ -24,9 +29,13 @@ mmc0: mmc@1123 {
interrupts = ;
vmmc-supply = <_vemc_3v3_reg>;
vqmmc-supply = <_vio18_reg>;
-   clocks = < CLK_PERI_MSDC30_0>, < 
CLK_TOP_MSDC50_0_H_SEL>;
+   clocks = < CLK_PERI_MSDC30_0>,
+< CLK_TOP_MSDC50_0_H_SEL>;
clock-names = "source", "hclk";
pinctrl-names = "default", "state_uhs";
pinctrl-0 = <_pins_default>;
pinctrl-1 = <_pins_uhs>;
+   assigned-clocks = < CLK_TOP_MSDC50_0_SEL>;
+   assigned-clock-parents = < CLK_TOP_MSDCPLL_D2>;
+   hs400-ds-delay = <0x14015>;
 };
-- 
1.8.1.1.dirty

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[PATCH v2 5/9] mmc: mediatek: fix got GPD checksum error interrupt when data transfer

[Chaotian Jing]

Even if we only use one gpd, we need alloc 2 gpd and make
the gpd->next pointer to the second gpd, or may get gpd checksum
error, this was checked by hardware

Signed-off-by: Chaotian Jing 
---
 drivers/mmc/host/mtk-sd.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index c877ded..3858163 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1145,11 +1145,14 @@ static void msdc_init_gpd_bd(struct msdc_host *host, 
struct msdc_dma *dma)
struct mt_bdma_desc *bd = dma->bd;
int i;
 
-   memset(gpd, 0, sizeof(struct mt_gpdma_desc));
+   memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
 
gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
gpd->ptr = (u32)dma->bd_addr; /* physical address */
-
+   /* gpd->next is must set for desc DMA
+* That's why must alloc 2 gpd structure.
+*/
+   gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
for (i = 0; i < (MAX_BD_NUM - 1); i++)
bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
@@ -1306,7 +1309,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
 
host->timeout_clks = 3 * 1048576;
host->dma.gpd = dma_alloc_coherent(>dev,
-   sizeof(struct mt_gpdma_desc),
+   2 * sizeof(struct mt_gpdma_desc),
>dma.gpd_addr, GFP_KERNEL);
host->dma.bd = dma_alloc_coherent(>dev,
MAX_BD_NUM * sizeof(struct mt_bdma_desc),
@@ -1347,7 +1350,7 @@ release:
 release_mem:
if (host->dma.gpd)
dma_free_coherent(>dev,
-   sizeof(struct mt_gpdma_desc),
+   2 * sizeof(struct mt_gpdma_desc),
host->dma.gpd, host->dma.gpd_addr);
if (host->dma.bd)
dma_free_coherent(>dev,
-- 
1.8.1.1.dirty

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[PATCH v5 0/8] Add support for Exynos SROM Controller driver

[Pankaj Dubey]

This patch set adds support for Exynos SROM controller DT based driver.
Currently SROM register sets are used only during S2R, so driver
basically added for taking care of S2R. It will help us in removing
static mapping from exynos.c and other extra code handline during S2R.

This patch set also updated exynos4 and exynos5 dtsi files for with device
node for srom, and added binding documentation for the same.

First two patches are some minor cleanup in mach-exynos.

Patchset v1 was posted here[1]
[1]: https://lkml.org/lkml/2015/4/29/98
Patchset v2 was posted here[2]
[2]: https://lkml.org/lkml/2015/8/24/125
Patchset v3 was posted here[3]
[3]: https://lkml.org/lkml/2015/10/13/392
Patchset v3 was posted here[4]
[4]: https://lkml.org/lkml/2015/10/19/278

This patchset, I have tested on Peach-Pi (Exynos5880) based chromebook for boot
and S2R functionality.

Change since v4:
 - Removed unnedded NULL assignments from exynos_srom_remove function.
 - Added PM depency for selecting CONFIG_EXYNOS_SROM. 
Changes since v3:
 - Rebased to lastet kgene tree.
 - Added platform data support, instead of using global variables for srom base
 - Addressed review comments from LABBE Corentin

Changes since v2:
 - Rebased to latest kgene tree.
 - Addressed review comments from Krzysztof Kozlowski.
 - Add new patch for MAINTAINER list update.
 - Reordered patch sequence for avoiding git bisect issues.

Changes since v1:
 - Rebased to latest kgene tree.
 - Addressed review comments from Krzysztof Kozlowski.
 - Add two new patches for minor cleanup in exynos.c and map.h

Pankaj Dubey (8):
  ARM: EXYNOS: remove unused static mapping of CMU for exynos5
  ARM: EXYNOS: code cleanup in map.h
  Documentation: dt-bindings: add exynos-srom binding information
  ARM: dts: add SROM device node for exynos4
  ARM: dts: add SROM device node for exynos5
  drivers: soc: add support for exynos SROM driver
  MAINTAINERS: add maintainers entry for drivers/soc/samsung
  ARM: EXYNOS: Remove SROM related register settings from mach-exynos

 .../bindings/arm/samsung/exynos-srom.txt   |  12 ++
 MAINTAINERS|   1 +
 arch/arm/boot/dts/exynos4.dtsi |   5 +
 arch/arm/boot/dts/exynos5.dtsi |   5 +
 arch/arm/mach-exynos/Kconfig   |   2 +
 arch/arm/mach-exynos/exynos.c  |  22 ---
 arch/arm/mach-exynos/include/mach/map.h|   8 -
 arch/arm/mach-exynos/regs-srom.h   |  53 ---
 arch/arm/mach-exynos/suspend.c |  20 +--
 arch/arm/plat-samsung/include/plat/map-s5p.h   |   1 -
 drivers/soc/Kconfig|   1 +
 drivers/soc/Makefile   |   1 +
 drivers/soc/samsung/Kconfig|  13 ++
 drivers/soc/samsung/Makefile   |   1 +
 drivers/soc/samsung/exynos-srom.c  | 175 +
 drivers/soc/samsung/exynos-srom.h  |  51 ++
 16 files changed, 269 insertions(+), 102 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
 delete mode 100644 arch/arm/mach-exynos/regs-srom.h
 create mode 100644 drivers/soc/samsung/Kconfig
 create mode 100644 drivers/soc/samsung/Makefile
 create mode 100644 drivers/soc/samsung/exynos-srom.c
 create mode 100644 drivers/soc/samsung/exynos-srom.h

-- 
2.4.5

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[PATCH v5 2/8] ARM: EXYNOS: code cleanup in map.h

[Pankaj Dubey]

Remove unused exynos5440 uart offset macro.

Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/mach-exynos/include/mach/map.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/mach-exynos/include/mach/map.h 
b/arch/arm/mach-exynos/include/mach/map.h
index a2acba3..86d8085 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -35,8 +35,4 @@
 #define EXYNOS4_PA_SROMC   0x1257
 #define EXYNOS5_PA_SROMC   0x1225
 
-/* Compatibility UART */
-
-#define EXYNOS5440_PA_UART00x000B
-
 #endif /* __ASM_ARCH_MAP_H */
-- 
2.4.5

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[PATCH v5 3/8] Documentation: dt-bindings: add exynos-srom binding information

[Pankaj Dubey]

This patch adds exynos-srom binding information for SROM Controller
driver on Exynos SoCs.

CC: Rob Herring 
CC: Mark Rutland 
CC: Ian Campbell 
Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 .../devicetree/bindings/arm/samsung/exynos-srom.txt  | 12 
 1 file changed, 12 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt

diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt 
b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
new file mode 100644
index 000..33886d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
@@ -0,0 +1,12 @@
+SAMSUNG Exynos SoCs SROM Controller driver.
+
+Required properties:
+- compatible : Should contain "samsung,exynos-srom".
+
+- reg: offset and length of the register set
+
+Example:
+   sromc@1257 {
+   compatible = "samsung,exynos-srom";
+   reg = <0x1257 0x10>;
+   };
-- 
2.4.5

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[PATCH v5 1/8] ARM: EXYNOS: remove unused static mapping of CMU for exynos5

[Pankaj Dubey]

Remove unused static mapping of exynos5 CMU and related code.

Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/mach-exynos/exynos.c   | 5 -
 arch/arm/mach-exynos/include/mach/map.h | 1 -
 2 files changed, 6 deletions(-)

diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..524aa6f 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -70,11 +70,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn= __phys_to_pfn(EXYNOS5_PA_SROMC),
.length = SZ_4K,
.type   = MT_DEVICE,
-   }, {
-   .virtual= (unsigned long)S5P_VA_CMU,
-   .pfn= __phys_to_pfn(EXYNOS5_PA_CMU),
-   .length = 144 * SZ_1K,
-   .type   = MT_DEVICE,
},
 };
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h 
b/arch/arm/mach-exynos/include/mach/map.h
index de3ae59..a2acba3 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -25,7 +25,6 @@
 #define EXYNOS_PA_CHIPID   0x1000
 
 #define EXYNOS4_PA_CMU 0x1003
-#define EXYNOS5_PA_CMU 0x1001
 
 #define EXYNOS4_PA_DMC00x1040
 #define EXYNOS4_PA_DMC10x1041
-- 
2.4.5

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[PATCH v5 5/8] ARM: dts: add SROM device node for exynos5

[Pankaj Dubey]

Add SROM controller device node for exynos5.

CC: Rob Herring 
CC: Mark Rutland 
CC: Ian Campbell 
Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/boot/dts/exynos5.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 110dbd4..b5d3437 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -30,6 +30,11 @@
reg = <0x1000 0x100>;
};
 
+   sromc@1225 {
+   compatible = "samsung,exynos-srom";
+   reg = <0x1225 0x10>;
+   };
+
combiner: interrupt-controller@1044 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
-- 
2.4.5

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[PATCH v5 4/8] ARM: dts: add SROM device node for exynos4

[Pankaj Dubey]

Add device node of SROM controller for exynos4.

CC: Rob Herring 
CC: Mark Rutland 
CC: Ian Campbell 
Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/boot/dts/exynos4.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3184e10..2f31f77 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -76,6 +76,11 @@
reg = <0x1000 0x100>;
};
 
+   sromc@1257 {
+   compatible = "samsung,exynos-srom";
+   reg = <0x1257 0x10>;
+   };
+
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
-- 
2.4.5

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[PATCH v5 7/8] MAINTAINERS: add maintainers entry for drivers/soc/samsung

[Pankaj Dubey]

This patch adds maintainers entry for new driver folder
drivers/soc/samsung

Signed-off-by: Pankaj Dubey 
Acked-by: Krzysztof Kozlowski 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..262bba6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1438,6 +1438,7 @@ F:arch/arm/mach-exynos*/
 F: drivers/*/*s3c2410*
 F: drivers/*/*/*s3c2410*
 F: drivers/spi/spi-s3c*
+F: drivers/soc/samsung/*
 F: sound/soc/samsung/*
 N: exynos
 
-- 
2.4.5

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[PATCH 05/10] drm/exynos/decon5433: fix timing registers writes

[Andrzej Hajda]

All timing registers should contain values decreased by one.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index b25d764..83e0939 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -104,7 +104,7 @@ static void decon_setup_trigger(struct decon_context *ctx)
 static void decon_commit(struct exynos_drm_crtc *crtc)
 {
struct decon_context *ctx = crtc->ctx;
-   struct drm_display_mode *mode = >base.mode;
+   struct drm_display_mode *m = >base.mode;
u32 val;
 
if (ctx->suspended)
@@ -122,29 +122,29 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
val |= VIDOUT_RGB_IF;
writel(val, ctx->addr + DECON_VIDOUTCON0);
 
-   val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
-   VIDTCON2_HOZVAL(mode->hdisplay - 1);
+   val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
+   VIDTCON2_HOZVAL(m->hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON2);
 
if (!ctx->i80_if) {
val = VIDTCON00_VBPD_F(
-   mode->crtc_vtotal - mode->crtc_vsync_end) |
+   m->crtc_vtotal - m->crtc_vsync_end - 1) |
VIDTCON00_VFPD_F(
-   mode->crtc_vsync_start - mode->crtc_vdisplay);
+   m->crtc_vsync_start - m->crtc_vdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON00);
 
val = VIDTCON01_VSPW_F(
-   mode->crtc_vsync_end - mode->crtc_vsync_start);
+   m->crtc_vsync_end - m->crtc_vsync_start - 1);
writel(val, ctx->addr + DECON_VIDTCON01);
 
val = VIDTCON10_HBPD_F(
-   mode->crtc_htotal - mode->crtc_hsync_end) |
+   m->crtc_htotal - m->crtc_hsync_end - 1) |
VIDTCON10_HFPD_F(
-   mode->crtc_hsync_start - mode->crtc_hdisplay);
+   m->crtc_hsync_start - m->crtc_hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON10);
 
val = VIDTCON11_HSPW_F(
-   mode->crtc_hsync_end - mode->crtc_hsync_start);
+   m->crtc_hsync_end - m->crtc_hsync_start - 1);
writel(val, ctx->addr + DECON_VIDTCON11);
}
 
-- 
1.9.1

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[PATCH 00/10] drm/exynos/decon5433: add support to DECON-TV

[Andrzej Hajda]

Hi Inki,

This patchset adds support to DECON-TV in Exynos5433 SoC.
The main patch is prepended with few preparation patches:
- add three clocks required by HDMI pipeline,
- small bindings update,
- driver cleanup.

The patchset is based on the latest exynos-drm-next branch.

Regards
Andrzej


Andrzej Hajda (10):
  clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks
  clk/samsung: exynos5433: add pclk_decon clock
  drm/exynos/decon5433: add PCLK clock
  dt-bindings: video: add PCLK clock entry to exynos5433-decon
  drm/exynos/decon5433: fix timing registers writes
  drm/exynos/decon5433: add function to set particular register bits
  drm/exynos/decon5433: merge different flag fields
  drm/exynos/decon5433: remove duplicated initialization
  dt-bindings: video: exynos5433-decon: add bindings for DECON-TV
  drm/exynos/decon5433: add support for DECON-TV

 .../devicetree/bindings/video/exynos5433-decon.txt |  23 +-
 drivers/clk/samsung/clk-exynos5433.c   |   8 +-
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c  | 320 ++---
 include/dt-bindings/clock/exynos5433.h |   7 +-
 include/video/exynos5433_decon.h   |  29 ++
 5 files changed, 214 insertions(+), 173 deletions(-)

-- 
1.9.1

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[PATCH 06/10] drm/exynos/decon5433: add function to set particular register bits

[Andrzej Hajda]

The driver often sets only particular bits of configuration registers.
Using separate function to such action simplifies the code.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 69 ---
 1 file changed, 19 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 83e0939..722c11a 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -62,6 +62,13 @@ static const uint32_t decon_formats[] = {
DRM_FORMAT_ARGB,
 };
 
+static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
+ u32 val)
+{
+   val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
+   writel(val, ctx->addr + reg);
+}
+
 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
 {
struct decon_context *ctx = crtc->ctx;
@@ -215,16 +222,8 @@ static void decon_win_set_pixfmt(struct decon_context 
*ctx, unsigned int win,
 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
bool protect)
 {
-   u32 val;
-
-   val = readl(ctx->addr + DECON_SHADOWCON);
-
-   if (protect)
-   val |= SHADOWCON_Wx_PROTECT(win);
-   else
-   val &= ~SHADOWCON_Wx_PROTECT(win);
-
-   writel(val, ctx->addr + DECON_SHADOWCON);
+   decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
+  protect ? ~0 : 0);
 }
 
 static void decon_atomic_begin(struct exynos_drm_crtc *crtc,
@@ -278,14 +277,10 @@ static void decon_update_plane(struct exynos_drm_crtc 
*crtc,
decon_win_set_pixfmt(ctx, win, state->fb);
 
/* window enable */
-   val = readl(ctx->addr + DECON_WINCONx(win));
-   val |= WINCONx_ENWIN_F;
-   writel(val, ctx->addr + DECON_WINCONx(win));
+   decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 
/* standalone update */
-   val = readl(ctx->addr + DECON_UPDATE);
-   val |= STANDALONE_UPDATE_F;
-   writel(val, ctx->addr + DECON_UPDATE);
+   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 }
 
 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
@@ -293,7 +288,6 @@ static void decon_disable_plane(struct exynos_drm_crtc 
*crtc,
 {
struct decon_context *ctx = crtc->ctx;
unsigned int win = plane->zpos;
-   u32 val;
 
if (ctx->suspended)
return;
@@ -301,16 +295,12 @@ static void decon_disable_plane(struct exynos_drm_crtc 
*crtc,
decon_shadow_protect_win(ctx, win, true);
 
/* window disable */
-   val = readl(ctx->addr + DECON_WINCONx(win));
-   val &= ~WINCONx_ENWIN_F;
-   writel(val, ctx->addr + DECON_WINCONx(win));
+   decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 
decon_shadow_protect_win(ctx, win, false);
 
/* standalone update */
-   val = readl(ctx->addr + DECON_UPDATE);
-   val |= STANDALONE_UPDATE_F;
-   writel(val, ctx->addr + DECON_UPDATE);
+   decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 }
 
 static void decon_atomic_flush(struct exynos_drm_crtc *crtc,
@@ -416,17 +406,12 @@ static void decon_disable(struct exynos_drm_crtc *crtc)
 void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 {
struct decon_context *ctx = crtc->ctx;
-   u32 val;
 
if (!test_bit(BIT_CLKS_ENABLED, >enabled))
return;
 
-   if (atomic_add_unless(>win_updated, -1, 0)) {
-   /* trigger */
-   val = readl(ctx->addr + DECON_TRIGCON);
-   val |= TRIGCON_SWTRIGCMD;
-   writel(val, ctx->addr + DECON_TRIGCON);
-   }
+   if (atomic_add_unless(>win_updated, -1, 0))
+   decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 
drm_crtc_handle_vblank(>crtc->base);
 }
@@ -435,7 +420,6 @@ static void decon_clear_channels(struct exynos_drm_crtc 
*crtc)
 {
struct decon_context *ctx = crtc->ctx;
int win, i, ret;
-   u32 val;
 
DRM_DEBUG_KMS("%s\n", __FILE__);
 
@@ -446,25 +430,10 @@ static void decon_clear_channels(struct exynos_drm_crtc 
*crtc)
}
 
for (win = 0; win < WINDOWS_NR; win++) {
-   /* shadow update disable */
-   val = readl(ctx->addr + DECON_SHADOWCON);
-   val |= SHADOWCON_Wx_PROTECT(win);
-   writel(val, ctx->addr + DECON_SHADOWCON);
-
-   /* window disable */
-   val = readl(ctx->addr + DECON_WINCONx(win));
-   val &= ~WINCONx_ENWIN_F;
-   writel(val, ctx->addr + DECON_WINCONx(win));
-
-   /* shadow update enable */
-   val = readl(ctx->addr + DECON_SHADOWCON);
-   val &= ~SHADOWCON_Wx_PROTECT(win);
-   writel(val, ctx->addr + 

[PATCH 04/10] dt-bindings: video: add PCLK clock entry to exynos5433-decon

[Andrzej Hajda]

DECON IP requires this clock to access configuration registers.

Signed-off-by: Andrzej Hajda 
---
 Documentation/devicetree/bindings/video/exynos5433-decon.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
index 377afbf..3dff78b 100644
--- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
+++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
@@ -16,7 +16,7 @@ Required properties:
 - clocks: must include clock specifiers corresponding to entries in the
  clock-names property.
 - clock-names: list of clock names sorted in the same order as the clocks
-  property. Must contain "aclk_decon", "aclk_smmu_decon0x",
+  property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
   "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
   "sclk_decon_eclk"
 - ports: contains a port which is connected to mic node. address-cells and
-- 
1.9.1

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[PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Andrzej Hajda]

HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.

Signed-off-by: Andrzej Hajda 
---
 drivers/clk/samsung/clk-exynos5433.c   | 6 --
 include/dt-bindings/clock/exynos5433.h | 5 -
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index 650ec13..e037406 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] 
__initdata = {
FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
1),
/* PHY clocks from HDMI_PHY */
-   FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 3),
-   FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 16600),
+   FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
+   NULL, CLK_IS_ROOT, 3),
+   FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, 
"phyclk_hdmiphy_pixel_clko_phy",
+   NULL, CLK_IS_ROOT, 16600),
 };
 
 static struct samsung_mux_clock disp_mux_clks[] __initdata = {
diff --git a/include/dt-bindings/clock/exynos5433.h 
b/include/dt-bindings/clock/exynos5433.h
index 5bd80d5..4f0d566 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,10 @@
 #define CLK_SCLK_RGB_VCLK  109
 #define CLK_SCLK_RGB_TV_VCLK   110
 
-#define DISP_NR_CLK111
+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
+
+#define DISP_NR_CLK113
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER  1
-- 
1.9.1

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[PATCH 03/10] drm/exynos/decon5433: add PCLK clock

[Andrzej Hajda]

PCLK clock is used by DECON IP. The patch also replaces magic number with
number of clocks in array definition.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 1ea26dbb..b25d764 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -27,13 +27,23 @@
 #define CURSOR_WIN 2
 #define MIN_FB_WIDTH_FOR_16WORD_BURST  128
 
+static const char * const decon_clks_name[] = {
+   "pclk",
+   "aclk_decon",
+   "aclk_smmu_decon0x",
+   "aclk_xiu_decon0x",
+   "pclk_smmu_decon0x",
+   "sclk_decon_vclk",
+   "sclk_decon_eclk",
+};
+
 struct decon_context {
struct device   *dev;
struct drm_device   *drm_dev;
struct exynos_drm_crtc  *crtc;
struct exynos_drm_plane planes[WINDOWS_NR];
void __iomem*addr;
-   struct clk  *clks[6];
+   struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
unsigned long   irq_flags;
int pipe;
boolsuspended;
@@ -45,15 +55,6 @@ struct decon_context {
atomic_twin_updated;
 };
 
-static const char * const decon_clks_name[] = {
-   "aclk_decon",
-   "aclk_smmu_decon0x",
-   "aclk_xiu_decon0x",
-   "pclk_smmu_decon0x",
-   "sclk_decon_vclk",
-   "sclk_decon_eclk",
-};
-
 static const uint32_t decon_formats[] = {
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGB565,
-- 
1.9.1

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[PATCH 02/10] clk/samsung: exynos5433: add pclk_decon clock

[Andrzej Hajda]

This undocumented gate clock is used by DECON IP.

Signed-off-by: Andrzej Hajda 
---
 drivers/clk/samsung/clk-exynos5433.c   | 2 ++
 include/dt-bindings/clock/exynos5433.h | 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index e037406..e7b4533 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2822,6 +2822,8 @@ static struct samsung_gate_clock disp_gate_clks[] 
__initdata = {
ENABLE_PCLK_DISP, 2, 0, 0),
GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
ENABLE_PCLK_DISP, 1, 0, 0),
+   GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
+   ENABLE_PCLK_DISP, 0, 0, 0),
 
/* ENABLE_SCLK_DISP */
GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
diff --git a/include/dt-bindings/clock/exynos5433.h 
b/include/dt-bindings/clock/exynos5433.h
index 4f0d566..5c2636c 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -768,7 +768,9 @@
 #define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
 
-#define DISP_NR_CLK113
+#define CLK_PCLK_DECON 113
+
+#define DISP_NR_CLK114
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER  1
-- 
1.9.1

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[PATCH v5 8/8] ARM: EXYNOS: Remove SROM related register settings from mach-exynos

[Pankaj Dubey]

As now we have dedicated driver for SROM controller, it will take care
of saving register banks during S2R so we can safely remove these
settings from mach-exynos.

Signed-off-by: Pankaj Dubey 
Reviewed-by: Krzysztof Kozlowski 
---
 arch/arm/mach-exynos/Kconfig |  2 ++
 arch/arm/mach-exynos/exynos.c| 17 -
 arch/arm/mach-exynos/include/mach/map.h  |  3 --
 arch/arm/mach-exynos/regs-srom.h | 53 
 arch/arm/mach-exynos/suspend.c   | 20 ++-
 arch/arm/plat-samsung/include/plat/map-s5p.h |  1 -
 6 files changed, 4 insertions(+), 92 deletions(-)
 delete mode 100644 arch/arm/mach-exynos/regs-srom.h

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a..62c3139 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,8 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+   select SOC_SAMSUNG
+   select EXYNOS_SROM if PM
help
  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
 
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 524aa6f..4ffb90e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -37,11 +37,6 @@ void __iomem *pmu_base_addr;
 
 static struct map_desc exynos4_iodesc[] __initdata = {
{
-   .virtual= (unsigned long)S5P_VA_SROMC,
-   .pfn= __phys_to_pfn(EXYNOS4_PA_SROMC),
-   .length = SZ_4K,
-   .type   = MT_DEVICE,
-   }, {
.virtual= (unsigned long)S5P_VA_CMU,
.pfn= __phys_to_pfn(EXYNOS4_PA_CMU),
.length = SZ_128K,
@@ -64,15 +59,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
},
 };
 
-static struct map_desc exynos5_iodesc[] __initdata = {
-   {
-   .virtual= (unsigned long)S5P_VA_SROMC,
-   .pfn= __phys_to_pfn(EXYNOS5_PA_SROMC),
-   .length = SZ_4K,
-   .type   = MT_DEVICE,
-   },
-};
-
 static struct platform_device exynos_cpuidle = {
.name  = "exynos_cpuidle",
 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@@ -144,9 +130,6 @@ static void __init exynos_map_io(void)
 {
if (soc_is_exynos4())
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-
-   if (soc_is_exynos5())
-   iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 }
 
 static void __init exynos_init_io(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h 
b/arch/arm/mach-exynos/include/mach/map.h
index 86d8085..351e839 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -32,7 +32,4 @@
 #define EXYNOS4_PA_COREPERI0x1050
 #define EXYNOS4_PA_L2CC0x10502000
 
-#define EXYNOS4_PA_SROMC   0x1257
-#define EXYNOS5_PA_SROMC   0x1225
-
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-exynos/regs-srom.h b/arch/arm/mach-exynos/regs-srom.h
deleted file mode 100644
index 5c4d442..000
--- a/arch/arm/mach-exynos/regs-srom.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * S5P SROMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __PLAT_SAMSUNG_REGS_SROM_H
-#define __PLAT_SAMSUNG_REGS_SROM_H __FILE__
-
-#include 
-
-#define S5P_SROMREG(x) (S5P_VA_SROMC + (x))
-
-#define S5P_SROM_BWS5P_SROMREG(0x0)
-#define S5P_SROM_BC0   S5P_SROMREG(0x4)
-#define S5P_SROM_BC1   S5P_SROMREG(0x8)
-#define S5P_SROM_BC2   S5P_SROMREG(0xc)
-#define S5P_SROM_BC3   S5P_SROMREG(0x10)
-#define S5P_SROM_BC4   S5P_SROMREG(0x14)
-#define S5P_SROM_BC5   S5P_SROMREG(0x18)
-
-/* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
-
-#define S5P_SROM_BW__DATAWIDTH__SHIFT  0
-#define S5P_SROM_BW__ADDRMODE__SHIFT   1
-#define S5P_SROM_BW__WAITENABLE__SHIFT 2
-#define S5P_SROM_BW__BYTEENABLE__SHIFT 3
-
-#define S5P_SROM_BW__CS_MASK   0xf
-
-#define S5P_SROM_BW__NCS0__SHIFT   0
-#define S5P_SROM_BW__NCS1__SHIFT   4
-#define S5P_SROM_BW__NCS2__SHIFT   8
-#define S5P_SROM_BW__NCS3__SHIFT   12
-#define S5P_SROM_BW__NCS4__SHIFT   16
-#define S5P_SROM_BW__NCS5__SHIFT   20
-
-/* applies to same to BCS0 - BCS3 */
-
-#define S5P_SROM_BCX__PMC__SHIFT   0
-#define S5P_SROM_BCX__TACP__SHIFT  4
-#define 

[PATCH v5 6/8] drivers: soc: add support for exynos SROM driver

[Pankaj Dubey]

This patch adds Exynos SROM controller driver which will handle
save restore of SROM registers during S2R.

Signed-off-by: Pankaj Dubey 
---
 drivers/soc/Kconfig   |   1 +
 drivers/soc/Makefile  |   1 +
 drivers/soc/samsung/Kconfig   |  13 +++
 drivers/soc/samsung/Makefile  |   1 +
 drivers/soc/samsung/exynos-srom.c | 175 ++
 drivers/soc/samsung/exynos-srom.h |  51 +++
 6 files changed, 242 insertions(+)
 create mode 100644 drivers/soc/samsung/Kconfig
 create mode 100644 drivers/soc/samsung/Makefile
 create mode 100644 drivers/soc/samsung/exynos-srom.c
 create mode 100644 drivers/soc/samsung/exynos-srom.h

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 96ddecb..69107c9 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
 
 source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
+source "drivers/soc/samsung/Kconfig"
 source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/ti/Kconfig"
 source "drivers/soc/versatile/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 0b12d77..a623616 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -5,6 +5,7 @@
 obj-$(CONFIG_MACH_DOVE)+= dove/
 obj-$(CONFIG_ARCH_MEDIATEK)+= mediatek/
 obj-$(CONFIG_ARCH_QCOM)+= qcom/
+obj-$(CONFIG_SOC_SAMSUNG)  += samsung/
 obj-$(CONFIG_ARCH_SUNXI)   += sunxi/
 obj-$(CONFIG_ARCH_TEGRA)   += tegra/
 obj-$(CONFIG_SOC_TI)   += ti/
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
new file mode 100644
index 000..2833b5b
--- /dev/null
+++ b/drivers/soc/samsung/Kconfig
@@ -0,0 +1,13 @@
+#
+# SAMSUNG SoC drivers
+#
+menu "Samsung SOC driver support"
+
+config SOC_SAMSUNG
+   bool
+
+config EXYNOS_SROM
+   bool
+   depends on ARM && ARCH_EXYNOS && PM
+
+endmenu
diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
new file mode 100644
index 000..9c554d5
--- /dev/null
+++ b/drivers/soc/samsung/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_EXYNOS_SROM)  += exynos-srom.o
diff --git a/drivers/soc/samsung/exynos-srom.c 
b/drivers/soc/samsung/exynos-srom.c
new file mode 100644
index 000..57a232d
--- /dev/null
+++ b/drivers/soc/samsung/exynos-srom.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2015 Samsung Electronics Co., Ltd.
+ *   http://www.samsung.com/
+ *
+ * EXYNOS - SROM Controller support
+ * Author: Pankaj Dubey 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "exynos-srom.h"
+
+static const unsigned long exynos_srom_offsets[] = {
+   /* SROM side */
+   EXYNOS_SROM_BW,
+   EXYNOS_SROM_BC0,
+   EXYNOS_SROM_BC1,
+   EXYNOS_SROM_BC2,
+   EXYNOS_SROM_BC3,
+};
+
+/**
+ * struct exynos_srom_reg_dump: register dump of SROM Controller registers.
+ * @offset: srom register offset from the controller base address.
+ * @value: the value of register under the offset.
+ */
+struct exynos_srom_reg_dump {
+   u32 offset;
+   u32 value;
+};
+
+/**
+ * struct exynos_srom: platform data for exynos srom controller driver.
+ * @dev: platform device pointer
+ * @reg_base: srom base address
+ * @reg_offset: exynos_srom_reg_dump pointer to hold offset and its value.
+ */
+struct exynos_srom {
+   struct device *dev;
+   void __iomem *reg_base;
+   struct exynos_srom_reg_dump *reg_offset;
+};
+
+static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump(
+   const unsigned long *rdump,
+   unsigned long nr_rdump)
+{
+   struct exynos_srom_reg_dump *rd;
+   unsigned int i;
+
+   rd = kcalloc(nr_rdump, sizeof(*rd), GFP_KERNEL);
+   if (!rd)
+   return NULL;
+
+   for (i = 0; i < nr_rdump; ++i)
+   rd[i].offset = rdump[i];
+
+   return rd;
+}
+
+static int exynos_srom_probe(struct platform_device *pdev)
+{
+   struct device_node *np;
+   struct exynos_srom *srom;
+   struct device *dev = >dev;
+
+   np = dev->of_node;
+   if (!np) {
+   dev_err(>dev, "could not find device info\n");
+   return -EINVAL;
+   }
+
+   srom = devm_kzalloc(>dev,
+   sizeof(struct exynos_srom), GFP_KERNEL);
+   if (!srom)
+   return -ENOMEM;
+
+   srom->dev = dev;
+   srom->reg_base = of_iomap(np, 0);
+   if (!srom->reg_base) {
+   dev_err(>dev, "iomap of exynos srom controller failed\n");
+   return -ENOMEM;
+   }
+
+   platform_set_drvdata(pdev, srom);
+
+   srom->reg_offset = exynos_srom_alloc_reg_dump(exynos_srom_offsets,
+

[PATCH 09/10] dt-bindings: video: exynos5433-decon: add bindings for DECON-TV

[Andrzej Hajda]

DECON-TV(Display and Enhancement Controller for TV) is a variation
of DECON IP. Its main purpose is to produce video stream for HDMI IP.

Signed-off-by: Andrzej Hajda 
---
 .../devicetree/bindings/video/exynos5433-decon.txt  | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
index 3dff78b..2a88c8d 100644
--- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
+++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
@@ -5,24 +5,27 @@ Exynos series of SoCs which transfers the image data from a 
video memory
 buffer to an external LCD interface.
 
 Required properties:
-- compatible: value should be "samsung,exynos5433-decon";
+- compatible: value should be one of:
+   "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
 - reg: physical base address and length of the DECON registers set.
-- interrupts: should contain a list of all DECON IP block interrupts in the
- order: VSYNC, LCD_SYSTEM. The interrupt specifier format
- depends on the interrupt controller used.
-- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
-  in the same order as they were listed in the interrupts
-  property.
+- interrupts: should contain interrupt specifier of VSYNC and optionally
+ LCD_SYSTEM. The interrupt specifier format depends on
+ the interrupt controller used.
+- interrupt-names: should contain the interrupt name "vsync" and optionally
+  "lcd_sys" in the same order as they were listed in
+  the interrupts property.
 - clocks: must include clock specifiers corresponding to entries in the
  clock-names property.
 - clock-names: list of clock names sorted in the same order as the clocks
   property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
   "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
   "sclk_decon_eclk"
+
+Optional properties:
 - ports: contains a port which is connected to mic node. address-cells and
-size-cells must 1 and 0, respectively.
+size-cells must be 1 and 0, respectively.
 - port: contains an endpoint node which is connected to the endpoint in the mic
-   node. The reg value muset be 0.
+   node. The reg value must be 0.
 - i80-if-timings: specify whether the panel which is connected to decon uses
  i80 lcd interface or mipi video interface. This node contains
  no timing information as that of fimd does. Because there is
-- 
1.9.1

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[PATCH 10/10] drm/exynos/decon5433: add support for DECON-TV

[Andrzej Hajda]

DECON-TV IP is responsible for generating video stream which is transferred
to HDMI IP. It is almost fully compatible with DECON IP.

The patch is based on initial work of Hyungwon Hwang.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 154 --
 include/video/exynos5433_decon.h  |  29 +
 2 files changed, 122 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 3c9aa4e..fbe1b31 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -37,6 +38,12 @@ static const char * const decon_clks_name[] = {
"sclk_decon_eclk",
 };
 
+enum decon_iftype {
+   IFTYPE_RGB,
+   IFTYPE_I80,
+   IFTYPE_HDMI
+};
+
 enum decon_flag_bits {
BIT_CLKS_ENABLED,
BIT_IRQS_ENABLED,
@@ -53,7 +60,8 @@ struct decon_context {
struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
int pipe;
unsigned long   flags;
-   booli80_if;
+   enum decon_iftype   out_type;
+   int first_win;
 };
 
 static const uint32_t decon_formats[] = {
@@ -80,7 +88,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
 
if (test_and_set_bit(BIT_IRQS_ENABLED, >flags)) {
val = VIDINTCON0_INTEN;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDINTCON0_FRAMEDONE;
else
val |= VIDINTCON0_INTFRMEN;
@@ -104,8 +112,11 @@ static void decon_disable_vblank(struct exynos_drm_crtc 
*crtc)
 
 static void decon_setup_trigger(struct decon_context *ctx)
 {
-   u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
-   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
+   u32 val = (ctx->out_type != IFTYPE_HDMI)
+   ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
+   : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
writel(val, ctx->addr + DECON_TRIGCON);
 }
 
@@ -118,13 +129,22 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
if (test_bit(BIT_SUSPENDED, >flags))
return;
 
+   if (ctx->out_type == IFTYPE_HDMI) {
+   m->crtc_hsync_start = m->crtc_hdisplay + 10;
+   m->crtc_hsync_end = m->crtc_htotal - 92;
+   m->crtc_vsync_start = m->crtc_vdisplay + 1;
+   m->crtc_vsync_end = m->crtc_vsync_start + 1;
+   }
+
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
+
/* enable clock gate */
val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
writel(val, ctx->addr + DECON_CMU);
 
/* lcd on and use command if */
val = VIDOUT_LCD_ON;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDOUT_COMMAND_IF;
else
val |= VIDOUT_RGB_IF;
@@ -134,7 +154,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
VIDTCON2_HOZVAL(m->hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON2);
 
-   if (!ctx->i80_if) {
+   if (ctx->out_type != IFTYPE_I80) {
val = VIDTCON00_VBPD_F(
m->crtc_vtotal - m->crtc_vsync_end - 1) |
VIDTCON00_VFPD_F(
@@ -159,15 +179,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
decon_setup_trigger(ctx);
 
/* enable output and display signal */
-   val = VIDCON0_ENVID | VIDCON0_ENVID_F;
-   writel(val, ctx->addr + DECON_VIDCON0);
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 }
 
-#define COORDINATE_X(x)(((x) & 0xfff) << 12)
-#define COORDINATE_Y(x)((x) & 0xfff)
-#define OFFSIZE(x) (((x) & 0x3fff) << 14)
-#define PAGEWIDTH(x)   ((x) & 0x3fff)
-
 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 struct drm_framebuffer *fb)
 {
@@ -238,6 +252,10 @@ static void decon_atomic_begin(struct exynos_drm_crtc 
*crtc,
decon_shadow_protect_win(ctx, plane->zpos, true);
 }
 
+#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
+#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
+#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
+
 static void decon_update_plane(struct exynos_drm_crtc *crtc,
   struct exynos_drm_plane *plane)
 {
@@ -271,8 +289,12 @@ static void decon_update_plane(struct exynos_drm_crtc 
*crtc,
val = plane->dma_addr[0] + pitch * 

[PATCH 08/10] drm/exynos/decon5433: remove duplicated initialization

[Andrzej Hajda]

Field .commit is already initialized few lines above.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 265a77f..3c9aa4e 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -448,7 +448,6 @@ static struct exynos_drm_crtc_ops decon_crtc_ops = {
.commit = decon_commit,
.enable_vblank  = decon_enable_vblank,
.disable_vblank = decon_disable_vblank,
-   .commit = decon_commit,
.atomic_begin   = decon_atomic_begin,
.update_plane   = decon_update_plane,
.disable_plane  = decon_disable_plane,
-- 
1.9.1

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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers

[Alim Akhtar]

Hi Moritz,

On 10/20/2015 02:48 AM, Moritz Fischer wrote:

On Sun, Oct 18, 2015 at 11:03 PM, Alim Akhtar  wrote:

Alim Akhtar (7):
   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
   ARM: exynos_defconfig: Normalize exynos defconfig
   ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
 drivers
   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs

  arch/arm/boot/dts/exynos3250.dtsi |   14 
  arch/arm/boot/dts/exynos4.dtsi|   14 
  arch/arm/boot/dts/exynos5.dtsi|   14 
  arch/arm/boot/dts/exynos5410.dtsi |   14 
  arch/arm/configs/exynos_defconfig |   11 +-
  arch/arm/mach-exynos/pmu.c|   43 -
  6 files changed, 61 insertions(+), 49 deletions(-)

--
1.7.10.4
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Feel free to add Acked-By: Moritz Fischer 
to the patches in your series


Thanks!

Moritz


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Re: [PATCH 1/7] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs

[Alim Akhtar]

Hi Javier,

On 10/19/2015 06:33 PM, Javier Martinez Canillas wrote:

Hello Alim,

On 10/19/2015 08:03 AM, Alim Akhtar wrote:

This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.

Signed-off-by: Alim Akhtar 
---
  arch/arm/boot/dts/exynos3250.dtsi |   14 ++
  1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def482fc3..af5d9ad4c7b7 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <>;
};

+   poweroff: syscon-poweroff {
+   compatible = "syscon-poweroff";
+   regmap = <_system_controller>;
+   offset = <0x330C>;
+   mask = <0x5200>;
+   };
+
+   reboot: syscon-reboot {
+   compatible = "syscon-reboot";
+   regmap = <_system_controller>;
+   offset = <0x0400>;
+   mask = <0x1>;
+   };
+


I don't have a Exynos3250 manual but I guess 0x330C is also named
PS_HOLD_CONTROL and 0x400 is SWRESET as the other Exynos SoCs.

I wonder if a macro could be used instead of magic numbers or at
least have a comment next to the offset field.

The patch looks good to me though and a comment can be added as
a follow up so:


Will add a comment about register offset next to it.


Reviewed-by: Javier Martinez Canillas 


Thanks!


Best regards,


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[PATCH v2 8/9] mmc: mediatek: add HS400 support

[Chaotian Jing]

add HS400 mode and tune support

Signed-off-by: Chaotian Jing 
---
 drivers/mmc/host/mtk-sd.c | 241 +-
 1 file changed, 236 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 5627644..528646c 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -72,6 +73,8 @@
 #define MSDC_PATCH_BIT   0xb0
 #define MSDC_PATCH_BIT1  0xb4
 #define MSDC_PAD_TUNE0xec
+#define PAD_DS_TUNE  0x188
+#define EMMC50_CFG0  0x208
 
 /*--*/
 /* Register Mask*/
@@ -88,6 +91,7 @@
 #define MSDC_CFG_CKSTB  (0x1 << 7) /* R  */
 #define MSDC_CFG_CKDIV  (0xff << 8)/* RW */
 #define MSDC_CFG_CKMOD  (0x3 << 16)/* RW */
+#define MSDC_CFG_HS400_CK_MODE  (0x1 << 18)/* RW */
 
 /* MSDC_IOCON mask */
 #define MSDC_IOCON_SDR104CKS(0x1 << 0) /* RW */
@@ -205,6 +209,17 @@
 #define MSDC_PATCH_BIT_SPCPUSH(0x1 << 29)  /* RW */
 #define MSDC_PATCH_BIT_DECRCTMO   (0x1 << 30)  /* RW */
 
+#define MSDC_PAD_TUNE_DATRRDLY   (0x1f <<  8)  /* RW */
+#define MSDC_PAD_TUNE_CMDRDLY(0x1f << 16)  /* RW */
+
+#define PAD_DS_TUNE_DLY1 (0x1f << 2)   /* RW */
+#define PAD_DS_TUNE_DLY2 (0x1f << 7)   /* RW */
+#define PAD_DS_TUNE_DLY3 (0x1f << 12)  /* RW */
+
+#define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0)   /* RW */
+#define EMMC50_CFG_CRCSTS_EDGE(0x1 << 3)   /* RW */
+#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4)   /* RW */
+
 #define REQ_CMD_EIO  (0x1 << 0)
 #define REQ_CMD_TMO  (0x1 << 1)
 #define REQ_DAT_ERR  (0x1 << 2)
@@ -220,6 +235,7 @@
 #define CMD_TIMEOUT (HZ/10 * 5)/* 100ms x5 */
 #define DAT_TIMEOUT (HZ* 5)/* 1000ms x5 */
 
+#define PAD_DELAY_MAX  32 /* PAD delay cells */
 /*--*/
 /* Descriptor Structure */
 /*--*/
@@ -266,6 +282,14 @@ struct msdc_save_para {
u32 pad_tune;
u32 patch_bit0;
u32 patch_bit1;
+   u32 pad_ds_tune;
+   u32 emmc50_cfg0;
+};
+
+struct msdc_delay_phase {
+   u8 maxlen;
+   u8 start;
+   u8 final_phase;
 };
 
 struct msdc_host {
@@ -300,6 +324,7 @@ struct msdc_host {
u32 sclk;   /* SD/MS bus clock frequency */
unsigned char timing;
bool vqmmc_enabled;
+   u32 hs400_ds_delay;
struct msdc_save_para save_para; /* used when gate HCLK */
 };
 
@@ -505,9 +530,15 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned 
char timing, u32 hz)
 
flags = readl(host->base + MSDC_INTEN);
sdr_clr_bits(host->base + MSDC_INTEN, flags);
+   sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
if (timing == MMC_TIMING_UHS_DDR50 ||
-   timing == MMC_TIMING_MMC_DDR52) {
-   mode = 0x2; /* ddr mode and use divisor */
+   timing == MMC_TIMING_MMC_DDR52 ||
+   timing == MMC_TIMING_MMC_HS400) {
+   if (timing == MMC_TIMING_MMC_HS400)
+   mode = 0x3;
+   else
+   mode = 0x2; /* ddr mode and use divisor */
+
if (hz >= (host->src_clk_freq >> 2)) {
div = 0; /* mean div = 1/4 */
sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
@@ -516,6 +547,13 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned 
char timing, u32 hz)
sclk = (host->src_clk_freq >> 2) / div;
div = (div >> 1);
}
+
+   if (timing == MMC_TIMING_MMC_HS400 &&
+   hz >= (host->src_clk_freq >> 1)) {
+   sdr_set_bits(host->base + MSDC_CFG, 
MSDC_CFG_HS400_CK_MODE);
+   sclk = host->src_clk_freq >> 1;
+   div = 0; /* div is ignore when bit18 is set */
+   }
} else if (hz >= host->src_clk_freq) {
mode = 0x1; /* no divisor */
div = 0;
@@ -894,7 +932,7 @@ static void msdc_data_xfer_next(struct msdc_host *host,
struct mmc_request *mrq, struct mmc_data *data)
 {
if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
-   (!data->bytes_xfered || !mrq->sbc))
+   !mrq->sbc)
msdc_start_command(host, mrq, mrq->stop);
else
msdc_request_done(host, mrq);
@@ -940,6 +978,8 @@ static bool msdc_data_xfer_done(struct msdc_host *host, u32 
events,
 
if (events & MSDC_INT_DATTMO)

[PATCH v2 9/9] arm64: dts: mediatek: add HS200/HS400/SDR50/SDR104 support

[Chaotian Jing]

add HS200/HS400 support for eMMC
add SDR50/SDR104 support for SD

Signed-off-by: Chaotian Jing 
---
 arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 27 ---
 1 file changed, 20 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 4be66ca..a061221 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -70,10 +70,16 @@
pinctrl-0 = <_pins_default>;
pinctrl-1 = <_pins_uhs>;
bus-width = <8>;
-   max-frequency = <5000>;
+   max-frequency = <2>;
cap-mmc-highspeed;
+   mmc-hs200-1_8v;
+   mmc-hs400-1_8v;
+   cap-mmc-hw-reset;
+   hs400-ds-delay = <0x14015>;
vmmc-supply = <_vemc_3v3_reg>;
vqmmc-supply = <_vio18_reg>;
+   assigned-clocks = < CLK_TOP_MSDC50_0_SEL>;
+   assigned-clock-parents = < CLK_TOP_MSDCPLL_D2>;
non-removable;
 };
 
@@ -83,9 +89,10 @@
pinctrl-0 = <_pins_default>;
pinctrl-1 = <_pins_uhs>;
bus-width = <4>;
-   max-frequency = <5000>;
+   max-frequency = <2>;
cap-sd-highspeed;
-   sd-uhs-sdr25;
+   sd-uhs-sdr50;
+   sd-uhs-sdr104;
cd-gpios = < 132 0>;
vmmc-supply = <_vmch_reg>;
vqmmc-supply = <_vmc_reg>;
@@ -154,13 +161,19 @@
 ,
 ;
input-enable;
-   drive-strength = ;
+   drive-strength = ;
bias-pull-up = ;
};
 
pins_clk {
pinmux = ;
-   drive-strength = ;
+   drive-strength = ;
+   bias-pull-down = ;
+   };
+
+   pins_ds {
+   pinmux = ;
+   drive-strength = ;
bias-pull-down = ;
};
 
@@ -178,13 +191,13 @@
 ,
 ;
input-enable;
-   drive-strength = ;
+   drive-strength = ;
bias-pull-up = ;
};
 
pins_clk {
pinmux = ;
-   drive-strength = ;
+   drive-strength = ;
bias-pull-down = ;
};
};
-- 
1.8.1.1.dirty

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[PATCH v2 7/9] mmc: mmc: extend the mmc_send_tuning()

[Chaotian Jing]

The mmc_execute_tuning() has already prepared the opcode,
there is no need to prepare it again at mmc_send_tuning(),
and, there is a BUG of mmc_send_tuning() to determine the opcode
by bus width, assume eMMC was running at HS200, 4bit mode,
then the mmc_send_tuning() will overwrite the opcode from CMD21
to CMD19, then got error.

in addition, extend an argument of "cmd_error" to allow getting
if there was cmd error when tune response.

Signed-off-by: Chaotian Jing 
---
 drivers/mmc/core/mmc_ops.c | 8 
 drivers/mmc/host/dw_mmc-exynos.c   | 4 ++--
 drivers/mmc/host/dw_mmc.c  | 2 +-
 drivers/mmc/host/dw_mmc.h  | 2 +-
 drivers/mmc/host/sdhci-esdhc-imx.c | 6 +++---
 drivers/mmc/host/sdhci-msm.c   | 2 +-
 drivers/mmc/host/sdhci-sirf.c  | 2 +-
 include/linux/mmc/core.h   | 2 +-
 8 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index 0e9ae1c..4305f75 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -589,7 +589,7 @@ int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 
value,
 }
 EXPORT_SYMBOL_GPL(mmc_switch);
 
-int mmc_send_tuning(struct mmc_host *host)
+int mmc_send_tuning(struct mmc_host *host, u32 opcode, int *cmd_error)
 {
struct mmc_request mrq = {NULL};
struct mmc_command cmd = {0};
@@ -599,16 +599,13 @@ int mmc_send_tuning(struct mmc_host *host)
const u8 *tuning_block_pattern;
int size, err = 0;
u8 *data_buf;
-   u32 opcode;
 
if (ios->bus_width == MMC_BUS_WIDTH_8) {
tuning_block_pattern = tuning_blk_pattern_8bit;
size = sizeof(tuning_blk_pattern_8bit);
-   opcode = MMC_SEND_TUNING_BLOCK_HS200;
} else if (ios->bus_width == MMC_BUS_WIDTH_4) {
tuning_block_pattern = tuning_blk_pattern_4bit;
size = sizeof(tuning_blk_pattern_4bit);
-   opcode = MMC_SEND_TUNING_BLOCK;
} else
return -EINVAL;
 
@@ -639,6 +636,9 @@ int mmc_send_tuning(struct mmc_host *host)
 
mmc_wait_for_req(host, );
 
+   if (cmd_error)
+   *cmd_error = cmd.error;
+
if (cmd.error) {
err = cmd.error;
goto out;
diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
index 1e75309..3a7e835 100644
--- a/drivers/mmc/host/dw_mmc-exynos.c
+++ b/drivers/mmc/host/dw_mmc-exynos.c
@@ -446,7 +446,7 @@ out:
return loc;
 }
 
-static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
+static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 {
struct dw_mci *host = slot->host;
struct dw_mci_exynos_priv_data *priv = host->priv;
@@ -461,7 +461,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot 
*slot)
mci_writel(host, TMOUT, ~0);
smpl = dw_mci_exynos_move_next_clksmpl(host);
 
-   if (!mmc_send_tuning(mmc))
+   if (!mmc_send_tuning(mmc, opcode, NULL))
candiates |= (1 << smpl);
 
} while (start_smpl != smpl);
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index fcbf552..be8441d 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1427,7 +1427,7 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, 
u32 opcode)
int err = -EINVAL;
 
if (drv_data && drv_data->execute_tuning)
-   err = drv_data->execute_tuning(slot);
+   err = drv_data->execute_tuning(slot, opcode);
return err;
 }
 
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/mmc/host/dw_mmc.h
index 8ce4674..394340f 100644
--- a/drivers/mmc/host/dw_mmc.h
+++ b/drivers/mmc/host/dw_mmc.h
@@ -281,7 +281,7 @@ struct dw_mci_drv_data {
void(*prepare_command)(struct dw_mci *host, u32 *cmdr);
void(*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
int (*parse_dt)(struct dw_mci *host);
-   int (*execute_tuning)(struct dw_mci_slot *slot);
+   int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
int (*prepare_hs400_tuning)(struct dw_mci *host,
struct mmc_ios *ios);
int (*switch_voltage)(struct mmc_host *mmc,
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c 
b/drivers/mmc/host/sdhci-esdhc-imx.c
index 886d230..1f1582f 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -759,7 +759,7 @@ static int esdhc_executing_tuning(struct sdhci_host *host, 
u32 opcode)
min = ESDHC_TUNE_CTRL_MIN;
while (min < ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, min);
-   if (!mmc_send_tuning(host->mmc))
+   if (!mmc_send_tuning(host->mmc, opcode, NULL))
break;
 

[PATCH v2 6/9] mmc: mediatek: add implement of ops->hw_reset()

[Chaotian Jing]

add implement of ops->hw_reset() for eMMC

Signed-off-by: Chaotian Jing 

---
 drivers/mmc/host/mtk-sd.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 3858163..5627644 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -64,6 +64,7 @@
 #define SDC_RESP20x48
 #define SDC_RESP30x4c
 #define SDC_BLK_NUM  0x50
+#define EMMC_IOCON   0x7c
 #define SDC_ACMD_RESP0x80
 #define MSDC_DMA_SA  0x90
 #define MSDC_DMA_CTRL0x98
@@ -1209,6 +1210,15 @@ end:
pm_runtime_put_autosuspend(host->dev);
 }
 
+static void msdc_hw_reset(struct mmc_host *mmc)
+{
+   struct msdc_host *host = mmc_priv(mmc);
+
+   sdr_set_bits(host->base + EMMC_IOCON, 1);
+   udelay(10); /* 10us is enough */
+   sdr_clr_bits(host->base + EMMC_IOCON, 1);
+}
+
 static struct mmc_host_ops mt_msdc_ops = {
.post_req = msdc_post_req,
.pre_req = msdc_pre_req,
@@ -1216,6 +1226,7 @@ static struct mmc_host_ops mt_msdc_ops = {
.set_ios = msdc_ops_set_ios,
.start_signal_voltage_switch = msdc_ops_switch_volt,
.card_busy = msdc_card_busy,
+   .hw_reset = msdc_hw_reset,
 };
 
 static int msdc_drv_probe(struct platform_device *pdev)
-- 
1.8.1.1.dirty

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Re: [PATCH 00/16] drm/exynos/hdmi: refactoring/cleanup patches

[Andrzej Hajda]

Hi Krzysztof,


On 10/12/2015 03:26 PM, Inki Dae wrote:
> Hi Andrzej,
>
> For all patches, merged excepting patch 2 which cleans up dt binding
> document.

Could you take this patch [1], it is just small binding cleanup.

[1]: https://patchwork.kernel.org/patch/7264251/

Regards
Andrzej

>
> Thanks,
> Inki Dae
>
> 2015년 09월 25일 21:48에 Andrzej Hajda 이(가) 쓴 글:
>> Hi,
>>
>> This is another set of cleanup/improvement patches for HDMI.
>>
>> The patchset is based on exynos-drm-next.
>> It was tested on Universal and Odroid U3.
>>
>> Regards
>> Andrzej
>>
>>
>> Andrzej Hajda (15):
>>drm/exynos/hdmi: remove support for deprecated compatible
>>dt-bindings: remove deprecated compatible string from exynos-hdmi
>>drm/exynos/hdmi: use mappings for registers with IP dependent address
>>drm/exynos/hdmi: move PLL stabilization check code to separate
>>  function
>>drm/exynos/hdmi: simplify HDMI-PHY power sequence
>>drm/exynos/hdmi: replace all writeb with writel
>>drm/exynos/hdmi: fix removal order
>>drm/exynos/hdmi: use optional regulator_get for hdmi-en
>>drm/exynos/hdmi: use constant size array for regulators
>>drm/exynos/hdmi: simplify clock re-parenting
>>drm/exynos/hdmi: convert to gpiod API
>>drm/exynos/hdmi: remove deprecated hdmi_resources structure
>>drm/exynos/hdmi: convert container_of macro to inline function
>>drm/exynos/hdmi: improve HDMI/ACR related code
>>drm/exynos/hdmi: remove unused field
>>
>> Tomasz Stanislawski (1):
>>drm: exynos: mixer: fix using usleep() in atomic context
>>
>>   .../devicetree/bindings/video/exynos_hdmi.txt  |   7 +-
>>   drivers/gpu/drm/exynos/exynos_hdmi.c   | 491 
>> +++--
>>   drivers/gpu/drm/exynos/exynos_mixer.c  |   2 +-
>>   drivers/gpu/drm/exynos/regs-hdmi.h |  33 +-
>>   4 files changed, 189 insertions(+), 344 deletions(-)
>>

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[PATCH v2 3/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5

[Alim Akhtar]

This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs.

Signed-off-by: Alim Akhtar 
Reviewed-by: Pankaj Dubey 
Reviewed-by: Javier Martinez Canillas 
Acked-by: Moritz Fischer 
---
 arch/arm/boot/dts/exynos5.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 110dbd4fb884..e2439e87ee4a 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -88,6 +88,20 @@
status = "disabled";
};
 
+   poweroff: syscon-poweroff {
+   compatible = "syscon-poweroff";
+   regmap = <_system_controller>;
+   offset = <0x330C>; /* PS_HOLD_CONTROL */
+   mask = <0x5200>; /* reset value */
+   };
+
+   reboot: syscon-reboot {
+   compatible = "syscon-reboot";
+   regmap = <_system_controller>;
+   offset = <0x0400>; /* SWRESET */
+   mask = <0x1>;
+   };
+
fimd: fimd@1440 {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <>;
-- 
1.7.10.4

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[PATCH v2 1/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs

[Alim Akhtar]

This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos3250 SoC.

Signed-off-by: Alim Akhtar 
Reviewed-by: Pankaj Dubey 
Reviewed-by: Javier Martinez Canillas 
Acked-by: Moritz Fischer 
---
 arch/arm/boot/dts/exynos3250.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos3250.dtsi 
b/arch/arm/boot/dts/exynos3250.dtsi
index 033def482fc3..46d469aa75a7 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -152,6 +152,20 @@
interrupt-parent = <>;
};
 
+   poweroff: syscon-poweroff {
+   compatible = "syscon-poweroff";
+   regmap = <_system_controller>;
+   offset = <0x330C>; /* PS_HOLD_CONTROL */
+   mask = <0x5200>; /* Reset value */
+   };
+
+   reboot: syscon-reboot {
+   compatible = "syscon-reboot";
+   regmap = <_system_controller>;
+   offset = <0x0400>; /* SWRESET */
+   mask = <0x1>;
+   };
+
mipi_phy: video-phy@10020710 {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
-- 
1.7.10.4

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[PATCH v2 4/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC

[Alim Akhtar]

This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5410 SoC.

Signed-off-by: Alim Akhtar 
Reviewed-by: Pankaj Dubey 
Reviewed-by: Javier Martinez Canillas 
Acked-by: Moritz Fischer 
---
 arch/arm/boot/dts/exynos5410.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5410.dtsi 
b/arch/arm/boot/dts/exynos5410.dtsi
index 731eefd23fa9..fad0779b1b6e 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -102,6 +102,20 @@
reg = <0x1004 0x5000>;
};
 
+   poweroff: syscon-poweroff {
+   compatible = "syscon-poweroff";
+   regmap = <_system_controller>;
+   offset = <0x330C>; /* PS_HOLD_CONTROL */
+   mask = <0x5200>; /* reset value */
+   };
+
+   reboot: syscon-reboot {
+   compatible = "syscon-reboot";
+   regmap = <_system_controller>;
+   offset = <0x0400>; /* SWRESET */
+   mask = <0x1>;
+   };
+
mct: mct@101C {
compatible = "samsung,exynos4210-mct";
reg = <0x101C 0xB00>;
-- 
1.7.10.4

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[PATCH v2 5/6] ARM: exynos: select POWER_RESET_SYSCON and POWER_RESET_SYSCON_POWEROFF

[Alim Akhtar]

Since we switch to use generic syscon regmap based reset/poweroff
driver for exynos SoC, lets select it from ARCH_EXYNOS instead of
enabling it from various defconfigs. This also select POWER_RESET
as SYSCON-{reset, poweroff} drivers depends on it.

Signed-off-by: Alim Akhtar 
---

Have run make for allyes, allmod, multi_v7 and exynos defconfigs
no error/warrning reported.

 arch/arm/mach-exynos/Kconfig |3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 3a10f1a8317a..d279edf9b10d 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -27,6 +27,9 @@ menuconfig ARCH_EXYNOS
select SRAM
select THERMAL
select MFD_SYSCON
+   select POWER_RESET
+   select POWER_RESET_SYSCON
+   select POWER_RESET_SYSCON_POWEROFF
help
  Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
 
-- 
1.7.10.4

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[PATCH v2 6/6] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs

[Alim Akhtar]

Now we can use the generic syscon-{reboot/poweroff} drivers,
so we don't need special handling for reboot/poweroff in
exynos pmu driver. This patch remove the same.

Note: This will break reboot/poweroff on boards with older dtbs
with a newer kernel.

Signed-off-by: Alim Akhtar 
Reviewed-by: Javier Martinez Canillas 
Acked-by: Moritz Fischer 
---
 arch/arm/mach-exynos/pmu.c |   43 ---
 1 file changed, 43 deletions(-)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index de68938ee6aa..393c04aa727e 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -14,9 +14,6 @@
 #include 
 #include 
 #include 
-#include 
-#include 
-
 
 #include "exynos-pmu.h"
 #include "regs-pmu.h"
@@ -681,23 +678,6 @@ static unsigned int const 
exynos5420_list_disable_pmu_reg[] = {
EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
 };
 
-static void exynos_power_off(void)
-{
-   unsigned int tmp;
-
-   pr_info("Power down.\n");
-   tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
-   tmp ^= (1 << 8);
-   pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
-
-   /* Wait a little so we don't give a false warning below */
-   mdelay(100);
-
-   pr_err("Power down failed, please power off system manually.\n");
-   while (1)
-   ;
-}
-
 static void exynos5420_powerdown_conf(enum sys_powerdown mode)
 {
u32 this_cluster;
@@ -875,14 +855,6 @@ static void exynos5420_pmu_init(void)
pr_info("EXYNOS5420 PMU initialized\n");
 }
 
-static int pmu_restart_notify(struct notifier_block *this,
-   unsigned long code, void *unused)
-{
-   pmu_raw_writel(0x1, EXYNOS_SWRESET);
-
-   return NOTIFY_DONE;
-}
-
 static const struct exynos_pmu_data exynos3250_pmu_data = {
.pmu_config = exynos3250_pmu_config,
.pmu_init   = exynos3250_pmu_init,
@@ -940,20 +912,11 @@ static const struct of_device_id 
exynos_pmu_of_device_ids[] = {
{ /*sentinel*/ },
 };
 
-/*
- * Exynos PMU restart notifier, handles restart functionality
- */
-static struct notifier_block pmu_restart_handler = {
-   .notifier_call = pmu_restart_notify,
-   .priority = 128,
-};
-
 static int exynos_pmu_probe(struct platform_device *pdev)
 {
const struct of_device_id *match;
struct device *dev = >dev;
struct resource *res;
-   int ret;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pmu_base_addr = devm_ioremap_resource(dev, res);
@@ -978,12 +941,6 @@ static int exynos_pmu_probe(struct platform_device *pdev)
 
platform_set_drvdata(pdev, pmu_context);
 
-   ret = register_restart_handler(_restart_handler);
-   if (ret)
-   dev_warn(dev, "can't register restart handler err=%d\n", ret);
-
-   pm_power_off = exynos_power_off;
-
dev_dbg(dev, "Exynos PMU Driver probe done\n");
return 0;
 }
-- 
1.7.10.4

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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Javier Martinez Canillas]

Hello Alim,

On 10/20/2015 11:24 AM, Alim Akhtar wrote:
> Now we have a nice way to reboot/poweroff system using a generic
> syscon regmap based drivers, this series moves exynos SoCs to
> make use of the same.
> 

I tested this series on an Exynos5800 Peach Pi and an Exynos5422 Odroid XU.
Reboot and poweroff are working correctly on both boards with these patches.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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[PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Alim Akhtar]

Now we have a nice way to reboot/poweroff system using a generic
syscon regmap based drivers, this series moves exynos SoCs to
make use of the same.

Changes since v1:
* Added a comment about the register information
* Droped defconfig changes as disscussed
* Collected various Reviewed-by, Tested-by and Acked-by tags
* Added SYSCON-{RESET, POWEROFF} to select from Kconfig

Alim Akhtar (6):
  arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
  arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
  arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
  arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
  ARM: exynos: select POWER_RESET_SYSCON and
POWER_RESET_SYSCON_POWEROFF
  ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs

 arch/arm/boot/dts/exynos3250.dtsi |   14 
 arch/arm/boot/dts/exynos4.dtsi|   14 
 arch/arm/boot/dts/exynos5.dtsi|   14 
 arch/arm/boot/dts/exynos5410.dtsi |   14 
 arch/arm/mach-exynos/Kconfig  |3 +++
 arch/arm/mach-exynos/pmu.c|   43 -
 6 files changed, 59 insertions(+), 43 deletions(-)

-- 
1.7.10.4

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[PATCH v2 2/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4

[Alim Akhtar]

This patch adds syscon-{reboot, poweroff} nodes to allow the
generic syscon-{reboot, poweroff} driver to reset/poweroff exynos4 SoC.

Signed-off-by: Alim Akhtar 
Reviewed-by: Pankaj Dubey 
Reviewed-by: Javier Martinez Canillas 
Tested-by: Tobias Jakobi 
Acked-by: Moritz Fischer 
---
 arch/arm/boot/dts/exynos4.dtsi |   14 ++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 98c0a368b777..1622f487e269 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -158,6 +158,20 @@
interrupt-parent = <>;
};
 
+   poweroff: syscon-poweroff {
+   compatible = "syscon-poweroff";
+   regmap = <_system_controller>;
+   offset = <0x330C>; /* PS_HOLD_CONTROL */
+   mask = <0x5200>; /* reset value */
+   };
+
+   reboot: syscon-reboot {
+   compatible = "syscon-reboot";
+   regmap = <_system_controller>;
+   offset = <0x0400>; /* SWRESET */
+   mask = <0x1>;
+   };
+
dsi_0: dsi@11C8 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C8 0x1>;
-- 
1.7.10.4

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Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver

[Javier Martinez Canillas]

Hello Yakir,

On 10/20/2015 04:10 AM, Yakir Yang wrote:
> Hi Javier,
> 
> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>> Hello Yakir,
>>
>> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>>> Hi all,
>>>
>>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>>> share the same IP, so a lot of parts can be re-used. I split the common
>>> code into bridge directory, then rk3288 and exynos only need to keep
>>> some platform code. Cause I can't find the exact IP name of exynos dp
>>> controller, so I decide to name dp core driver with "analogix" which I
>>> find in rk3288 eDP TRM :)
>>>
>>> But  there are still three light registers setting differents bewteen
>>> exynos and rk3288.
>>> 1. RK3288 have five special pll resigters which not indicata in exynos
>>> dp controller.
>>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>>> between rk3288 and exynos.
>>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>>> register).
>>>
>>> This series have been well tested on Rockchip platform with eDP panel
>>> on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
>>> to Javier@Samsung help me to find a way to install mainline kernel to
>>> Samsung Exynos Chromebooks, so this series also have been tested on Samsung
>>> Snow and Peach Pit Chromebooks which borrowed from my friends.
>>>
>>> Besides, This version was build on linux-next branch (tag next-20150918), 
>>> and
>>> the above test experiments also base on that tag. But I know the latest tag 
>>> is
>>> next-20151009, so i do rebase this series again on next-20151009, there were
>>> little conflicts(exynos_dp removed the suspend/resume).
>>>
>>> But after I retest this series on next-20151009, I saw kernel crashed in mmc
>>> driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
>>> module(after all I boot with USB device), and I can see eDP light up 
>>> normally
>>> in startup stage, but kernel keep crashed when it try to mount the 
>>> filesystem.
>>> I thought this isn't related to dp driver directly, so i choice not to debug
>>> more depth.
>>>
>>> That's to say if someone want to test this series, I suggest you applied 
>>> this
>>> series on tag-20150918, just need to fix some light conflicts with the 01 & 
>>> 02
>>> patches (or just email me, I can send you directly).
>>>
>>> Thanks,
>> Do you have a branch that I can use to test this series?
> 
> Thank you for your kind assistance, I have created a tree which checkout from 
> the next-20151019. Surely there were some conflicts to applied this series on 
> that tag, but things still works for me, here is the git address 
> [https://github.com/yakir-Yang/linux/tree/analogix_dp]
>

I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
working on boot. I also tested DPMS and S2R and things are still working
so for the whole series feel free to add:

Tested-by: Javier Martinez Canillas 

> Best regards,
> - Yakir
> 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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Re: [PATCH v2 5/6] ARM: exynos: select POWER_RESET_SYSCON and POWER_RESET_SYSCON_POWEROFF

[Javier Martinez Canillas]

Hello Alim,

On 10/20/2015 11:24 AM, Alim Akhtar wrote:
> Since we switch to use generic syscon regmap based reset/poweroff
> driver for exynos SoC, lets select it from ARCH_EXYNOS instead of
> enabling it from various defconfigs. This also select POWER_RESET
> as SYSCON-{reset, poweroff} drivers depends on it.
> 
> Signed-off-by: Alim Akhtar 
> ---
> 

Patch looks good to me.

Reviewed-by: Javier Martinez Canillas 
Tested-by: Javier Martinez Canillas 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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Re: [PATCH v2 6/6] ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs

[Javier Martinez Canillas]

Hello Alim,

On 10/20/2015 11:24 AM, Alim Akhtar wrote:
> Now we can use the generic syscon-{reboot/poweroff} drivers,
> so we don't need special handling for reboot/poweroff in
> exynos pmu driver. This patch remove the same.
> 
> Note: This will break reboot/poweroff on boards with older dtbs
> with a newer kernel.
> 
> Signed-off-by: Alim Akhtar 
> Reviewed-by: Javier Martinez Canillas 
> Acked-by: Moritz Fischer 
> ---
>  arch/arm/mach-exynos/pmu.c |   43 ---
>  1 file changed, 43 deletions(-)
> 

Tested-by: Javier Martinez Canillas 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Marek Szyprowski]

Hello,

On 2015-10-20 12:34, Michael Turquette wrote:

Quoting Andrzej Hajda (2015-10-20 02:22:32)

HDMI driver must re-parent respective muxes during HDMI-PHY on/off
to HDMI-PHY output clocks. To reference those clocks their
definitions should be added.

Signed-off-by: Andrzej Hajda 
---
  drivers/clk/samsung/clk-exynos5433.c   | 6 --
  include/dt-bindings/clock/exynos5433.h | 5 -
  2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c 
b/drivers/clk/samsung/clk-exynos5433.c
index 650ec13..e037406 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock disp_fixed_clks[] 
__initdata = {
 FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
 1),
 /* PHY clocks from HDMI_PHY */
-   FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 3),
-   FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 16600),
+   FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
+   NULL, CLK_IS_ROOT, 3),
+   FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, 
"phyclk_hdmiphy_pixel_clko_phy",
+   NULL, CLK_IS_ROOT, 16600),
  };
  
  static struct samsung_mux_clock disp_mux_clks[] __initdata = {

diff --git a/include/dt-bindings/clock/exynos5433.h 
b/include/dt-bindings/clock/exynos5433.h
index 5bd80d5..4f0d566 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -765,7 +765,10 @@
  #define CLK_SCLK_RGB_VCLK  109
  #define CLK_SCLK_RGB_TV_VCLK   110
  
-#define DISP_NR_CLK111

+#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
+#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
+
+#define DISP_NR_CLK113

Why break compatibility with older DTBs?


This patch just adds support for 2 more clocks to exynos 5433 clk driver,
which were previously undefined. How this break compatibility with older 
DTBs?


Best regards
--
Marek Szyprowski, PhD
Samsung R Institute Poland

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Re: [PATCH v5 6/8] drivers: soc: add support for exynos SROM driver

[Andi Shyti]

On Tue, Oct 20, 2015 at 02:45:37PM +0530, Pankaj Dubey wrote:
> This patch adds Exynos SROM controller driver which will handle
> save restore of SROM registers during S2R.
> 
> Signed-off-by: Pankaj Dubey 

...

> +config EXYNOS_SROM
> + bool
> + depends on ARM && ARCH_EXYNOS && PM

Cool, thanks! If you want you can add my review.

Andi
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Re: [PATCH v2 3/6] arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5

[Javier Martinez Canillas]

Hello Alim,

On 10/20/2015 11:24 AM, Alim Akhtar wrote:
> This patch adds syscon-{reboot, poweroff} nodes to allow the
> generic syscon-{reboot, poweroff} driver to reset/poweroff exynos5 SoCs.
> 
> Signed-off-by: Alim Akhtar 
> Reviewed-by: Pankaj Dubey 
> Reviewed-by: Javier Martinez Canillas 
> Acked-by: Moritz Fischer 
> ---
>  arch/arm/boot/dts/exynos5.dtsi |   14 ++
>  1 file changed, 14 insertions(+)
> 

Tested-by: Javier Martinez Canillas 

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America
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Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Michael Turquette]

Quoting Andrzej Hajda (2015-10-20 02:22:32)
> HDMI driver must re-parent respective muxes during HDMI-PHY on/off
> to HDMI-PHY output clocks. To reference those clocks their
> definitions should be added.
> 
> Signed-off-by: Andrzej Hajda 
> ---
>  drivers/clk/samsung/clk-exynos5433.c   | 6 --
>  include/dt-bindings/clock/exynos5433.h | 5 -
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c 
> b/drivers/clk/samsung/clk-exynos5433.c
> index 650ec13..e037406 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -2614,8 +2614,10 @@ static struct samsung_fixed_rate_clock 
> disp_fixed_clks[] __initdata = {
> FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, CLK_IS_ROOT,
> 1),
> /* PHY clocks from HDMI_PHY */
> -   FRATE(0, "phyclk_hdmiphy_tmds_clko_phy", NULL, CLK_IS_ROOT, 
> 3),
> -   FRATE(0, "phyclk_hdmiphy_pixel_clko_phy", NULL, CLK_IS_ROOT, 
> 16600),
> +   FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, 
> "phyclk_hdmiphy_tmds_clko_phy",
> +   NULL, CLK_IS_ROOT, 3),
> +   FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, 
> "phyclk_hdmiphy_pixel_clko_phy",
> +   NULL, CLK_IS_ROOT, 16600),
>  };
>  
>  static struct samsung_mux_clock disp_mux_clks[] __initdata = {
> diff --git a/include/dt-bindings/clock/exynos5433.h 
> b/include/dt-bindings/clock/exynos5433.h
> index 5bd80d5..4f0d566 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -765,7 +765,10 @@
>  #define CLK_SCLK_RGB_VCLK  109
>  #define CLK_SCLK_RGB_TV_VCLK   110
>  
> -#define DISP_NR_CLK111
> +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
> +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
> +
> +#define DISP_NR_CLK113

Why break compatibility with older DTBs?

Regards,
Mike

>  
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER  1
> -- 
> 1.9.1
> 
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Re: [PATCH 01/10] clk/samsung: exynos5433: add definitions of HDMI-PHY output clocks

[Sylwester Nawrocki]

On 20/10/15 12:34, Michael Turquette wrote:
>> diff --git a/include/dt-bindings/clock/exynos5433.h 
>> b/include/dt-bindings/clock/exynos5433.h
>> > index 5bd80d5..4f0d566 100644
>> > --- a/include/dt-bindings/clock/exynos5433.h
>> > +++ b/include/dt-bindings/clock/exynos5433.h
>> > @@ -765,7 +765,10 @@
>> >  #define CLK_SCLK_RGB_VCLK  109
>> >  #define CLK_SCLK_RGB_TV_VCLK   110
>> >  
>> > -#define DISP_NR_CLK111
>> > +#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY  111
>> > +#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY   112
>> > +
>> > +#define DISP_NR_CLK113
>
> Why break compatibility with older DTBs?

I used to be resistant to changing those _NR_CLK defines
in the past but then realized they are not part of the DT ABI.
These defines are used only in drivers and affect only size
of the provider's allocated clock array. The confusion may be
caused by the fact that the whole header is shared by the kernel
source and dts.

$ git grep -l _NR_CLK arch/arm/boot/dts drivers/clk/samsung/
drivers/clk/samsung/clk-exynos-clkout.c
drivers/clk/samsung/clk-exynos3250.c
drivers/clk/samsung/clk-exynos4.c
drivers/clk/samsung/clk-exynos4415.c
drivers/clk/samsung/clk-exynos5250.c
drivers/clk/samsung/clk-exynos5260.c
drivers/clk/samsung/clk-exynos5410.c
drivers/clk/samsung/clk-exynos5420.c
drivers/clk/samsung/clk-exynos5433.c
drivers/clk/samsung/clk-exynos5440.c
drivers/clk/samsung/clk-exynos7.c

There is no *_NR_CLK in any dts file.
New kernel will work will older DTB, the driver will just
register more clocks, which will not be dereferenced anywhere
in older dtb.

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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers

[Krzysztof Kozlowski]

2015-10-20 22:43 GMT+09:00 Markus Reichl :
> Am 19.10.2015 um 08:03 schrieb Alim Akhtar:
>> Alim Akhtar (7):
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>>   ARM: exynos_defconfig: Normalize exynos defconfig
>>   ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
>> drivers
>>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>
>>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>>  arch/arm/boot/dts/exynos4.dtsi|   14 
>>  arch/arm/boot/dts/exynos5.dtsi|   14 
>>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>>  arch/arm/configs/exynos_defconfig |   11 +-
>>  arch/arm/mach-exynos/pmu.c|   43 
>> -
>>  6 files changed, 61 insertions(+), 49 deletions(-)
>>
> Hi,
>
> I have tested this patch on my Odroid U3 and U3+ using 4.3.0-rc6 from
> Tobias' repo at https://github.com/tobiasjakobi/linux-odroid/tree/odroid-4.3.y
>
> and his debug config:
> https://raw.githubusercontent.com/tobiasjakobi/odroid-environment/master/sourcecode/system/vanilla-4.3-debug.conf
>
> halt -p works (power goes down to 0W)
>
> reboot does not work, stuck at 0.5W, right after
> "systemd-shutdown[1]: rebooting".
>
> reboot did work with 4.3.0-rc3 from above repo (without Alim's patch).

Hi Markus,

You replied to v1 so I assume you tested v1. Please test latest version: v2.

Mentioned Tobias' repo does not look like vanilla 4.3.0-rc6. Because
of that it may contain additional patches which can fix something...
or break something (like the reboot).
Please test it on latest mainline release or some recent linux-next.

In my case I tested it on linux-next on Oroid XU3 and tomorrow I will
give it a try on Trats2.

Best regards,
Krzysztof
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Re: [PATCH 0/7] Switch to generic syscon regmap based drivers

[Markus Reichl]

Am 19.10.2015 um 08:03 schrieb Alim Akhtar:
> Alim Akhtar (7):
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>   ARM: exynos_defconfig: Normalize exynos defconfig
>   ARM: exynos_defconfig: Enable generic syscon-{reboot, poweroff}
> drivers
>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
> 
>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>  arch/arm/boot/dts/exynos4.dtsi|   14 
>  arch/arm/boot/dts/exynos5.dtsi|   14 
>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>  arch/arm/configs/exynos_defconfig |   11 +-
>  arch/arm/mach-exynos/pmu.c|   43 
> -
>  6 files changed, 61 insertions(+), 49 deletions(-)
> 
Hi,

I have tested this patch on my Odroid U3 and U3+ using 4.3.0-rc6 from
Tobias' repo at https://github.com/tobiasjakobi/linux-odroid/tree/odroid-4.3.y

and his debug config:
https://raw.githubusercontent.com/tobiasjakobi/odroid-environment/master/sourcecode/system/vanilla-4.3-debug.conf

halt -p works (power goes down to 0W)

reboot does not work, stuck at 0.5W, right after
"systemd-shutdown[1]: rebooting".

reboot did work with 4.3.0-rc3 from above repo (without Alim's patch).

Thanks,
-- 
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Re: [PATCH 02/10] clk/samsung: exynos5433: add pclk_decon clock

[Krzysztof Kozlowski]

2015-10-20 18:22 GMT+09:00 Andrzej Hajda :
> This undocumented gate clock is used by DECON IP.
>
> Signed-off-by: Andrzej Hajda 
> ---
>  drivers/clk/samsung/clk-exynos5433.c   | 2 ++
>  include/dt-bindings/clock/exynos5433.h | 4 +++-
>  2 files changed, 5 insertions(+), 1 deletion(-)
>

Indeed looks undocumented... but vendor tree has it so it makes sense to me:

Reviewed-by: Krzysztof Kozlowski 

Best regards,
Krzysztof
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Re: [PATCH 04/10] dt-bindings: video: add PCLK clock entry to exynos5433-decon

[Sylwester Nawrocki]

On 20/10/15 14:24, Krzysztof Kozlowski wrote:
> W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
>> > DECON IP requires this clock to access configuration registers.
>> > 
>> > Signed-off-by: Andrzej Hajda 
>> > ---
>> >  Documentation/devicetree/bindings/video/exynos5433-decon.txt | 2 +-
>> >  1 file changed, 1 insertion(+), 1 deletion(-)
>> > 
>> > diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
>> > b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > index 377afbf..3dff78b 100644
>> > --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> > @@ -16,7 +16,7 @@ Required properties:
>> >  - clocks: must include clock specifiers corresponding to entries in the
>> >  clock-names property.
>> >  - clock-names: list of clock names sorted in the same order as the clocks
>> > - property. Must contain "aclk_decon", "aclk_smmu_decon0x",
>> > + property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
>
> I assume that old DTB wouldn't work at all, so there is no point in
> maintaining ABI compatibility?

As you know there is no single exynos5433 board dts that would use
the DECON IP block in mainline yet. I doubt anyone at this point
in mainline cares whether we require this additional clock or not.

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Re: [PATCH 09/10] dt-bindings: video: exynos5433-decon: add bindings for DECON-TV

[Krzysztof Kozlowski]

2015-10-20 21:53 GMT+09:00 Andrzej Hajda :
> On 10/20/2015 02:30 PM, Krzysztof Kozlowski wrote:
>> W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
>>> DECON-TV(Display and Enhancement Controller for TV) is a variation
>>> of DECON IP. Its main purpose is to produce video stream for HDMI IP.
>>>
>>> Signed-off-by: Andrzej Hajda 
>>> ---
>>>  .../devicetree/bindings/video/exynos5433-decon.txt  | 21 
>>> -
>>>  1 file changed, 12 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
>>> b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>>> index 3dff78b..2a88c8d 100644
>>> --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>>> +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>>> @@ -5,24 +5,27 @@ Exynos series of SoCs which transfers the image data from 
>>> a video memory
>>>  buffer to an external LCD interface.
>>>
>>>  Required properties:
>>> -- compatible: value should be "samsung,exynos5433-decon";
>>> +- compatible: value should be one of:
>>> +"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
>> Until this point it looked good.
>>
>>>  - reg: physical base address and length of the DECON registers set.
>>> -- interrupts: should contain a list of all DECON IP block interrupts in the
>>> -  order: VSYNC, LCD_SYSTEM. The interrupt specifier format
>>> -  depends on the interrupt controller used.
>>> -- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
>>> -   in the same order as they were listed in the interrupts
>>> -   property.
>>> +- interrupts: should contain interrupt specifier of VSYNC and optionally
>>> +  LCD_SYSTEM. The interrupt specifier format depends on
>>> +  the interrupt controller used.
>>> +- interrupt-names: should contain the interrupt name "vsync" and optionally
>>> +   "lcd_sys" in the same order as they were listed in
>>> +   the interrupts property.
>> The driver already did not require both interrupts, right? Only one of them?
>
> Right. More precisely it did not require since beginning.

So can you move it to the cleanup patch with change below?

Best regards,
Krzysztof
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Re: [PATCH 00/10] drm/exynos/decon5433: add support to DECON-TV

[Krzysztof Kozlowski]

2015-10-20 18:22 GMT+09:00 Andrzej Hajda :
> Hi Inki,
>
> This patchset adds support to DECON-TV in Exynos5433 SoC.
> The main patch is prepended with few preparation patches:
> - add three clocks required by HDMI pipeline,
> - small bindings update,
> - driver cleanup.
>
> The patchset is based on the latest exynos-drm-next branch.

So I am assuming this will go through Exynos drm tree. Please ping me
if you need something from my side (except dt-bindings I guess?).

Best regards,
Krzysztof
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Re: [PATCH 04/10] dt-bindings: video: add PCLK clock entry to exynos5433-decon

[Krzysztof Kozlowski]

W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
> DECON IP requires this clock to access configuration registers.
> 
> Signed-off-by: Andrzej Hajda 
> ---
>  Documentation/devicetree/bindings/video/exynos5433-decon.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
> b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> index 377afbf..3dff78b 100644
> --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> @@ -16,7 +16,7 @@ Required properties:
>  - clocks: must include clock specifiers corresponding to entries in the
> clock-names property.
>  - clock-names: list of clock names sorted in the same order as the clocks
> -property. Must contain "aclk_decon", "aclk_smmu_decon0x",
> +property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",

I assume that old DTB wouldn't work at all, so there is no point in
maintaining ABI compatibility?

Best regards,
Krzysztof

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Re: [PATCH v5 6/8] drivers: soc: add support for exynos SROM driver

[Krzysztof Kozlowski]

W dniu 20.10.2015 o 18:15, Pankaj Dubey pisze:
> This patch adds Exynos SROM controller driver which will handle
> save restore of SROM registers during S2R.
> 
> Signed-off-by: Pankaj Dubey 
> ---
>  drivers/soc/Kconfig   |   1 +
>  drivers/soc/Makefile  |   1 +
>  drivers/soc/samsung/Kconfig   |  13 +++
>  drivers/soc/samsung/Makefile  |   1 +
>  drivers/soc/samsung/exynos-srom.c | 175 
> ++
>  drivers/soc/samsung/exynos-srom.h |  51 +++
>  6 files changed, 242 insertions(+)
>  create mode 100644 drivers/soc/samsung/Kconfig
>  create mode 100644 drivers/soc/samsung/Makefile
>  create mode 100644 drivers/soc/samsung/exynos-srom.c
>  create mode 100644 drivers/soc/samsung/exynos-srom.h
> 

Looks good to me, thanks:

Reviewed-by: Krzysztof Kozlowski 

Best regards,
Krzysztof

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[PATCHv2] ARM: dts: use vmmc-supply of emmc/sd for exynos5422-odroidxu3

[Anand Moon]

Changes need for host controller to detect UHS-I highspeed cards.
Changes in VDDQ_MMC2 voltage range help scale
the required voltage to detect and load the microSD cards.

Signed-off-by: Anand Moon 
---
Changes based on 
git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git 
v4.4-next/dt-samsung branch

Changes:
Drop the ranp_delay for LDO9.

Thanks to : Krzysztof, Doug Anderson, Jaehoon Chung for helping
me out figure out the mmc core requirement.

Also drop the previous changes:
use cd-gpio method to detect sd-card.
Added UHS-I bus speed support.

[4.713553] random: nonblocking pool is initialized
[4.718423] 1453.hdmi supply hdmi-en not found, using dummy regulator
[4.726206] exynos-drm exynos-drm: bound 1440.fimd (ops 
fimd_component_ops)
[4.732555] exynos-drm exynos-drm: bound 1445.mixer (ops 
mixer_component_ops)
[4.740180] exynos-drm exynos-drm: bound 1453.hdmi (ops 
hdmi_component_ops)
[4.746936] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[4.753428] [drm] No driver support for vblank timestamp query.
[4.940794] Console: switching to colour frame buffer device 274x77
[4.995344] exynos-drm exynos-drm: fb0:  frame buffer device
[5.024573] [drm] Initialized exynos 1.0.0 20110530 on minor 0
[5.031164] exynos-dwc3 usb@1200: no suspend clk specified
[5.054571] usb 2-1: new full-speed USB device number 2 using exynos-ohci
[5.159527] dwmmc_exynos 1222.mmc: Busy; trying anyway
[5.163705] mmc_host mmc1: Timeout sending command (cmd 0x202000 arg 0x0 
status 0x0)
---
 arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi 
b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 1af5bdc..a4be3e0 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -182,9 +182,10 @@
 
ldo13_reg: LDO13 {
regulator-name = "vdd_ldo13";
-   regulator-min-microvolt = <280>;
+   regulator-min-microvolt = <180>;
regulator-max-microvolt = <280>;
regulator-always-on;
+   regulator-ramp-delay = <12000>;
};
 
ldo15_reg: LDO15 {
@@ -213,6 +214,7 @@
regulator-min-microvolt = <280>;
regulator-max-microvolt = <280>;
regulator-always-on;
+   regulator-ramp-delay = <12000>;
};
 
ldo24_reg: LDO24 {
@@ -338,6 +340,7 @@
samsung,dw-mshc-ddr-timing = <0 2>;
samsung,dw-mshc-hs400-timing = <0 2>;
samsung,read-strobe-delay = <90>;
+   vmmc-supply = <_reg>;
pinctrl-names = "default";
pinctrl-0 = <_clk _cmd _bus1 _bus4 _bus8 _cd 
_rclk>;
bus-width = <8>;
@@ -355,6 +358,8 @@
pinctrl-names = "default";
pinctrl-0 = <_clk _cmd _cd _bus1 _bus4>;
bus-width = <4>;
+   vmmc-supply = <_reg>;
+   vqmmc-supply = <_reg>;
cap-sd-highspeed;
 };
 
-- 
2.1.4

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Re: [PATCH v6 0/17] Add Analogix Core Display Port Driver

[Yakir Yang]

Hi Javier,

On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:

Hello Yakir,

On 10/20/2015 04:10 AM, Yakir Yang wrote:

Hi Javier,

On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:

Hello Yakir,

On 10/10/2015 05:35 PM, Yakir Yang wrote:

Hi all,

 The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM :)

But  there are still three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
 dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
 between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
 register).

This series have been well tested on Rockchip platform with eDP panel
on Jerry Chromebook and Display Port Monitor on RK3288 board and thanks
to Javier@Samsung help me to find a way to install mainline kernel to
Samsung Exynos Chromebooks, so this series also have been tested on Samsung
Snow and Peach Pit Chromebooks which borrowed from my friends.

Besides, This version was build on linux-next branch (tag next-20150918), and
the above test experiments also base on that tag. But I know the latest tag is
next-20151009, so i do rebase this series again on next-20151009, there were
little conflicts(exynos_dp removed the suspend/resume).

But after I retest this series on next-20151009, I saw kernel crashed in mmc
driver(dw_mci_probe failed to get regulator). So i have to disabled the MMC
module(after all I boot with USB device), and I can see eDP light up normally
in startup stage, but kernel keep crashed when it try to mount the filesystem.
I thought this isn't related to dp driver directly, so i choice not to debug
more depth.

That's to say if someone want to test this series, I suggest you applied this
series on tag-20150918, just need to fix some light conflicts with the 01 & 02
patches (or just email me, I can send you directly).

Thanks,

Do you have a branch that I can use to test this series?

Thank you for your kind assistance, I have created a tree which checkout from 
the next-20151019. Surely there were some conflicts to applied this series on 
that tag, but things still works for me, here is the git address 
[https://github.com/yakir-Yang/linux/tree/analogix_dp]


I tested your branch on an Exynos5800 Peach Pi Chromebook and display is
working on boot. I also tested DPMS and S2R and things are still working
so for the whole series feel free to add:

Tested-by: Javier Martinez Canillas 


Thanks a lot;)

- Yakir


Best regards,
- Yakir


Best regards,



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Re: [PATCH 00/16] drm/exynos/hdmi: refactoring/cleanup patches

[Krzysztof Kozlowski]

2015-10-20 18:19 GMT+09:00 Andrzej Hajda :
> Hi Krzysztof,
>
>
> On 10/12/2015 03:26 PM, Inki Dae wrote:
>> Hi Andrzej,
>>
>> For all patches, merged excepting patch 2 which cleans up dt binding
>> document.
>
> Could you take this patch [1], it is just small binding cleanup.
>
> [1]: https://patchwork.kernel.org/patch/7264251/

Sure, I can. I haven't received it directly but it still sits in my
samsung-soc archives.

Unfortunately I'm done with current v4.4 cycle, so this will go into
v4.5. Nevertheless I'll take care of it.

Best regards,
Krzysztof
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Re: [PATCH 09/10] dt-bindings: video: exynos5433-decon: add bindings for DECON-TV

[Krzysztof Kozlowski]

W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
> DECON-TV(Display and Enhancement Controller for TV) is a variation
> of DECON IP. Its main purpose is to produce video stream for HDMI IP.
> 
> Signed-off-by: Andrzej Hajda 
> ---
>  .../devicetree/bindings/video/exynos5433-decon.txt  | 21 
> -
>  1 file changed, 12 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
> b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> index 3dff78b..2a88c8d 100644
> --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
> @@ -5,24 +5,27 @@ Exynos series of SoCs which transfers the image data from a 
> video memory
>  buffer to an external LCD interface.
>  
>  Required properties:
> -- compatible: value should be "samsung,exynos5433-decon";
> +- compatible: value should be one of:
> + "samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";

Until this point it looked good.

>  - reg: physical base address and length of the DECON registers set.
> -- interrupts: should contain a list of all DECON IP block interrupts in the
> -   order: VSYNC, LCD_SYSTEM. The interrupt specifier format
> -   depends on the interrupt controller used.
> -- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
> -in the same order as they were listed in the interrupts
> -property.
> +- interrupts: should contain interrupt specifier of VSYNC and optionally
> +   LCD_SYSTEM. The interrupt specifier format depends on
> +   the interrupt controller used.
> +- interrupt-names: should contain the interrupt name "vsync" and optionally
> +"lcd_sys" in the same order as they were listed in
> +the interrupts property.

The driver already did not require both interrupts, right? Only one of them?

>  - clocks: must include clock specifiers corresponding to entries in the
> clock-names property.
>  - clock-names: list of clock names sorted in the same order as the clocks
>  property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
>  "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
>  "sclk_decon_eclk"
> +
> +Optional properties:
>  - ports: contains a port which is connected to mic node. address-cells and
> -  size-cells must 1 and 0, respectively.
> +  size-cells must be 1 and 0, respectively.
>  - port: contains an endpoint node which is connected to the endpoint in the 
> mic
> - node. The reg value muset be 0.
> + node. The reg value must be 0.
>  - i80-if-timings: specify whether the panel which is connected to decon uses
> i80 lcd interface or mipi video interface. This node contains
> no timing information as that of fimd does. Because there is
> 

This is cleanup, please split it.

Best regards,
Krzysztof
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Re: [PATCH 09/10] dt-bindings: video: exynos5433-decon: add bindings for DECON-TV

[Andrzej Hajda]

On 10/20/2015 02:30 PM, Krzysztof Kozlowski wrote:
> W dniu 20.10.2015 o 18:22, Andrzej Hajda pisze:
>> DECON-TV(Display and Enhancement Controller for TV) is a variation
>> of DECON IP. Its main purpose is to produce video stream for HDMI IP.
>>
>> Signed-off-by: Andrzej Hajda 
>> ---
>>  .../devicetree/bindings/video/exynos5433-decon.txt  | 21 
>> -
>>  1 file changed, 12 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/video/exynos5433-decon.txt 
>> b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> index 3dff78b..2a88c8d 100644
>> --- a/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> +++ b/Documentation/devicetree/bindings/video/exynos5433-decon.txt
>> @@ -5,24 +5,27 @@ Exynos series of SoCs which transfers the image data from 
>> a video memory
>>  buffer to an external LCD interface.
>>  
>>  Required properties:
>> -- compatible: value should be "samsung,exynos5433-decon";
>> +- compatible: value should be one of:
>> +"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
> Until this point it looked good.
>
>>  - reg: physical base address and length of the DECON registers set.
>> -- interrupts: should contain a list of all DECON IP block interrupts in the
>> -  order: VSYNC, LCD_SYSTEM. The interrupt specifier format
>> -  depends on the interrupt controller used.
>> -- interrupt-names: should contain the interrupt names: "vsync", "lcd_sys"
>> -   in the same order as they were listed in the interrupts
>> -   property.
>> +- interrupts: should contain interrupt specifier of VSYNC and optionally
>> +  LCD_SYSTEM. The interrupt specifier format depends on
>> +  the interrupt controller used.
>> +- interrupt-names: should contain the interrupt name "vsync" and optionally
>> +   "lcd_sys" in the same order as they were listed in
>> +   the interrupts property.
> The driver already did not require both interrupts, right? Only one of them?

Right. More precisely it did not require since beginning.

>
>>  - clocks: must include clock specifiers corresponding to entries in the
>>clock-names property.
>>  - clock-names: list of clock names sorted in the same order as the clocks
>> property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
>> "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
>> "sclk_decon_eclk"
>> +
>> +Optional properties:
>>  - ports: contains a port which is connected to mic node. address-cells and
>> - size-cells must 1 and 0, respectively.
>> + size-cells must be 1 and 0, respectively.
>>  - port: contains an endpoint node which is connected to the endpoint in the 
>> mic
>> -node. The reg value muset be 0.
>> +node. The reg value must be 0.
>>  - i80-if-timings: specify whether the panel which is connected to decon uses
>>i80 lcd interface or mipi video interface. This node contains
>>no timing information as that of fimd does. Because there is
>>
> This is cleanup, please split it.

Ok. I will split it into cleanup/fix patch, and 2nd one adding compatible.

Regards
Andrzej
>
> Best regards,
> Krzysztof
>

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RE: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Pavel Fedin]

 Hello!

> AFAIR Fedin was talking about missing functionality, not about adding
> the contribution by himself. So he might add it or he might not. I did
> not receive any commitments from him.

 I am waiting for the driver to be integrated, because i see it's constantly 
redesigned. Then i'll post my patches. By the way, they
will be useful only if pin controller driver for 5410 is accepted upstream, 
several authors have done it but i still didn't see it
in upstream.
 Pin controller is needed in order to configure multi-functional pins correctly.

> The driver should be "proper" for
> the time being (which could mean !PM dependency). If there is a need,
> then the dependency will be removed.

 I can do it later if you prefer.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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Re: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Krzysztof Kozlowski]

On 20.10.2015 15:33, Pavel Fedin wrote:
>  Hello!
> 
>> AFAIR Fedin was talking about missing functionality, not about adding
>> the contribution by himself. So he might add it or he might not. I did
>> not receive any commitments from him.
> 
>  I am waiting for the driver to be integrated, because i see it's constantly 
> redesigned. Then i'll post my patches.

That means you will extend the driver? Great! So from my point of view
it is fine.

Dear Pankaj,

With the fix of unneeded NULL assignments:

Reviewed-by: Krzysztof Kozlowski 


> By the way, they
> will be useful only if pin controller driver for 5410 is accepted upstream, 
> several authors have done it but i still didn't see it
> in upstream.
>  Pin controller is needed in order to configure multi-functional pins 
> correctly.

Are there any obstacles for upstreaming it?

Best regards,
Krzysztof

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RE: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Pavel Fedin]

 Hello!

> >  Pin controller is needed in order to configure multi-functional pins 
> > correctly.
> 
> Are there any obstacles for upstreaming it?

 I don't know. The last post on this topic is from March, 2015:
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330862.html. 
Patch 0003 has been acked-by, and nothing more since
that.
 Actually, only 0002 and 0003 of this series are needed for the pin controller. 
0001 has been accepted
(27284129522e7e2a5b89e80bd44ea3345f79c9e8).

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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Re: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Pankaj Dubey]

On Tuesday 20 October 2015 12:18 PM, Krzysztof Kozlowski wrote:

On 20.10.2015 15:33, Pavel Fedin wrote:

  Hello!


AFAIR Fedin was talking about missing functionality, not about adding
the contribution by himself. So he might add it or he might not. I did
not receive any commitments from him.


  I am waiting for the driver to be integrated, because i see it's constantly 
redesigned. Then i'll post my patches.


That means you will extend the driver? Great! So from my point of view
it is fine.

Dear Pankaj,

With the fix of unneeded NULL assignments:

Reviewed-by: Krzysztof Kozlowski 



Thanks. Will update v5 soon with suggested modification.

Thanks,
Pankaj Dubey



By the way, they
will be useful only if pin controller driver for 5410 is accepted upstream, 
several authors have done it but i still didn't see it
in upstream.
  Pin controller is needed in order to configure multi-functional pins 
correctly.


Are there any obstacles for upstreaming it?

Best regards,
Krzysztof



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Re: [PATCH v4 6/8] drivers: soc: add support for exynos SROM driver

[Andi Shyti]

Hi Pavel,

> > AFAIR Fedin was talking about missing functionality, not about adding
> > the contribution by himself. So he might add it or he might not. I did
> > not receive any commitments from him.
> 
>  I am waiting for the driver to be integrated, because i see it's constantly 
> redesigned. Then i'll post my patches. By the way, they
> will be useful only if pin controller driver for 5410 is accepted upstream, 
> several authors have done it but i still didn't see it
> in upstream.
>  Pin controller is needed in order to configure multi-functional pins 
> correctly.
> 
> > The driver should be "proper" for
> > the time being (which could mean !PM dependency). If there is a need,
> > then the dependency will be removed.
> 
>  I can do it later if you prefer.

can we add the "depends on ... && PM" now, later, once
you'll extend it, you remove it again?

Personally I'd prefer this way rather than having a driver that 
does nothing in case of !PM.

Andi
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Re: [PATCH] hwrng: exynos - Fix unbalanced PM runtime get/puts

[Herbert Xu]

On Fri, Oct 16, 2015 at 05:01:51PM +0100, Daniel Thompson wrote:
> Currently this driver calls pm_runtime_get_sync() rampantly
> but never puts anything back. This makes it impossible for the
> device to autosuspend properly; it will remain fully active
> after the first use.
> 
> Fix in the obvious way.
> 
> Signed-off-by: Daniel Thompson 
> Cc: Kukjin Kim 
> Cc: Krzysztof Kozlowski 

Patch applied.  Thanks.
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Re: [PATCH 0/4] hwrng: exynos - Add Device Tree support

[Herbert Xu]

On Mon, Oct 19, 2015 at 01:37:38PM +0900, Krzysztof Kozlowski wrote:
> Hi,
> 
> The patchset fixes known issues in Exynos hardware random number
> generator and adds Device Tree support for it.
> 
> The device was tested on Trats2 board (Exynos4412). It should work
> on other Exynos4 and Exynos5 as well... altough it seems that
> on some of Exynos542x boards the SSS module is secured.

All applied.  Thanks.
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Alim Akhtar]

Hi Markus,

On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl  wrote:
> Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
>> Now we have a nice way to reboot/poweroff system using a generic
>> syscon regmap based drivers, this series moves exynos SoCs to
>> make use of the same.
>>
>> Changes since v1:
>> * Added a comment about the register information
>> * Droped defconfig changes as disscussed
>> * Collected various Reviewed-by, Tested-by and Acked-by tags
>> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
>>
>> Alim Akhtar (6):
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>>   ARM: exynos: select POWER_RESET_SYSCON and
>> POWER_RESET_SYSCON_POWEROFF
>>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>
>>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>>  arch/arm/boot/dts/exynos4.dtsi|   14 
>>  arch/arm/boot/dts/exynos5.dtsi|   14 
>>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>>  arch/arm/mach-exynos/Kconfig  |3 +++
>>  arch/arm/mach-exynos/pmu.c|   43 
>> -
>>  6 files changed, 59 insertions(+), 43 deletions(-)
>>
>
> Hi Alim,
>
> I have installed your patch set above with git am on top of
> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
> with make exynos_defconfig on Odroid U3.
>
which exynos soc Odroid U3 uses?

> "halt -p" worked (power 0.0W).
> "reboot" got stuck at 0.5W.
>
reboot stuck mean system does not reboot any more?
As far as I can see there in __no__ functional changes that my patch introduce.
So ideally it should have work. My patches are based on the top on
vanilla v4.3-rc5.
(25cb62b Linux 4.3-rc5), can you check at this commit?

Will check with the commit mentioned by you tomorrow.

>
> Without your patch set reboot worked.
>
>
> Thanks,
> --
> Markus Reichl
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
> in
> the body of a message to majord...@vger.kernel.org
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-- 
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Alim
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Markus Reichl]

Am Dienstag, 20. Oktober 2015, 21:22:05 schrieb Alim Akhtar:
> On Tue, Oct 20, 2015 at 9:17 PM, Alim Akhtar  wrote:
> > Hi Markus,
> >
> > On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl  
> > wrote:
> >> Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
> >>> Now we have a nice way to reboot/poweroff system using a generic
> >>> syscon regmap based drivers, this series moves exynos SoCs to
> >>> make use of the same.
> >>>
> >>> Changes since v1:
> >>> * Added a comment about the register information
> >>> * Droped defconfig changes as disscussed
> >>> * Collected various Reviewed-by, Tested-by and Acked-by tags
> >>> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
> >>>
> >>> Alim Akhtar (6):
> >>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
> >>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
> >>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
> >>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
> >>>   ARM: exynos: select POWER_RESET_SYSCON and
> >>> POWER_RESET_SYSCON_POWEROFF
> >>>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
> >>>
> >>>  arch/arm/boot/dts/exynos3250.dtsi |   14 
> >>>  arch/arm/boot/dts/exynos4.dtsi|   14 
> >>>  arch/arm/boot/dts/exynos5.dtsi|   14 
> >>>  arch/arm/boot/dts/exynos5410.dtsi |   14 
> >>>  arch/arm/mach-exynos/Kconfig  |3 +++
> >>>  arch/arm/mach-exynos/pmu.c|   43 
> >>> -
> >>>  6 files changed, 59 insertions(+), 43 deletions(-)
> >>>
> >>
> >> Hi Alim,
> >>
> >> I have installed your patch set above with git am on top of
> >> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
> >> with make exynos_defconfig on Odroid U3.
> >>
> > which exynos soc Odroid U3 uses?
> >
> OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does
> include exynos4.dtsi,
> so these should have worked.
> 
> >> "halt -p" worked (power 0.0W).
> >> "reboot" got stuck at 0.5W.
> >>
> > reboot stuck mean system does not reboot any more?

It freezes when going for reboot.
Have to power off/on to boot again.

Btw I use an mmc, not an sd-card.
No other HW connected, just LAN-cable.
Bootloader is u-boot v2015.10.

> > As far as I can see there in __no__ functional changes that my patch 
> > introduce.
> > So ideally it should have work. My patches are based on the top on
> > vanilla v4.3-rc5.
> > (25cb62b Linux 4.3-rc5), can you check at this commit?

Will try tomorrow.

> >
> > Will check with the commit mentioned by you tomorrow.
> >
> >>
> >> Without your patch set reboot worked.
> >>
> >>
> >> Thanks,
> >> --
> >> Markus Reichl
> >> --
> >> To unsubscribe from this list: send the line "unsubscribe 
> >> linux-samsung-soc" in
> >> the body of a message to majord...@vger.kernel.org
> >> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> >
> >
> >
> > --
> > Regards,
> > Alim
> 
> 
> 
> 
Thanks,
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Alim Akhtar]

On Tue, Oct 20, 2015 at 9:17 PM, Alim Akhtar  wrote:
> Hi Markus,
>
> On Tue, Oct 20, 2015 at 8:29 PM, Markus Reichl  wrote:
>> Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
>>> Now we have a nice way to reboot/poweroff system using a generic
>>> syscon regmap based drivers, this series moves exynos SoCs to
>>> make use of the same.
>>>
>>> Changes since v1:
>>> * Added a comment about the register information
>>> * Droped defconfig changes as disscussed
>>> * Collected various Reviewed-by, Tested-by and Acked-by tags
>>> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
>>>
>>> Alim Akhtar (6):
>>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>>>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>>>   ARM: exynos: select POWER_RESET_SYSCON and
>>> POWER_RESET_SYSCON_POWEROFF
>>>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
>>>
>>>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>>>  arch/arm/boot/dts/exynos4.dtsi|   14 
>>>  arch/arm/boot/dts/exynos5.dtsi|   14 
>>>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>>>  arch/arm/mach-exynos/Kconfig  |3 +++
>>>  arch/arm/mach-exynos/pmu.c|   43 
>>> -
>>>  6 files changed, 59 insertions(+), 43 deletions(-)
>>>
>>
>> Hi Alim,
>>
>> I have installed your patch set above with git am on top of
>> 4.3.0-rc6-00108-gce1fad2 torvalds/linux of today
>> with make exynos_defconfig on Odroid U3.
>>
> which exynos soc Odroid U3 uses?
>
OK, I can see its uses exynos4412 and exynos4412-odroidu3.dts does
include exynos4.dtsi,
so these should have worked.

>> "halt -p" worked (power 0.0W).
>> "reboot" got stuck at 0.5W.
>>
> reboot stuck mean system does not reboot any more?
> As far as I can see there in __no__ functional changes that my patch 
> introduce.
> So ideally it should have work. My patches are based on the top on
> vanilla v4.3-rc5.
> (25cb62b Linux 4.3-rc5), can you check at this commit?
>
> Will check with the commit mentioned by you tomorrow.
>
>>
>> Without your patch set reboot worked.
>>
>>
>> Thanks,
>> --
>> Markus Reichl
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" 
>> in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Regards,
> Alim



-- 
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Re: [PATCH v2 0/9] Add tune support of Mediatek MMC driver

[Ulf Hansson]

On 20 October 2015 at 11:13, Chaotian Jing  wrote:
> Change in v2:
> Drop the 400mhz and use assigned-clock-parents to instead
> Split the original tune patch to several independent patches
> Re-write the mmc_send_tuning()
> Fix GPD checksum error
> Move the HS400 setting to ops->prepare_hs400_tuning()
> Modify SD driving settings
>
> Change in v1:
> Add DT bindings for eMMC hardware reset
> Add pinctrl of data strobe pin for HS400 mode
> Modify eMMC driving settings
> Add 400mhz source clock for HS400 mode
> Add eMMC HS200/HS400 mode support
> Add SD SDR50/SDR104 mode support
> Add implement of tune function with CMD19/CMD21
>
> Chaotian Jing (9):
>   mmc: core: Add DT bindings for eMMC hardware reset support
>   mmc: dt-bindings: update Mediatek MMC bindings
>   mmc: mediatek: make cmd_ints_mask to const
>   mmc: mediatek: change the argument "ddr" to "timing"
>   mmc: mediatek: fix got GPD checksum error interrupt when data transfer
>   mmc: mediatek: add implement of ops->hw_reset()
>   mmc: mmc: extend the mmc_send_tuning()
>   mmc: mediatek: add HS400 support
>   arm64: dts: mediatek: add HS200/HS400/SDR50/SDR104 support
>
>  Documentation/devicetree/bindings/mmc/mmc.txt|   1 +
>  Documentation/devicetree/bindings/mmc/mtk-sd.txt |  11 +-
>  arch/arm64/boot/dts/mediatek/mt8173-evb.dts  |  27 ++-
>  drivers/mmc/core/host.c  |   2 +
>  drivers/mmc/core/mmc_ops.c   |   8 +-
>  drivers/mmc/host/dw_mmc-exynos.c |   4 +-
>  drivers/mmc/host/dw_mmc.c|   2 +-
>  drivers/mmc/host/dw_mmc.h|   2 +-
>  drivers/mmc/host/mtk-sd.c| 296 
> ---
>  drivers/mmc/host/sdhci-esdhc-imx.c   |   6 +-
>  drivers/mmc/host/sdhci-msm.c |   2 +-
>  drivers/mmc/host/sdhci-sirf.c|   2 +-
>  include/linux/mmc/core.h |   2 +-
>  13 files changed, 314 insertions(+), 51 deletions(-)
>
> --
> 1.8.1.1.dirty

I have reviewed the patches, I think they overall looks good! Some
comments though.

You need to split patch 9, the DT parts enabling hw reset shall go in
separately.

Regarding the hw-reset changes in patch1, patch6 and patch9, I believe
I requested you to separate the HW reset changes from $subject
patchset as they are unrelated, please do this.

Running checkpatch, it gave me warnings and errors for patch 8.
Patch7 didn't apply to my next branch.

Kind regards
Uffe
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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Markus Reichl]

Am 20.10.2015 um 11:24 schrieb Alim Akhtar:
> Now we have a nice way to reboot/poweroff system using a generic
> syscon regmap based drivers, this series moves exynos SoCs to
> make use of the same.
> 
> Changes since v1:
> * Added a comment about the register information
> * Droped defconfig changes as disscussed
> * Collected various Reviewed-by, Tested-by and Acked-by tags
> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
> 
> Alim Akhtar (6):
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>   ARM: exynos: select POWER_RESET_SYSCON and
> POWER_RESET_SYSCON_POWEROFF
>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
> 
>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>  arch/arm/boot/dts/exynos4.dtsi|   14 
>  arch/arm/boot/dts/exynos5.dtsi|   14 
>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>  arch/arm/mach-exynos/Kconfig  |3 +++
>  arch/arm/mach-exynos/pmu.c|   43 
> -
>  6 files changed, 59 insertions(+), 43 deletions(-)
> 

Hi Alim,

I have installed your patch set above with git am on top of 
4.3.0-rc6-00108-gce1fad2 torvalds/linux of today 
with make exynos_defconfig on Odroid U3.

"halt -p" worked (power 0.0W).
"reboot" got stuck at 0.5W.


Without your patch set reboot worked.  


Thanks,
-- 
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[PATCH 1/2] dt-bindings: Consolidate Exynos SoC bindings under Samsung directory

[Krzysztof Kozlowski]

Exynos SoC Device Tree bindings are spread over arm/exynos/ and
arm/samsung/ directories. There is no need for that separation and it
actually confuses. Put everything under arm/samsung/.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kukjin Kim 
---
 .../devicetree/bindings/arm/{exynos => samsung}/power_domain.txt  | 0
 Documentation/devicetree/bindings/arm/{ => samsung}/samsung-boards.txt| 0
 Documentation/devicetree/bindings/arm/{exynos => samsung}/smp-sysram.txt  | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/arm/{exynos => 
samsung}/power_domain.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => samsung}/samsung-boards.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{exynos => 
samsung}/smp-sysram.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/samsung/power_domain.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/exynos/power_domain.txt
rename to Documentation/devicetree/bindings/arm/samsung/power_domain.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt 
b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/samsung-boards.txt
rename to Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
diff --git a/Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt 
b/Documentation/devicetree/bindings/arm/samsung/smp-sysram.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt
rename to Documentation/devicetree/bindings/arm/samsung/smp-sysram.txt
-- 
1.9.1

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[PATCH 2/2] dt-bindings: EXYNOS: Document compatibles from other vendors

[Krzysztof Kozlowski]

Document compatibles used on other Exynos-based boards (non-Samsung):
FriendlyARM, Google, Hardkernel and Insignal.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kukjin Kim 
Cc: Javier Martinez Canillas 
Cc: Hakjoo Kim 
---
 .../bindings/arm/samsung/samsung-boards.txt| 44 +-
 1 file changed, 43 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt 
b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index 43589d2466a7..da078702ae73 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -16,7 +16,49 @@ Required root node properties:
- "samsung,sd5v1"   - for Exynos5440-based Samsung board.
- "samsung,ssdk5440"- for Exynos5440-based Samsung board.
 
-Optional:
+* Other companies Exynos SoC based
+  * FriendlyARM
+- "friendlyarm,tiny4412"  - for Exynos4412-based FriendlyARM
+TINY4412 board.
+
+  * Google
+- "google,pi" - for Exynos5800-based Google Peach Pi
+Rev 10+ board,
+  also: "google,pi-rev16", "google,pi-rev15", "google,pi-rev14",
+   "google,pi-rev13", "google,pi-rev12", "google,pi-rev11",
+"google,pi-rev10", "google,peach".
+
+- "google,pit"- for Exynos5420-based Google Peach Pit
+Rev 6+ (Exynos5420),
+  also: "google,pit-rev16", "google,pit-rev15", "google,pit-rev14",
+"google,pit-rev13", "google,pit-rev12", "google,pit-rev11",
+"google,pit-rev10", "google,pit-rev9", "google,pit-rev8",
+"google,pit-rev7", "google,pit-rev6", "google,peach".
+
+- "google,snow-rev4"  - for Exynos5250-based Google Snow board,
+  also: "google,snow"
+- "google,snow-rev5"  - for Exynos5250-based Google Snow
+Rev 5+ board.
+- "google,spring" - for Exynos5250-based Google Spring board.
+
+  * Hardkernel
+- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
+- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
+- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
+- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
+- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
+ Odroid XU3 Lite board.
+- "hardkernel,odroid-xu4" - for Exynos5422-based Hardkernel Odroid XU4.
+
+  * Insignal
+- "insignal,arndale"  - for Exynos5250-based Insignal Arndale 
board.
+- "insignal,arndale-octa" - for Exynos5420-based Insignal Arndale
+Octa board.
+- "insignal,origen"   - for Exynos4210-based Insignal Origen board.
+- "insignal,origen4412- for Exynos4412-based Insignal Origen board.
+
+
+Optional nodes:
 - firmware node, specifying presence and type of secure firmware:
 - compatible: only "samsung,secure-firmware" is currently supported
 - reg: address of non-secure SYSRAM used for communication with 
firmware
-- 
1.9.1

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Re: [PATCH v5 0/8] Add support for Exynos SROM Controller driver

[Krzysztof Kozlowski]

On 20.10.2015 18:15, Pankaj Dubey wrote:
> This patch set adds support for Exynos SROM controller DT based driver.
> Currently SROM register sets are used only during S2R, so driver
> basically added for taking care of S2R. It will help us in removing
> static mapping from exynos.c and other extra code handline during S2R.
> 
> This patch set also updated exynos4 and exynos5 dtsi files for with device
> node for srom, and added binding documentation for the same.
> 
> First two patches are some minor cleanup in mach-exynos.
> 
> Patchset v1 was posted here[1]
> [1]: https://lkml.org/lkml/2015/4/29/98
> Patchset v2 was posted here[2]
> [2]: https://lkml.org/lkml/2015/8/24/125
> Patchset v3 was posted here[3]
> [3]: https://lkml.org/lkml/2015/10/13/392
> Patchset v3 was posted here[4]
> [4]: https://lkml.org/lkml/2015/10/19/278
> 
> This patchset, I have tested on Peach-Pi (Exynos5880) based chromebook for 
> boot
> and S2R functionality.
> 

Entire patchset tested on Trats2 (Exynos4412) board. Unless Kukjin picks
it also, I plan to take it for v4.5.

Best regards,
Krzysztof

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Re: [PATCH v2 0/6] Switch to generic syscon regmap based drivers

[Krzysztof Kozlowski]

On 20.10.2015 18:24, Alim Akhtar wrote:
> Now we have a nice way to reboot/poweroff system using a generic
> syscon regmap based drivers, this series moves exynos SoCs to
> make use of the same.
> 
> Changes since v1:
> * Added a comment about the register information
> * Droped defconfig changes as disscussed
> * Collected various Reviewed-by, Tested-by and Acked-by tags
> * Added SYSCON-{RESET, POWEROFF} to select from Kconfig
> 
> Alim Akhtar (6):
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos3250 SoCs
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos4
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5
>   arm: dts: Add syscon-{reboot, poweroff} nodes for exynos5410 SoC
>   ARM: exynos: select POWER_RESET_SYSCON and
> POWER_RESET_SYSCON_POWEROFF
>   ARM: EXYNOS: Remove code for restart and poweroff for exynos SoCs
> 
>  arch/arm/boot/dts/exynos3250.dtsi |   14 
>  arch/arm/boot/dts/exynos4.dtsi|   14 
>  arch/arm/boot/dts/exynos5.dtsi|   14 
>  arch/arm/boot/dts/exynos5410.dtsi |   14 
>  arch/arm/mach-exynos/Kconfig  |3 +++
>  arch/arm/mach-exynos/pmu.c|   43 
> -
>  6 files changed, 59 insertions(+), 43 deletions(-)
> 

Entire patchset tested on Odroid XU3-Lite and Trats2 boards:

Tested-by: Krzysztof Kozlowski 

Best regards,
Krzysztof

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Re: [PATCH v2 5/6] ARM: exynos: select POWER_RESET_SYSCON and POWER_RESET_SYSCON_POWEROFF

[Krzysztof Kozlowski]

On 20.10.2015 18:24, Alim Akhtar wrote:
> Since we switch to use generic syscon regmap based reset/poweroff
> driver for exynos SoC, lets select it from ARCH_EXYNOS instead of
> enabling it from various defconfigs. This also select POWER_RESET
> as SYSCON-{reset, poweroff} drivers depends on it.
> 
> Signed-off-by: Alim Akhtar 
> ---
> 
> Have run make for allyes, allmod, multi_v7 and exynos defconfigs
> no error/warrning reported.
> 
>  arch/arm/mach-exynos/Kconfig |3 +++
>  1 file changed, 3 insertions(+)

Thanks for update:

Reviewed-by: Krzysztof Kozlowski 

Best regards,
Krzysztof

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[PATCH] MAINTAINERS: ARM: EXYNOS: Add documentation and dt-bindings

[Krzysztof Kozlowski]

Extend the Samsung Exynos maintainer entry to match SoC documentation
and SoC dt-bindings directories. Without that some files, like
bindings/arm/samsung/pmu.txt, are not matched by existing patterns.

This also may serve as a hint where new documentation and bindings (not
matching specific subsystem) should be put.

Signed-off-by: Krzysztof Kozlowski 
Cc: Kukjin Kim 
---
 MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b556aad90930..cad7b6b628b2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1459,6 +1459,8 @@ F:drivers/*/*s3c2410*
 F: drivers/*/*/*s3c2410*
 F: drivers/spi/spi-s3c*
 F: sound/soc/samsung/*
+F: Documentation/arm/Samsung/
+F: Documentation/devicetree/bindings/arm/samsung/
 N: exynos
 
 ARM/SAMSUNG MOBILE MACHINE SUPPORT
-- 
1.9.1

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Re: [RFC PATCH] ARM: exynos_defconfig: Increase CONFIG_BLK_DEV_RAM_SIZE to 64K

[Alim Akhtar]

Hi Arnd

On 10/19/2015 06:52 PM, Arnd Bergmann wrote:

On Monday 19 October 2015 16:18:35 Alim Akhtar wrote:

Spam Status: CRM114
CONFIG_BLK_DEV_RAM_SIZE is currently set to 8K, which is a bit on the
smaller side, lets bump it up to 64K so that a bigger RAM_DISK can
be used with defconfig.

Signed-off-by: Alim Akhtar 
---
Every time I build exynos_defconfig, I need to manually change RAM_SIZE
to match my ramdisk image size. I am not sure what is the best ramdisk size
might be, but bumping it to 64K might be a reasonable one.


Is there still a reason to use ramdisks these days? If 8MB is not
enough to have a useful initrd, that might mean that everyone else
uses initramfs and you should just do the same thing?

There is not specific reason to still use ramdisks, but I feel till we 
remove this config, lets modify it to be used by few like me.

I am ok with either way.
Thanks

Then we can also remove this option here.

Arnd


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