Re: [PATCH 2/2] clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)
On Wed, Aug 12, 2015 at 4:12 PM, Stephen Boyd wrote: > Use the provider based method to get a clock's name so that we > can get rid of the clk member in struct clk_hw one day. Mostly > converted with the following coccinelle script. > > @@ > struct clk_hw *E; > @@ > > -__clk_get_name(E->clk) > +clk_hw_get_name(E) > > Cc: Heiko Stuebner > Cc: Sylwester Nawrocki > Cc: Tomasz Figa > Cc: Peter De Schrijver > Cc: Prashant Gaikwad > Cc: Stephen Warren > Cc: Thierry Reding > Cc: Alexandre Courbot > Cc: Tero Kristo > Cc: Ulf Hansson > Cc: Sebastian Hesselbarth > Cc: Andrew Bresticker > Cc: Ezequiel Garcia > Cc: Ralf Baechle > Cc: Kevin Cernekee > Cc: Geert Uytterhoeven > Cc: Ulrich Hecht > Cc: linux-arm-ker...@lists.infradead.org > Cc: linux-rockc...@lists.infradead.org > Cc: linux-samsung-soc@vger.kernel.org > Cc: linux-te...@vger.kernel.org > Cc: linux-o...@vger.kernel.org > Signed-off-by: Stephen Boyd > drivers/clk/pistachio/clk-pll.c | 4 ++-- For Pistachio, Acked-by: Andrew Bresticker -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: nv u-boot for spring (was: building nv-uboot for nyan-big.)
Stephan, Andreas, On Mon, Nov 3, 2014 at 5:05 AM, Andreas Färber wrote: > Dear Stephan, > > Am 03.11.2014 um 11:42 schrieb S.J.R. van Schaik: >> [...] I have done some research to figure out how to build >> a working nv u-boot binary, and working instructions can be found on the >> linux-exynos wiki [1]. However, when I tried to apply them to the snow >> and spring boards, by selecting a different branch and a different >> u-boot configuration, those attempts were of no success. [...] > [...] >> The u-boot.bin binary seems to build fine. However, the problem is similar >> to the snow and spring boards, where I can't seem to build the DTB-files. > > You didn't ask me. ;) My Spring branch with patches is located here: > https://github.com/afaerber/u-boot/commits/spring > > For my convenience I changed the sources to default to the right device > tree, and I manually inlined exynos-periph-id.dtsi. > > If you need further info on my build steps, I can look them up in my > scripts (on another machine) - I mainly derived them from the official > instructions for Snow on the Chromium Wiki. I'm pretty sure I did not > mess with the EC firmware at all. > > But whatever workarounds exist, the Chromium folks should really be > working on upstreaming U-Boot support for all those Chromebooks, that > usually sanitizes the build process as a side-effect, resulting in less > user questions. :) For Snow I believe that to be done. Unlike the Exynos Chromebooks, the Tegra Chromebooks do not use U-Boot as their firmware/bootloader - they instead use Coreboot (firmware) and Depthcharge (bootloader) like the x86 Chromebooks. You can, however, update your firmware with U-Boot as a legacy mode (Ctrl+L at the dev screen) payload - I've added Julius who can provide more detail about this process. Note that we do not maintain U-Boot support for these devices, but they are very similar to Venice2 which is well-supported upstream. I can't guarantee that a Venice2 U-Boot payload will "just work" though. -Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 5/7] mfd: cros_ec: wait for completion of commands that return IN_PROGRESS
On Mon, Sep 8, 2014 at 4:39 AM, Javier Martinez Canillas wrote: > Hello Lee, > > On 09/04/2014 10:34 AM, Lee Jones wrote: >> On Mon, 25 Aug 2014, Javier Martinez Canillas wrote: >>> From: Andrew Bresticker >>> >>> When an EC command returns EC_RES_IN_PROGRESS, we need to query >>> the state of the EC until it indicates that it is no longer busy. >>> Do this in cros_ec_cmd_xfer() under the EC's mutex so that other >>> commands (e.g. keyboard, I2C passtru) aren't issued to the EC while >>> it is working on the in-progress command. >>> >>> Signed-off-by: Andrew Bresticker >>> Reviewed-by: Simon Glass >>> Signed-off-by: Javier Martinez Canillas >>> --- >>> >>> Changes since v1: >>> - The *xfer() calls don't modify the passed cros_ec_command so there is >>>no need to populate it inside the for loop. Suggested by Lee Jones. >>> --- >>> drivers/mfd/cros_ec.c | 34 +- >>> 1 file changed, 33 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/mfd/cros_ec.c b/drivers/mfd/cros_ec.c >>> index c53804a..cd0c93c 100644 >>> --- a/drivers/mfd/cros_ec.c >>> +++ b/drivers/mfd/cros_ec.c >>> @@ -23,6 +23,10 @@ >>> #include >>> #include >>> #include >>> +#include >>> + >>> +#define EC_COMMAND_RETRIES 50 >>> +#define EC_RETRY_DELAY_MS 10 >> >> Where did these values come from? >> > > These patches were taken from the ChromeOS 3.8 kernel so I don't really know > why these values were chosen. I'll let Andrew or one of the ChromiumOS folks > to answer this question. These are the values flashrom used when retrying commands. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start
> [1] While waiting for the forth-coming patch from Andrew to enable the > CCI port for the boot cluster), I do this from u-boot before starting > the kernel (based on earlier email from Doug): > > mw.l 10d25000 3 # Enable CCI from U-Boot >From the other thread, it sounds like Nicolas wants enabling of the boot cluster's CCI port to be done unconditionally for all MCPM platforms. Nicolas, are you preparing a patch for this or should I? The only issue I see with making the MCPM loopback generic is that although all current mainline MCPM platforms have the same cache flush procedure, a future platform could be different. Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: EXYNOS: mcpm: Don't rely on firmware's secondary_cpu_start
>> If this is all that is needed to solve the problem being discussed in >> the other thread I have absolutely no issue with such a workaround going >> into mainline. > > This plus the CCI fix that Andrew is planning to post. Right - we'll need a patch to enable the CCI port for the cluster we booted on at boot and resume time since the first CPU up won't enter through exynos_pm_power_up_setup(). I'll try to post something later today or Monday. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: exynos5420: Add 5800 specific clocks
Hi Arun,
On Fri, May 2, 2014 at 6:03 AM, Arun Kumar K wrote:
> From: Alim Akhtar
>
> Exynos5800 clock structure is mostly similar to 5420 with only
> a small delta changes. So the 5420 clock file is re-used for
> 5800 also. The common clocks for both are seggreagated and few
> clocks which are different for both are separately initialized.
As Tomasz mentioned, this will certainly conflict with Shaik and
Rahul's 5420 clock cleanup series. That series adds/fixes the MAU,
WCORE, and ISP blocks which also have differences from 5420 to 5800.
>
> Signed-off-by: Alim Akhtar
> Signed-off-by: Arun Kumar K
> ---
> .../devicetree/bindings/clock/exynos5420-clock.txt |3 +-
> drivers/clk/samsung/clk-exynos5420.c | 192
> +++-
> include/dt-bindings/clock/exynos5420.h |1 +
> 3 files changed, 150 insertions(+), 46 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> index ca88c97..d54f42c 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> @@ -1,12 +1,13 @@
> * Samsung Exynos5420 Clock Controller
>
> The Exynos5420 clock controller generates and supplies clock to various
> -controllers within the Exynos5420 SoC.
> +controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
>
> Required Properties:
>
> - compatible: should be one of the following.
>- "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
> + - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
>
> - reg: physical base address of the controller and length of memory mapped
>region.
> diff --git a/drivers/clk/samsung/clk-exynos5420.c
> b/drivers/clk/samsung/clk-exynos5420.c
> index 60b2681..0543cb7 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -51,6 +51,7 @@
> #define SRC_TOP5 0x10214
> #define SRC_TOP6 0x10218
> #define SRC_TOP7 0x1021c
> +#define SRC_TOP9 0x10224 /* 5800 specific */
> #define SRC_DISP10 0x1022c
> #define SRC_MAU0x10240
> #define SRC_FSYS 0x10244
> @@ -59,6 +60,7 @@
> #define SRC_TOP10 0x10280
> #define SRC_TOP11 0x10284
> #define SRC_TOP12 0x10288
> +#define SRC_TOP13 0x1028c /* 5800 specific */
> #defineSRC_MASK_DISP10 0x1032c
> #define SRC_MASK_FSYS 0x10340
> #define SRC_MASK_PERIC00x10350
> @@ -66,6 +68,7 @@
> #define DIV_TOP0 0x10500
> #define DIV_TOP1 0x10504
> #define DIV_TOP2 0x10508
> +#define DIV_TOP9 0x10524 /* 5800 specific */
> #define DIV_DISP10 0x1052c
> #define DIV_MAU0x10544
> #define DIV_FSYS0 0x10548
> @@ -102,8 +105,14 @@
> #define SRC_KFC0x28200
> #define DIV_KFC0 0x28500
>
> +/* Exynos5x SoC type */
> +enum exynos5x_soc {
> + EXYNOS5420,
> + EXYNOS5800,
> +};
> +
> /* list of PLLs */
> -enum exynos5420_plls {
> +enum exynos5x_plls {
> apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
> bpll, kpll,
> nr_plls /* number of PLLs */
> @@ -112,13 +121,13 @@ enum exynos5420_plls {
> static void __iomem *reg_base;
>
> #ifdef CONFIG_PM_SLEEP
> -static struct samsung_clk_reg_dump *exynos5420_save;
> +static struct samsung_clk_reg_dump *exynos5x_save;
>
> /*
> * list of controller registers to be saved and restored during a
> * suspend/resume cycle.
> */
> -static unsigned long exynos5420_clk_regs[] __initdata = {
> +static unsigned long exynos5x_clk_regs[] __initdata = {
> SRC_CPU,
> DIV_CPU0,
> DIV_CPU1,
> @@ -182,16 +191,16 @@ static unsigned long exynos5420_clk_regs[] __initdata =
> {
>
> static int exynos5420_clk_suspend(void)
> {
> - samsung_clk_save(reg_base, exynos5420_save,
> - ARRAY_SIZE(exynos5420_clk_regs));
> + samsung_clk_save(reg_base, exynos5x_save,
> + ARRAY_SIZE(exynos5x_clk_regs));
>
> return 0;
> }
>
> static void exynos5420_clk_resume(void)
> {
> - samsung_clk_restore(reg_base, exynos5420_save,
> - ARRAY_SIZE(exynos5420_clk_regs));
> + samsung_clk_restore(reg_base, exynos5x_save,
> + ARRAY_SIZE(exynos5x_clk_regs));
> }
>
> static struct syscore_ops exynos5420_clk_syscore_ops = {
> @@ -201,9 +210,9 @@ static struct syscore_ops exynos5420_clk_syscore_ops = {
>
> static void exynos5420_clk_sleep_init(void)
> {
> - exynos5420_save = samsung_clk_alloc_reg_dump(exynos5420_clk_regs,
> - ARRAY_SIZE(ex
Re: [PATCH V4 1/6] clk: exynos-audss: convert to platform device
Hi Mike and Kukjin,
Any decisions regarding this patchset? I believe all comments have
been addressed.
Thanks,
Andrew
On Wed, Sep 25, 2013 at 2:12 PM, Andrew Bresticker
wrote:
> The Exynos AudioSS clock controller will later be modified to allow
> input clocks to be specified via device-tree in order to support
> multiple Exynos SoCs. This will introduce a dependency on the core
> SoC clock controller being initialized first so that the AudioSS driver
> can look up its input clocks, but the order in which clock providers
> are probed in of_clk_init() is not guaranteed. Since deferred probing
> is not supported in of_clk_init() and the AudioSS block is not the core
> controller, we can initialize it later as a platform device.
>
> Signed-off-by: Andrew Bresticker
> Acked-by: Tomasz Figa
> Reviewed-by: Sylwester Nawrocki
> ---
> Changes since v3:
> - __init -> __exit for module exit function
> - fixed nits from Sylwester
> Changes since v2:
> - add error handling to probe callback
> - fixed ordering of of_clk_{add,del}_provider
> - fixed nits from Tomasz and Sylwester
> Changes since v1:
> - add clk_unregister() calls to remove callback
> - fixed minor nits from Tomasz
> ---
> drivers/clk/samsung/clk-exynos-audss.c | 104
> -
> 1 file changed, 88 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c
> b/drivers/clk/samsung/clk-exynos-audss.c
> index 39b40aa..742dabc 100644
> --- a/drivers/clk/samsung/clk-exynos-audss.c
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -14,6 +14,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> #include
>
> @@ -62,24 +64,26 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
> #endif /* CONFIG_PM_SLEEP */
>
> /* register exynos_audss clocks */
> -static void __init exynos_audss_clk_init(struct device_node *np)
> +static int exynos_audss_clk_probe(struct platform_device *pdev)
> {
> - reg_base = of_iomap(np, 0);
> - if (!reg_base) {
> - pr_err("%s: failed to map audss registers\n", __func__);
> - return;
> + int i, ret = 0;
> + struct resource *res;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + reg_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(reg_base)) {
> + dev_err(&pdev->dev, "failed to map audss registers\n");
> + return PTR_ERR(reg_base);
> }
>
> - clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> + clk_table = devm_kzalloc(&pdev->dev,
> + sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> GFP_KERNEL);
> - if (!clk_table) {
> - pr_err("%s: could not allocate clk lookup table\n", __func__);
> - return;
> - }
> + if (!clk_table)
> + return -ENOMEM;
>
> clk_data.clks = clk_table;
> clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
> - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>
> clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
> mout_audss_p, ARRAY_SIZE(mout_audss_p),
> @@ -123,13 +127,81 @@ static void __init exynos_audss_clk_init(struct
> device_node *np)
> "div_pcm0", CLK_SET_RATE_PARENT,
> reg_base + ASS_CLK_GATE, 5, 0, &lock);
>
> + for (i = 0; i < clk_data.clk_num; i++) {
> + if (IS_ERR(clk_table[i])) {
> + dev_err(&pdev->dev, "failed to register clock %d\n",
> i);
> + ret = PTR_ERR(clk_table[i]);
> + goto unregister;
> + }
> + }
> +
> + ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
> + &clk_data);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to add clock provider\n");
> + goto unregister;
> + }
> +
> #ifdef CONFIG_PM_SLEEP
> register_syscore_ops(&exynos_audss_clk_syscore_ops);
> #endif
>
> - pr_info("Exynos: Audss: clock setup completed\n");
> + dev_info(&pdev->dev, "setup completed\n");
> +
> + return 0;
> +
> +unregister:
> + for (i = 0; i < clk_data.clk_num; i++) {
> + if (!IS_ERR(clk_table[i]))
> +
[PATCH V4 5/6] clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker
---
Changes since v3:
- set clk_data.clk_num to correct value in non-5420 case
Changes since v1:
- added type enum and made comparison against that instead of compatibility
string
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 7 ++--
drivers/clk/samsung/clk-exynos-audss.c | 40 ++
include/dt-bindings/clk/exynos-audss-clk.h | 3 +-
3 files changed, 40 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 85b9e28..180e883 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4
SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5
SoCs.
-
+ - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+SoCs.
+ - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -49,6 +51,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 7cb10f2..e607176 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,6 +19,12 @@
#include
+enum exynos_audss_clk_type {
+ TYPE_EXYNOS4210,
+ TYPE_EXYNOS5250,
+ TYPE_EXYNOS5420,
+};
+
static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
@@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock",
+ .data = (void *)TYPE_EXYNOS4210, },
+ { .compatible = "samsung,exynos5250-audss-clock",
+ .data = (void *)TYPE_EXYNOS5250, },
+ { .compatible = "samsung,exynos5420-audss-clock",
+ .data = (void *)TYPE_EXYNOS5420, },
+ {},
+};
+
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
@@ -68,6 +84,13 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
+ const struct of_device_id *match;
+ enum exynos_audss_clk_type variant;
+
+ match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
+ if (!match)
+ return -EINVAL;
+ variant = (enum exynos_audss_clk_type)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -83,7 +106,10 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
return -ENOMEM;
clk_data.clks = clk_table;
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+ if (variant == TYPE_EXYNOS5420)
+ clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+ else
+ clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1;
pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
pll_in = devm_clk_get(&pdev->dev, "pll_in");
@@ -142,6 +168,12 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ if (variant == TYPE_EXYNOS5420) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, &lock);
+ }
+
for (i = 0; i < clk_data.clk_num; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to register clock %d\n", i);
@@ -188,12 +220,6 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
return 0;
}
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = "samsung,exynos4210-audss-cl
[PATCH V4 4/6] ARM: dts: exynos5250: add input clocks to audss clock controller
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS
clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5250.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc77..2d6a93d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -88,6 +88,8 @@
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
timer {
--
1.8.4
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[PATCH V4 1/6] clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker
Acked-by: Tomasz Figa
Reviewed-by: Sylwester Nawrocki
---
Changes since v3:
- __init -> __exit for module exit function
- fixed nits from Sylwester
Changes since v2:
- add error handling to probe callback
- fixed ordering of of_clk_{add,del}_provider
- fixed nits from Tomasz and Sylwester
Changes since v1:
- add clk_unregister() calls to remove callback
- fixed minor nits from Tomasz
---
drivers/clk/samsung/clk-exynos-audss.c | 104 -
1 file changed, 88 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 39b40aa..742dabc 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -62,24 +64,26 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
-static void __init exynos_audss_clk_init(struct device_node *np)
+static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("%s: failed to map audss registers\n", __func__);
- return;
+ int i, ret = 0;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
}
- clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table) {
- pr_err("%s: could not allocate clk lookup table\n", __func__);
- return;
- }
+ if (!clk_table)
+ return -ENOMEM;
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
@@ -123,13 +127,81 @@ static void __init exynos_audss_clk_init(struct
device_node *np)
"div_pcm0", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (IS_ERR(clk_table[i])) {
+ dev_err(&pdev->dev, "failed to register clock %d\n", i);
+ ret = PTR_ERR(clk_table[i]);
+ goto unregister;
+ }
+ }
+
+ ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add clock provider\n");
+ goto unregister;
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
- pr_info("Exynos: Audss: clock setup completed\n");
+ dev_info(&pdev->dev, "setup completed\n");
+
+ return 0;
+
+unregister:
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister(clk_table[i]);
+ }
+
+ return ret;
+}
+
+static int exynos_audss_clk_remove(struct platform_device *pdev)
+{
+ int i;
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ for (i = 0; i < clk_data.clk_num; i++) {
+ if (!IS_ERR(clk_table[i]))
+ clk_unregister(clk_table[i]);
+ }
+
+ return 0;
}
-CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
- exynos_audss_clk_init);
-CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
- exynos_audss_clk_init);
+
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss
[PATCH V4 2/6] clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- listed input clocks as required properties
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 32 --
drivers/clk/samsung/clk-exynos-audss.c | 25 +
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 75e2e19..85b9e28 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -14,6 +14,21 @@ Required Properties:
- #clock-cells: should be 1.
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
+not specified.
+ - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
+specified.
+
+- clock-names: Aliases for the above clocks. They should be "pll_ref",
+ "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -35,15 +50,28 @@ sclk_i2s7
pcm_bus 8
sclk_pcm9
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x0381 0x0C>;
+ #clock-cells = <1>;
+};
+
+Example 2: An example of a clock controller node with the input clocks
+ specified.
clock_audss: audss-clock-controller@381 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
+ <&ext_i2s_clk>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 742dabc..7cb10f2 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+ const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+ const char *sclk_pcm_p = "sclk_pcm0";
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -85,11 +85,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+ pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ pll_in = devm_clk_get(&pdev->dev, "pll_in");
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ if (!IS_ERR(pll_in))
+ mout_audss_p[1] = __clk_get_name(pll_in);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout
[PATCH V4 3/6] clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker
Reviewed-by: Tomasz Figa
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..67e9a47 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -62,6 +62,7 @@ clock which they consume.
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
+ div_pcm0 160
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..dec5376 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -108,7 +108,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
- div_i2s1, div_i2s2, sclk_hdmiphy,
+ div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
__initdata = {
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
- DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
--
1.8.4
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[PATCH V4 6/6] ARM: dts: exynos5420: add input clocks to audss clock controller
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5420.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..056b55e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -72,8 +72,8 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
- clocks = <&clock 148>;
- clock-names = "sclk_audio";
+ clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
codec@1100 {
--
1.8.4
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Re: [PATCH V3 1/6] clk: exynos-audss: convert to platform device
>> +static int exynos_audss_clk_remove(struct platform_device *pdev)
>> +{
>> + int i;
>> +
>> + of_clk_del_provider(pdev->dev.of_node);
>> +
>> + for (i = 0; i< EXYNOS_AUDSS_MAX_CLKS; i++) {
>> + if (!IS_ERR_OR_NULL(clk_table[i]))
>> + clk_unregister(clk_table[i]);
>> + }
>
>
> Since we only get here if all the clocks are registered properly and we
> always register EXYNOS_AUDSS_MAX_CLKS clocks, couldn't this simply be:
>
>
> for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++)
> clk_unregister(clk_table[i]);
>
> ?
Once support is added for Exynos5420, we won't always register
EXYNOS_AUDSS_MAX_CLKS clocks, so we'd still need the NULL check.
Thanks,
Andrew
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[PATCH V3 3/6] clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker
Reviewed-by: Tomasz Figa
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..67e9a47 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -62,6 +62,7 @@ clock which they consume.
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
+ div_pcm0 160
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..dec5376 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -108,7 +108,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
- div_i2s1, div_i2s2, sclk_hdmiphy,
+ div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
__initdata = {
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
- DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
--
1.8.4
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[PATCH V3 2/6] clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- listed input clocks as required properties
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 32 --
drivers/clk/samsung/clk-exynos-audss.c | 25 +
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 75e2e19..85b9e28 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -14,6 +14,21 @@ Required Properties:
- #clock-cells: should be 1.
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
+not specified.
+ - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
+specified.
+
+- clock-names: Aliases for the above clocks. They should be "pll_ref",
+ "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -35,15 +50,28 @@ sclk_i2s7
pcm_bus 8
sclk_pcm9
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x0381 0x0C>;
+ #clock-cells = <1>;
+};
+
+Example 2: An example of a clock controller node with the input clocks
+ specified.
clock_audss: audss-clock-controller@381 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
+ <&ext_i2s_clk>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 319c6e4..e7e800a 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
{
int i, ret = 0;
struct resource *res;
+ const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+ const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+ const char *sclk_pcm_p = "sclk_pcm0";
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -82,11 +82,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
if (!clk_table)
return -ENOMEM;
+ pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ pll_in = devm_clk_get(&pdev->dev, "pll_in");
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ if (!IS_ERR(pll_in))
+ mout_audss_p[1] = __clk_get_name(pll_in);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_aud
[PATCH V3 6/6] ARM: dts: exynos5420: add input clocks to audss clock controller
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5420.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..056b55e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -72,8 +72,8 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
- clocks = <&clock 148>;
- clock-names = "sclk_audio";
+ clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
codec@1100 {
--
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[PATCH V3 5/6] clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- added type enum and made comparison against that instead of compatibility
string
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++--
drivers/clk/samsung/clk-exynos-audss.c | 35 ++
include/dt-bindings/clk/exynos-audss-clk.h | 3 +-
3 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 85b9e28..180e883 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4
SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5
SoCs.
-
+ - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+SoCs.
+ - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -49,6 +51,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index e7e800a..35cae41 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,6 +19,12 @@
#include
+enum exynos_audss_clk_type {
+ TYPE_EXYNOS4210,
+ TYPE_EXYNOS5250,
+ TYPE_EXYNOS5420,
+};
+
static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
@@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock",
+ .data = (void *)TYPE_EXYNOS4210, },
+ { .compatible = "samsung,exynos5250-audss-clock",
+ .data = (void *)TYPE_EXYNOS5250, },
+ { .compatible = "samsung,exynos5420-audss-clock",
+ .data = (void *)TYPE_EXYNOS5420, },
+ {},
+};
+
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
@@ -68,6 +84,13 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
+ const struct of_device_id *match;
+ enum exynos_audss_clk_type variant;
+
+ match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
+ if (!match)
+ return -EINVAL;
+ variant = (enum exynos_audss_clk_type)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -139,6 +162,12 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ if (variant == TYPE_EXYNOS5420) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, &lock);
+ }
+
for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {
if (IS_ERR(clk_table[i])) {
dev_err(&pdev->dev, "failed to regsiter clock %d\n", i);
@@ -187,12 +216,6 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
return 0;
}
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = "samsung,exynos4210-audss-clock", },
- { .compatible = "samsung,exynos5250-audss-clock", },
- {},
-};
-
static struct platform_driver exynos_audss_clk_driver = {
.driver = {
.name = "exynos-audss-clk",
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define
[PATCH V3 1/6] clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker
---
Changes since v2:
- add error handling to probe callback
- fixed ordering of of_clk_{add,del}_provider
- fixed nits from Tomasz and Sylwester
Changes since v1:
- add clk_unregister() calls to remove callback
- fixed minor nits from Tomasz
---
drivers/clk/samsung/clk-exynos-audss.c | 109 +++--
1 file changed, 90 insertions(+), 19 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 39b40aa..319c6e4 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -62,24 +64,23 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
-static void __init exynos_audss_clk_init(struct device_node *np)
+static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("%s: failed to map audss registers\n", __func__);
- return;
+ int i, ret = 0;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
}
- clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
- if (!clk_table) {
- pr_err("%s: could not allocate clk lookup table\n", __func__);
- return;
- }
-
- clk_data.clks = clk_table;
- clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ if (!clk_table)
+ return -ENOMEM;
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
@@ -123,13 +124,83 @@ static void __init exynos_audss_clk_init(struct
device_node *np)
"div_pcm0", CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {
+ if (IS_ERR(clk_table[i])) {
+ dev_err(&pdev->dev, "failed to regsiter clock %d\n", i);
+ ret = PTR_ERR(clk_table[i]);
+ goto unregister;
+ }
+ }
+
+ clk_data.clks = clk_table;
+ clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+ ret = of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add clock provider\n");
+ goto unregister;
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
- pr_info("Exynos: Audss: clock setup completed\n");
+ dev_info(&pdev->dev, "setup completed\n");
+
+ return 0;
+
+unregister:
+ for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {
+ if (!IS_ERR_OR_NULL(clk_table[i]))
+ clk_unregister(clk_table[i]);
+ }
+
+ return ret;
}
-CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
- exynos_audss_clk_init);
-CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
- exynos_audss_clk_init);
+
+static int exynos_audss_clk_remove(struct platform_device *pdev)
+{
+ int i;
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {
+ if (!IS_ERR_OR_NULL(clk_table[i]))
+ clk_unregister(clk_table[i]);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock", },
+
[PATCH V3 4/6] ARM: dts: exynos5250: add input clocks to audss clock controller
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS
clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5250.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc77..2d6a93d 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -88,6 +88,8 @@
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
timer {
--
1.8.4
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[PATCH V2 6/6] ARM: dts: exynos5420: add input clocks to audss clock controller
Specify the remaining input clocks (pll_ref, pll_in, and sclk_pcm_in)
for the AudioSS clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5420.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..056b55e 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -72,8 +72,8 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
- clocks = <&clock 148>;
- clock-names = "sclk_audio";
+ clocks = <&clock 1>, <&clock 5>, <&clock 148>, <&clock 149>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
codec@1100 {
--
1.8.4
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[PATCH V2 5/6] clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- added type enum and made comparison against that instead of compatibility
string
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++--
drivers/clk/samsung/clk-exynos-audss.c | 35 ++
include/dt-bindings/clk/exynos-audss-clk.h | 3 +-
3 files changed, 36 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 85b9e28..180e883 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4
SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5
SoCs.
-
+ - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+SoCs.
+ - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -49,6 +51,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index afb53de..8ccf3788 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -19,6 +19,12 @@
#include
+enum exynos_audss_clk_type {
+ TYPE_EXYNOS4210,
+ TYPE_EXYNOS5250,
+ TYPE_EXYNOS5420,
+};
+
static DEFINE_SPINLOCK(lock);
static struct clk **clk_table;
static void __iomem *reg_base;
@@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
};
#endif /* CONFIG_PM_SLEEP */
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock",
+ .data = (void *)TYPE_EXYNOS4210, },
+ { .compatible = "samsung,exynos5250-audss-clock",
+ .data = (void *)TYPE_EXYNOS5250, },
+ { .compatible = "samsung,exynos5420-audss-clock",
+ .data = (void *)TYPE_EXYNOS5420, },
+ {},
+};
+
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
@@ -67,6 +83,13 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
const char *sclk_pcm_p = "sclk_pcm0";
struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
struct resource *res;
+ const struct of_device_id *match;
+ enum exynos_audss_clk_type variant;
+
+ match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node);
+ if (!match)
+ return -EINVAL;
+ variant = (enum exynos_audss_clk_type)match->data;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
reg_base = devm_ioremap_resource(&pdev->dev, res);
@@ -145,6 +168,12 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ if (variant == TYPE_EXYNOS5420) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, &lock);
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
@@ -168,12 +197,6 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
return 0;
}
-static const struct of_device_id exynos_audss_clk_of_match[] = {
- { .compatible = "samsung,exynos4210-audss-clock", },
- { .compatible = "samsung,exynos5250-audss-clock", },
- {},
-};
-
static struct platform_driver exynos_audss_clk_driver = {
.driver = {
.name = "exynos-audss-clk",
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define EXYNOS_ADMA10
-#define EXYNOS_AUDSS_MAX_CLKS 10
+#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
--
1.8.4
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[PATCH V2 4/6] ARM: dts: exynos5250: add input clocks to audss clock controller
Specify pll_ref, pll_in, sclk_audio, and sclk_pcm_in for the AudioSS
clock controller.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- specified additional input clocks
---
arch/arm/boot/dts/exynos5250.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc77..35e2838 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -88,6 +88,8 @@
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>;
+ clock-names = "pll_ref, "pll_in", "sclk_audio", "sclk_pcm_in";
};
timer {
--
1.8.4
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[PATCH V2 3/6] clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker
Reviewed-by: Tomasz Figa
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..67e9a47 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -62,6 +62,7 @@ clock which they consume.
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
+ div_pcm0 160
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..dec5376 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -108,7 +108,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
- div_i2s1, div_i2s2, sclk_hdmiphy,
+ div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
__initdata = {
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
- DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
--
1.8.4
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[PATCH V2 2/6] clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- listed input clocks as required properties
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 32 --
drivers/clk/samsung/clk-exynos-audss.c | 25 +
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 75e2e19..85b9e28 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -14,6 +14,21 @@ Required Properties:
- #clock-cells: should be 1.
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
+not specified.
+ - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
+specified.
+
+- clock-names: Aliases for the above clocks. They should be "pll_ref",
+ "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -35,15 +50,28 @@ sclk_i2s7
pcm_bus 8
sclk_pcm9
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x0381 0x0C>;
+ #clock-cells = <1>;
+};
+
+Example 2: An example of a clock controller node with the input clocks
+ specified.
clock_audss: audss-clock-controller@381 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
+ <&ext_i2s_clk>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index c512efd..afb53de 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -66,6 +62,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
+ const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+ const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+ const char *sclk_pcm_p = "sclk_pcm0";
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -88,11 +88,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
&clk_data);
+ pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ pll_in = devm_clk_get(&pdev->dev, "pll_in");
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ if (!IS_ERR(pll_in))
+ mout_audss_p[1] = __clk_get_name(pll_in);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss&q
[PATCH V2 1/6] clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker
---
Changes since v1:
- add clk_unregister() calls to remove callback
- fixed minor nits from Tomasz
---
drivers/clk/samsung/clk-exynos-audss.c | 78 --
1 file changed, 65 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 39b40aa..c512efd 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -62,24 +64,29 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
-static void __init exynos_audss_clk_init(struct device_node *np)
+static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("%s: failed to map audss registers\n", __func__);
- return;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
}
- clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
if (!clk_table) {
- pr_err("%s: could not allocate clk lookup table\n", __func__);
- return;
+ dev_err(&pdev->dev, "could not allocate clk lookup table\n");
+ return -ENOMEM;
}
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
@@ -128,8 +135,53 @@ static void __init exynos_audss_clk_init(struct
device_node *np)
#endif
pr_info("Exynos: Audss: clock setup completed\n");
+
+ return 0;
+}
+
+static int exynos_audss_clk_remove(struct platform_device *pdev)
+{
+ int i;
+
+ for (i = 0; i < EXYNOS_AUDSS_MAX_CLKS; i++) {
+ if (clk_table[i])
+ clk_unregister(clk_table[i]);
+ }
+
+ of_clk_del_provider(pdev->dev.of_node);
+
+ return 0;
}
-CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
- exynos_audss_clk_init);
-CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
- exynos_audss_clk_init);
+
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock", },
+ { .compatible = "samsung,exynos5250-audss-clock", },
+ {},
+};
+
+static struct platform_driver exynos_audss_clk_driver = {
+ .driver = {
+ .name = "exynos-audss-clk",
+ .owner = THIS_MODULE,
+ .of_match_table = exynos_audss_clk_of_match,
+ },
+ .probe = exynos_audss_clk_probe,
+ .remove = exynos_audss_clk_remove,
+};
+
+static int __init exynos_audss_clk_init(void)
+{
+ return platform_driver_register(&exynos_audss_clk_driver);
+}
+core_initcall(exynos_audss_clk_init);
+
+static void __init exynos_audss_clk_exit(void)
+{
+ platform_driver_unregister(&exynos_audss_clk_driver);
+}
+module_exit(exynos_audss_clk_exit);
+
+MODULE_AUTHOR("Padmavathi Venna ");
+MODULE_DESCRIPTION("Exynos Audio Subsystem Clock Controller");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:exynos-audss-clk");
--
1.8.4
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[PATCH 2/6] clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker
---
.../devicetree/bindings/clock/clk-exynos-audss.txt | 33 --
drivers/clk/samsung/clk-exynos-audss.c | 25
2 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 75e2e19..d51a2f9 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -14,6 +14,23 @@ Required Properties:
- #clock-cells: should be 1.
+Optional Properties:
+
+- clocks:
+ - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
+is used if not specified.
+ - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
+is used if not specified.
+ - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+specified.
+ - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
+not specified.
+ - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
+specified.
+
+- clock-names: Aliases for the above clocks. They should be "pll_ref",
+ "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
+
The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
@@ -35,15 +52,27 @@ sclk_i2s7
pcm_bus 8
sclk_pcm9
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+ clock names is listed below.
+
+clock_audss: audss-clock-controller@381 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x0381 0x0C>;
+ #clock-cells = <1>;
+};
+
+Example 2: An example of a clock controller node with audio bus input clock
+ specified is listed below.
clock_audss: audss-clock-controller@381 {
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 138>;
+ clock-names = "sclk_audio";
};
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
controller. Refer to the standard clock bindings for information
about 'clocks' and 'clock-names' property.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 7571e88..aac5342 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = {
{ASS_CLK_GATE, 0},
};
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
-
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void)
{
@@ -66,6 +62,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
/* register exynos_audss clocks */
static int exynos_audss_clk_probe(struct platform_device *pdev)
{
+ const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+ const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+ const char *sclk_pcm_p = "sclk_pcm0";
+ struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in;
struct resource *res;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -88,11 +88,23 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
&clk_data);
+ pll_ref = devm_clk_get(&pdev->dev, "pll_ref");
+ pll_in = devm_clk_get(&pdev->dev, "pll_in");
+ if (!IS_ERR(pll_ref))
+ mout_audss_p[0] = __clk_get_name(pll_ref);
+ if (!IS_ERR(pll_in))
+ mout_audss_p[1] = __clk_get_name(pll_in);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
CLK_SET_RATE_NO_REPARENT,
reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
[PATCH 6/6] ARM: dts: exynos5420: add sclk_pcm_in to audss clock controller
The parent of sclk_pcm in the AudioSS block is sclk_maupcm0.
Signed-off-by: Andrew Bresticker
---
arch/arm/boot/dts/exynos5420.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index d537cd7..339ab93 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -72,8 +72,8 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
- clocks = <&clock 148>;
- clock-names = "sclk_audio";
+ clocks = <&clock 148>, <&clock 149>;
+ clock-names = "sclk_audio", "sclk_pcm_in";
};
codec@1100 {
--
1.8.4
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[PATCH 1/6] clk: exynos-audss: convert to platform device
The Exynos AudioSS clock controller will later be modified to allow
input clocks to be specified via device-tree in order to support
multiple Exynos SoCs. This will introduce a dependency on the core
SoC clock controller being initialized first so that the AudioSS driver
can look up its input clocks, but the order in which clock providers
are probed in of_clk_init() is not guaranteed. Since deferred probing
is not supported in of_clk_init() and the AudioSS block is not the core
controller, we can initialize it later as a platform device.
Signed-off-by: Andrew Bresticker
---
drivers/clk/samsung/clk-exynos-audss.c | 71 +++---
1 file changed, 58 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index 39b40aa..7571e88 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -14,6 +14,8 @@
#include
#include
#include
+#include
+#include
#include
@@ -62,24 +64,29 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
#endif /* CONFIG_PM_SLEEP */
/* register exynos_audss clocks */
-static void __init exynos_audss_clk_init(struct device_node *np)
+static int exynos_audss_clk_probe(struct platform_device *pdev)
{
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_err("%s: failed to map audss registers\n", __func__);
- return;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(reg_base)) {
+ dev_err(&pdev->dev, "failed to map audss registers\n");
+ return PTR_ERR(reg_base);
}
- clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+ clk_table = devm_kzalloc(&pdev->dev,
+ sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
GFP_KERNEL);
if (!clk_table) {
- pr_err("%s: could not allocate clk lookup table\n", __func__);
- return;
+ dev_err(&pdev->dev, "could not allocate clk lookup table\n");
+ return -ENOMEM;
}
clk_data.clks = clk_table;
clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+ of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get,
+ &clk_data);
clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
mout_audss_p, ARRAY_SIZE(mout_audss_p),
@@ -128,8 +135,46 @@ static void __init exynos_audss_clk_init(struct
device_node *np)
#endif
pr_info("Exynos: Audss: clock setup completed\n");
+
+ return 0;
+}
+
+static int exynos_audss_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+
+ return 0;
}
-CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
- exynos_audss_clk_init);
-CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
- exynos_audss_clk_init);
+
+static const struct of_device_id exynos_audss_clk_of_match[] = {
+ { .compatible = "samsung,exynos4210-audss-clock", },
+ { .compatible = "samsung,exynos5250-audss-clock", },
+ {},
+};
+
+static struct platform_driver exynos_audss_clk_driver = {
+ .driver = {
+ .name = "exynos-audss-clk",
+ .owner = THIS_MODULE,
+ .of_match_table = exynos_audss_clk_of_match,
+ },
+ .probe = exynos_audss_clk_probe,
+ .remove = exynos_audss_clk_remove,
+};
+
+static int __init exynos_audss_clk_init(void)
+{
+ return platform_driver_register(&exynos_audss_clk_driver);
+}
+core_initcall(exynos_audss_clk_init);
+
+static void __init exynos_audss_clk_exit(void)
+{
+ platform_driver_unregister(&exynos_audss_clk_driver);
+}
+module_exit(exynos_audss_clk_exit);
+
+MODULE_AUTHOR("Padmavathi Venna ");
+MODULE_DESCRIPTION("Exynos AudioSS Clock Controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:exynos-audss-clk");
--
1.8.4
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[PATCH 3/6] clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker
---
Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 +
drivers/clk/samsung/clk-exynos5250.c | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 24765c1..67e9a47 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -62,6 +62,7 @@ clock which they consume.
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
+ div_pcm0 160
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index adf3234..dec5376 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -108,7 +108,7 @@ enum exynos5250_clks {
sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3,
sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm,
sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
- div_i2s1, div_i2s2, sclk_hdmiphy,
+ div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0,
/* gate clocks */
gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0,
@@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[]
__initdata = {
DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4),
DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
- DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
--
1.8.4
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[PATCH 4/6] ARM: dts: exynos5250: add sclk_pcm_in to audss clock controller
The parent of sclk_pcm in the AudioSS block is div_pcm0.
Signed-off-by: Andrew Bresticker
---
arch/arm/boot/dts/exynos5250.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 7d7cc77..bedc7a8 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -88,6 +88,8 @@
compatible = "samsung,exynos5250-audss-clock";
reg = <0x0381 0x0C>;
#clock-cells = <1>;
+ clocks = <&clock 160>;
+ clock-names = "sclk_pcm_in";
};
timer {
--
1.8.4
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[PATCH 5/6] clk: exynos-audss: add support for Exynos 5420
The AudioSS block on Exynos 5420 has an additional clock gate for the
ADMA bus clock.
Signed-off-by: Andrew Bresticker
---
Documentation/devicetree/bindings/clock/clk-exynos-audss.txt | 7 +--
drivers/clk/samsung/clk-exynos-audss.c | 8
include/dt-bindings/clk/exynos-audss-clk.h | 3 ++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index d51a2f9..a10c648 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -8,8 +8,10 @@ Required Properties:
- compatible: should be one of the following:
- "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4
SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5
SoCs.
-
+ - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
+SoCs.
+ - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
+SoCs.
- reg: physical base address and length of the controller's register set.
- #clock-cells: should be 1.
@@ -51,6 +53,7 @@ i2s_bus 6
sclk_i2s7
pcm_bus 8
sclk_pcm9
+adma10 Exynos5420
Example 1: An example of a clock controller node using the default input
clock names is listed below.
diff --git a/drivers/clk/samsung/clk-exynos-audss.c
b/drivers/clk/samsung/clk-exynos-audss.c
index aac5342..07c8dbd 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -145,6 +145,13 @@ static int exynos_audss_clk_probe(struct platform_device
*pdev)
sclk_pcm_p, CLK_SET_RATE_PARENT,
reg_base + ASS_CLK_GATE, 5, 0, &lock);
+ if (of_device_is_compatible(pdev->dev.of_node,
+ "samsung,exynos5420-audss-clock")) {
+ clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma",
+ "dout_srp", CLK_SET_RATE_PARENT,
+ reg_base + ASS_CLK_GATE, 9, 0, &lock);
+ }
+
#ifdef CONFIG_PM_SLEEP
register_syscore_ops(&exynos_audss_clk_syscore_ops);
#endif
@@ -164,6 +171,7 @@ static int exynos_audss_clk_remove(struct platform_device
*pdev)
static const struct of_device_id exynos_audss_clk_of_match[] = {
{ .compatible = "samsung,exynos4210-audss-clock", },
{ .compatible = "samsung,exynos5250-audss-clock", },
+ { .compatible = "samsung,exynos5420-audss-clock", },
{},
};
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h
b/include/dt-bindings/clk/exynos-audss-clk.h
index 8279f42..0ae6f5a 100644
--- a/include/dt-bindings/clk/exynos-audss-clk.h
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -19,7 +19,8 @@
#define EXYNOS_SCLK_I2S7
#define EXYNOS_PCM_BUS 8
#define EXYNOS_SCLK_PCM9
+#define EXYNOS_ADMA10
-#define EXYNOS_AUDSS_MAX_CLKS 10
+#define EXYNOS_AUDSS_MAX_CLKS 11
#endif
--
1.8.4
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Re: [PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree
Hi Tomasz, > Well, this is basically how it should be done, but in current state of > clock core I can see a problem: can we really rely on the order of clock > initialization? I mean, we can't defer initialization of particular clock > controller until all external clocks it needs are available, because there > is no probing involved here. Right, we can't. The reason I added the device-tree lookup of input clocks was because Exynos5420 has different names for several of the input clocks to the audio block. We already need a separate compatibility string because of the ADMA clock, so we could just use that to determine the parent clock names. It's not ideal, but it's a workaround for the initialization order issue. Thoughts? Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 13/20] pwm: Add new pwm-samsung driver
> ..it should not be defined as non-static in this case (= an ifdef is > needed in this header). I believe I had this already fixed, not sure what > happened with the fix... Perhaps this is it: https://patchwork.kernel.org/patch/2787271/. That should probably land with this patchset too. Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 13/20] pwm: Add new pwm-samsung driver
Hi Tomasz, > +#ifndef CONFIG_CLKSRC_SAMSUNG_PWM > +/* > + * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers > + * and some registers need access synchronization. If both drivers are > + * compiled in, the spinlock is defined in the clocksource driver, > + * otherwise following definition is used. > + * > + * Currently we do not need any more complex synchronization method > + * because all the supported SoCs contain only one instance of the PWM > + * IP. Should this change, both drivers will need to be modified to > + * properly synchronize accesses to particular instances. > + */ > +static DEFINE_SPINLOCK(samsung_pwm_lock); Shouldn't this not be static? It's declared in clocksource/samsung_pwm.h whether or not the samsung_pwm_timer is compiled in or not. Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v5 7/7] clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC
> +static __initdata struct samsung_pll_rate_table epll_24mhz_tbl[] = {
> + /* sorted in descending order */
> + /* PLL_36XX_RATE(rate, m, p, s, k) */
> + PLL_36XX_RATE(19200, 48, 3, 1, 0),
> + PLL_36XX_RATE(180633600, 45, 3, 1, 10381),
> + PLL_36XX_RATE(18000, 45, 3, 1, 0),
> + PLL_36XX_RATE(73728000, 73, 3, 3, 47710),
> + PLL_36XX_RATE(67737600, 90, 4, 3, 20762),
> + PLL_36XX_RATE(49152000, 49, 3, 3, 9962),
> + PLL_36XX_RATE(45158400, 45, 3, 3, 10381),
> + PLL_36XX_RATE(32768000, 131, 3, 5, 4719),
> + { },
> +};
I believe the UM says that 64 <= m <= 511. Although the above seems
to work on 5250 and 5420, it might be better to use a table that
conforms to the constraint on m:
PLL_36XX_RATE(19200, 64, 2, 2, 0),
PLL_36XX_RATE(180633600, 90, 3, 2, 20762),
PLL_36XX_RATE(18000, 90, 3, 2, 0),
PLL_36XX_RATE(73728000, 98, 2, 4, 19923),
PLL_36XX_RATE(67737600, 90, 2, 4, 20762),
PLL_36XX_RATE(49152000, 98, 3, 4, 19923),
PLL_36XX_RATE(45158400, 90, 3, 4, 20762),
PLL_36XX_RATE(32768000, 131, 3, 5, 4719)
Thanks,
Andrew
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Re: [PATCH v2 06/10] clk: exynos5420: register clocks using common clock framework
Hi Chander, > + [Core Clocks] > + > + ClockID > + > + > + oscclk 1 I know the UM refers to this as 'oscclk', but could we instead call this 'fin_pll' to be consistent with Exynos 4 and Exynos 5250? Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 1/6] clk: samsung: Use clk->base instead of directly using clk->con0 for PLL3xxx
Doug,
>> Hmm, if done properly, it could simplify PLL registration in SoC clock
>> initialization code a lot.
>>
>> I'm not sure if this is really the best solution (feel free to suggest
>> anything better), but we could put PLLs in an array, like other clocks,
>> e.g.
>>
>> ... exynos4210_pll_clks[] = {
>> CLK_PLL45XX(...),
>> CLK_PLL45XX(...),
>> CLK_PLL46XX(...),
>> CLK_PLL46XX(...),
>> };
>>
>> and then just call a helper like
>>
>> samsung_clk_register_pll(exynos4210_pll_clks,
>> ARRAY_SIZE(exynos4210_pll_clks));
>
> Something like that looks like what I was thinking. I'd have to see
> it actually coded up to see if there's something I'm missing that
> would prevent us from doing that, but I don't see anything.
The only issue I see with this is that we may only want to register a
rate table with a PLL only if fin_pll is running at a certain rate.
On 5250 and 5420, for example, we have EPLL and VPLL rate tables that
should only be registered if fin_pll is 24Mhz. We may have to
register those separately, but this approach seems fine otherwise.
-Andrew
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Re: [PATCH 09/13] clk: exynos5420: register clocks using common clock framework
Tomasz,
>> + apll = samsung_clk_register_pll35xx("fout_apll", "oscclk",
>> + reg_base + 0x100);
>> + bpll = samsung_clk_register_pll35xx("fout_bpll", "oscclk",
>> + reg_base + 0x20110);
>> + cpll = samsung_clk_register_pll35xx("fout_cpll", "oscclk",
>> + reg_base + 0x10120);
>> + dpll = samsung_clk_register_pll35xx("fout_dpll", "oscclk",
>> + reg_base + 0x10128);
>> + epll = samsung_clk_register_pll35xx("fout_epll", "oscclk",
>> + reg_base + 0x10130);
>> + ipll = samsung_clk_register_pll35xx("fout_ipll", "oscclk",
>> + reg_base + 0x10150);
>> + kpll = samsung_clk_register_pll35xx("fout_kpll", "oscclk",
>> + reg_base + 0x28100);
>> + mpll = samsung_clk_register_pll35xx("fout_mpll", "oscclk",
>> + reg_base + 0x10180);
>> + rpll = samsung_clk_register_pll35xx("fout_rpll", "oscclk",
>> + reg_base + 0x10140);
>> + spll = samsung_clk_register_pll35xx("fout_spll", "oscclk",
>> + reg_base + 0x10160);
>> + vpll = samsung_clk_register_pll35xx("fout_vpll", "oscclk",
>> + reg_base + 0x10170);
>
> Are all those PLLs really PLL35xx? At least for VPLL and EPLL a PLL
> without the K factor looks a bit awkward.
No they are not... EPLL and RPLL should be pll36xx, but the rest are pll35xx.
Thanks,
Andrew
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Re: [PATCH V4 2/4] clk: samsung: register audio subsystem clocks using common clock framework
>> +static unsigned long reg_save[][2] = {
>> + {ASS_CLK_SRC, 0},
>> + {ASS_CLK_DIV, 0},
>> + {ASS_CLK_GATE, 0},
>> +};
>> +
>> +/* list of all parent clock list */
>> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>
> I think this is supposed to be "xxti" which might or might not be
> "fin_pll". In the exynos4 code these are two different clocks that
> are chosen by OM[0]. I'd bet that 99% of the time they are the same,
> but it seems better to use "xxti".
OM[0] also appears to mux the input here between "xxti" and "xusbxti"
as well. So this should probably remain "fin_pll".
> At the moment the 5250 code doesn't expose "xxti". It probably
> should. Andrew (CCed) is looking at this.
Yes, xxti is used directly elsewhere (SPI and UART, from what I can
tell), but not here.
-Andrew
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Re: [PATCH] thermal: exynos: fix handling of invalid frequency table entries
> can you please verify > commit fc35b35cbe24ef021ea9acfba21e54da958df747 > commit 57df8106932b57427df1eaaa13871857f75b1194 > at > http://git.kernel.org/cgit/linux/kernel/git/rzhang/linux.git/log/?h=thermal > fixes the problem for you? It does. Thanks! -Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] thermal: exynos: fix handling of invalid frequency table entries
Similar to the error described in "thermal: cpu_cooling: fix handling
of invalid frequency table entries," exynos_get_frequency_level() will
enter an infinite loop if any CPU frequency table entries are invalid.
This patch fixes the handling of invalid frequency entries so that
there is no infinite loop and the correct level is returned.
Signed-off-by: Andrew Bresticker
---
drivers/thermal/exynos_thermal.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index d5e6267..524b2a0 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -237,7 +237,7 @@ static int exynos_get_crit_temp(struct thermal_zone_device
*thermal,
static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
{
- int i = 0, ret = -EINVAL;
+ int i, level = 0, ret = -EINVAL;
struct cpufreq_frequency_table *table = NULL;
#ifdef CONFIG_CPU_FREQ
table = cpufreq_frequency_get_table(cpu);
@@ -245,12 +245,12 @@ static int exynos_get_frequency_level(unsigned int cpu,
unsigned int freq)
if (!table)
return ret;
- while (table[i].frequency != CPUFREQ_TABLE_END) {
+ for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
continue;
if (table[i].frequency == freq)
- return i;
- i++;
+ return level;
+ level++;
}
return ret;
}
--
1.8.1.3
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