[PATCH v2 0/3] iio: exynos-adc: use syscon instead of ioremap
Changes since v1: 1. Rebased on top of togreg branch of IIO git. This patch set does the following 1. Use the syscon and Regmap API instead of ioremappaing the ADC_PHY register from PMU. 2. Updates the Documentation in exynos-adc.txt with syscon phandle for the ADC nodes. 3. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250, Exynos5420 with the syscon phandle. Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI by verifying sysfs entries provided by HWMON based NTC thermistors. Tested-By for Exynos3250, Exynos4x12 would be appreciated. Naveen Krishna Chatradhi (3): iio: exyno-adc: use syscon for PMU register access Documentation: dt-bindings: update exynos-adc.txt with syscon handle ARM: dts: exynos: Add sysreg phandle to ADC node .../devicetree/bindings/arm/samsung/exynos-adc.txt |9 -- arch/arm/boot/dts/exynos3250.dtsi |3 +- arch/arm/boot/dts/exynos4x12.dtsi |3 +- arch/arm/boot/dts/exynos5250.dtsi |3 +- arch/arm/boot/dts/exynos5420.dtsi |3 +- drivers/iio/adc/exynos_adc.c | 30 ++-- 6 files changed, 36 insertions(+), 15 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/3] ARM: dts: exynos: Add sysreg phandle to ADC node
Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.
This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-samsung-soc@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi |3 ++-
arch/arm/boot/dts/exynos4x12.dtsi |3 ++-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
arch/arm/boot/dts/exynos5420.dtsi |3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 1d52de6..b997a4c 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -272,12 +272,13 @@
adc: adc@126C {
compatible = samsung,exynos3250-adc,
samsung,exynos-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
clock-names = adc, sclk;
clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index 861bb91..9ee77d3 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -108,13 +108,14 @@
adc: adc@126C {
compatible = samsung,exynos-adc-v1;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupt-parent = combiner;
interrupts = 10 3;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..108adc5 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -765,12 +765,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
clocks = clock CLK_ADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index bfe056d..5fd587a 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -541,12 +541,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v2;
- reg = 0x12D1 0x100, 0x10040720 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
--
1.7.9.5
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[PATCH v2 1/3] iio: exyno-adc: use syscon for PMU register access
This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-...@vger.kernel.org
---
Changes since v1:
Rebased on top of togreg branch of IIO git
drivers/iio/adc/exynos_adc.c | 30 +-
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index 43620fd..fe03177 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -39,6 +39,8 @@
#include linux/iio/iio.h
#include linux/iio/machine.h
#include linux/iio/driver.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
@@ -90,11 +92,14 @@
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
+#define EXYNOS_ADCV1_PHY_OFFSET0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET0x0720
+
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
void __iomem*regs;
- void __iomem*enable_reg;
+ struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned intirq;
@@ -110,6 +115,7 @@ struct exynos_adc_data {
int num_channels;
bool needs_sclk;
bool needs_adc_phy;
+ int phy_offset;
u32 mask;
void (*init_hw)(struct exynos_adc *info);
@@ -183,7 +189,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
u32 con1;
if (info-data-needs_adc_phy)
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -198,7 +204,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
u32 con;
if (info-data-needs_adc_phy)
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V1_CON(info-regs));
con |= ADC_V1_CON_STANDBY;
@@ -225,6 +231,7 @@ static const struct exynos_adc_data exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
.mask = ADC_DATX_MASK,/* 12 bit ADC resolution */
.needs_adc_phy = true,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw= exynos_adc_v1_init_hw,
.exit_hw= exynos_adc_v1_exit_hw,
@@ -314,7 +321,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
u32 con1, con2;
if (info-data-needs_adc_phy)
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info-regs));
@@ -332,7 +339,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
u32 con;
if (info-data-needs_adc_phy)
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V2_CON1(info-regs));
con = ~ADC_CON_EN_START;
@@ -362,6 +369,7 @@ static const struct exynos_adc_data exynos_adc_v2_data = {
.num_channels = MAX_ADC_V2_CHANNELS,
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_adc_phy = true,
+ .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
.init_hw= exynos_adc_v2_init_hw,
.exit_hw= exynos_adc_v2_exit_hw,
@@ -374,6 +382,7 @@ static const struct exynos_adc_data exynos3250_adc_data = {
.mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
.needs_sclk = true,
.needs_adc_phy = true,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw= exynos_adc_v2_init_hw,
.exit_hw= exynos_adc_v2_exit_hw,
@@ -558,10 +567,13 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (info-data-needs_adc_phy) {
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info-enable_reg = devm_ioremap_resource(pdev-dev, mem);
- if (IS_ERR(info-enable_reg))
- return PTR_ERR(info-enable_reg);
+ info-pmu_map = syscon_regmap_lookup_by_phandle(
+ pdev-dev.of_node,
+ samsung,syscon-phandle);
+ if (IS_ERR(info-pmu_map)) {
+ dev_err(pdev-dev, syscon regmap lookup failed.\n);
+ return PTR_ERR(info-pmu_map);
+ }
}
irq = platform_get_irq(pdev, 0);
--
1.7.9.5
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[PATCH v2 2/3] Documentation: dt-bindings: update exynos-adc.txt with syscon handle
This patch updates the DT bindings for ADC in exynos-adc.txt with the
syscon phandle to the ADC nodes.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: devicet...@vger.kernel.org
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt |9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 709efaa..c368210 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -43,13 +43,16 @@ Required properties:
compatible ADC block)
- vdd-supply VDD input supply.
+- samsung,syscon-phandle Contains the PMU system controller node
+ (To access the ADC_PHY register on
Exynos5250/5420/5800/3250)
+
Note: child nodes can be added for auto probing from device tree.
Example: adding device info in dtsi file
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
#io-channel-cells = 1;
io-channel-ranges;
@@ -58,13 +61,14 @@ adc: adc@12D1 {
clock-names = adc;
vdd-supply = buck5_reg;
+ samsung,syscon-phandle = pmu_system_controller;
};
Example: adding device info in dtsi file for Exynos3250 with additional sclk
adc: adc@126C {
compatible = samsung,exynos3250-adc, samsung,exynos-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
#io-channel-cells = 1;
io-channel-ranges;
@@ -73,6 +77,7 @@ adc: adc@126C {
clock-names = adc, sclk;
vdd-supply = buck5_reg;
+ samsung,syscon-phandle = pmu_system_controller;
};
Example: Adding child nodes in dts file
--
1.7.9.5
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[PATCH 1/2] i2c: exynos: add support for HSI2C module on Exynos7
The HSI2C module on Exynos7 differs in the transfer status
bits. Transfer status bits were moved to INT_ENABLE and
INT_STATUS registers
This patch adds support for the HSI2C module on Exynos7.
1. Implementes a hw field in the variant struct to distinguish
the hardware.
2. Updates the dt-new compatible in dt-binding documenation
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Wolfram Sang w...@the-dreams.de
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|2 +
drivers/i2c/busses/i2c-exynos5.c | 71 ++--
2 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index d4745e3..2dbc0b6 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -12,6 +12,8 @@ Required properties:
on Exynos5250 and Exynos5420 SoCs.
- samsung,exynos5260-hsi2c, for i2c compatible with HSI2C available
on Exynos5260 SoCs.
+ - samsung,exynos7-hsi2c, for i2c compatible with HSI2C available
+ on Exynos7 SoCs.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 28073f1..81e6263 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -83,7 +83,6 @@
#define HSI2C_INT_TX_ALMOSTEMPTY_EN(1u 0)
#define HSI2C_INT_RX_ALMOSTFULL_EN (1u 1)
#define HSI2C_INT_TRAILING_EN (1u 6)
-#define HSI2C_INT_I2C_EN (1u 9)
/* I2C_INT_STAT Register bits */
#define HSI2C_INT_TX_ALMOSTEMPTY (1u 0)
@@ -95,6 +94,17 @@
#define HSI2C_INT_TRAILING (1u 6)
#define HSI2C_INT_I2C (1u 9)
+#define HSI2C_INT_TRANS_DONE (1u 7)
+#define HSI2C_INT_TRANS_ABORT (1u 8)
+#define HSI2C_INT_NO_DEV_ACK (1u 9)
+#define HSI2C_INT_NO_DEV (1u 10)
+#define HSI2C_INT_TIMEOUT (1u 11)
+#define HSI2C_INT_I2C_TRANS(HSI2C_INT_TRANS_DONE | \
+ HSI2C_INT_TRANS_ABORT | \
+ HSI2C_INT_NO_DEV_ACK | \
+ HSI2C_INT_NO_DEV | \
+ HSI2C_INT_TIMEOUT)
+
/* I2C_FIFO_STAT Register bits */
#define HSI2C_RX_FIFO_EMPTY(1u 24)
#define HSI2C_RX_FIFO_FULL (1u 23)
@@ -143,6 +153,8 @@
#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
+#define HSI2C_EXYNOS7 BIT(0)
+
struct exynos5_i2c {
struct i2c_adapter adap;
unsigned intsuspended:1;
@@ -192,6 +204,7 @@ struct exynos5_i2c {
*/
struct exynos_hsi2c_variant {
unsigned intfifo_depth;
+ unsigned inthw;
};
static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
@@ -202,6 +215,11 @@ static const struct exynos_hsi2c_variant
exynos5260_hsi2c_data = {
.fifo_depth = 16,
};
+static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
+ .fifo_depth = 16,
+ .hw = HSI2C_EXYNOS7,
+};
+
static const struct of_device_id exynos5_i2c_match[] = {
{
.compatible = samsung,exynos5-hsi2c,
@@ -212,6 +230,9 @@ static const struct of_device_id exynos5_i2c_match[] = {
}, {
.compatible = samsung,exynos5260-hsi2c,
.data = exynos5260_hsi2c_data
+ }, {
+ .compatible = samsung,exynos7-hsi2c,
+ .data = exynos7_hsi2c_data
}, {},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
@@ -256,13 +277,24 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c
*i2c, int mode)
i2c-hs_clock : i2c-fs_clock;
/*
+* In case of HSI2C controller in Exynos5 series
* FPCLK / FI2C =
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
+*
+* In case of HSI2C controllers in Exynos7 series
+* FPCLK / FI2C =
+* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
+*
* utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
* utemp1 = (TSCLK_L + TSCLK_H + 2)
*/
t_ftl_cycle = (readl(i2c-regs + HSI2C_CONF) 16) 0x7;
- utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
+ utemp0 = (clkin / op_clk) - 8;
+
+ if (i2c-variant-hw == HSI2C_EXYNOS7)
+ utemp0 -= t_ftl_cycle;
+ else
+ utemp0 -= 2 * t_ftl_cycle;
/* CLK_DIV max is 256 */
for (div = 0; div 256; div++) {
@@ -407,7 +439,28
[PATCH 2/2] i2c: exynos5: Add Kconfig dependencies
The i2c-exynos5.c driver can be reused for the HSI2C controller on Exynos7 SoCs from Samsung. This patch adds the Kconfig dependency to choose i2c-exynos5.c for CONFIG_ARCH_EXYNOS7. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Wolfram Sang w...@the-dreams.de --- drivers/i2c/busses/Kconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 2ac87fa..1f3b9cb 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -465,7 +465,7 @@ config I2C_EG20T config I2C_EXYNOS5 tristate Exynos5 high-speed I2C driver - depends on ARCH_EXYNOS5 OF + depends on ARCH_EXYNOS OF default y help High-speed I2C controller on Exynos5 based Samsung SoCs. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/2] i2c: Add i2c support for Exynos7 SoC
This patchset adds code to the i2c-exynos5.c driver to support the HSI2C H/W available on Exynos7 SoC. Also, modifies the Kconfig dependencies to be able to select for ARCH_EXYNOS7 platform. The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next Following patches are required for this series: 1. tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg36208.html 2. dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3. [PATCH v4 0/8] arch: arm64: enable support for Samsung Exynos7 SoC http://www.spinics.net/lists/devicetree/msg49130.html 4. [PATCH 0/4] Add initial support for pinctrl on Exynos7 http://www.spinics.net/lists/devicetree/msg49237.html Naveen Krishna Chatradhi (2): i2c: exynos: add support for HSI2C module on Exynos7 i2c: exynos5: Add Kconfig dependencies .../devicetree/bindings/i2c/i2c-exynos5.txt|2 + drivers/i2c/busses/Kconfig |2 +- drivers/i2c/busses/i2c-exynos5.c | 71 ++-- 3 files changed, 68 insertions(+), 7 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/8] arch: arm64: enable support for Samsung Exynos7 SoC
Changes since v3: - Removed aliases for serial controllers from dtsi file and moved it into board specific dts file as suggested by Arnd. - Based this series on Robert Richter's patches for adding vendor device tree sub-directories for arm64. http://comments.gmane.org/gmane.linux.kbuild.devel/12131 This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next The following patches are required for this series. 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2- dts, kbuild: Implement support for dtb vendor subdirs patch set http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Alim Akhtar (1): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support Naveen Krishna Chatradhi (6): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 tty/serial: samsung: enable usage for 64-bit Exynos platforms Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/clock/exynos7-clock.txt| 37 ++ arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/Makefile|5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 39 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 160 arch/arm64/boot/dts/include/dt-bindings|1 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 417 drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ drivers/tty/serial/Kconfig |2 +- include/dt-bindings/clock/exynos7-clk.h| 39 ++ 16 files changed, 898 insertions(+), 165 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 1/8] clk: samsung: add support for 145xx and 1460x PLLs
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 25 -
drivers/clk/samsung/clk-pll.h |4
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2..9d70e5c 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
pll_con0 = __raw_readl(pll-con_reg);
pll_con1 = __raw_readl(pll-con_reg + 4);
- mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) ((pll-type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
sdiv = (pll_con0 PLL46XX_SDIV_SHIFT) PLL46XX_SDIV_MASK;
kdiv = pll-type == pll_4650c ? pll_con1 PLL4650C_KDIV_MASK :
pll_con1 PLL46XX_KDIV_MASK;
- shift = pll-type == pll_4600 ? 16 : 10;
+ shift = ((pll-type == pll_4600) || (pll-type == pll_1460x)) ? 16 : 10;
+
fvco *= (mdiv shift) + kdiv;
do_div(fvco, (pdiv sdiv));
fvco = shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,
unsigned long drate,
lock = 0x;
/* Set PLL PMS and VSEL values. */
- con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ if (pll-type == pll_1460x) {
+ con0 = ~((PLL1460X_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT));
+ } else {
+ con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT) |
(PLL46XX_VSEL_MASK PLL46XX_VSEL_SHIFT));
+ con0 |= rate-vsel PLL46XX_VSEL_SHIFT;
+ }
+
con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
(rate-pdiv PLL46XX_PDIV_SHIFT) |
- (rate-sdiv PLL46XX_SDIV_SHIFT) |
- (rate-vsel PLL46XX_VSEL_SHIFT);
+ (rate-sdiv PLL46XX_SDIV_SHIFT);
/* Set PLL K, MFR and MRR values. */
con1 = __raw_readl(pll-con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
/* clk_ops for 35xx and 2550 are similar */
case pll_35xx:
case pll_2550:
+ case pll_1450x:
+ case pll_1451x:
+ case pll_1452x:
if (!pll-rate_table)
init.ops = samsung_pll35xx_clk_min_ops;
else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
case pll_4600:
case pll_4650:
case pll_4650c:
+ case pll_1460x:
if (!pll-rate_table)
init.ops = samsung_pll46xx_clk_min_ops;
else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c0ed4d4..213de9a 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -33,6 +33,10 @@ enum samsung_pll_type {
pll_s3c2440_mpll,
pll_2550xx,
pll_2650xx,
+ pll_1450x,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
--
1.7.9.5
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[PATCH v4 2/8] clk: samsung: Factor out the common code to clk.c
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-exynos5260.c | 185 +-
drivers/clk/samsung/clk.c| 95 +
drivers/clk/samsung/clk.h| 34 +++
3 files changed, 155 insertions(+), 159 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97..b08ac19 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -11,10 +11,8 @@
#include linux/clk.h
#include linux/clkdev.h
-#include linux/clk-provider.h
#include linux/of.h
#include linux/of_address.h
-#include linux/syscore_ops.h
#include clk-exynos5260.h
#include clk.h
@@ -22,39 +20,6 @@
#include dt-bindings/clock/exynos5260-clk.h
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
- struct list_head node;
- void __iomem *reg_base;
- struct samsung_clk_reg_dump *rdump;
- unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
- /* list of pll clocks and respective count */
- struct samsung_pll_clock *pll_clks;
- unsigned int nr_pll_clks;
- /* list of mux clocks and respective count */
- struct samsung_mux_clock *mux_clks;
- unsigned int nr_mux_clks;
- /* list of div clocks and respective count */
- struct samsung_div_clock *div_clks;
- unsigned int nr_div_clks;
- /* list of gate clocks and respective count */
- struct samsung_gate_clock *gate_clks;
- unsigned int nr_gate_clks;
- /* list of fixed clocks and respective count */
- struct samsung_fixed_rate_clock *fixed_clks;
- unsigned int nr_fixed_clks;
- /* total number of clocks with IDs assigned*/
- unsigned int nr_clk_ids;
-
- /* list and number of clocks registers */
- unsigned long *clk_regs;
- unsigned int nr_clk_regs;
-};
-
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[]
__initdata = {
PLL_36XX_RATE(6600, 176, 2, 5, 0),
};
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_save(cache-reg_base, cache-rdump,
- cache-rd_num);
-
- return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_restore(cache-reg_base, cache-rdump,
- cache-rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
- .suspend = exynos5260_clk_suspend,
- .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump)
-{
- struct exynos5260_clock_reg_cache *reg_cache;
-
- reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
- GFP_KERNEL);
- if (!reg_cache)
- panic(could not allocate register cache.\n);
-
- reg_cache-rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
- if (!reg_cache-rdump)
- panic(could not allocate register dump storage.\n);
-
- if (list_empty(clock_reg_cache_list))
- register_syscore_ops(exynos5260_clk_syscore_ops);
-
- reg_cache-rd_num = nr_rdump;
- reg_cache-reg_base = reg_base;
- list_add_tail(reg_cache-node, clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
- struct exynos5260_cmu_info *cmu)
-{
- void __iomem *reg_base;
- struct samsung_clk_provider *ctx;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic(%s: failed to map registers\n, __func__);
-
- ctx = samsung_clk_init(np, reg_base, cmu-nr_clk_ids);
- if (!ctx)
- panic(%s: unable
[PATCH v4 3/8] clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk.c |3 +++
drivers/clk/samsung/clk.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index a043654..4b31267 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -402,6 +402,9 @@ void __init exynos_cmu_register_one(struct device_node *np,
if (cmu-fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu-fixed_clks,
cmu-nr_fixed_clks);
+ if (cmu-fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu-fixed_factor_clks,
+ cmu-nr_fixed_factor_clks);
if (cmu-clk_regs)
exynos_clk_sleep_init(reg_base, cmu-clk_regs,
cmu-nr_clk_regs);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 552d155..993b51c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -347,6 +347,9 @@ struct exynos_cmu_info {
/* list of fixed clocks and respective count */
struct samsung_fixed_rate_clock *fixed_clks;
unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
/* total number of clocks with IDs assigned*/
unsigned int nr_clk_ids;
--
1.7.9.5
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[PATCH v4 4/8] clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/exynos7-clock.txt| 37 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos7.c | 417
include/dt-bindings/clock/exynos7-clk.h| 39 ++
4 files changed, 494 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos7.c
create mode 100644 include/dt-bindings/clock/exynos7-clk.h
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 000..798eb10
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - fin_pll - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+ compatible strings to indicate the clock controller
+ functionality.
+
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+
+ - reg: physical base address of the controller and the length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000..3ea8d0e
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -0,0 +1,417 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Chatradhi ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+
+#include clk.h
+#include dt-bindings/clock/exynos7-clk.h
+
+/* Register Offset definitions for CMU_TOPC (0x1057) */
+#define CC_PLL_LOCK0x
+#define BUS0_PLL_LOCK 0x0004
+#define BUS1_DPLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000C
+#define AUD_PLL_LOCK 0x0010
+#define CC_PLL_CON00x0100
+#define BUS0_PLL_CON0 0x0110
+#define BUS1_DPLL_CON0 0x0120
+#define MFC_PLL_CON0 0x0130
+#define AUD_PLL_CON0 0x0140
+#define MUX_SEL_TOPC0 0x0200
+#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC1 0x0604
+#define DIV_TOPC3 0x060C
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
+ FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus0_pll_div4,
+ ffac_topc_bus0_pll_div2, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus1_pll_div2, mout_bus1_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_cc_pll_div2, mout_cc_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_mfc_pll_div2, mout_mfc_pll_ctrl, 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
+PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
+PNAME(mout_cc_pll_ctrl_p) = { fin_pll, fout_cc_pll };
+PNAME(mout_mfc_pll_ctrl_p) = { fin_pll, fout_mfc_pll };
+
+PNAME(mout_topc_group2)= { mout_sclk_bus0_pll_cmuc,
+ mout_sclk_bus1_pll_cmuc, mout_sclk_cc_pll_cmuc,
+ mout_sclk_mfc_pll_cmuc
[PATCH v4 5/8] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/Makefile |5 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 39 ++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 160 +++
4 files changed, 205 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/Makefile
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 309c3dc..b13bf21 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dts-dirs += apm
dts-dirs += arm
+dts-dirs += exynos
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/exynos/Makefile
b/arch/arm64/boot/dts/exynos/Makefile
new file mode 100644
index 000..20310e5
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..e2c8283
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,39 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ aliases {
+ serial0 = serial_2;
+ };
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..c5b1b86
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,160 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000
[PATCH v4 8/8] arm64: dts: add dt-bindings/ symlink
From: Pankaj Dubey pankaj.du...@samsung.com Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299aa8754 (kbuild: create an include chroot for DT bindings) merged in v3.10-rc1 for details. CC: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com --- arch/arm64/boot/dts/include/dt-bindings |1 + 1 file changed, 1 insertion(+) create mode 12 arch/arm64/boot/dts/include/dt-bindings diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings new file mode 12 index 000..08c00e4 --- /dev/null +++ b/arch/arm64/boot/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../../include/dt-bindings \ No newline at end of file -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v4 0/8] arch: arm64: enable support for Samsung Exynos7 SoC
Changes since v3: - Removed aliases for serial controllers from dtsi file and moved it into board specific dts file as suggested by Arnd. - Based this series on Robert Richter's patches for adding vendor device tree sub-directories for arm64. http://comments.gmane.org/gmane.linux.kbuild.devel/12131 This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next The following patches are required for this series. 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2- dts, kbuild: Implement support for dtb vendor subdirs patch set http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Alim Akhtar (1): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support Naveen Krishna Chatradhi (6): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 tty/serial: samsung: enable usage for 64-bit Exynos platforms Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/clock/exynos7-clock.txt| 37 ++ arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/Makefile|5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 39 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 160 arch/arm64/boot/dts/include/dt-bindings|1 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 417 drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ drivers/tty/serial/Kconfig |2 +- include/dt-bindings/clock/exynos7-clk.h| 39 ++ 16 files changed, 898 insertions(+), 165 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 6/8] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/8] clk: samsung: Factor out the common code to clk.c
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-exynos5260.c | 185 +-
drivers/clk/samsung/clk.c| 95 +
drivers/clk/samsung/clk.h| 34 +++
3 files changed, 155 insertions(+), 159 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97..b08ac19 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -11,10 +11,8 @@
#include linux/clk.h
#include linux/clkdev.h
-#include linux/clk-provider.h
#include linux/of.h
#include linux/of_address.h
-#include linux/syscore_ops.h
#include clk-exynos5260.h
#include clk.h
@@ -22,39 +20,6 @@
#include dt-bindings/clock/exynos5260-clk.h
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
- struct list_head node;
- void __iomem *reg_base;
- struct samsung_clk_reg_dump *rdump;
- unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
- /* list of pll clocks and respective count */
- struct samsung_pll_clock *pll_clks;
- unsigned int nr_pll_clks;
- /* list of mux clocks and respective count */
- struct samsung_mux_clock *mux_clks;
- unsigned int nr_mux_clks;
- /* list of div clocks and respective count */
- struct samsung_div_clock *div_clks;
- unsigned int nr_div_clks;
- /* list of gate clocks and respective count */
- struct samsung_gate_clock *gate_clks;
- unsigned int nr_gate_clks;
- /* list of fixed clocks and respective count */
- struct samsung_fixed_rate_clock *fixed_clks;
- unsigned int nr_fixed_clks;
- /* total number of clocks with IDs assigned*/
- unsigned int nr_clk_ids;
-
- /* list and number of clocks registers */
- unsigned long *clk_regs;
- unsigned int nr_clk_regs;
-};
-
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[]
__initdata = {
PLL_36XX_RATE(6600, 176, 2, 5, 0),
};
-#ifdef CONFIG_PM_SLEEP
-
-static int exynos5260_clk_suspend(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_save(cache-reg_base, cache-rdump,
- cache-rd_num);
-
- return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_restore(cache-reg_base, cache-rdump,
- cache-rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
- .suspend = exynos5260_clk_suspend,
- .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump)
-{
- struct exynos5260_clock_reg_cache *reg_cache;
-
- reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
- GFP_KERNEL);
- if (!reg_cache)
- panic(could not allocate register cache.\n);
-
- reg_cache-rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
- if (!reg_cache-rdump)
- panic(could not allocate register dump storage.\n);
-
- if (list_empty(clock_reg_cache_list))
- register_syscore_ops(exynos5260_clk_syscore_ops);
-
- reg_cache-rd_num = nr_rdump;
- reg_cache-reg_base = reg_base;
- list_add_tail(reg_cache-node, clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
- struct exynos5260_cmu_info *cmu)
-{
- void __iomem *reg_base;
- struct samsung_clk_provider *ctx;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic(%s: failed to map registers\n, __func__);
-
- ctx = samsung_clk_init(np, reg_base, cmu-nr_clk_ids);
- if (!ctx)
- panic(%s: unable
[PATCH v3 0/8] arch: arm64: enable support for Samsung Exynos7 SoC
This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next The following patches are required for this series. 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html Alim Akhtar (1): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support Naveen Krishna Chatradhi (6): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 tty/serial: samsung: enable usage for 64-bit Exynos platforms Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/clock/exynos7-clock.txt| 37 ++ arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 35 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 167 arch/arm64/boot/dts/include/dt-bindings|1 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 438 drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ drivers/tty/serial/Kconfig |2 +- include/dt-bindings/clock/exynos7-clk.h| 55 +++ 15 files changed, 933 insertions(+), 165 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 4/8] clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/exynos7-clock.txt| 37 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos7.c | 438
include/dt-bindings/clock/exynos7-clk.h| 55 +++
4 files changed, 531 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos7.c
create mode 100644 include/dt-bindings/clock/exynos7-clk.h
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 000..798eb10
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - fin_pll - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+ compatible strings to indicate the clock controller
+ functionality.
+
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+
+ - reg: physical base address of the controller and the length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000..25e12b3
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -0,0 +1,438 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Chatradhi ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+
+#include clk.h
+#include dt-bindings/clock/exynos7-clk.h
+
+/* Register Offset definitions for CMU_TOPC (0x1057) */
+#define CC_PLL_LOCK0x
+#define BUS0_PLL_LOCK 0x0004
+#define BUS1_DPLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000C
+#define AUD_PLL_LOCK 0x0010
+#define CC_PLL_CON00x0100
+#define BUS0_PLL_CON0 0x0110
+#define BUS1_DPLL_CON0 0x0120
+#define MFC_PLL_CON0 0x0130
+#define AUD_PLL_CON0 0x0140
+#define AUD_PLL_CON1 0x0144
+#define AUD_PLL_CON2 0x0148
+#define MIF_PLL_CON0 0x0150
+#define MIF_PLL_CON1 0x0154
+#define MIF_PLL_CON2 0x0158
+#define MUX_SEL_TOPC0 0x0200
+#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC1 0x0604
+#define DIV_TOPC3 0x060C
+#define ENABLE_ACLK_TOPC1 0x0804
+#define ENABLE_SCLK_TOPC1 0x0A04
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
+ FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus0_pll_div4,
+ ffac_topc_bus0_pll_div2, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus1_pll_div2, mout_bus1_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_cc_pll_div2, mout_cc_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_mfc_pll_div2, mout_mfc_pll_ctrl, 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
+PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
+PNAME
[PATCH v3 5/8] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 35 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 167 +++
3 files changed, 203 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..a3bc18a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos/exynos7-espresso.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..4f69991
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,35 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+fin_pll {
+ clock-frequency = 2400;
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..56ec5f4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,167 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000
[PATCH v3 8/8] arm64: dts: add dt-bindings/ symlink
From: Pankaj Dubey pankaj.du...@samsung.com Add symlink to include/dt-bindings from arch/arm64/boot/dts/include/ to match the ones in ARM architectures so that preprocessed device tree files can include various useful constant definitions. See commit c58299aa8754 (kbuild: create an include chroot for DT bindings) merged in v3.10-rc1 for details. CC: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com --- arch/arm64/boot/dts/include/dt-bindings |1 + 1 file changed, 1 insertion(+) create mode 12 arch/arm64/boot/dts/include/dt-bindings diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings new file mode 12 index 000..08c00e4 --- /dev/null +++ b/arch/arm64/boot/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../../include/dt-bindings \ No newline at end of file -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 3/8] clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk.c |3 +++
drivers/clk/samsung/clk.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index a043654..4b31267 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -402,6 +402,9 @@ void __init exynos_cmu_register_one(struct device_node *np,
if (cmu-fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu-fixed_clks,
cmu-nr_fixed_clks);
+ if (cmu-fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu-fixed_factor_clks,
+ cmu-nr_fixed_factor_clks);
if (cmu-clk_regs)
exynos_clk_sleep_init(reg_base, cmu-clk_regs,
cmu-nr_clk_regs);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 552d155..993b51c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -347,6 +347,9 @@ struct exynos_cmu_info {
/* list of fixed clocks and respective count */
struct samsung_fixed_rate_clock *fixed_clks;
unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
/* total number of clocks with IDs assigned*/
unsigned int nr_clk_ids;
--
1.7.9.5
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[PATCH v3 1/8] clk: samsung: add support for 145xx and 1460x PLLs
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 25 -
drivers/clk/samsung/clk-pll.h |4
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2..9d70e5c 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
pll_con0 = __raw_readl(pll-con_reg);
pll_con1 = __raw_readl(pll-con_reg + 4);
- mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) ((pll-type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
sdiv = (pll_con0 PLL46XX_SDIV_SHIFT) PLL46XX_SDIV_MASK;
kdiv = pll-type == pll_4650c ? pll_con1 PLL4650C_KDIV_MASK :
pll_con1 PLL46XX_KDIV_MASK;
- shift = pll-type == pll_4600 ? 16 : 10;
+ shift = ((pll-type == pll_4600) || (pll-type == pll_1460x)) ? 16 : 10;
+
fvco *= (mdiv shift) + kdiv;
do_div(fvco, (pdiv sdiv));
fvco = shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,
unsigned long drate,
lock = 0x;
/* Set PLL PMS and VSEL values. */
- con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ if (pll-type == pll_1460x) {
+ con0 = ~((PLL1460X_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT));
+ } else {
+ con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT) |
(PLL46XX_VSEL_MASK PLL46XX_VSEL_SHIFT));
+ con0 |= rate-vsel PLL46XX_VSEL_SHIFT;
+ }
+
con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
(rate-pdiv PLL46XX_PDIV_SHIFT) |
- (rate-sdiv PLL46XX_SDIV_SHIFT) |
- (rate-vsel PLL46XX_VSEL_SHIFT);
+ (rate-sdiv PLL46XX_SDIV_SHIFT);
/* Set PLL K, MFR and MRR values. */
con1 = __raw_readl(pll-con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
/* clk_ops for 35xx and 2550 are similar */
case pll_35xx:
case pll_2550:
+ case pll_1450x:
+ case pll_1451x:
+ case pll_1452x:
if (!pll-rate_table)
init.ops = samsung_pll35xx_clk_min_ops;
else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
case pll_4600:
case pll_4650:
case pll_4650c:
+ case pll_1460x:
if (!pll-rate_table)
init.ops = samsung_pll46xx_clk_min_ops;
else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c0ed4d4..213de9a 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -33,6 +33,10 @@ enum samsung_pll_type {
pll_s3c2440_mpll,
pll_2550xx,
pll_2650xx,
+ pll_1450x,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
--
1.7.9.5
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[PATCH v3 7/8] tty/serial: samsung: enable usage for 64-bit Exynos platforms
Allow Samsung serial driver to be usable on Exynos 64-bit SoC based platforms. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- drivers/tty/serial/Kconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 26cec64..3383744 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -220,7 +220,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate Samsung SoC serial support - depends on PLAT_SAMSUNG + depends on PLAT_SAMSUNG || ARCH_EXYNOS select SERIAL_CORE help Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] tty/serial: fix config dependencies for samsung serial
From: Pankaj Dubey pankaj.du...@samsung.com Make the config symbols SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS depend on SERIAL_SAMSUNG rather than PLAT_SAMSUNG. Signed-off-by: Pankaj Dubey pankaj.du...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Greg Kroah-Hartman gre...@linuxfoundation.org --- drivers/tty/serial/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 26cec64..4f27f0c 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -230,14 +230,14 @@ config SERIAL_SAMSUNG config SERIAL_SAMSUNG_UARTS_4 bool - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442) help Internal node for the common case of 4 Samsung compatible UARTs config SERIAL_SAMSUNG_UARTS int - depends on PLAT_SAMSUNG + depends on SERIAL_SAMSUNG default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416 default 3 help -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] irqchip: exynos-combiner: Fix compilation error on ARM64
The following compilation error occurs on 64-bit Exynos7 SoC: drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’: drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of function ‘set_irq_flags’ [-Werror=implicit-function-declaration] set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ^ drivers/irqchip/exynos-combiner.c:162:21: error: ‘IRQF_VALID’ undeclared (first use in this function) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ^ drivers/irqchip/exynos-combiner.c:162:21: note: each undeclared identifier is reported only once for each function it appears in drivers/irqchip/exynos-combiner.c:162:34: error: ‘IRQF_PROBE’ undeclared (first use in this function) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); Fix the build error by including asm/hardirq.h. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Thomas Gleixner t...@linutronix.de --- drivers/irqchip/exynos-combiner.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index f8636a6..7fbedcc 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -18,6 +18,8 @@ #include linux/of_address.h #include linux/of_irq.h +#include asm/hardirq.h + #include irqchip.h #define COMBINER_ENABLE_SET0x0 -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/7] arch: arm64: enable support for Samsung Exynos7 SoC
Changes since v1: - Reduced the number of features targetted for the initial platform support. This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. NOTE: We tested these patches with the arm64: dts: add dt-bindings/ symlink change posted @ https://lkml.org/lkml/2014/9/1/688 The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next The following patches are required for this series. 1- irqchip: exynos-combiner: Fix compilation error on ARM64 https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36209.html 2- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html Alim Akhtar (1): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support Naveen Krishna Chatradhi (6): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC tty/serial: samsung: enable usage for 64-bit Exynos platforms arm64: dts: Add initial device tree support for EXYNOS7 .../devicetree/bindings/clock/exynos7-clock.txt| 37 ++ arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 31 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 168 drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5260.c | 183 ++-- drivers/clk/samsung/clk-exynos7.c | 438 drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ drivers/tty/serial/Kconfig |2 +- include/dt-bindings/clock/exynos7-clk.h| 55 +++ 14 files changed, 929 insertions(+), 163 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/7] clk: samsung: add support for 145xx and 1460x PLLs
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-pll.c | 25 -
drivers/clk/samsung/clk-pll.h |4
2 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2..9d70e5c 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
@@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
pll_con0 = __raw_readl(pll-con_reg);
pll_con1 = __raw_readl(pll-con_reg + 4);
- mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) ((pll-type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
sdiv = (pll_con0 PLL46XX_SDIV_SHIFT) PLL46XX_SDIV_MASK;
kdiv = pll-type == pll_4650c ? pll_con1 PLL4650C_KDIV_MASK :
pll_con1 PLL46XX_KDIV_MASK;
- shift = pll-type == pll_4600 ? 16 : 10;
+ shift = ((pll-type == pll_4600) || (pll-type == pll_1460x)) ? 16 : 10;
+
fvco *= (mdiv shift) + kdiv;
do_div(fvco, (pdiv sdiv));
fvco = shift;
@@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,
unsigned long drate,
lock = 0x;
/* Set PLL PMS and VSEL values. */
- con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ if (pll-type == pll_1460x) {
+ con0 = ~((PLL1460X_MDIV_MASK PLL46XX_MDIV_SHIFT) |
+ (PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
+ (PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT));
+ } else {
+ con0 = ~((PLL46XX_MDIV_MASK PLL46XX_MDIV_SHIFT) |
(PLL46XX_PDIV_MASK PLL46XX_PDIV_SHIFT) |
(PLL46XX_SDIV_MASK PLL46XX_SDIV_SHIFT) |
(PLL46XX_VSEL_MASK PLL46XX_VSEL_SHIFT));
+ con0 |= rate-vsel PLL46XX_VSEL_SHIFT;
+ }
+
con0 |= (rate-mdiv PLL46XX_MDIV_SHIFT) |
(rate-pdiv PLL46XX_PDIV_SHIFT) |
- (rate-sdiv PLL46XX_SDIV_SHIFT) |
- (rate-vsel PLL46XX_VSEL_SHIFT);
+ (rate-sdiv PLL46XX_SDIV_SHIFT);
/* Set PLL K, MFR and MRR values. */
con1 = __raw_readl(pll-con_reg + 0x4);
@@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
/* clk_ops for 35xx and 2550 are similar */
case pll_35xx:
case pll_2550:
+ case pll_1450x:
+ case pll_1451x:
+ case pll_1452x:
if (!pll-rate_table)
init.ops = samsung_pll35xx_clk_min_ops;
else
@@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct
samsung_clk_provider *ctx,
case pll_4600:
case pll_4650:
case pll_4650c:
+ case pll_1460x:
if (!pll-rate_table)
init.ops = samsung_pll46xx_clk_min_ops;
else
diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h
index c0ed4d4..213de9a 100644
--- a/drivers/clk/samsung/clk-pll.h
+++ b/drivers/clk/samsung/clk-pll.h
@@ -33,6 +33,10 @@ enum samsung_pll_type {
pll_s3c2440_mpll,
pll_2550xx,
pll_2650xx,
+ pll_1450x,
+ pll_1451x,
+ pll_1452x,
+ pll_1460x,
};
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
--
1.7.9.5
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[PATCH v2 3/7] clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
Add the fields fixed_factor_clks and nr_fixed_factor_clks to
struct exynos_cmu_info to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk.c |3 +++
drivers/clk/samsung/clk.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index a043654..4b31267 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -402,6 +402,9 @@ void __init exynos_cmu_register_one(struct device_node *np,
if (cmu-fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu-fixed_clks,
cmu-nr_fixed_clks);
+ if (cmu-fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu-fixed_factor_clks,
+ cmu-nr_fixed_factor_clks);
if (cmu-clk_regs)
exynos_clk_sleep_init(reg_base, cmu-clk_regs,
cmu-nr_clk_regs);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 552d155..993b51c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -347,6 +347,9 @@ struct exynos_cmu_info {
/* list of fixed clocks and respective count */
struct samsung_fixed_rate_clock *fixed_clks;
unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
/* total number of clocks with IDs assigned*/
unsigned int nr_clk_ids;
--
1.7.9.5
--
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[PATCH v2 2/7] clk: samsung: Factor out the common code to clk.c
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
---
drivers/clk/samsung/clk-exynos5260.c | 183 +-
drivers/clk/samsung/clk.c| 95 ++
drivers/clk/samsung/clk.h| 34 +++
3 files changed, 155 insertions(+), 157 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97..d72c982 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -11,10 +11,8 @@
#include linux/clk.h
#include linux/clkdev.h
-#include linux/clk-provider.h
#include linux/of.h
#include linux/of_address.h
-#include linux/syscore_ops.h
#include clk-exynos5260.h
#include clk.h
@@ -22,39 +20,6 @@
#include dt-bindings/clock/exynos5260-clk.h
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
- struct list_head node;
- void __iomem *reg_base;
- struct samsung_clk_reg_dump *rdump;
- unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
- /* list of pll clocks and respective count */
- struct samsung_pll_clock *pll_clks;
- unsigned int nr_pll_clks;
- /* list of mux clocks and respective count */
- struct samsung_mux_clock *mux_clks;
- unsigned int nr_mux_clks;
- /* list of div clocks and respective count */
- struct samsung_div_clock *div_clks;
- unsigned int nr_div_clks;
- /* list of gate clocks and respective count */
- struct samsung_gate_clock *gate_clks;
- unsigned int nr_gate_clks;
- /* list of fixed clocks and respective count */
- struct samsung_fixed_rate_clock *fixed_clks;
- unsigned int nr_fixed_clks;
- /* total number of clocks with IDs assigned*/
- unsigned int nr_clk_ids;
-
- /* list and number of clocks registers */
- unsigned long *clk_regs;
- unsigned int nr_clk_regs;
-};
-
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -115,102 +80,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[]
__initdata = {
#ifdef CONFIG_PM_SLEEP
-static int exynos5260_clk_suspend(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_save(cache-reg_base, cache-rdump,
- cache-rd_num);
-
- return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_restore(cache-reg_base, cache-rdump,
- cache-rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
- .suspend = exynos5260_clk_suspend,
- .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump)
-{
- struct exynos5260_clock_reg_cache *reg_cache;
-
- reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
- GFP_KERNEL);
- if (!reg_cache)
- panic(could not allocate register cache.\n);
-
- reg_cache-rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
- if (!reg_cache-rdump)
- panic(could not allocate register dump storage.\n);
-
- if (list_empty(clock_reg_cache_list))
- register_syscore_ops(exynos5260_clk_syscore_ops);
-
- reg_cache-rd_num = nr_rdump;
- reg_cache-reg_base = reg_base;
- list_add_tail(reg_cache-node, clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
- struct exynos5260_cmu_info *cmu)
-{
- void __iomem *reg_base;
- struct samsung_clk_provider *ctx;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic(%s: failed to map registers\n, __func__);
-
- ctx = samsung_clk_init(np, reg_base, cmu-nr_clk_ids);
- if (!ctx)
- panic(%s: unable to alllocate ctx\n, __func__);
-
- if (cmu-pll_clks
[PATCH v2 5/7] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC and board dts file
to support Espresso board based on Exynos7 SoC.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile|1 +
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 31 +
arch/arm64/boot/dts/exynos/exynos7.dtsi | 168 +++
3 files changed, 200 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..a3bc18a 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos/exynos7-espresso.dtb
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
new file mode 100644
index 000..f6a8879
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts
@@ -0,0 +1,31 @@
+/*
+ * SAMSUNG Exynos7 Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos7.dtsi
+
+/ {
+ model = Samsung Exynos7 Espresso board based on EXYNOS7;
+ compatible = samsung,exynos7-espresso, samsung,exynos7;
+
+ chosen {
+ linux,stdout-path = serial_2;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x0 0x4000 0x0 0xC000;
+ };
+};
+
+serial_2 {
+ status = okay;
+};
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi
b/arch/arm64/boot/dts/exynos/exynos7.dtsi
new file mode 100644
index 000..e593af55
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@ -0,0 +1,168 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 2;
+ #size-cells = 2;
+
+ aliases {
+ serial0 = serial_0;
+ serial1 = serial_1;
+ serial2 = serial_2;
+ serial3 = serial_3;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x1;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ enable-method = psci;
+ reg = 0x3;
+ };
+ };
+
+ psci {
+ compatible = arm,psci-0.2;
+ method = smc;
+ };
+
+ soc: soc {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 0 0 0x1800;
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000
[PATCH v2 7/7] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 12 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..b4d1dc2 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,18 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS + bool + help + This enables support for Samsung Exynos SoC family + +config ARCH_EXYNOS7 + bool ARMv8 based Samsung Exynos7 + select ARCH_EXYNOS + select COMMON_CLK_SAMSUNG + help + This enables support for Samsung Exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/7] clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
---
.../devicetree/bindings/clock/exynos7-clock.txt| 37 ++
drivers/clk/samsung/Makefile |1 +
drivers/clk/samsung/clk-exynos7.c | 438
include/dt-bindings/clock/exynos7-clk.h| 55 +++
4 files changed, 531 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos7.c
create mode 100644 include/dt-bindings/clock/exynos7-clk.h
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 000..798eb10
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - fin_pll - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+ compatible strings to indicate the clock controller
+ functionality.
+
+ - samsung,exynos7-clock-topc
+ - samsung,exynos7-clock-top0
+ - samsung,exynos7-clock-peric0
+ - samsung,exynos7-clock-peric1
+ - samsung,exynos7-clock-peris
+
+ - reg: physical base address of the controller and the length of
+ memory mapped region.
+
+ - #clock-cells: should be 1.
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..5da0ba9 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
obj-$(CONFIG_ARCH_S5PV210) += clk-s5pv210.o clk-s5pv210-audss.o
+obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
diff --git a/drivers/clk/samsung/clk-exynos7.c
b/drivers/clk/samsung/clk-exynos7.c
new file mode 100644
index 000..25e12b3
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -0,0 +1,438 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Chatradhi ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+
+#include clk.h
+#include dt-bindings/clock/exynos7-clk.h
+
+/* Register Offset definitions for CMU_TOPC (0x1057) */
+#define CC_PLL_LOCK0x
+#define BUS0_PLL_LOCK 0x0004
+#define BUS1_DPLL_LOCK 0x0008
+#define MFC_PLL_LOCK 0x000C
+#define AUD_PLL_LOCK 0x0010
+#define CC_PLL_CON00x0100
+#define BUS0_PLL_CON0 0x0110
+#define BUS1_DPLL_CON0 0x0120
+#define MFC_PLL_CON0 0x0130
+#define AUD_PLL_CON0 0x0140
+#define AUD_PLL_CON1 0x0144
+#define AUD_PLL_CON2 0x0148
+#define MIF_PLL_CON0 0x0150
+#define MIF_PLL_CON1 0x0154
+#define MIF_PLL_CON2 0x0158
+#define MUX_SEL_TOPC0 0x0200
+#define MUX_SEL_TOPC1 0x0204
+#define MUX_SEL_TOPC3 0x020C
+#define DIV_TOPC1 0x0604
+#define DIV_TOPC3 0x060C
+#define ENABLE_ACLK_TOPC1 0x0804
+#define ENABLE_SCLK_TOPC1 0x0A04
+
+static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata =
{
+ FFACTOR(0, ffac_topc_bus0_pll_div2, mout_bus0_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus0_pll_div4,
+ ffac_topc_bus0_pll_div2, 1, 2, 0),
+ FFACTOR(0, ffac_topc_bus1_pll_div2, mout_bus1_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_cc_pll_div2, mout_cc_pll_ctrl, 1, 2, 0),
+ FFACTOR(0, ffac_topc_mfc_pll_div2, mout_mfc_pll_ctrl, 1, 2, 0),
+};
+
+/* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_bus0_pll_ctrl_p)= { fin_pll, fout_bus0_pll };
+PNAME(mout_bus1_pll_ctrl_p)= { fin_pll, fout_bus1_pll };
+PNAME
[PATCH v2] irqchip: exynos-combiner: Fix compilation error on ARM64
The following compilation error occurs on 64-bit Exynos7 SoC: drivers/irqchip/exynos-combiner.c: In function ‘combiner_irq_domain_map’: drivers/irqchip/exynos-combiner.c:162:2: error: implicit declaration of function ‘set_irq_flags’ [-Werror=implicit-function-declaration] set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ^ drivers/irqchip/exynos-combiner.c:162:21: error: ‘IRQF_VALID’ undeclared (first use in this function) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ^ drivers/irqchip/exynos-combiner.c:162:21: note: each undeclared identifier is reported only once for each function it appears in drivers/irqchip/exynos-combiner.c:162:34: error: ‘IRQF_PROBE’ undeclared (first use in this function) set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); Fix the build error by including linux/interrupt.h. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Thomas Gleixner t...@linutronix.de Cc: Jason Cooper ja...@lakedaemon.net Cc: Sudeep Holla sudeep.ho...@arm.com --- Changes since v1: Used linux/interrupt.h instead of asm/hardirq.h drivers/irqchip/exynos-combiner.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c index f8636a6..5945223 100644 --- a/drivers/irqchip/exynos-combiner.c +++ b/drivers/irqchip/exynos-combiner.c @@ -15,6 +15,7 @@ #include linux/slab.h #include linux/irqdomain.h #include linux/irqchip/chained_irq.h +#include linux/interrupt.h #include linux/of_address.h #include linux/of_irq.h -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/14] arm64: dts: Add initial device tree support for EXYNOS7
Add initial device tree nodes for EXYNOS7 SoC.
Also, includes the dt-binding definitions for clock ids.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/exynos7.dtsi | 553 ++
1 file changed, 553 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7.dtsi
diff --git a/arch/arm64/boot/dts/exynos7.dtsi b/arch/arm64/boot/dts/exynos7.dtsi
new file mode 100644
index 000..6b9eaf4
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7.dtsi
@@ -0,0 +1,553 @@
+/*
+ * SAMSUNG EXYNOS7 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS7 SoC device nodes are listed in this file.
+ * EXYNOS7 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos7-clk.h
+
+/ {
+ compatible = samsung,exynos7;
+ interrupt-parent = gic;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ pinctrl0 = pinctrl_0;
+ pinctrl1 = pinctrl_1;
+ pinctrl2 = pinctrl_2;
+ pinctrl3 = pinctrl_3;
+ pinctrl4 = pinctrl_4;
+ pinctrl5 = pinctrl_5;
+ pinctrl6 = pinctrl_6;
+ pinctrl7 = pinctrl_7;
+ pinctrl8 = pinctrl_8;
+ pinctrl9 = pinctrl_9;
+ mshc0 = mmc_0;
+ mshc2 = mmc_2;
+ };
+
+ chipid@1000 {
+ compatible = samsung,exynos4210-chipid;
+ reg = 0x1000 0x100;
+ };
+
+ cpus {
+ #address-cells = 2;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a57, arm,armv8;
+ reg = 0x0 0x0;
+ };
+ };
+
+ fin_pll: xxti {
+ compatible = fixed-clock;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ #clock-cells = 0;
+ };
+
+ gic: interrupt-controller@11001000 {
+ compatible = arm,gic-400;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x11001000 0x1000,
+ 0x11002000 0x1000,
+ 0x11004000 0x2000,
+ 0x11006000 0x2000;
+ };
+
+ hsi2c_0: hsi2c@1364 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1364 0x1000;
+ interrupts = 0 441 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c0_bus;
+ clocks = clock_peric0 PCLK_HSI2C0;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_1: hsi2c@1365 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1365 0x1000;
+ interrupts = 0 442 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c1_bus;
+ clocks = clock_peric0 PCLK_HSI2C1;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_2: hsi2c@14E6 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x14E6 0x1000;
+ interrupts = 0 459 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c2_bus;
+ clocks = clock_peric1 PCLK_HSI2C2;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_3: hsi2c@14E7 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x14E7 0x1000;
+ interrupts = 0 460 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c3_bus;
+ clocks = clock_peric1 PCLK_HSI2C3;
+ clock-names = hsi2c;
+ status = disabled;
+ };
+
+ hsi2c_4: hsi2c@1366 {
+ compatible = samsung,exynos7-hsi2c;
+ reg = 0x1366 0x1000;
+ interrupts = 0 443 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ pinctrl-names = default;
+ pinctrl-0 = hs_i2c4_bus;
+ clocks = clock_peric0 PCLK_HSI2C4
[PATCH 10/14] arm64: dts: add pinctrl support to EXYNOS7
Add the required pin configuration support to EXYNOS7
using pinctrl interface.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Thomas Abraham thomas...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/exynos7-pinctrl.dtsi | 691 ++
1 file changed, 691 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/boot/dts/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos7-pinctrl.dtsi
new file mode 100644
index 000..96e9d99
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7-pinctrl.dtsi
@@ -0,0 +1,691 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ /* ALIVE block @1058 */
+ pinctrl@1058 {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ interrupt-parent = gic;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+ };
+
+ /* AUD block @114B */
+ pinctrl@114B {
+ gpz0: gpz0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpz1: gpz1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+ };
+
+ /* BUS0 block @1347 */
+ pinctrl@1347 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd5: gpd5 {
+ gpio
[PATCH 12/14] arm64: dts: add Exynos7 based Espresso board dts file
This patch adds initial dts file for the Espresso board
based on Exynos7 from Samsung.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
---
arch/arm64/boot/dts/Makefile |1 +
arch/arm64/boot/dts/exynos7-espresso.dts | 69 ++
2 files changed, 70 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos7-espresso.dts
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index c52bdb0..d160de1 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
targets += dtbs
targets += $(dtb-y)
diff --git a/arch/arm64/boot/dts/exynos7-espresso.dts
b/arch/arm64/boot/dts/exynos7-espresso.dts
new file mode 100644
index 000..e35e83c
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos7-espresso.dts
@@ -0,0 +1,69 @@
+/*
+ * SAMSUNG Espresso board device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include dt-bindings/gpio/gpio.h
+#include exynos7.dtsi
+
+/ {
+ model = Samsung ESPRESSO board based on EXYNOS7;
+ compatible = samsung,espresso, samsung,exynos7;
+
+ chosen {
+ bootargs = console=ttySAC2,115200n8 root=/dev/ram0
ramdisk=16384 initrd=0x4200,16M init=/linuxrc;
+ };
+
+ memory@4000 {
+ device_type = memory;
+ reg = 0x4000 0xC000;
+ };
+
+ mmc@1574 {
+ status = okay;
+ num-slots = 1;
+ broken-cd;
+ caps2-mmc-hs200-1_8v;
+ supports-highspeed;
+ non-removable;
+ card-detect-delay = 200;
+ clock-frequency = 8;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd0_clk sd0_cmd sd0_rdqs sd0_bus1 sd0_bus4
sd0_bus8;
+ bus-width = 8;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1556 {
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ clock-frequency = 4;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ pinctrl-names = default;
+ pinctrl-0 = sd2_clk sd2_cmd sd2_cd sd2_bus1 sd2_bus4;
+ bus-width = 4;
+
+ slot@0 {
+ reg = 0;
+ disable-wp;
+ bus-width = 4;
+ };
+ };
+};
--
1.7.9.5
--
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[PATCH 13/14] arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support
From: Alim Akhtar alim.akh...@samsung.com This patch adds the necessary Kconfig entries to enable support for the ARMv8 based Exynos7 SoC. Signed-off-by: Alim Akhtar alim.akh...@samsung.com Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Rob Herring r...@kernel.org Cc: Catalin Marinas catalin.mari...@arm.com --- arch/arm64/Kconfig | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index fd4e81a..d58 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -134,6 +134,23 @@ source kernel/Kconfig.freezer menu Platform selection +config ARCH_EXYNOS7 + bool ARMv8 based SAMSUNG EXYNOS7 + select HAVE_S3C2410_WATCHDOG if WATCHDOG + select CLKSRC_OF + select COMMON_CLK_SAMSUNG + select GPIOLIB + select PINCTRL + select PINCTRL_EXYNOS + select RTC_CLASS + select HAVE_S3C_RTC + select GENERIC_GPIO + select ARCH_REQUIRE_GPIOLIB + select HAVE_CLK + select HAVE_SMP + help + This enables support for SAMSUNG exynos7 SoC family + config ARCH_VEXPRESS bool ARMv8 software model (Versatile Express) select ARCH_REQUIRE_GPIOLIB -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/14] i2c: exynos5: Add Kconfig dependencies
The i2c-exynos5.c driver can be reused for the HSI2C controller on Exynos7 SoCs from Samsung. This patch adds the Kconfig dependency to choose i2c-exynos5.c for CONFIG_ARCH_EXYNOS7. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com To: linux-...@vger.kernel.org Cc: Wolfram Sang w...@the-dreams.de --- drivers/i2c/busses/Kconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 2ac87fa..bd18fa6 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -465,7 +465,7 @@ config I2C_EG20T config I2C_EXYNOS5 tristate Exynos5 high-speed I2C driver - depends on ARCH_EXYNOS5 OF + depends on (ARCH_EXYNOS5 || ARCH_EXYNOS7) OF default y help High-speed I2C controller on Exynos5 based Samsung SoCs. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 07/14] i2c: exynos: add support for HSI2C module on Exynos7
The HSI2C module on Exynos7 differs in the transfer status
bits. Transfer status bits were moved to INT_ENABLE and
INT_STATUS registers
This patch adds support for the HSI2C module on Exynos7.
1. Implementes a hw field in the variant struct to distinguish
the hardware.
2. Updates the dt-new compatible in dt-binding documenation
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-...@vger.kernel.org
Cc: Wolfram Sang w...@the-dreams.de
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|2 +
drivers/i2c/busses/i2c-exynos5.c | 71 ++--
2 files changed, 67 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index d4745e3..2dbc0b6 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -12,6 +12,8 @@ Required properties:
on Exynos5250 and Exynos5420 SoCs.
- samsung,exynos5260-hsi2c, for i2c compatible with HSI2C available
on Exynos5260 SoCs.
+ - samsung,exynos7-hsi2c, for i2c compatible with HSI2C available
+ on Exynos7 SoCs.
- reg: physical base address of the controller and length of memory mapped
region.
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 28073f1..81e6263 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -83,7 +83,6 @@
#define HSI2C_INT_TX_ALMOSTEMPTY_EN(1u 0)
#define HSI2C_INT_RX_ALMOSTFULL_EN (1u 1)
#define HSI2C_INT_TRAILING_EN (1u 6)
-#define HSI2C_INT_I2C_EN (1u 9)
/* I2C_INT_STAT Register bits */
#define HSI2C_INT_TX_ALMOSTEMPTY (1u 0)
@@ -95,6 +94,17 @@
#define HSI2C_INT_TRAILING (1u 6)
#define HSI2C_INT_I2C (1u 9)
+#define HSI2C_INT_TRANS_DONE (1u 7)
+#define HSI2C_INT_TRANS_ABORT (1u 8)
+#define HSI2C_INT_NO_DEV_ACK (1u 9)
+#define HSI2C_INT_NO_DEV (1u 10)
+#define HSI2C_INT_TIMEOUT (1u 11)
+#define HSI2C_INT_I2C_TRANS(HSI2C_INT_TRANS_DONE | \
+ HSI2C_INT_TRANS_ABORT | \
+ HSI2C_INT_NO_DEV_ACK | \
+ HSI2C_INT_NO_DEV | \
+ HSI2C_INT_TIMEOUT)
+
/* I2C_FIFO_STAT Register bits */
#define HSI2C_RX_FIFO_EMPTY(1u 24)
#define HSI2C_RX_FIFO_FULL (1u 23)
@@ -143,6 +153,8 @@
#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
+#define HSI2C_EXYNOS7 BIT(0)
+
struct exynos5_i2c {
struct i2c_adapter adap;
unsigned intsuspended:1;
@@ -192,6 +204,7 @@ struct exynos5_i2c {
*/
struct exynos_hsi2c_variant {
unsigned intfifo_depth;
+ unsigned inthw;
};
static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
@@ -202,6 +215,11 @@ static const struct exynos_hsi2c_variant
exynos5260_hsi2c_data = {
.fifo_depth = 16,
};
+static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
+ .fifo_depth = 16,
+ .hw = HSI2C_EXYNOS7,
+};
+
static const struct of_device_id exynos5_i2c_match[] = {
{
.compatible = samsung,exynos5-hsi2c,
@@ -212,6 +230,9 @@ static const struct of_device_id exynos5_i2c_match[] = {
}, {
.compatible = samsung,exynos5260-hsi2c,
.data = exynos5260_hsi2c_data
+ }, {
+ .compatible = samsung,exynos7-hsi2c,
+ .data = exynos7_hsi2c_data
}, {},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
@@ -256,13 +277,24 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c
*i2c, int mode)
i2c-hs_clock : i2c-fs_clock;
/*
+* In case of HSI2C controller in Exynos5 series
* FPCLK / FI2C =
* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
+*
+* In case of HSI2C controllers in Exynos7 series
+* FPCLK / FI2C =
+* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
+*
* utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
* utemp1 = (TSCLK_L + TSCLK_H + 2)
*/
t_ftl_cycle = (readl(i2c-regs + HSI2C_CONF) 16) 0x7;
- utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
+ utemp0 = (clkin / op_clk) - 8;
+
+ if (i2c-variant-hw == HSI2C_EXYNOS7)
+ utemp0 -= t_ftl_cycle;
+ else
+ utemp0 -= 2 * t_ftl_cycle;
/* CLK_DIV max is 256 */
for (div = 0; div 256
[PATCH 09/14] watchdog: s3c2410_wdt: Add support for Watchdog device on Exynos7
Exynos7 SoC has a Watchdog for Atlas (A57) cores
This patch adds support for the Atlas watchdog.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Wim Van Sebroeck w...@iguana.be
---
.../devicetree/bindings/watchdog/samsung-wdt.txt |1 +
drivers/watchdog/s3c2410_wdt.c | 11 +++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index cfff375..8f3d96a 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -9,6 +9,7 @@ Required properties:
(a) samsung,s3c2410-wdt for Exynos4 and previous SoCs
(b) samsung,exynos5250-wdt for Exynos5250
(c) samsung,exynos5420-wdt for Exynos5420
+ (c) samsung,exynos7-wdt for Exynos7
- reg : base physical address of the controller and length of memory mapped
region.
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 7c6ccd0..015256e 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -155,6 +155,15 @@ static const struct s3c2410_wdt_variant
drv_data_exynos5420 = {
.quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
};
+static const struct s3c2410_wdt_variant drv_data_exynos7 = {
+ .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET,
+ .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET,
+ .mask_bit = 0,
+ .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 23, /* A57 WDTRESET */
+ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT,
+};
+
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = samsung,s3c2410-wdt,
.data = drv_data_s3c2410 },
@@ -162,6 +171,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
.data = drv_data_exynos5250 },
{ .compatible = samsung,exynos5420-wdt,
.data = drv_data_exynos5420 },
+ { .compatible = samsung,exynos7-wdt,
+ .data = drv_data_exynos7 },
{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
--
1.7.9.5
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[PATCH 14/14] tty/serial: samsung: add support for exynos7
From: Alim Akhtar alim.akh...@samsung.com
This patch enables upcoming exynos7 SoCs serial driver.
This also modifies various dependencies for Kconfig
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
---
drivers/tty/serial/Kconfig |6 +++---
drivers/tty/serial/samsung.c |2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 26cec64..f858d57 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -220,7 +220,7 @@ config SERIAL_CLPS711X_CONSOLE
config SERIAL_SAMSUNG
tristate Samsung SoC serial support
- depends on PLAT_SAMSUNG
+ depends on PLAT_SAMSUNG || ARCH_EXYNOS7
select SERIAL_CORE
help
Support for the on-chip UARTs on the Samsung S3C24XX series CPUs,
@@ -230,14 +230,14 @@ config SERIAL_SAMSUNG
config SERIAL_SAMSUNG_UARTS_4
bool
- depends on PLAT_SAMSUNG
+ depends on SERIAL_SAMSUNG
default y if !(CPU_S3C2410 || CPU_S3C2412 || CPU_S3C2440 || CPU_S3C2442)
help
Internal node for the common case of 4 Samsung compatible UARTs
config SERIAL_SAMSUNG_UARTS
int
- depends on PLAT_SAMSUNG
+ depends on SERIAL_SAMSUNG
default 4 if SERIAL_SAMSUNG_UARTS_4 || CPU_S3C2416
default 3
help
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index c78f43a..31be983 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1770,7 +1770,7 @@ static struct s3c24xx_serial_drv_data
s5pv210_serial_drv_data = {
#define S5PV210_SERIAL_DRV_DATA(kernel_ulong_t)NULL
#endif
-#if defined(CONFIG_ARCH_EXYNOS)
+#if defined(CONFIG_ARCH_EXYNOS) || defined(CONFIG_ARCH_EXYNOS7)
static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
.info = (struct s3c24xx_uart_info) {
.name = Samsung Exynos4 UART,
--
1.7.9.5
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[PATCH 03/14] clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
This patch adds the needed fields fixed_factor_clks and
nr_fixed_factor_clks to struct exynos_cmu_info
The same fields are used in the function exynos_cmu_register_one()
for registering the fixed factor clocks.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk.c |3 +++
drivers/clk/samsung/clk.h |3 +++
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index ef73edf..ed907cf 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -408,6 +408,9 @@ void __init exynos_cmu_register_one(struct device_node *np,
if (cmu-fixed_clks)
samsung_clk_register_fixed_rate(ctx, cmu-fixed_clks,
cmu-nr_fixed_clks);
+ if (cmu-fixed_factor_clks)
+ samsung_clk_register_fixed_factor(ctx, cmu-fixed_factor_clks,
+ cmu-nr_fixed_factor_clks);
if (cmu-clk_regs)
exynos_clk_sleep_init(reg_base, cmu-clk_regs,
cmu-nr_clk_regs);
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 552d155..993b51c 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -347,6 +347,9 @@ struct exynos_cmu_info {
/* list of fixed clocks and respective count */
struct samsung_fixed_rate_clock *fixed_clks;
unsigned int nr_fixed_clks;
+ /* list of fixed factor clocks and respective count */
+ struct samsung_fixed_factor_clock *fixed_factor_clks;
+ unsigned int nr_fixed_factor_clks;
/* total number of clocks with IDs assigned*/
unsigned int nr_clk_ids;
--
1.7.9.5
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[PATCH 04/14] clk: samsung: Add clock description for basic CMU blocks
This patch adds clock description for MUX, DIV, GATE and PLL clocks available in TOPC, TOP0, TOP1, BUS0, BUS1, FSYS0, FSYS1, CCORE, PERIC0, PERIC1, PERIS, DISP, G3D, MSCL and MFC blocks. Adds Gate clocks for UART, HSI2C, SPI, SPDIF, TMU, PWM, WDT, USB, MMC, RTC and DISP block clocks. This patch adds PLL tables for the following PLLs 1450x PLL which drives A57, DPHY block 1451x PLL which drives BUS0 block 1452x PLL which drives BUS1, MFC, G3D, HSIC blocks 1460x PLL which drives AUD, DISP blocks on Exynos7 SoC. Also adds the documentation for device tree bindings Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Tomasz Figa t.f...@samsung.com Cc: Mike Turquette mturque...@linaro.org Cc: Thomas Abraham thomas...@samsung.com --- Currently about 13 CMU blocks have been described in clk-exynos7.c If required, I can split it and group them to different files. .../devicetree/bindings/clock/exynos7-clock.txt| 209 +++ drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos7.c | 1929 include/dt-bindings/clock/exynos7-clk.h| 236 +++ 4 files changed, 2375 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt new file mode 100644 index 000..c361525 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt @@ -0,0 +1,209 @@ +* Samsung Exynos7 Clock Controller + +Exynos7 clock controller has 25 blocks which are instantiated +independently from the device-tree. These clock controllers +generate and supply clocks to various hardware blocks within +the SoC. + +Each clock is assigned an identifier and client nodes can use +this identifier to specify the clock which they consume. All +available clocks are defined as preprocessor macros in +dt-bindings/clock/exynos7-clk.h header and can be used in +device tree sources. + +External clocks: + +There are several clocks that are generated outside the SoC. It +is expected that they are defined using standard clock bindings +with following clock-output-names: + + - fin_pll - PLL input clock from XXTI + +Phy clocks: + +There are several clocks which are generated by specific PHYs. +These clocks are fed into the clock controller and then routed to +the hardware blocks. These clocks are defined as fixed clocks in the +driver with following names: + +Required Properties for Clock Controller: + + - compatible: should be one of the following. + 1) samsung,exynos7-clock-topc + 2) samsung,exynos7-clock-top0 + 3) samsung,exynos7-clock-top1 + 4) samsung,exynos7-clock-atlas + 5) samsung,exynos7-clock-ccore + 6) samsung,exynos7-clock-imem + 7) samsung,exynos7-clock-g3d + 8) samsung,exynos7-clock-mif0 + 9) samsung,exynos7-clock-mif1 + 10) samsung,exynos7-clock-mif2 + 11) samsung,exynos7-clock-mif3 + 12) samsung,exynos7-clock-peric0 + 13) samsung,exynos7-clock-peric1 + 14) samsung,exynos7-clock-peris + 15) samsung,exynos7-clock-bus0 + 16) samsung,exynos7-clock-bus1 + 17) samsung,exynos7-clock-fsys0 + 18) samsung,exynos7-clock-fsys1 + 19) samsung,exynos7-clock-disp + 20) samsung,exynos7-clock-aud + 21) samsung,exynos7-clock-mscl + 22) samsung,exynos7-clock-mfc + + - reg: physical base address of the controller and the length of + memory mapped region. + + - #clock-cells: should be 1. + + - clocks: list of clock identifiers which are fed as the input to + the given clock controller. Please refer the next section to find + the input clocks for a given controller. + + - clock-names: list of names of clocks which are fed as the input + to the given clock controller. + +Input clocks for topc clock controller: + - fin_pll + - fout_aud_pll + - fout_bus0_pl + - fout_bus1_pl + - fout_cc_pll + - fout_mfc_pll + - dout_sclk_cmu_apbif + +Input clocks for top0 clock controller: + - fin_pll + - fout_mif01_pll + - sclk_bus0_pll_mif + - sclk_bus0_pll_a + - sclk_bus1_pll_a + - sclk_cc_pll_a + - sclk_mfc_pll_a + - sclk_aud_pll + - sclk_cmu_apbif + - ioclk_audiocdclk0 + - ioclk_audiocdclk1 + - ioclk_spdif_extclk + +Input clocks for top1 clock controller: + - fin_pll + - fout_mif23_pll + - sclk_bus0_pll_mif + - sclk_bus0_pll_b + - sclk_bus1_pll_b + - sclk_cc_pll_b + - sclk_mfc_pll_b + - sclk_cmu_apbif + +Input clocks for ccore clock controller: + - fin_pll + - aclk_ccore_532 + - aclk_ccore_133 + +Input clocks for peric0 clock controller: + - fin_pll
[PATCH 02/14] clk: samsung: Factor out the common code to clk.c
This patch factors out the code that can be reused from
clk-exynos5260.c to clk-samsung/clk.c and clk-samsung/clk.h
As Clock controller in Exynos7 support various blocks in
CMU. The common functions and structures can be reused to
support Clock controller in Exynos7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos5260.c | 181 +-
drivers/clk/samsung/clk.c| 101 +++
drivers/clk/samsung/clk.h| 34 +++
3 files changed, 161 insertions(+), 155 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-exynos5260.c
index ce3de97..7655d4e 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -22,39 +22,6 @@
#include dt-bindings/clock/exynos5260-clk.h
-static LIST_HEAD(clock_reg_cache_list);
-
-struct exynos5260_clock_reg_cache {
- struct list_head node;
- void __iomem *reg_base;
- struct samsung_clk_reg_dump *rdump;
- unsigned int rd_num;
-};
-
-struct exynos5260_cmu_info {
- /* list of pll clocks and respective count */
- struct samsung_pll_clock *pll_clks;
- unsigned int nr_pll_clks;
- /* list of mux clocks and respective count */
- struct samsung_mux_clock *mux_clks;
- unsigned int nr_mux_clks;
- /* list of div clocks and respective count */
- struct samsung_div_clock *div_clks;
- unsigned int nr_div_clks;
- /* list of gate clocks and respective count */
- struct samsung_gate_clock *gate_clks;
- unsigned int nr_gate_clks;
- /* list of fixed clocks and respective count */
- struct samsung_fixed_rate_clock *fixed_clks;
- unsigned int nr_fixed_clks;
- /* total number of clocks with IDs assigned*/
- unsigned int nr_clk_ids;
-
- /* list and number of clocks registers */
- unsigned long *clk_regs;
- unsigned int nr_clk_regs;
-};
-
/*
* Applicable for all 2550 Type PLLS for Exynos5260, listed below
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -115,102 +82,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[]
__initdata = {
#ifdef CONFIG_PM_SLEEP
-static int exynos5260_clk_suspend(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_save(cache-reg_base, cache-rdump,
- cache-rd_num);
-
- return 0;
-}
-
-static void exynos5260_clk_resume(void)
-{
- struct exynos5260_clock_reg_cache *cache;
-
- list_for_each_entry(cache, clock_reg_cache_list, node)
- samsung_clk_restore(cache-reg_base, cache-rdump,
- cache-rd_num);
-}
-
-static struct syscore_ops exynos5260_clk_syscore_ops = {
- .suspend = exynos5260_clk_suspend,
- .resume = exynos5260_clk_resume,
-};
-
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump)
-{
- struct exynos5260_clock_reg_cache *reg_cache;
-
- reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
- GFP_KERNEL);
- if (!reg_cache)
- panic(could not allocate register cache.\n);
-
- reg_cache-rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
-
- if (!reg_cache-rdump)
- panic(could not allocate register dump storage.\n);
-
- if (list_empty(clock_reg_cache_list))
- register_syscore_ops(exynos5260_clk_syscore_ops);
-
- reg_cache-rd_num = nr_rdump;
- reg_cache-reg_base = reg_base;
- list_add_tail(reg_cache-node, clock_reg_cache_list);
-}
-
-#else
-static void exynos5260_clk_sleep_init(void __iomem *reg_base,
- unsigned long *rdump,
- unsigned long nr_rdump){}
-#endif
-
-/*
- * Common function which registers plls, muxes, dividers and gates
- * for each CMU. It also add CMU register list to register cache.
- */
-
-void __init exynos5260_cmu_register_one(struct device_node *np,
- struct exynos5260_cmu_info *cmu)
-{
- void __iomem *reg_base;
- struct samsung_clk_provider *ctx;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base)
- panic(%s: failed to map registers\n, __func__);
-
- ctx = samsung_clk_init(np, reg_base, cmu-nr_clk_ids);
- if (!ctx)
- panic(%s: unable to alllocate ctx\n, __func__);
-
- if (cmu-pll_clks)
- samsung_clk_register_pll(ctx, cmu-pll_clks, cmu-nr_pll_clks,
- reg_base);
- if (cmu-mux_clks)
- samsung_clk_register_mux(ctx, cmu-mux_clks,
- cmu
[PATCH 01/14] clk: samsung: add support for 145xx and 1460x PLLs
By registers bits and offsets the 145xx PLL is similar to
pll_type pll_35xx. Also, 1460x PLL is similar to pll_type
pll_46xx.
Hence, reusing the functions defined for pll_35xx and pll_46xx
to support 145xx and 1460x PLLs respectively.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: Mike Turquette mturque...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-pll.c | 50 -
drivers/clk/samsung/clk-pll.h |4
2 files changed, 43 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index b07fad2..fe24e4d 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -130,6 +130,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
*/
/* Maximum lock time can be 270 * PDIV cycles */
#define PLL35XX_LOCK_FACTOR(270)
+#define PLL145XX_LOCK_FACTOR (150)
#define PLL35XX_MDIV_MASK (0x3FF)
#define PLL35XX_PDIV_MASK (0x3F)
@@ -139,6 +140,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = {
#define PLL35XX_PDIV_SHIFT (8)
#define PLL35XX_SDIV_SHIFT (0)
#define PLL35XX_LOCK_STAT_SHIFT(29)
+#define PLL145XX_ENABLEBIT(31)
static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
@@ -186,6 +188,10 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw,
unsigned long drate,
tmp = __raw_readl(pll-con_reg);
+ /* Enable PLL */
+ if (pll-type == (pll_1450x || pll_1451x || pll_1452x))
+ tmp |= PLL145XX_ENABLE;
+
if (!(samsung_pll35xx_mp_change(rate, tmp))) {
/* If only s change, change just s value only*/
tmp = ~(PLL35XX_SDIV_MASK PLL35XX_SDIV_SHIFT);
@@ -196,8 +202,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw,
unsigned long drate,
}
/* Set PLL lock time. */
- __raw_writel(rate-pdiv * PLL35XX_LOCK_FACTOR,
- pll-lock_reg);
+ if (pll-type == (pll_1450x || pll_1451x || pll_1452x))
+ __raw_writel(rate-pdiv * PLL145XX_LOCK_FACTOR,
+ pll-lock_reg);
+ else
+ __raw_writel(rate-pdiv * PLL35XX_LOCK_FACTOR,
+ pll-lock_reg);
/* Change PLL PMS values */
tmp = ~((PLL35XX_MDIV_MASK PLL35XX_MDIV_SHIFT) |
@@ -356,7 +366,6 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
#define PLL45XX_ENABLE BIT(31)
#define PLL45XX_LOCKED BIT(29)
-
static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
@@ -482,6 +491,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
#define PLL46XX_VSEL_MASK (1)
#define PLL46XX_MDIV_MASK (0x1FF)
+#define PLL1460X_MDIV_MASK (0x3FF)
+
#define PLL46XX_PDIV_MASK (0x3F)
#define PLL46XX_SDIV_MASK (0x7)
#define PLL46XX_VSEL_SHIFT (27)
@@ -511,13 +522,14 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
pll_con0 = __raw_readl(pll-con_reg);
pll_con1 = __raw_readl(pll-con_reg + 4);
- mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) ((pll-type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
sdiv = (pll_con0 PLL46XX_SDIV_SHIFT) PLL46XX_SDIV_MASK;
- kdiv = pll-type == pll_4650c ? pll_con1 PLL4650C_KDIV_MASK :
+ kdiv = (pll-type == pll_4650c) ? pll_con1 PLL4650C_KDIV_MASK :
pll_con1 PLL46XX_KDIV_MASK;
- shift = pll-type == pll_4600 ? 16 : 10;
+ shift = (pll-type == (pll_4600 || pll_1460x)) ? 16 : 10;
fvco *= (mdiv shift) + kdiv;
do_div(fvco, (pdiv sdiv));
fvco = shift;
@@ -526,11 +538,14 @@ static unsigned long samsung_pll46xx_recalc_rate(struct
clk_hw *hw,
}
static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1,
- const struct samsung_pll_rate_table *rate)
+ const struct samsung_pll_rate_table *rate,
+ struct samsung_clk_pll *pll)
{
u32 old_mdiv, old_pdiv, old_kdiv;
- old_mdiv = (pll_con0 PLL46XX_MDIV_SHIFT) PLL46XX_MDIV_MASK;
+ old_mdiv = (pll_con0 PLL46XX_MDIV_SHIFT)
+ ((pll-type == pll_1460x) ?
+ PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
old_pdiv = (pll_con0 PLL46XX_PDIV_SHIFT) PLL46XX_PDIV_MASK;
old_kdiv = (pll_con1 PLL46XX_KDIV_SHIFT) PLL46XX_KDIV_MASK;
@@ -557,7 +572,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,
unsigned long drate,
con0
[PATCH 05/14] pinctrl: exynos: Add driver data for Exynos7
This patch adds driver data for Exynos7
to pinctrl-exynos driver. Exynos7 includes 229 multi-functional
input/output ports. There are 40 general port groups.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Tomasz Figa t.f...@samsung.com
Cc: linus.wall...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
.../bindings/pinctrl/samsung-pinctrl.txt |1 +
drivers/pinctrl/samsung/Kconfig|2 +-
drivers/pinctrl/samsung/pinctrl-exynos.c | 145
drivers/pinctrl/samsung/pinctrl-samsung.c |2 +
drivers/pinctrl/samsung/pinctrl-samsung.h |1 +
5 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..2da258f 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -18,6 +18,7 @@ Required Properties:
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
- samsung,exynos5260-pinctrl: for Exynos5260 compatible pin-controller.
- samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
+ - samsung,exynos7-pinctrl: for Exynos7 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index d0461cd..c660d31 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -8,7 +8,7 @@ config PINCTRL_SAMSUNG
config PINCTRL_EXYNOS
bool Pinctrl driver data for Samsung EXYNOS SoCs other than 5440
- depends on OF GPIOLIB (ARCH_EXYNOS || ARCH_S5PV210)
+ depends on OF GPIOLIB (ARCH_EXYNOS || ARCH_S5PV210 ||
ARCH_EXYNOS7)
select PINCTRL_SAMSUNG
config PINCTRL_EXYNOS5440
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 003bfd8..8e9152b 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1121,3 +1121,148 @@ struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
.label = exynos5420-gpio-ctrl4,
},
};
+
+/* pin banks of exynos7 pin-controller 0 */
+static struct samsung_pin_bank exynos7_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTW(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0x060, gpa3, 0x0c),
+};
+
+/* pin banks of exynos7 pin-controller 1 (AUD) */
+static struct samsung_pin_bank exynos7_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(4, 0x020, gpz1, 0x04),
+};
+
+/* pin banks of exynos7 pin-controller 2 (BUS0) */
+static struct samsung_pin_bank exynos7_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, gpb0, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpc0, 0x08),
+ EXYNOS_PIN_BANK_EINTG(2, 0x040, gpc1, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x060, gpc2, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, gpc3, 0x14),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0a0, gpd0, 0x18),
+ EXYNOS_PIN_BANK_EINTG(6, 0x0c0, gpd1, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0e0, gpd2, 0x20),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, gpd4, 0x24),
+ EXYNOS_PIN_BANK_EINTG(4, 0x120, gpd5, 0x28),
+ EXYNOS_PIN_BANK_EINTG(6, 0x140, gpd6, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(3, 0x160, gpd7, 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x180, gpd8, 0x34),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1a0, gpg0, 0x38),
+ EXYNOS_PIN_BANK_EINTG(4, 0x1c0, gpg3, 0x3c),
+};
+
+/* pin banks of exynos7 pin-controller 3 (BUS1) */
+static struct samsung_pin_bank exynos7_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpf0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpf1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(4, 0x060, gpf2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpf3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0a0, gpf4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0c0, gpf5, 0x14),
+ EXYNOS_PIN_BANK_EINTG(5, 0x0e0, gpg1, 0x18),
+ EXYNOS_PIN_BANK_EINTG(5, 0x100, gpg2, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(6, 0x120, gph1, 0x20),
+ EXYNOS_PIN_BANK_EINTG(3, 0x140, gpv6, 0x24),
+};
+
+/* pin banks of exynos7 pin-controller 4 (NFC) */
+static struct samsung_pin_bank exynos7_pin_banks4[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj0, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 5 (TOUCH) */
+static struct samsung_pin_bank exynos7_pin_banks5[] = {
+ EXYNOS_PIN_BANK_EINTG(3, 0x000, gpj1, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 6 (FF) */
+static struct samsung_pin_bank exynos7_pin_banks6[] = {
+ EXYNOS_PIN_BANK_EINTG(4, 0x000, gpg4, 0x00),
+};
+
+/* pin banks of exynos7 pin-controller 7 (ESE
[PATCH 06/14] pinctrl: samsung: use CONFIG_PINCTRL_SAMSUNG symbol in makefile
Samsung Exynos7 is a ARM64bit processor. Which does not select the CONFIG_PLAT_SAMSUNG symbol. CONFIG_PINCTRL_SAMSUNG is being selected for both PLAT_SAMSUNG and ARCH_EXYNOS7 symbols. This patch modifes the pinctrl/Makefile to use CONFIG_PINCTRL_SAMSUNG symbol to compile the pinctrl/samsung/*.c Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Tomasz Figa t.f...@samsung.com Cc: linus.wall...@linaro.org Cc: Thomas Abraham thomas...@samsung.com --- drivers/pinctrl/Makefile |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 05d2275..801777e 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -58,7 +58,7 @@ obj-$(CONFIG_ARCH_BERLIN) += berlin/ obj-$(CONFIG_PLAT_ORION)+= mvebu/ obj-y += nomadik/ obj-$(CONFIG_ARCH_QCOM)+= qcom/ -obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ +obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_ARCH_SHMOBILE)+= sh-pfc/ obj-$(CONFIG_SUPERH) += sh-pfc/ obj-$(CONFIG_PLAT_SPEAR) += spear/ -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/4 v2] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
The DT bindings in exynos-adc.txt applies to the ADC
driver (exynos-adc.c) developed based on IIO framework.
The bindings are more appropriate to be under
Documentation/devicetree/bindings/iio/adc/
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: devicet...@vger.kernel.org
---
Changes since v1:
Use git format-patch -M to reduce the patch size
.../{arm/samsung = iio/adc}/exynos-adc.txt|0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{arm/samsung =
iio/adc}/exynos-adc.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
rename to Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
--
1.7.9.5
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[PATCH 4/4 v2] ARM: dts: exynos: Add sysreg phandle to ADC node
Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.
This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-samsung-soc@vger.kernel.org
---
Changes since v1:
None
arch/arm/boot/dts/exynos3250.dtsi |3 ++-
arch/arm/boot/dts/exynos4x12.dtsi |3 ++-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
arch/arm/boot/dts/exynos5420.dtsi |3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index c5e15db..51c9b0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -262,12 +262,13 @@
adc: adc@126C {
compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
clock-names = adc, sclk_adc;
clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..9a18d9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -114,13 +114,14 @@
adc: adc@126C {
compatible = samsung,exynos-adc-v1;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupt-parent = combiner;
interrupts = 10 3;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..6003777 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -762,12 +762,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100
interrupts = 0 106 0;
clocks = clock CLK_ADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..6979da8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -525,12 +525,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v2;
- reg = 0x12D1 0x100, 0x10040720 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
--
1.7.9.5
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[PATCH 0/4 v2] iio: exynos-adc: use syscon instead of ioremap
Syscon is a regmap based framework to help various drivers access misc bits in registers which does not belong to another module. For example, Power Module, SYSREGs. With syscon, ADC can use generic regmap API to access registers of PMU which are registered into syscon. This patch does the following 1. Use the syscon and Regmap API instead of ioremappaing the ADC_PHY register from PMU. 2. Moves the exynos-adc.txt from bindings/arm/samsung/ to bindings/iio/adc/. 3. Updates the Documentation in exynos-adc.txt with syscon phandle for the ADC nodes. 4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250, Exynos5420 with the syscon phandle. Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI by verifying sysfs entries provided by HWMON based NTC thermistors. Tested-By for Exynos3250, Exynos4x12 would be appreciated. Changes since v1: Adding syscon description in commit message Rebased on top of v5 version of ADC for exynos3250 from Changwoo. iio: adc: exynos_adc: Support Exynos3250 ADC and code clean https://lkml.org/lkml/2014/6/27/16 Naveen Krishna Chatradhi (4): iio: exyno-adc: use syscon for PMU register access Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/ Documentation: dt-bindings: update exynos-adc.txt with syscon handle ARM: dts: exynos: Add sysreg phandle to ADC node .../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 -- .../devicetree/bindings/iio/adc/exynos-adc.txt | 87 arch/arm/boot/dts/exynos3250.dtsi |3 +- arch/arm/boot/dts/exynos4x12.dtsi |3 +- arch/arm/boot/dts/exynos5250.dtsi |3 +- arch/arm/boot/dts/exynos5420.dtsi |3 +- drivers/iio/adc/exynos_adc.c | 29 +-- 7 files changed, 115 insertions(+), 95 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4 v2] Documentation: dt-bindings: update exynos-adc.txt with syscon handle
This patch updates the DT bindings in exynos-adc.txt with the
syscon phandle to the ADC nodes.
Also removes the 2nd reg property, which used to carry the
ADC_PHY regiser base from PMU.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: devicet...@vger.kernel.org
---
Changes since v1:
rebased on top of Changwoo's v5 ADC patches for exynos3250
iio: adc: exynos_adc: Support Exynos3250 ADC and code clean
https://lkml.org/lkml/2014/6/27/16
.../devicetree/bindings/iio/adc/exynos-adc.txt | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
index 0b0ed85..1634df3 100644
--- a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
@@ -1,10 +1,11 @@
Samsung Exynos Analog to Digital Converter bindings
The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
+Exynos4 and Exynos5 series SoCs from Samsung.
+Now supports Exynos3250 too.
New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+1. Supports ADC IF found on Exynos3250/EXYNOS4412/EXYNOS5 series
and future SoCs from Samsung
2. Add ADC driver under iio/adc framework
3. Also adds the Documentation for device tree bindings
@@ -18,7 +19,7 @@ Required properties:
for controllers compatible with ADC of
Exynos3250.
- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
+ length)
- interrupts: Contains the interrupt information for the timer. The
format is being dependent on which interrupt controller
the Samsung device uses.
@@ -31,6 +32,8 @@ Required properties:
- sclk_adc : ADC special clock (only for Exynos3250
and compatible ADC block)
- vdd-supply VDD input supply.
+- samsung,syscon-phandle Contains the PMU system controller node
+ (To access the ADC_PHY register)
Note: child nodes can be added for auto probing from device tree.
@@ -38,7 +41,7 @@ Example: adding device info in dtsi file
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
#io-channel-cells = 1;
io-channel-ranges;
@@ -47,13 +50,14 @@ adc: adc@12D1 {
clock-names = adc;
vdd-supply = buck5_reg;
+ samsung,syscon-phandle = pmu_system_controller;
};
Example: adding device info in dtsi file for Exynos3250 with additional sclk
adc: adc@126C {
compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
#io-channel-cells = 1;
io-channel-ranges;
@@ -62,6 +66,7 @@ adc: adc@126C {
clock-names = adc, sclk_adc;
vdd-supply = buck5_reg;
+ samsung,syscon-phandle = pmu_system_controller;
};
Example: Adding child nodes in dts file
--
1.7.9.5
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[PATCH 1/4 v2] iio: exyno-adc: use syscon for PMU register access
This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-...@vger.kernel.org
---
Changes since v1:
None
drivers/iio/adc/exynos_adc.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index b63e882..60847ef 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -38,6 +38,8 @@
#include linux/iio/iio.h
#include linux/iio/machine.h
#include linux/iio/driver.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
/* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
@@ -79,11 +81,14 @@
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
+#define EXYNOS_ADCV1_PHY_OFFSET0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET0x0720
+
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
void __iomem*regs;
- void __iomem*enable_reg;
+ struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned intirq;
@@ -98,6 +103,7 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ int phy_offset;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -169,7 +175,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -183,7 +189,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V1_CON(info-regs));
con |= ADC_V1_CON_STANDBY;
@@ -208,6 +214,7 @@ static void exynos_adc_v1_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw= exynos_adc_v1_init_hw,
.exit_hw= exynos_adc_v1_exit_hw,
@@ -219,7 +226,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info-regs));
@@ -236,7 +243,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V2_CON1(info-regs));
con = ~ADC_CON_EN_START;
@@ -271,10 +278,12 @@ static void exynos_adc_v2_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
};
static struct exynos_adc_data const exynos3250_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.needs_sclk = true,
};
@@ -437,10 +446,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info-regs))
return PTR_ERR(info-regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info-enable_reg = devm_ioremap_resource(pdev-dev, mem);
- if (IS_ERR(info-enable_reg))
- return PTR_ERR(info-enable_reg);
+ info-pmu_map = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
+ samsung,syscon-phandle);
+ if (IS_ERR(info-pmu_map)) {
+ dev_err(pdev-dev, syscon regmap lookup failed.\n);
+ return PTR_ERR(info-pmu_map);
+ }
irq = platform_get_irq(pdev, 0);
if (irq 0) {
--
1.7.9.5
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[PATCH] ARM: config: update multi_v7_defconfig
Enabled S3C24XX I2C driver and MAX77686 PMIC MFD and Voltage regulator drivers used on Exynos5250 based Snow board. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com --- By enabling the symbols to compile S3C24XX I2C driver, MAX77686 PMIC under MFD and REGULATOR. http://arm-soc.lixom.net/bootlogs/next/next-20140711/snow-multi_v7_defconfig.html The warnings by cpufreq on Snow board are fixed. Booted and verified on on Exynos5420 based Snow board arch/arm/configs/multi_v7_defconfig |3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 5348364..1aaf91d 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -193,6 +193,7 @@ CONFIG_I2C_CADENCE=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_EXYNOS5=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_S3C2410=y CONFIG_I2C_SIRF=y CONFIG_I2C_TEGRA=y CONFIG_SPI=y @@ -231,6 +232,7 @@ CONFIG_MFD_AS3722=y CONFIG_MFD_BCM590XX=y CONFIG_MFD_CROS_EC=y CONFIG_MFD_CROS_EC_SPI=y +CONFIG_MFD_MAX77686=y CONFIG_MFD_MAX8907=y CONFIG_MFD_SEC_CORE=y CONFIG_MFD_PALMAS=y @@ -243,6 +245,7 @@ CONFIG_REGULATOR_AS3722=y CONFIG_REGULATOR_BCM590XX=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8907=y +CONFIG_REGULATOR_MAX77686=y CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_S5M8767=y -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] spi: s3c64xx: fix the driver to use cs-gpios property
Current SPI core has generic implementation for configuring the Chip select gpios during .setup() .cleanup(). By modifying the spi-s3c64xx.c driver to expect the cs-gpios property in SPI device node instead of the subnode controller-data. This way we can avoid parsing the cs-gpios in the driver. This patch set also does the following 1. Validate the struct s3c64xx_spi_csinfo *cs object and the CS gpio for both DT and NON-DT before using them. 2. Correct the dt-bindings for exynos4210-smdkv310.dts, exynos4412-trats2.dts and exynos5250-smdk5250.dts 3. Updates the DT bindings. Note: This patchset is a rework of the changes under review @ http://www.mail-archive.com/devicetree@vger.kernel.org/msg34501.html Tested on Exynos5420 and Exynos5250 based Peach PIT, PI and Snow boards respectively using the flashrom utility to access SPI flash. This patchset is needed by the changes http://www.gossamer-threads.com/lists/linux/kernel/1951607 Tested-by on boards based on Exynos4, S5P, S3C series SoCs would be appreciated. Naveen Krishna Chatradhi (3): spi: s3c64xx: move property cs-gpio from controller_data subnode to SPI DT node spi: s3c64xx: validate s3c64xx_spi_csinfo before using ARM: DTS: fix the chip select gpios definition in the SPI nodes .../devicetree/bindings/spi/spi-samsung.txt| 10 arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +- arch/arm/boot/dts/exynos4412-trats2.dts|2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +- drivers/spi/spi-s3c64xx.c | 27 +++- 5 files changed, 17 insertions(+), 26 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] spi: s3c64xx: validate s3c64xx_spi_csinfo before using
This patch validates the cs-line (Chip select gpio) and
struct s3c64xx_spi_csinfo *cs object for both DT and NON-DT
platforms before using in .setup().
Also, check gpio_is_valid(spi-cs_gpio) in cleanup() before
freeing up.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
---
drivers/spi/spi-s3c64xx.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 72bfba6..8971076 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -773,12 +773,6 @@ static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
/* The CS line is asserted/deasserted by the gpio pin */
cs-line = spi-cs_gpio;
- if (!gpio_is_valid(cs-line)) {
- dev_err(spi-dev, chip select gpio is not specified or
invalid\n);
- kfree(cs);
- return ERR_PTR(-EINVAL);
- }
-
data_np = of_get_child_by_name(slave_np, controller-data);
if (!data_np) {
dev_err(spi-dev, child node 'controller-data' not found\n);
@@ -805,15 +799,14 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
int err;
sdd = spi_master_get_devdata(spi-master);
- if (!cs spi-dev.of_node) {
+ if (spi-dev.of_node)
cs = s3c64xx_get_slave_ctrldata(spi);
- spi-controller_data = cs;
- }
- if (IS_ERR_OR_NULL(cs)) {
+ if (IS_ERR_OR_NULL(cs) || !gpio_is_valid(cs-line)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
return -ENODEV;
}
+ spi-controller_data = cs;
if (!spi_get_ctldata(spi)) {
/* Request gpio only if cs line is asserted by gpio pins */
@@ -898,7 +891,7 @@ static void s3c64xx_spi_cleanup(struct spi_device *spi)
struct s3c64xx_spi_driver_data *sdd;
sdd = spi_master_get_devdata(spi-master);
- if (spi-cs_gpio) {
+ if (gpio_is_valid(spi-cs_gpio)) {
gpio_free(spi-cs_gpio);
if (spi-dev.of_node)
kfree(cs);
--
1.7.9.5
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[PATCH 1/3] spi: s3c64xx: move cs-gpio from subnode to SPI DT node
This patch modifies the spi-s3c64xx.c driver to fetch the
Chip select or Slave select gpio line property cs-gpios
from SPI node instead of controller_data subnode.
Rename the property cs-gpio to cs-gpios in accordance
with the SPI core. Such that s3c64xx.c can use spi-cs_gpio
instead of parsing the property in the driver.
Update the dt-bindings ion spi/spi-samsung.txt
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
This patch is a rework of the change @
http://www.mail-archive.com/devicetree@vger.kernel.org/msg34500.html
I'm not sure if i can carry forward the other Signed-offs and Tested-bys
.../devicetree/bindings/spi/spi-samsung.txt| 10 +-
drivers/spi/spi-s3c64xx.c | 18 --
2 files changed, 13 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt
b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 655b665..ff3c4c9 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -39,15 +39,15 @@ Optional Board Specific Properties:
- num-cs: Specifies the number of chip select lines supported. If
not specified, the default number of chip select lines is set to 1.
+- cs-gpios: A gpio specifier that specifies the gpio line used as
+ the slave select line by the spi controller. The format of the gpio
+ specifier depends on the gpio controller (Also read spi-bus.txt).
+
SPI Controller specific data in SPI slave nodes:
- The spi slave nodes should provide the following information which is
required
by the spi controller.
- - cs-gpio: A gpio specifier that specifies the gpio line used as
-the slave select line by the spi controller. The format of the gpio
-specifier depends on the gpio controller.
-
- samsung,spi-feedback-delay: The sampling phase shift to be applied on the
miso line (to account for any lag in the miso line). The following are the
valid values.
@@ -85,6 +85,7 @@ Example:
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = spi0_bus;
+ cs-gpios = gpa2 5 1 0 3;
w25q80bw@0 {
#address-cells = 1;
@@ -94,7 +95,6 @@ Example:
spi-max-frequency = 1;
controller-data {
- cs-gpio = gpa2 5 1 0 3;
samsung,spi-feedback-delay = 0;
};
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a5696..72bfba6 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -764,12 +764,6 @@ static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
return ERR_PTR(-EINVAL);
}
- data_np = of_get_child_by_name(slave_np, controller-data);
- if (!data_np) {
- dev_err(spi-dev, child node 'controller-data' not found\n);
- return ERR_PTR(-EINVAL);
- }
-
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
if (!cs) {
of_node_put(data_np);
@@ -777,13 +771,17 @@ static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
}
/* The CS line is asserted/deasserted by the gpio pin */
- if (sdd-cs_gpio)
- cs-line = of_get_named_gpio(data_np, cs-gpio, 0);
+ cs-line = spi-cs_gpio;
if (!gpio_is_valid(cs-line)) {
dev_err(spi-dev, chip select gpio is not specified or
invalid\n);
kfree(cs);
- of_node_put(data_np);
+ return ERR_PTR(-EINVAL);
+ }
+
+ data_np = of_get_child_by_name(slave_np, controller-data);
+ if (!data_np) {
+ dev_err(spi-dev, child node 'controller-data' not found\n);
return ERR_PTR(-EINVAL);
}
@@ -1077,7 +1075,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
sdd-sfr_start = mem_res-start;
sdd-cs_gpio = true;
if (pdev-dev.of_node) {
- if (!of_find_property(pdev-dev.of_node, cs-gpio, NULL))
+ if (!of_find_property(pdev-dev.of_node, cs-gpios, NULL))
sdd-cs_gpio = false;
ret = of_alias_get_id(pdev-dev.of_node, spi);
--
1.7.9.5
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[PATCH 3/3] ARM: DTS: fix the chip select gpios definition in the SPI nodes
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@ http://www.spinics.net/lists/linux-samsung-soc/msg32282.html
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
This change is being reviewed @
http://www.mail-archive.com/devicetree@vger.kernel.org/msg34498.html
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d166..676e6e0 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -168,6 +168,7 @@
};
spi_2: spi@1394 {
+ cs-gpios = gpc1 2 0;
status = okay;
w25x80@0 {
@@ -178,7 +179,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpc1 2 0;
samsung,spi-feedback-delay = 0;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..11967f4 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -589,6 +589,7 @@
spi_1: spi@1393 {
pinctrl-names = default;
pinctrl-0 = spi1_bus;
+ cs-gpios = gpb 5 0;
status = okay;
s5c73m3_spi: s5c73m3 {
@@ -596,7 +597,6 @@
spi-max-frequency = 5000;
reg = 0;
controller-data {
- cs-gpio = gpb 5 0;
samsung,spi-feedback-delay = 2;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..0c6433a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
};
spi_1: spi@12d3 {
+ cs-gpios = gpa2 5 0;
status = okay;
w25q80bw@0 {
@@ -326,7 +327,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpa2 5 0;
samsung,spi-feedback-delay = 0;
};
--
1.7.9.5
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[PATCH 1/3] serial: samsung: get fifosize via device tree
UART modules on some SoCs only differ in the fifosize of each
UART channel. Its useless to duplicate the drv_data structure
or create a compatible name for such a change.
We can get fifosize via the device tree nodes (not mandating it).
Also updates the documentation.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
.../devicetree/bindings/serial/samsung_uart.txt|4
drivers/tty/serial/samsung.c | 12 +---
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt
b/Documentation/devicetree/bindings/serial/samsung_uart.txt
index 85e8ee2..e85f37e 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.txt
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.txt
@@ -29,6 +29,9 @@ Required properties:
[1] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
+Optional properties:
+- samsung,uart-fifosize: The fifo size supported by the UART channel
+
Note: Each Samsung UART should have an alias correctly numbered in the
aliases node, according to serialN format, where N is the port number
(non-negative decimal integer) as specified by User's Manual of respective
@@ -51,4 +54,5 @@ Example:
clk_uart_baud3;
clocks = clocks PCLK_UART1, clocks PCLK_UART1,
clocks SCLK_UART;
+ samsung,uart-fifosize = 16;
};
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 6be852d..e49a945 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1295,9 +1295,15 @@ static int s3c24xx_serial_probe(struct platform_device
*pdev)
dev_get_platdata(pdev-dev) :
ourport-drv_data-def_cfg;
- ourport-port.fifosize = (ourport-info-fifosize) ?
- ourport-info-fifosize :
- ourport-drv_data-fifosize[index];
+ if (pdev-dev.of_node)
+ of_property_read_u32(pdev-dev.of_node,
+ samsung,uart-fifosize, ourport-port.fifosize);
+
+ if (!ourport-port.fifosize) {
+ ourport-port.fifosize = (ourport-info-fifosize) ?
+ ourport-info-fifosize :
+ ourport-drv_data-fifosize[index];
+ }
probe_index++;
--
1.7.9.5
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[PATCH 3/3] serial: samsung: improve code clarity by defining a variable
The of_node is derived from pdev for every usage, define a
device_node variable instead.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: gre...@linuxfoundation.org
---
drivers/tty/serial/samsung.c |9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index d98f93d..4aff02d 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1269,12 +1269,13 @@ static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
static int s3c24xx_serial_probe(struct platform_device *pdev)
{
+ struct device_node *np = pdev-dev.of_node;
struct s3c24xx_uart_port *ourport;
int index = probe_index;
int ret;
- if (pdev-dev.of_node) {
- ret = of_alias_get_id(pdev-dev.of_node, serial);
+ if (np) {
+ ret = of_alias_get_id(np, serial);
if (ret = 0)
index = ret;
}
@@ -1295,8 +1296,8 @@ static int s3c24xx_serial_probe(struct platform_device
*pdev)
dev_get_platdata(pdev-dev) :
ourport-drv_data-def_cfg;
- if (pdev-dev.of_node)
- of_property_read_u32(pdev-dev.of_node,
+ if (np)
+ of_property_read_u32(np,
samsung,uart-fifosize, ourport-port.fifosize);
if (!ourport-port.fifosize) {
--
1.7.9.5
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[PATCH 2/3] serial: samsung: correct the case and default order in switch
The cases should comes before default in a switch. Even if we want the case and default to share same code. Its good to define the case first followed by default. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: gre...@linuxfoundation.org --- drivers/tty/serial/samsung.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index e49a945..d98f93d 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1542,8 +1542,8 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, case S3C2410_LCON_CS7: *bits = 7; break; - default: case S3C2410_LCON_CS8: + default: *bits = 8; break; } -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] serial: samsung: get fifosize from DT and clean up
This patch set does the following 1: Get fifosize from DT node. But, not mandating it. 2. Corrects the case and default order in a switch 3. Defines a variable to simply the code. Console messages on Exynos5420 based peach pit and pi works fine. Naveen Krishna Chatradhi (3): serial: samsung: get fifosize via device tree serial: samsung: correct the case and default order in switch serial: samsung: improve code clarity by defining a variable .../devicetree/bindings/serial/samsung_uart.txt|4 drivers/tty/serial/samsung.c | 19 +-- 2 files changed, 17 insertions(+), 6 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/3 v6] ARM: DTS: fix the chip select gpios definition in the SPI nodes
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@ http://www.spinics.net/lists/linux-samsung-soc/msg32282.html
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
Changes since v5:
None
Changes since v4:
1. Added reviewed by from Javier and Doug.
2. Maintained the status and cs-gpios ordering
Changes since v3:
None
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d166..676e6e0 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -168,6 +168,7 @@
};
spi_2: spi@1394 {
+ cs-gpios = gpc1 2 0;
status = okay;
w25x80@0 {
@@ -178,7 +179,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpc1 2 0;
samsung,spi-feedback-delay = 0;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 7787844..11967f4 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -589,6 +589,7 @@
spi_1: spi@1393 {
pinctrl-names = default;
pinctrl-0 = spi1_bus;
+ cs-gpios = gpb 5 0;
status = okay;
s5c73m3_spi: s5c73m3 {
@@ -596,7 +597,6 @@
spi-max-frequency = 5000;
reg = 0;
controller-data {
- cs-gpio = gpb 5 0;
samsung,spi-feedback-delay = 2;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..0c6433a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
};
spi_1: spi@12d3 {
+ cs-gpios = gpa2 5 0;
status = okay;
w25q80bw@0 {
@@ -326,7 +327,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpa2 5 0;
samsung,spi-feedback-delay = 0;
};
--
1.7.9.5
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[PATCH 2/3 v6] spi: s3c64xx: for DT platofrms always get the chipselect info from DT node
Use controller_data structure only for the Non Device tree platforms.
For Device tree platforms, always derive the chipselect info from
DT node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Doug Anderson diand...@chromium.org
---
Changes since v5:
None
Changes since v4:
1. Added reviewed by from Javier and Tested by from Doug
Changes since v3:
New change
drivers/spi/spi-s3c64xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b61ff3d..a4b1af0 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -795,14 +795,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
int err;
sdd = spi_master_get_devdata(spi-master);
- if (!cs spi-dev.of_node) {
+ if (spi-dev.of_node) {
cs = s3c64xx_get_slave_ctrldata(spi);
spi-controller_data = cs;
- }
-
- /* For the non-DT platforms derive chip selects from controller data */
- if (!spi-dev.of_node)
+ } else {
+ /* For the non-DT platforms derive chip
+* selects from controller data
+*/
spi-cs_gpio = cs-line;
+ }
if (IS_ERR_OR_NULL(cs)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
--
1.7.9.5
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[PATCH 0/3 v6] spi: s3c64xx: use cs-gpios in spi node instead of cs-gpio
Currently, spi-s3c64xx.c needs cs-gpio chip select GPIO to be
defined under controller-data node under each slave node.
spi_x {
cs-gpios ;
...
slave_node {
controller-data {
cs-gpio = ;
...
};
...
};
...
};
Where as, SPI core and many other drivers uses cs-gpios for
from device tree node.
Hence, make changes in spi-s3c64xx.c driver to make use of
cs-gpios from SPI node(parent) instead of cs-gpio defined in
slaves controller-data(child) node.
Also, fixes a compilation warning and corrects the DTS nodes for
Exynos4210 based SMDKv310, Exynos4412 based Trats2, Exynos5250 based
SMDK5250 boards.
Changes since v5:
1. Fixed the making a GPIO chip select mandatory bug.
Naveen Krishna Chatradhi (3):
spi: s3c64xx: fix broken cs_gpios usage in the driver
spi: s3c64xx: for DT platofrms always get the chipselect info from DT
node
ARM: DTS: fix the chip select gpios definition in the SPI nodes
.../devicetree/bindings/spi/spi-samsung.txt|8 ++--
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts|2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
drivers/spi/spi-s3c64xx.c | 41
5 files changed, 22 insertions(+), 33 deletions(-)
--
1.7.9.5
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[PATCH 1/3 v6] spi: s3c64xx: fix broken cs_gpios usage in the driver
Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
spi-s3c64xx.c driver expects
1. chip select gpios from cs-gpio(singular) under the
controller-data node of the client/slave device of the SPI.
2. cs-gpio(singular) entry to be present in the SPI device node.
Eg of current broken usage:
spi_1 {
cs-gpio ; /* this entry is checked during probe */
...
slave_node {
controller-data {
cs-gpio gpioa2 5 0;
/* This field is parsed during .setup() */
}
};
};
The following dts files which were using this driver. But,
din't have the cs-gpio entry under SPI node.
-- arch/arm/boot/dts/exynos4210-smdkv310.dts
-- arch/arm/boot/dts/exynos4412-trats2.dts
-- arch/arm/boot/dts/exynos5250-smdk5250.dts
Also, the SPI core and many drivers moved on to using cs-gpios
from SPI node and removed the gpio handling code from drivers
(including spi-s3c64xx.c).
Hence, spi-s3c64xx.c is broken since Jun 21 11:26:12 2013 and
considering the time with no compliants about the breakage.
We are assuming it is safe to remove the cs-gpio(singular) usage
from device tree binding of spi-samsung.txt and makes appropriate
changes in the driver to use cs-gpios(plural) from
SPI device node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
Changes since v5:
Fixed the making a GPIO chip select mandatory bug.
Changes since v4:
1. Added reviewed by from Javier and Tested by from Doug
Changes since v3:
1. Remove the sdd-cs_gpio and use gpio_is_valid(spi-cs_gpio) instead
2. Keep cs-line only for Non-DT platforms and use spi-cs_gpio
for DT platforms
.../devicetree/bindings/spi/spi-samsung.txt|8 ++---
drivers/spi/spi-s3c64xx.c | 38
2 files changed, 17 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt
b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 655b665..792efba 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -39,15 +39,13 @@ Optional Board Specific Properties:
- num-cs: Specifies the number of chip select lines supported. If
not specified, the default number of chip select lines is set to 1.
+- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
+
SPI Controller specific data in SPI slave nodes:
- The spi slave nodes should provide the following information which is
required
by the spi controller.
- - cs-gpio: A gpio specifier that specifies the gpio line used as
-the slave select line by the spi controller. The format of the gpio
-specifier depends on the gpio controller.
-
- samsung,spi-feedback-delay: The sampling phase shift to be applied on the
miso line (to account for any lag in the miso line). The following are the
valid values.
@@ -85,6 +83,7 @@ Example:
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = spi0_bus;
+ cs-gpios = gpa2 5 0;
w25q80bw@0 {
#address-cells = 1;
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
controller-data {
- cs-gpio = gpa2 5 1 0 3;
samsung,spi-feedback-delay = 0;
};
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a5696..b61ff3d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -197,7 +197,6 @@ struct s3c64xx_spi_driver_data {
struct s3c64xx_spi_dma_data tx_dma;
struct s3c64xx_spi_port_config *port_conf;
unsigned intport_id;
- boolcs_gpio;
};
static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
@@ -776,17 +775,6 @@ static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
return ERR_PTR(-ENOMEM);
}
- /* The CS line is asserted/deasserted by the gpio pin */
- if (sdd-cs_gpio)
- cs-line = of_get_named_gpio(data_np, cs-gpio, 0);
-
- if (!gpio_is_valid(cs-line)) {
- dev_err(spi-dev, chip select gpio is not specified or
invalid\n);
- kfree(cs);
- of_node_put(data_np);
- return ERR_PTR(-EINVAL);
- }
-
of_property_read_u32(data_np, samsung,spi-feedback-delay, fb_delay);
cs-fb_delay = fb_delay;
of_node_put(data_np);
@@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spi-controller_data = cs;
}
+ /* For the non-DT platforms derive
[PATCH 2/4] Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/
The DT bindings in exynos-adc.txt applies to the ADC
driver (exynos-adc.c) developed based on IIO framework.
The bindings are more appropriate to be under
Documentation/devicetree/bindings/iio/adc/
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: devicet...@vger.kernel.org
---
.../devicetree/bindings/arm/samsung/exynos-adc.txt | 82
.../devicetree/bindings/iio/adc/exynos-adc.txt | 82
2 files changed, 82 insertions(+), 82 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
deleted file mode 100644
index b87749a..000
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-Samsung Exynos Analog to Digital Converter bindings
-
-The devicetree bindings are for the new ADC driver written for
-Exynos4 and upward SoCs from Samsung.
-
-New driver handles the following
-1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
- and future SoCs from Samsung
-2. Add ADC driver under iio/adc framework
-3. Also adds the Documentation for device tree bindings
-
-Required properties:
-- compatible: Must be samsung,exynos-adc-v1
- for exynos4412/5250 controllers.
- Must be samsung,exynos-adc-v2 for
- future controllers.
- Must be samsung,exynos3250-adc-v2 for
- for controllers compatible with ADC of
- Exynos3250.
-- reg: Contains ADC register address range (base address and
- length) and the address of the phy enable register.
-- interrupts: Contains the interrupt information for the timer. The
- format is being dependent on which interrupt controller
- the Samsung device uses.
-- #io-channel-cells = 1; As ADC has multiple outputs
-- clocks From common clock bindings: handles to clocks specified
- in clock-names property, in the same order.
-- clock-names From common clock bindings: list of clock input names
- used by ADC block:
- - adc : ADC bus clock
- - sclk_adc : ADC special clock (only for Exynos3250
- and compatible ADC block)
-- vdd-supply VDD input supply.
-
-Note: child nodes can be added for auto probing from device tree.
-
-Example: adding device info in dtsi file
-
-adc: adc@12D1 {
- compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
- interrupts = 0 106 0;
- #io-channel-cells = 1;
- io-channel-ranges;
-
- clocks = clock 303;
- clock-names = adc;
-
- vdd-supply = buck5_reg;
-};
-
-Example: adding device info in dtsi file for Exynos3250 with additional sclk
-
-adc: adc@126C {
- compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
- interrupts = 0 137 0;
- #io-channel-cells = 1;
- io-channel-ranges;
-
- clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
- clock-names = adc, sclk_adc;
-
- vdd-supply = buck5_reg;
-};
-
-Example: Adding child nodes in dts file
-
-adc@12D1 {
-
- /* NTC thermistor is a hwmon device */
- ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
- pullup-uv = 180;
- pullup-ohm = 47000;
- pulldown-ohm = 0;
- io-channels = adc 4;
- };
-};
-
-Note: Does not apply to ADC driver under arch/arm/plat-samsung/
-Note: The child node can be added under the adc node or separately.
diff --git a/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
new file mode 100644
index 000..b87749a
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/exynos-adc.txt
@@ -0,0 +1,82 @@
+Samsung Exynos Analog to Digital Converter bindings
+
+The devicetree bindings are for the new ADC driver written for
+Exynos4 and upward SoCs from Samsung.
+
+New driver handles the following
+1. Supports ADC IF found on EXYNOS4412/EXYNOS5250
+ and future SoCs from Samsung
+2. Add ADC driver under iio/adc framework
+3. Also adds the Documentation for device tree bindings
+
+Required properties:
+- compatible: Must be samsung,exynos-adc-v1
+ for exynos4412/5250 controllers.
+ Must be samsung,exynos-adc-v2 for
+ future controllers.
+ Must be samsung,exynos3250-adc-v2 for
+ for controllers compatible
[PATCH 0/4] iio: exynos-adc: use syscon instead of ioremap
This patch does the following 1. Use the syscon and Regmap API instead of ioremappaing the ADC_PHY register from PMU. 2. Moves the exynos-adc.txt from bindings/arm/samsung/ to bindings/iio/adc/. 3. Updates the Documentation in exynos-adc.txt with syscon phandle for the ADC nodes. 4. Updates the Dts files for Exynos3250, Exynos4x12, Exynos5250, Exynos5420 with the syscon phandle. Tested on Exynos5420 based Peach PIT and Exynos5800 based Peach PI by verifying sysfs entries provided by HWMON based NTC thermistors. Tested-By for Exynos3250, Exynos4x12 would be appreciated. Naveen Krishna Chatradhi (4): iio: exyno-adc: use syscon for PMU register access Documentation: dt-bindings: move exynos-adc.txt to more iio/adc/ Documentation: dt-bindings: update exynos-adc.txt with syscon handle ARM: dts: exynos: Add sysreg phandle to ADC node .../devicetree/bindings/arm/samsung/exynos-adc.txt | 82 -- .../devicetree/bindings/iio/adc/exynos-adc.txt | 87 arch/arm/boot/dts/exynos3250.dtsi |3 +- arch/arm/boot/dts/exynos4x12.dtsi |3 +- arch/arm/boot/dts/exynos5250.dtsi |3 +- arch/arm/boot/dts/exynos5420.dtsi |3 +- drivers/iio/adc/exynos_adc.c | 29 +-- 7 files changed, 115 insertions(+), 95 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt create mode 100644 Documentation/devicetree/bindings/iio/adc/exynos-adc.txt -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] iio: exyno-adc: use syscon for PMU register access
This patch updates the IIO based ADC driver to use syscon and regmap
APIs to access and use PMU registers instead of remapping the PMU
registers in the driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-...@vger.kernel.org
---
drivers/iio/adc/exynos_adc.c | 29 -
1 file changed, 20 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
index b63e882..60847ef 100644
--- a/drivers/iio/adc/exynos_adc.c
+++ b/drivers/iio/adc/exynos_adc.c
@@ -38,6 +38,8 @@
#include linux/iio/iio.h
#include linux/iio/machine.h
#include linux/iio/driver.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
/* EXYNOS4412/5250 ADC_V1 registers definitions */
#define ADC_V1_CON(x) ((x) + 0x00)
@@ -79,11 +81,14 @@
#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
+#define EXYNOS_ADCV1_PHY_OFFSET0x0718
+#define EXYNOS_ADCV2_PHY_OFFSET0x0720
+
struct exynos_adc {
struct exynos_adc_data *data;
struct device *dev;
void __iomem*regs;
- void __iomem*enable_reg;
+ struct regmap *pmu_map;
struct clk *clk;
struct clk *sclk;
unsigned intirq;
@@ -98,6 +103,7 @@ struct exynos_adc {
struct exynos_adc_data {
int num_channels;
bool needs_sclk;
+ int phy_offset;
void (*init_hw)(struct exynos_adc *info);
void (*exit_hw)(struct exynos_adc *info);
@@ -169,7 +175,7 @@ static void exynos_adc_v1_init_hw(struct exynos_adc *info)
{
u32 con1;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
/* set default prescaler values and Enable prescaler */
con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
@@ -183,7 +189,7 @@ static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V1_CON(info-regs));
con |= ADC_V1_CON_STANDBY;
@@ -208,6 +214,7 @@ static void exynos_adc_v1_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v1_data = {
.num_channels = MAX_ADC_V1_CHANNELS,
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.init_hw= exynos_adc_v1_init_hw,
.exit_hw= exynos_adc_v1_exit_hw,
@@ -219,7 +226,7 @@ static void exynos_adc_v2_init_hw(struct exynos_adc *info)
{
u32 con1, con2;
- writel(1, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 1);
con1 = ADC_V2_CON1_SOFT_RESET;
writel(con1, ADC_V2_CON1(info-regs));
@@ -236,7 +243,7 @@ static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
{
u32 con;
- writel(0, info-enable_reg);
+ regmap_write(info-pmu_map, info-data-phy_offset, 0);
con = readl(ADC_V2_CON1(info-regs));
con = ~ADC_CON_EN_START;
@@ -271,10 +278,12 @@ static void exynos_adc_v2_start_conv(struct exynos_adc
*info,
static struct exynos_adc_data const exynos_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
};
static struct exynos_adc_data const exynos3250_adc_v2_data = {
__EXYNOS_ADC_V2_DATA
+ .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
.needs_sclk = true,
};
@@ -437,10 +446,12 @@ static int exynos_adc_probe(struct platform_device *pdev)
if (IS_ERR(info-regs))
return PTR_ERR(info-regs);
- mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- info-enable_reg = devm_ioremap_resource(pdev-dev, mem);
- if (IS_ERR(info-enable_reg))
- return PTR_ERR(info-enable_reg);
+ info-pmu_map = syscon_regmap_lookup_by_phandle(pdev-dev.of_node,
+ samsung,syscon-phandle);
+ if (IS_ERR(info-pmu_map)) {
+ dev_err(pdev-dev, syscon regmap lookup failed.\n);
+ return PTR_ERR(info-pmu_map);
+ }
irq = platform_get_irq(pdev, 0);
if (irq 0) {
--
1.7.9.5
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[PATCH 4/4] ARM: dts: exynos: Add sysreg phandle to ADC node
Instead of using the ADC_PHY register base address, use sysreg phandle
in ADC node to control ADC_PHY configuration register.
This patch adds syscon node for Exynos3250, Exynos4x12, Exynos5250,
and Exynos5420, Exynos5800.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
To: linux-samsung-soc@vger.kernel.org
---
arch/arm/boot/dts/exynos3250.dtsi |3 ++-
arch/arm/boot/dts/exynos4x12.dtsi |3 ++-
arch/arm/boot/dts/exynos5250.dtsi |3 ++-
arch/arm/boot/dts/exynos5420.dtsi |3 ++-
4 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index c5e15db..51c9b0d 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -262,12 +262,13 @@
adc: adc@126C {
compatible = samsung,exynos3250-adc-v2;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupts = 0 137 0;
clock-names = adc, sclk_adc;
clocks = cmu CLK_TSADC, cmu CLK_SCLK_TSADC;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi
b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..9a18d9b 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -114,13 +114,14 @@
adc: adc@126C {
compatible = samsung,exynos-adc-v1;
- reg = 0x126C 0x100, 0x10020718 0x4;
+ reg = 0x126C 0x100;
interrupt-parent = combiner;
interrupts = 10 3;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..6003777 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -762,12 +762,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v1;
- reg = 0x12D1 0x100, 0x10040718 0x4;
+ reg = 0x12D1 0x100
interrupts = 0 106 0;
clocks = clock CLK_ADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index e385322..6979da8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -525,12 +525,13 @@
adc: adc@12D1 {
compatible = samsung,exynos-adc-v2;
- reg = 0x12D1 0x100, 0x10040720 0x4;
+ reg = 0x12D1 0x100;
interrupts = 0 106 0;
clocks = clock CLK_TSADC;
clock-names = adc;
#io-channel-cells = 1;
io-channel-ranges;
+ samsung,syscon-phandle = pmu_system_controller;
status = disabled;
};
--
1.7.9.5
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[PATCH v2 2/2] ARM: DTS: Add thermistor dts fragment used by exynos based Peach boards
This patch creates a thermistor fragment carrying the NTC Thermistor
nodes as children of the IIO based ADC.
This fragment is included in exynos5420-peach-pit.dts and
exynos5800-peach-pi.dts.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v1:
As per the comments https://lkml.org/lkml/2014/6/26/271
and discussion about fragments vs common dtsi
@ http://patchwork.ozlabs.org/patch/362633/.
Created a thermistors fragment instead of a common dtsi file
cat sysfs entries exported by hwmon for 4 thermistors
and verified the values on Peach pit and pi boards.
arch/arm/boot/dts/cros-adc-thermistors.dtsi | 44 +++
arch/arm/boot/dts/exynos5420-peach-pit.dts |6
arch/arm/boot/dts/exynos5800-peach-pi.dts |6
3 files changed, 56 insertions(+)
create mode 100644 arch/arm/boot/dts/cros-adc-thermistors.dtsi
diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi
b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
new file mode 100644
index 000..17fce72
--- /dev/null
+++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Thermistor dts fragment for devices that use Thermistors as
+ * children of the IIO based ADC.
+ *
+ * Currently, used by Exynos5420 based Peach PIT and
+ * Exynos5800 based Peach PI.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+adc {
+ ncp15wb473@3 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 3;
+ };
+ ncp15wb473@4 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 4;
+ };
+ ncp15wb473@5 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 5;
+ };
+ ncp15wb473@6 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 6;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index d124394..7c64009 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -101,6 +101,11 @@
};
};
+adc {
+ status = okay;
+ vdd-supply = ldo9_reg;
+};
+
dp {
status = okay;
pinctrl-names = default;
@@ -775,3 +780,4 @@
};
#include cros-ec-keyboard.dtsi
+#include cros-adc-thermistors.dtsi
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index c36c9ce..4fd48b9 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -99,6 +99,11 @@
};
};
+adc {
+ status = okay;
+ vdd-supply = ldo9_reg;
+};
+
dp {
status = okay;
pinctrl-names = default;
@@ -773,3 +778,4 @@
};
#include cros-ec-keyboard.dtsi
+#include cros-adc-thermistors.dtsi
--
1.7.9.5
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[PATCH v2 1/2] ARM: DTS: use new compatible string for thermistors in trats2
As Murata Manufactures the NTC based thermistors. The vendor
name in the compatibility is preposed to change to murata
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
Changes since v1: None
arch/arm/boot/dts/exynos4412-trats2.dts |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4..d35755a 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -771,7 +771,7 @@
};
thermistor-ap@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
@@ -779,7 +779,7 @@
};
thermistor-battery@1 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
--
1.7.9.5
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[PATCH 0/2 v2] ARM: DTS: create thermistor fragment dtsi for Peach boards
This patchset does the following 1. Create a thermistor dtsi fragment file cros-adc-thermistors.dtsi for exynos5420-peach-pit.dts and exynos5800-peach-pi.dts 2. Adds the ADC based Thermistor nodes and enables them in peach_pit.dts and peach_pi.dts 3. Corrects the vendor prefix for thermistors in exynos4412-trats2.dts This patch depends on (1/4 and 2/4 patches of) patchset posted http://www.spinics.net/lists/linux-iio/msg13486.html Which were applied on to Guenter Roeck's tree. cat sysfs entries exported by hwmon for 4 thermistors and verified the values on Peach pit and pi boards. Changes since v1: 1. Dropped 2/3 ARM: DTS: Add NTC thermistor nodes to Exynos5250 based Snow https://lkml.org/lkml/2014/6/26/192 As large number of Snow boards dint have thermistors. 2. Created a thermistor fragment instead of common dtsi file Naveen Krishna Chatradhi (2): ARM: DTS: use new compatible string for thermistors in trats2 ARM: DTS: Add thermistor dts fragment needed by exynos based peach boards arch/arm/boot/dts/cros-adc-thermistors.dtsi | 44 +++ arch/arm/boot/dts/exynos4412-trats2.dts |4 +-- arch/arm/boot/dts/exynos5420-peach-pit.dts |6 arch/arm/boot/dts/exynos5800-peach-pi.dts |6 4 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/cros-adc-thermistors.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/3] ARM: DTS: create common dtsi for Peach pit and pi boards
This patchset does the following 1. Create a common dtsi file cros-exynos-peach.dtsi for exynos5420-peach-pit.dts and exynos5800-peach-pi.dts 2. Adds the ADC based Thermistor nodes and enables them in peach_pit.dts and peach_pi.dts 3. Adds the ADC based Thermistor nodes for Exynos5250 based Snow 4. Corrects the vendor prefix for thermistors in exynos4412-trats2.dts Naveen Krishna Chatradhi (3): ARM: DTS: use new compatible string for thermistors in trats2 ARM: DTS: Add NTC thermistor nodes to Exynos5250 based Snow ARM: DTS: Add common dts file for Peach PIT and PI along with ADC nodes arch/arm/boot/dts/cros-exynos-peach.dtsi | 41 arch/arm/boot/dts/exynos4412-trats2.dts|4 +-- arch/arm/boot/dts/exynos5250-snow.dts | 34 +++ arch/arm/boot/dts/exynos5420-peach-pit.dts |6 arch/arm/boot/dts/exynos5800-peach-pi.dts |6 5 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/cros-exynos-peach.dtsi -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] ARM: DTS: use new compatible string for thermistors in trats2
As Murata Manufactures the NTC based thermistors. The vendor
name in the compatibility is preposed to change to murata
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Chanwoo Choi cw00.c...@samsung.com
Reviewed-by: Chanwoo Choi cw00.c...@samsung.com
---
This patch is carried forward (tracking purpose) along with the other
dts changes in the patch set discussed
http://www.spinics.net/lists/linux-iio/msg13486.html
This patch was posted
http://www.spinics.net/lists/linux-samsung-soc/msg33037.html
arch/arm/boot/dts/exynos4412-trats2.dts |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4..d35755a 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -771,7 +771,7 @@
};
thermistor-ap@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
@@ -779,7 +779,7 @@
};
thermistor-battery@1 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
--
1.7.9.5
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[PATCH 2/3] ARM: DTS: Add NTC thermistor nodes to Exynos5250 based Snow
Exynos5250 based Snow board has 4 NTC thermistors to measure
temperatures at various points on the board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the HWMON interface.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Posted earlier by Doug Anderson @ https://lkml.org/lkml/2013/3/27/453
This patch depends on (1/4 and 2/4 patches of) patchset posted
http://www.spinics.net/lists/linux-iio/msg13486.html
Which were applied on to Guenter Roeck's tree.
cat sysfs entries exported by hwmon for 4 thermistors
and verified the values on Snow.
arch/arm/boot/dts/exynos5250-snow.dts | 34 +
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index 7bd2df1..0fa7067 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -20,6 +20,40 @@
i2c104 = i2c_104;
};
+ adc@12D1 {
+ status = okay;
+ vdd-supply = buck5_reg;
+
+ ncp15wb473@3 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 3;
+ };
+ ncp15wb473@4 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 4;
+ };
+ ncp15wb473@5 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 5;
+ };
+ ncp15wb473@6 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 6;
+ };
+ };
+
rtc@101E {
status = okay;
};
--
1.7.9.5
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[PATCH 3/3] ARM: DTS: Add common dts file for Peach PIT and PI along with ADC nodes
DTS files exynos5420-peach-pit.dts and exynos5800-peach-pi.dts
have lots of device tree nodes in common.
This patch creates a cros-exynos-peach.dts file, which can carry the
device tree nodes common across exynos5420-peach-pit.dts and
exynos5800-peach-pi.dts. Starting with ADC based Thermistor nodes.
Also, enables ADC based thermistors for peach_pi and peach_pit.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
This patchset needs
[PATCH v4 00/14] Add Maxim 77802 PMIC support by Javier Martinez Canillas
Posted https://lkml.org/lkml/2014/6/25/668
Intention is to slowly move the common DT nodes across exynos5420-peach-pit.dts
and exynos5800-peach-pi.dts into cros-exynos-peach.dts
I'm unsure of the naming conventions for dts files
Named it cros-exynos-peach.dts as below.
used for cros + based on exynos + boards named peach in common.
cat sysfs entries exported by hwmon for 4 thermistors
and verified the values on peach pit.
arch/arm/boot/dts/cros-exynos-peach.dtsi | 41
arch/arm/boot/dts/exynos5420-peach-pit.dts |6
arch/arm/boot/dts/exynos5800-peach-pi.dts |6
3 files changed, 53 insertions(+)
create mode 100644 arch/arm/boot/dts/cros-exynos-peach.dtsi
diff --git a/arch/arm/boot/dts/cros-exynos-peach.dtsi
b/arch/arm/boot/dts/cros-exynos-peach.dtsi
new file mode 100644
index 000..86135bd
--- /dev/null
+++ b/arch/arm/boot/dts/cros-exynos-peach.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Common device tree include for Exynos5420 based Peach PIT and
+ * Exynos5800 based Peach PI.
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+adc {
+ ncp15wb473@3 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 3;
+ };
+ ncp15wb473@4 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 4;
+ };
+ ncp15wb473@5 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 5;
+ };
+ ncp15wb473@6 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 6;
+ };
+};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index d124394..682b9c2 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -12,6 +12,7 @@
#include dt-bindings/input/input.h
#include dt-bindings/gpio/gpio.h
#include exynos5420.dtsi
+#include cros-exynos-peach.dtsi
/ {
model = Google Peach Pit Rev 6+;
@@ -101,6 +102,11 @@
};
};
+adc {
+ status = okay;
+ vdd-supply = ldo9_reg;
+};
+
dp {
status = okay;
pinctrl-names = default;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts
b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index c36c9ce..7552173 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -12,6 +12,7 @@
#include dt-bindings/input/input.h
#include dt-bindings/gpio/gpio.h
#include exynos5800.dtsi
+#include cros-exynos-peach.dtsi
/ {
model = Google Peach Pi Rev 10+;
@@ -99,6 +100,11 @@
};
};
+adc {
+ status = okay;
+ vdd-supply = ldo9_reg;
+};
+
dp {
status = okay;
pinctrl-names = default;
--
1.7.9.5
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[PATCH 1/4 v2] devicetree: bindings: Document murata vendor prefix
Add Murata Manufacturing Co., Ltd. to the list of device tree vendor prefixes. Murata manufactures NTC (Negative Temperature Coefficient) based Thermistors for small scale applications like Mobiles and PDAs. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Acked-by: Mark Rutland mark.rutl...@arm.com Cc: Guenter Roeck li...@roeck-us.net --- Changes since v1: 1. Rearranged vendor-prefix alphabetically 2. Added Acked-by from Mark Rutland .../devicetree/bindings/vendor-prefixes.txt|1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4d7f375..46a311e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -83,6 +83,7 @@ mosaixtechMosaix Technologies, Inc. moxa Moxa mplMPL AG mundoreaderMundo Reader S.L. +murata Murata Manufacturing Co., Ltd. mxicy Macronix International Co., Ltd. national National Semiconductor neonodeNeonode Inc. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 4/4 v2] ARM: DTS: Add NTC thermistor nodes to Exynos5420 based Peach_PIT
Exynos5420 based Peach PIT board has 4 NTC thermistors to measure
temperatures at various points on the board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the HWMON interface.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Doug Anderson diand...@chromium.org
---
Changes since v1:
1. Arranged the ADC node alphabetical
2. Added status = okay to the ADC node
This patch needs
1. MAX77802 PMIC device tree nodes (for ldo9)
https://www.mail-archive.com/devicetree@vger.kernel.org/msg31430.html
2. Uses the DT documentation for NTC thermistors updated with vendor-prefix
This patch set is tested
1. On Peach PIT board via sysfs entry exposed by hwmon
localhost ~ # cat /sys/class/hwmon/hwmon*/device/temp1_input
37436
36449
38560
38059
2. Backward compatibility is tested by replacing murata with ntc
in the dts nodes and running the above test.
arch/arm/boot/dts/exynos5420-peach-pit.dts | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index b96a66a..19d733d 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -101,6 +101,40 @@
};
};
+adc {
+ status = okay;
+ vdd-supply = ldo9_reg;
+
+ ncp15wb473@3 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 3;
+ };
+ ncp15wb473@4 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 4;
+ };
+ ncp15wb473@5 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 5;
+ };
+ ncp15wb473@6 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 6;
+ };
+};
+
dp {
status = okay;
pinctrl-names = default;
--
1.7.9.5
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[PATCH 3/4 v2] ARM: DTS: use new compatible string for thermistors in trats2
As Murata Manufactures the NTC based thermistors. The vendor
name in the compatibility is preposed to change to murata
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Chanwoo Choi cw00.c...@samsung.com
---
Changes since v1:
None
arch/arm/boot/dts/exynos4412-trats2.dts |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4..d35755a 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -771,7 +771,7 @@
};
thermistor-ap@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
@@ -779,7 +779,7 @@
};
thermistor-battery@1 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
--
1.7.9.5
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[PATCH 2/4 v2] hwmon: ntc_thermistor: Use the manufacturer name properly
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses NTC as the vendor name.
This patch corrects the vendor name also updates the
compatibility strings according to the vendor-prefix.txt
Note: Drivers continue to support the previous compatible strings
but further addition of these compatible strings in device tree
is deprecated.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Guenter Roeck li...@roeck-us.net
---
Changes since v1:
1. Kept the old compatible string marked as DEPRECATED in code and
in the Documentation.
.../devicetree/bindings/arm/samsung/exynos-adc.txt |2 +-
.../devicetree/bindings/hwmon/ntc_thermistor.txt | 20 ++--
Documentation/hwmon/ntc_thermistor |8
drivers/hwmon/Kconfig |5 +++--
drivers/hwmon/ntc_thermistor.c | 14 +-
5 files changed, 35 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 5d49f2b..832fe8c 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -48,7 +48,7 @@ adc@12D1 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180;
pullup-ohm = 47000;
pulldown-ohm = 0;
diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
index c6f6667..b117b2e 100644
--- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
+++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
@@ -3,11 +3,19 @@ NTC Thermistor hwmon sensors
Requires node properties:
- compatible value : one of
- ntc,ncp15wb473
- ntc,ncp18wb473
- ntc,ncp21wb473
- ntc,ncp03wb473
- ntc,ncp15wl333
+ murata,ncp15wb473
+ murata,ncp18wb473
+ murata,ncp21wb473
+ murata,ncp03wb473
+ murata,ncp15wl333
+
+/* Usage of vendor name ntc is deprecated */
+DEPRECATED ntc,ncp15wb473
+DEPRECATED ntc,ncp18wb473
+DEPRECATED ntc,ncp21wb473
+DEPRECATED ntc,ncp03wb473
+DEPRECATED ntc,ncp15wl333
+
- pullup-uv Pull up voltage in micro volts
- pullup-ohm Pull up resistor value in ohms
- pulldown-ohm Pull down resistor value in ohms
@@ -21,7 +29,7 @@ Read more about iio bindings at
Example:
ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180;
pullup-ohm = 47000;
pulldown-ohm = 0;
diff --git a/Documentation/hwmon/ntc_thermistor
b/Documentation/hwmon/ntc_thermistor
index 3bfda94..057b770 100644
--- a/Documentation/hwmon/ntc_thermistor
+++ b/Documentation/hwmon/ntc_thermistor
@@ -1,7 +1,7 @@
Kernel driver ntc_thermistor
=
-Supported thermistors:
+Supported thermistors from Murata:
* Murata NTC Thermistors NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473,
NCP15WL333
Prefixes: 'ncp15wb473', 'ncp18wb473', 'ncp21wb473', 'ncp03wb473',
'ncp15wl333'
Datasheet: Publicly available at Murata
@@ -15,9 +15,9 @@ Authors:
Description
---
-The NTC thermistor is a simple thermistor that requires users to provide the
-resistance and lookup the corresponding compensation table to get the
-temperature input.
+The NTC (Negative Temperature Coefficient) thermistor is a simple thermistor
+that requires users to provide the resistance and lookup the corresponding
+compensation table to get the temperature input.
The NTC driver provides lookup tables with a linear approximation function
and four circuit models with an option not to use any of the four models.
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 08531a1..154851b 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1052,7 +1052,7 @@ config SENSORS_PC87427
will be called pc87427.
config SENSORS_NTC_THERMISTOR
- tristate NTC thermistor support
+ tristate NTC thermistor support from Murata
depends on !OF || IIO=n || IIO
help
This driver supports NTC thermistors sensor reading and its
@@ -1060,7 +1060,8 @@ config SENSORS_NTC_THERMISTOR
send notifications about the temperature.
Currently, this driver supports
- NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, and NCP15WL333.
+ NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, and NCP15WL333
+ from Murata.
This driver can also be built as a module. If so, the module
will be called ntc-thermistor.
diff --git a/drivers/hwmon/ntc_thermistor.c b/drivers/hwmon
[PATCH 1/2] i2c: exynos5: remove an unnecessary read of FIFO_STATUS register
This patch removes an extra read of FIFO_STATUS register in the interrrupt
service routine. Which is read again before the actual use.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 63d2292..0d1a7bc 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -405,7 +405,6 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
int_status = readl(i2c-regs + HSI2C_INT_STATUS);
writel(int_status, i2c-regs + HSI2C_INT_STATUS);
- fifo_status = readl(i2c-regs + HSI2C_FIFO_STATUS);
/* handle interrupt related to the transfer status */
if (int_status HSI2C_INT_I2C) {
--
1.7.9.5
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[PATCH 2/2] i2c: exynos5: fix minor styling nits
This patch removes an extra line and fixes a styling nit
in exynos5_i2c_message_start()
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
drivers/i2c/busses/i2c-exynos5.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 0d1a7bc..4c2e6f3 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -525,7 +525,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
if (i2c-msg-flags I2C_M_RD) {
i2c_ctl |= HSI2C_RXCHON;
- i2c_auto_conf = HSI2C_READ_WRITE;
+ i2c_auto_conf |= HSI2C_READ_WRITE;
trig_lvl = (i2c-msg-len i2c-variant-fifo_depth) ?
(i2c-variant-fifo_depth * 3 / 4) : i2c-msg-len;
@@ -548,7 +548,6 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
writel(fifo_ctl, i2c-regs + HSI2C_FIFO_CTL);
writel(i2c_ctl, i2c-regs + HSI2C_CTL);
-
/*
* Enable interrupts before starting the transfer so that we don't
* miss any INT_I2C interrupts.
--
1.7.9.5
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[PATCH 1/2 v2] i2c: exynos5: remove an unnecessary read of FIFO_STATUS register
This patch removes an extra read of FIFO_STATUS register in the interrrupt
service routine. Which is read again before the actual use.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v1:
None
drivers/i2c/busses/i2c-exynos5.c |1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 63d2292..0d1a7bc 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -405,7 +405,6 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
int_status = readl(i2c-regs + HSI2C_INT_STATUS);
writel(int_status, i2c-regs + HSI2C_INT_STATUS);
- fifo_status = readl(i2c-regs + HSI2C_FIFO_STATUS);
/* handle interrupt related to the transfer status */
if (int_status HSI2C_INT_I2C) {
--
1.7.9.5
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[PATCH 2/2 v2] i2c: exynos5: remove extra line and fix an assignment
This patch does the following in exynos5_i2c_message_start() function
1. Fixes an assignment
As, i2c_auto_conf is initialized to '0' at the beginning of the
function and HSI2C_READ_WRITE is defined as (1u 16)
Using |= for the first assignment is more readable.
2. Removes an extra line
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v1:
Edited commit message for clarity
drivers/i2c/busses/i2c-exynos5.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 0d1a7bc..4c2e6f3 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -525,7 +525,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
if (i2c-msg-flags I2C_M_RD) {
i2c_ctl |= HSI2C_RXCHON;
- i2c_auto_conf = HSI2C_READ_WRITE;
+ i2c_auto_conf |= HSI2C_READ_WRITE;
trig_lvl = (i2c-msg-len i2c-variant-fifo_depth) ?
(i2c-variant-fifo_depth * 3 / 4) : i2c-msg-len;
@@ -548,7 +548,6 @@ static void exynos5_i2c_message_start(struct exynos5_i2c
*i2c, int stop)
writel(fifo_ctl, i2c-regs + HSI2C_FIFO_CTL);
writel(i2c_ctl, i2c-regs + HSI2C_CTL);
-
/*
* Enable interrupts before starting the transfer so that we don't
* miss any INT_I2C interrupts.
--
1.7.9.5
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[PATCH 0/4] hwmon: ntc_thermistor: prepose vendor prefix change
As Murata is the manufacturer of the NTC (Negative Temperature coefficient) based Thermistors. ntc_thermistor driver extensively used the prefix ntc. But, vendor-prefix should be murata instead of ntc. This patchset 1. Updates the vendor-prefix, DT bindings and Documentation, where ever necessary. 2. Adds thermistor nodes to Exynos5420 and Exynos5800 based boards. Patches: 1/4. devicetree: bindings: Document murata vendor prefix Adds the vendor prefix murata to vendor-prefixes.txt. 2/4. hwmon: ntc_thermistor: Use the manufacturer name properly Updates the driver, Kconfig, device tree bindings and Documentation with the Manufacturer/vendor information. 3/4. ARM: DTS: use new compatible string as per the documentation Updates the device node in Exynos4412 based Trats2 board with the new device tree bindings. 4/4. ARM: DTS: Add NTC thermistor nodes as child nodes to ADC Adds Thermistor nodes to Exynos5420 and Exynos5800 based boards. This patchset Naveen Krishna Chatradhi (4): devicetree: bindings: Document murata vendor prefix hwmon: ntc_thermistor: Use the manufacturer name properly ARM: DTS: Add NTC thermistor nodes as child nodes to ADC ARM: DTS: use new compatible string as per the documentation .../devicetree/bindings/arm/samsung/exynos-adc.txt |2 +- .../devicetree/bindings/hwmon/ntc_thermistor.txt | 12 .../devicetree/bindings/vendor-prefixes.txt|1 + Documentation/hwmon/ntc_thermistor |8 ++--- arch/arm/boot/dts/exynos4412-trats2.dts|4 +-- arch/arm/boot/dts/exynos5420-peach-pit.dts | 32 drivers/hwmon/Kconfig |5 +-- drivers/hwmon/ntc_thermistor.c | 12 8 files changed, 55 insertions(+), 21 deletions(-) -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] devicetree: bindings: Document murata vendor prefix
Add Murata Manufacturing Co., Ltd. to the list of device tree vendor prefixes. Murata manufactures NTC (Negative Temperature Coefficient) based Thermistors for small scale applications like Mobiles and PDAs. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com Cc: Guenter Roeck li...@roeck-us.net --- This changes is needed for the following reasons 1. The vendor prefix ntc is not defined in vendor-prefixes.txt Thus, giving an error when checked with scripts/checkpatch.pl 2. Murata Manufacturing Co., Ltd. Is the vendor for the NTC (Negative Temperature Coefficient) based thermistors. Hence, murata is the right vendor-prefix, Not ntc. 3. NTC is a technology used, But the prefix ntc is wrongly and heavily used in the driver and the documentation. .../devicetree/bindings/vendor-prefixes.txt|1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 4d7f375..a39b7d7 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -84,6 +84,7 @@ moxa Moxa mplMPL AG mundoreaderMundo Reader S.L. mxicy Macronix International Co., Ltd. +murata Murata Manufacturing Co., Ltd. national National Semiconductor neonodeNeonode Inc. netgearNETGEAR -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/4] ARM: DTS: use new compatible string as per the documentation
As Murata is the Manufactures the NTC thermistors. The vendor
name in the compatibility is preposed to change to murata, ncpXXX
This patch uses the new compatibility string in exynos4412 based
Trats2 board.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Chanwoo Choi cw00.c...@samsung.com
---
1. Updates the thermistor node in Exynos4412 based Trats2 dts
using the new DT bindings for NTC thermistors updated with vendor-prefix
arch/arm/boot/dts/exynos4412-trats2.dts |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 11967f4..d35755a 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -771,7 +771,7 @@
};
thermistor-ap@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
@@ -779,7 +779,7 @@
};
thermistor-battery@1 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180; /* VCC_1.8V_AP */
pullup-ohm = 10; /* 100K */
pulldown-ohm = 10; /* 100K */
--
1.7.9.5
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[PATCH 2/4] hwmon: ntc_thermistor: Use the manufacturer name properly
Murata Manufacturing Co., Ltd is the vendor for
NTC (Negative Temperature coefficient) based Thermistors.
But, the driver extensively uses NTC as the vendor name.
This patch corrects the vendor name also updates the
compatibility strings according to the vendor-prefix.txt
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Guenter Roeck li...@roeck-us.net
---
This changes is needed for the following reasons
1. The vendor prefix ntc is not defined in vendor-prefixes.txt
Thus, giving an error when checked with scripts/checkpatch.pl
2. Murata Manufacturing Co., Ltd. Is the vendor for the
NTC (Negative Temperature Coefficient) based thermistors.
Hence, murata is the right vendor-prefix, Not ntc.
3. NTC is a technology used, But the prefix ntc is wrongly
and heavily used in the driver and the documentation.
.../devicetree/bindings/arm/samsung/exynos-adc.txt |2 +-
.../devicetree/bindings/hwmon/ntc_thermistor.txt | 12 ++--
Documentation/hwmon/ntc_thermistor |8
drivers/hwmon/Kconfig |5 +++--
drivers/hwmon/ntc_thermistor.c | 12 ++--
5 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
index 5d49f2b..832fe8c 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-adc.txt
@@ -48,7 +48,7 @@ adc@12D1 {
/* NTC thermistor is a hwmon device */
ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180;
pullup-ohm = 47000;
pulldown-ohm = 0;
diff --git a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
index c6f6667..4e9f344 100644
--- a/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
+++ b/Documentation/devicetree/bindings/hwmon/ntc_thermistor.txt
@@ -3,11 +3,11 @@ NTC Thermistor hwmon sensors
Requires node properties:
- compatible value : one of
- ntc,ncp15wb473
- ntc,ncp18wb473
- ntc,ncp21wb473
- ntc,ncp03wb473
- ntc,ncp15wl333
+ murata,ncp15wb473
+ murata,ncp18wb473
+ murata,ncp21wb473
+ murata,ncp03wb473
+ murata,ncp15wl333
- pullup-uv Pull up voltage in micro volts
- pullup-ohm Pull up resistor value in ohms
- pulldown-ohm Pull down resistor value in ohms
@@ -21,7 +21,7 @@ Read more about iio bindings at
Example:
ncp15wb473@0 {
- compatible = ntc,ncp15wb473;
+ compatible = murata,ncp15wb473;
pullup-uv = 180;
pullup-ohm = 47000;
pulldown-ohm = 0;
diff --git a/Documentation/hwmon/ntc_thermistor
b/Documentation/hwmon/ntc_thermistor
index 3bfda94..057b770 100644
--- a/Documentation/hwmon/ntc_thermistor
+++ b/Documentation/hwmon/ntc_thermistor
@@ -1,7 +1,7 @@
Kernel driver ntc_thermistor
=
-Supported thermistors:
+Supported thermistors from Murata:
* Murata NTC Thermistors NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473,
NCP15WL333
Prefixes: 'ncp15wb473', 'ncp18wb473', 'ncp21wb473', 'ncp03wb473',
'ncp15wl333'
Datasheet: Publicly available at Murata
@@ -15,9 +15,9 @@ Authors:
Description
---
-The NTC thermistor is a simple thermistor that requires users to provide the
-resistance and lookup the corresponding compensation table to get the
-temperature input.
+The NTC (Negative Temperature Coefficient) thermistor is a simple thermistor
+that requires users to provide the resistance and lookup the corresponding
+compensation table to get the temperature input.
The NTC driver provides lookup tables with a linear approximation function
and four circuit models with an option not to use any of the four models.
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 08531a1..154851b 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1052,7 +1052,7 @@ config SENSORS_PC87427
will be called pc87427.
config SENSORS_NTC_THERMISTOR
- tristate NTC thermistor support
+ tristate NTC based thermistor support from Murata
depends on !OF || IIO=n || IIO
help
This driver supports NTC thermistors sensor reading and its
@@ -1060,7 +1060,8 @@ config SENSORS_NTC_THERMISTOR
send notifications about the temperature.
Currently, this driver supports
- NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, and NCP15WL333.
+ NCP15WB473, NCP18WB473, NCP21WB473, NCP03WB473, and NCP15WL333
+ from Murata.
This driver can also be built as a module. If so, the module
will be called ntc-thermistor.
diff --git a/drivers/hwmon/ntc_thermistor.c b/drivers/hwmon
[PATCH 4/4] ARM: DTS: Add NTC thermistor nodes as child nodes to ADC
Exynos5420 based Peach PIT and Exynos5800 based PI boards have
4 NTC thermistors to measure temperatures at various points on the
board.
IIO based ADC becomes the parent and NTC thermistors are the childs,
via the HWMON interface.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Doug Anderson diand...@chromium.org
---
This patch needs
1. MAX77802 PMIC device tree nodes (for ldo9)
https://www.mail-archive.com/devicetree@vger.kernel.org/msg31430.html
2. Uses the DT documentation for NTC thermistors updated with vendor-prefix
arch/arm/boot/dts/exynos5420-peach-pit.dts | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts
b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index b96a66a..852a220 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -751,4 +751,36 @@
timeout-sec = 32;
};
+adc {
+ vdd-supply = ldo9_reg;
+ ncp15wb473@3 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 3;
+ };
+ ncp15wb473@4 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 4;
+ };
+ ncp15wb473@5 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 5;
+ };
+ ncp15wb473@6 {
+ compatible = murata,ncp15wb473;
+ pullup-uv = 180;
+ pullup-ohm = 47000;
+ pulldown-ohm = 0;
+ io-channels = adc 6;
+ };
+};
+
#include cros-ec-keyboard.dtsi
--
1.7.9.5
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[PATCH] ARM: DTS: correct the capability string for mmc0
MMC capability for HS200 is parsed in mmc/core/host.c as dts string mmc-hs200-1_8v. This patch corrects the dts string for Exynos5420 based peach-pit and Exynos5800 based peach-pi boards. Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com --- arch/arm/boot/dts/exynos5420-peach-pit.dts |2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 7649982..7dea480 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -173,7 +173,7 @@ status = okay; num-slots = 1; broken-cd; - caps2-mmc-hs200-1_8v; + mmc-hs200-1_8v; supports-highspeed; non-removable; card-detect-delay = 200; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 2c2c137..bb3ee76 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -171,7 +171,7 @@ status = okay; num-slots = 1; broken-cd; - caps2-mmc-hs200-1_8v; + mmc-hs200-1_8v; supports-highspeed; non-removable; card-detect-delay = 200; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3 v4] spi: s3c64xx: for DT platofrms always get the chipselect info from DT node
Use controller_data structure only for the Non Device tree platforms.
For Device tree platforms, always derive the chipselect info from
DT node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
drivers/spi/spi-s3c64xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b888c66..f27e15d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -795,14 +795,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
int err;
sdd = spi_master_get_devdata(spi-master);
- if (!cs spi-dev.of_node) {
+ if (spi-dev.of_node) {
cs = s3c64xx_get_slave_ctrldata(spi);
spi-controller_data = cs;
- }
-
- /* For the non-DT platforms derive chip selects from controller data */
- if (!spi-dev.of_node)
+ } else {
+ /* For the non-DT platforms derive chip
+* selects from controller data
+*/
spi-cs_gpio = cs-line;
+ }
if (IS_ERR_OR_NULL(cs)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
--
1.7.9.5
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[PATCH 3/3 v4] ARM: DTS: fix the chip select gpios definition in the SPI nodes
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@ http://www.spinics.net/lists/linux-samsung-soc/msg32282.html
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d166..9191491 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -169,6 +169,7 @@
spi_2: spi@1394 {
status = okay;
+ cs-gpios = gpc1 2 0;
w25x80@0 {
#address-cells = 1;
@@ -178,7 +179,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpc1 2 0;
samsung,spi-feedback-delay = 0;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 8a558b7..204b0de 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -512,6 +512,7 @@
spi_1: spi@1393 {
pinctrl-names = default;
pinctrl-0 = spi1_bus;
+ cs-gpios = gpb 5 0;
status = okay;
s5c73m3_spi: s5c73m3 {
@@ -519,7 +520,6 @@
spi-max-frequency = 5000;
reg = 0;
controller-data {
- cs-gpio = gpb 5 0;
samsung,spi-feedback-delay = 2;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..0c6433a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
};
spi_1: spi@12d3 {
+ cs-gpios = gpa2 5 0;
status = okay;
w25q80bw@0 {
@@ -326,7 +327,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpa2 5 0;
samsung,spi-feedback-delay = 0;
};
--
1.7.9.5
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[PATCH 2/3 v5] spi: s3c64xx: for DT platofrms always get the chipselect info from DT node
Use controller_data structure only for the Non Device tree platforms.
For Device tree platforms, always derive the chipselect info from
DT node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Doug Anderson diand...@chromium.org
---
Changes since v4:
1. Added reviewed by from Javier and Tested by from Doug
Changes since v3:
New change
drivers/spi/spi-s3c64xx.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index b888c66..f27e15d 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -795,14 +795,15 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
int err;
sdd = spi_master_get_devdata(spi-master);
- if (!cs spi-dev.of_node) {
+ if (spi-dev.of_node) {
cs = s3c64xx_get_slave_ctrldata(spi);
spi-controller_data = cs;
- }
-
- /* For the non-DT platforms derive chip selects from controller data */
- if (!spi-dev.of_node)
+ } else {
+ /* For the non-DT platforms derive chip
+* selects from controller data
+*/
spi-cs_gpio = cs-line;
+ }
if (IS_ERR_OR_NULL(cs)) {
dev_err(spi-dev, No CS for SPI(%d)\n, spi-chip_select);
--
1.7.9.5
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[PATCH 3/3 v5] ARM: DTS: fix the chip select gpios definition in the SPI nodes
This patch replaces the cs-gpio from controller-data node
as was specified in the old binding and use the standard
cs-gpios property expected by the SPI core as is defined in
the new binding.
Respective changes are preposed to spi-s3c64xx.c driver.
@ http://www.spinics.net/lists/linux-samsung-soc/msg32282.html
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Reviewed-by: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
Changes since v4:
1. Added reviewed by from Javier and Doug.
2. Maintained the status and cs-gpios ordering
Changes since v3:
None
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d166..676e6e0 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -168,6 +168,7 @@
};
spi_2: spi@1394 {
+ cs-gpios = gpc1 2 0;
status = okay;
w25x80@0 {
@@ -178,7 +179,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpc1 2 0;
samsung,spi-feedback-delay = 0;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 8a558b7..204b0de 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -512,6 +512,7 @@
spi_1: spi@1393 {
pinctrl-names = default;
pinctrl-0 = spi1_bus;
+ cs-gpios = gpb 5 0;
status = okay;
s5c73m3_spi: s5c73m3 {
@@ -519,7 +520,6 @@
spi-max-frequency = 5000;
reg = 0;
controller-data {
- cs-gpio = gpb 5 0;
samsung,spi-feedback-delay = 2;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..0c6433a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
};
spi_1: spi@12d3 {
+ cs-gpios = gpa2 5 0;
status = okay;
w25q80bw@0 {
@@ -326,7 +327,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpa2 5 0;
samsung,spi-feedback-delay = 0;
};
--
1.7.9.5
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[PATCH 1/3 v5] spi: s3c64xx: fix broken cs_gpios usage in the driver
Since, (3146bee spi: s3c64xx: Added provision for dedicated cs pin)
spi-s3c64xx.c driver expects
1. chip select gpios from cs-gpio(singular) under the
controller-data node of the client/slave device of the SPI.
2. cs-gpio(singular) entry to be present in the SPI device node.
Eg of current broken usage:
spi_1 {
cs-gpio ; /* this entry is checked during probe */
...
slave_node {
controller-data {
cs-gpio gpioa2 5 0;
/* This field is parsed during .setup() */
}
};
};
The following dts files which were using this driver. But,
din't have the cs-gpio entry under SPI node.
-- arch/arm/boot/dts/exynos4210-smdkv310.dts
-- arch/arm/boot/dts/exynos4412-trats2.dts
-- arch/arm/boot/dts/exynos5250-smdk5250.dts
Also, the SPI core and many drivers moved on to using cs-gpios
from SPI node and removed the gpio handling code from drivers
(including spi-s3c64xx.c).
Hence, spi-s3c64xx.c is broken since Jun 21 11:26:12 2013 and
considering the time with no compliants about the breakage.
We are assuming it is safe to remove the cs-gpio(singular) usage
from device tree binding of spi-samsung.txt and makes appropriate
changes in the driver to use cs-gpios(plural) from
SPI device node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Reviewed-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
Changes since v4:
1. Added reviewed by from Javier and Tested by from Doug
Changes since v3:
1. Remove the sdd-cs_gpio and use gpio_is_valid(spi-cs_gpio) instead
2. Keep cs-line only for Non-DT platforms and use spi-cs_gpio
for DT platforms
.../devicetree/bindings/spi/spi-samsung.txt|8 ++--
drivers/spi/spi-s3c64xx.c | 41
2 files changed, 20 insertions(+), 29 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt
b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 86aa061..2d29dac 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -42,15 +42,13 @@ Optional Board Specific Properties:
- num-cs: Specifies the number of chip select lines supported. If
not specified, the default number of chip select lines is set to 1.
+- cs-gpios: should specify GPIOs used for chipselects (see spi-bus.txt)
+
SPI Controller specific data in SPI slave nodes:
- The spi slave nodes should provide the following information which is
required
by the spi controller.
- - cs-gpio: A gpio specifier that specifies the gpio line used as
-the slave select line by the spi controller. The format of the gpio
-specifier depends on the gpio controller.
-
- samsung,spi-feedback-delay: The sampling phase shift to be applied on the
miso line (to account for any lag in the miso line). The following are the
valid values.
@@ -85,6 +83,7 @@ Example:
#size-cells = 0;
pinctrl-names = default;
pinctrl-0 = spi0_bus;
+ cs-gpios = gpa2 5 0;
w25q80bw@0 {
#address-cells = 1;
@@ -94,7 +93,6 @@ Example:
spi-max-frequency = 1;
controller-data {
- cs-gpio = gpa2 5 1 0 3;
samsung,spi-feedback-delay = 0;
};
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a5696..b888c66 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -197,7 +197,6 @@ struct s3c64xx_spi_driver_data {
struct s3c64xx_spi_dma_data tx_dma;
struct s3c64xx_spi_port_config *port_conf;
unsigned intport_id;
- boolcs_gpio;
};
static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
@@ -776,17 +775,6 @@ static struct s3c64xx_spi_csinfo
*s3c64xx_get_slave_ctrldata(
return ERR_PTR(-ENOMEM);
}
- /* The CS line is asserted/deasserted by the gpio pin */
- if (sdd-cs_gpio)
- cs-line = of_get_named_gpio(data_np, cs-gpio, 0);
-
- if (!gpio_is_valid(cs-line)) {
- dev_err(spi-dev, chip select gpio is not specified or
invalid\n);
- kfree(cs);
- of_node_put(data_np);
- return ERR_PTR(-EINVAL);
- }
-
of_property_read_u32(data_np, samsung,spi-feedback-delay, fb_delay);
cs-fb_delay = fb_delay;
of_node_put(data_np);
@@ -812,6 +800,10 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
spi-controller_data = cs;
}
+ /* For the non-DT platforms derive chip selects from controller data */
+ if (!spi-dev.of_node
[PATCH 2/2 v3] ARM: DTS: move cs-gpio from controller-data to under spi node
This patch moves the cs-gpio field from controller-data child
node to under the spi device node.
Respective changes are preposed to spi-s3c64xx.c driver.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Acked-by: Rob Herring r...@kernel.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
Cc: Tomasz Figa t.f...@samsung.com
---
Changes since v2:
None
arch/arm/boot/dts/exynos4210-smdkv310.dts |2 +-
arch/arm/boot/dts/exynos4412-trats2.dts |2 +-
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts
b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 636d166..9191491 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -169,6 +169,7 @@
spi_2: spi@1394 {
status = okay;
+ cs-gpios = gpc1 2 0;
w25x80@0 {
#address-cells = 1;
@@ -178,7 +179,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpc1 2 0;
samsung,spi-feedback-delay = 0;
};
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts
b/arch/arm/boot/dts/exynos4412-trats2.dts
index 8a558b7..204b0de 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -512,6 +512,7 @@
spi_1: spi@1393 {
pinctrl-names = default;
pinctrl-0 = spi1_bus;
+ cs-gpios = gpb 5 0;
status = okay;
s5c73m3_spi: s5c73m3 {
@@ -519,7 +520,6 @@
spi-max-frequency = 5000;
reg = 0;
controller-data {
- cs-gpio = gpb 5 0;
samsung,spi-feedback-delay = 2;
};
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index a794a70..0c6433a 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -316,6 +316,7 @@
};
spi_1: spi@12d3 {
+ cs-gpios = gpa2 5 0;
status = okay;
w25q80bw@0 {
@@ -326,7 +327,6 @@
spi-max-frequency = 100;
controller-data {
- cs-gpio = gpa2 5 0;
samsung,spi-feedback-delay = 0;
};
--
1.7.9.5
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[PATCH 1/3] spi: s3c64xx: use cs-gpios from spi node instead of cs-gpio
This patch makes the changes in spi-s3c64xx.c driver to make use of
cs-gpios from SPI node(parent) instead of cs-gpio defined in
slaves controller-data(child) node.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
---
drivers/spi/spi-s3c64xx.c | 56 -
1 file changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a5696..0c6013f 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -750,47 +750,56 @@ static int s3c64xx_spi_transfer_one(struct spi_master
*master,
}
static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
- struct spi_device *spi)
+ struct spi_device *spi,
+ struct s3c64xx_spi_csinfo *cs)
{
- struct s3c64xx_spi_csinfo *cs;
- struct device_node *slave_np, *data_np = NULL;
- struct s3c64xx_spi_driver_data *sdd;
+ struct device_node *data_np = NULL;
u32 fb_delay = 0;
- sdd = spi_master_get_devdata(spi-master);
- slave_np = spi-dev.of_node;
- if (!slave_np) {
- dev_err(spi-dev, device node not found\n);
+ data_np = of_get_child_by_name(spi-dev.of_node, controller-data);
+ if (!data_np) {
+ dev_err(spi-dev, child node 'controller-data' not found\n);
return ERR_PTR(-EINVAL);
}
- data_np = of_get_child_by_name(slave_np, controller-data);
- if (!data_np) {
- dev_err(spi-dev, child node 'controller-data' not found\n);
+ of_property_read_u32(data_np, samsung,spi-feedback-delay, fb_delay);
+ cs-fb_delay = fb_delay;
+ of_node_put(data_np);
+
+ return cs;
+}
+
+static struct s3c64xx_spi_csinfo *s3c64xx_get_cs_gpios(struct spi_device *spi)
+{
+ struct device_node *parent_np = NULL;
+ struct s3c64xx_spi_driver_data *sdd;
+ struct s3c64xx_spi_csinfo *cs;
+
+ parent_np = of_get_parent(spi-dev.of_node);
+ if (!parent_np) {
+ dev_err(spi-dev, Parent node not found\n);
return ERR_PTR(-EINVAL);
}
+ sdd = spi_master_get_devdata(spi-master);
+
cs = kzalloc(sizeof(*cs), GFP_KERNEL);
if (!cs) {
- of_node_put(data_np);
+ of_node_put(parent_np);
return ERR_PTR(-ENOMEM);
}
/* The CS line is asserted/deasserted by the gpio pin */
if (sdd-cs_gpio)
- cs-line = of_get_named_gpio(data_np, cs-gpio, 0);
+ cs-line = of_get_named_gpio(parent_np, cs-gpios, 0);
if (!gpio_is_valid(cs-line)) {
dev_err(spi-dev, chip select gpio is not specified or
invalid\n);
- kfree(cs);
- of_node_put(data_np);
+ of_node_put(parent_np);
return ERR_PTR(-EINVAL);
}
- of_property_read_u32(data_np, samsung,spi-feedback-delay, fb_delay);
- cs-fb_delay = fb_delay;
- of_node_put(data_np);
- return cs;
+ return s3c64xx_get_slave_ctrldata(spi, cs);
}
/*
@@ -806,9 +815,14 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
struct s3c64xx_spi_info *sci;
int err;
+ if (!spi-dev.of_node) {
+ dev_err(spi-dev, device node not found\n);
+ return ERR_PTR(-EINVAL);
+ }
+
sdd = spi_master_get_devdata(spi-master);
if (!cs spi-dev.of_node) {
- cs = s3c64xx_get_slave_ctrldata(spi);
+ cs = s3c64xx_get_cs_gpios(spi);
spi-controller_data = cs;
}
@@ -1077,7 +1091,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
sdd-sfr_start = mem_res-start;
sdd-cs_gpio = true;
if (pdev-dev.of_node) {
- if (!of_find_property(pdev-dev.of_node, cs-gpio, NULL))
+ if (!of_find_property(pdev-dev.of_node, cs-gpios, NULL))
sdd-cs_gpio = false;
ret = of_alias_get_id(pdev-dev.of_node, spi);
--
1.7.9.5
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[PATCH 2/3] spi: s3c64xx: remove a compilation warning with an assignment
This patch returns an integer error value instead of the
pointer.
warning: return makes integer from pointer without a cast
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Doug Anderson diand...@chromium.org
---
drivers/spi/spi-s3c64xx.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 0c6013f..4594dde 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -817,7 +817,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
if (!spi-dev.of_node) {
dev_err(spi-dev, device node not found\n);
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
}
sdd = spi_master_get_devdata(spi-master);
--
1.7.9.5
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