[PATCH RESEND] i2c: s3c2410: Add SMBus emulation for block read

[Prasanna Kumar]

From: Jaemin Yoo jmin@samsung.com

SMBus read and write are supported by the emulation layer of i2c
framework if the controller doesn't have SMBus features.

I2C_M_RECV_LEN flag is used to let i2c drivers know rx length is not
yet determined but will be read to the first byte in rx buffer.

s3c2410 doesn't handle this flag. So only one byte is read from slave.
There fore following two features are added to the driver code.

1. skip rx length check if I2C_M_RECV_LEN is set and the length is 1.
2. add actual bytes to the rx length after reading first bytes if
   I2C_M_RECV_LEN.

I2C_M_RECV_LEN is only set for SMBus command. So this code does not
affect legacy codes which only use i2c command for s3c2410.

Signed-off-by: Jaemin Yoo jmin@samsung.com
Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 drivers/i2c/busses/i2c-s3c2410.c |9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 17c5c37..e4ab9ea 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -309,6 +309,12 @@ static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 
 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 {
+   /* msg-len is always 1 for the first byte of smbus block read.
+* Actual length will be read from slave. More bytes will be
+* read according to the length then. */
+   if (i2c-msg-flags  I2C_M_RECV_LEN  i2c-msg-len == 1)
+   return 0;
+
return i2c-msg_ptr == i2c-msg-len-1;
 }
 
@@ -448,6 +454,9 @@ static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, 
unsigned long iicstat)
byte = readb(i2c-regs + S3C2410_IICDS);
i2c-msg-buf[i2c-msg_ptr++] = byte;
 
+   /* Add actual length to read for smbus block read */
+   if (i2c-msg-flags  I2C_M_RECV_LEN  i2c-msg-len == 1)
+   i2c-msg-len += byte;
  prepare_read:
if (is_msglast(i2c)) {
/* last byte of buffer */
-- 
1.7.10.4

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Re: [PATCH] clk: exynos5250: Added MUX, DIV and GATE clocks for Gscaler and MFC

[Prasanna Kumar]

Hi,

Current clock driver of exynos5250 does not contain sub mux clock
definition for aclk_266  and aclk_333. These sub mux clocks are driven by
output of divider clocks. These sub mux clocks drive the gate clocks
of Gscaler and MFC. Currently Gscaler and MFC gate clocks are
referring to divider
clocks instead of sub mux clocks. Hence these  clocks are added.

In addition, gscaler block is also driven aclk_300. The entire clock
tree is added
for this.

I will add above information in Changelog and resend the patch


On Wed, Mar 27, 2013 at 7:34 AM, Mike Turquette mturque...@linaro.org wrote:
 Quoting Prasanna Kumar (2013-03-25 21:26:26)
 From: Prasanna Kumar prasanna...@samsung.com

 No need for the above line.


 Gscaler :

   1. For aclk_300_gscl,following clocks are added
   Mux clocks
 mout_aclk_300_gscl_mid,
 mout_aclk_300_gscl_mid1,
 mout_aclk_300_gscl
   Divider clock
 div_aclk300_gscl
   Sub-Mux clock ( driven from output of divider clock)
 mout_sub_aclk300
   2. For aclk_266_gscl,
Sub-Mux clock mout_sub_aclk266 added
Divider clock has been modified to refer Sub-Mux clock

 MFC :
For aclk_333
 Sub-Mux clock mout_sub_aclk333 added
Divider clock has been modified to refer Sub-Mux clock
 Signed-off-by: Prasanna Kumar prasanna...@samsung.com

 The changelog above is not very human-readable.  Can you include some
 explanation of why you are making this change (e.g. enables some
 device)?

 Thanks,
 Mike

 ---
  drivers/clk/samsung/clk-exynos5250.c |   57 
 +
  1 files changed, 43 insertions(+), 14 deletions(-)

 diff --git a/drivers/clk/samsung/clk-exynos5250.c 
 b/drivers/clk/samsung/clk-exynos5250.c
 index e40d6af..40dff9d 100644
 --- a/drivers/clk/samsung/clk-exynos5250.c
 +++ b/drivers/clk/samsung/clk-exynos5250.c
 @@ -24,7 +24,9 @@
  #define DIV_CPU0   0x500
  #define SRC_CORE1  0x4204
  #define SRC_TOP0   0x10210
 +#define SRC_TOP1   0x10214
  #define SRC_TOP2   0x10218
 +#define SRC_TOP3   0x1021C
  #define SRC_GSCL   0x10220
  #define SRC_DISP1_00x1022c
  #define SRC_MAU0x10240
 @@ -112,7 +114,9 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
 DIV_CPU0,
 SRC_CORE1,
 SRC_TOP0,
 +   SRC_TOP1,
 SRC_TOP2,
 +   SRC_TOP3,
 SRC_GSCL,
 SRC_DISP1_0,
 SRC_MAU,
 @@ -167,6 +171,13 @@ PNAME(mout_mpll_user_p)= { fin_pll, sclk_mpll };
  PNAME(mout_bpll_user_p)= { fin_pll, sclk_bpll };
  PNAME(mout_aclk166_p)  = { sclk_cpll, sclk_mpll_user };
  PNAME(mout_aclk200_p)  = { sclk_mpll_user, sclk_bpll_user };
 +PNAME(mout_sub_aclk266_p) = { fin_pll, div_aclk266 };
 +PNAME(mout_aclk_300_gscl_mid_p) = { sclk_mpll_user, sclk_bpll_user};
 +PNAME(mout_aclk_300_gscl_mid1_p) = { sclk_vpll, sclk_cpll};
 +PNAME(mout_aclk_300_gscl_p) = { mout_aclk_300_gscl_mid,
 +   mout_aclk_300_gscl_mid1 };
 +PNAME(mout_sub_aclk300_p) = { fin_pll, div_aclk300_gscl };
 +PNAME(mout_sub_aclk333_p) = { fin_pll, div_aclk333 };
  PNAME(mout_hdmi_p) = { div_hdmi_pixel, sclk_hdmiphy };
  PNAME(mout_usb3_p) = { sclk_mpll_user, sclk_cpll };
  PNAME(mout_group1_p)   = { fin_pll, fin_pll, sclk_hdmi27m,
 @@ -220,8 +231,20 @@ struct samsung_mux_clock exynos5250_mux_clks[] 
 __initdata = {
 MUX(none, sclk_mpll_user, mout_mpll_user_p, SRC_TOP2, 20, 1),
 MUX(none, sclk_bpll_user, mout_bpll_user_p, SRC_TOP2, 24, 1),
 MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8, 1),
 -   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
 MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
 +   MUX_A(none, mout_sub_aclk266, mout_sub_aclk266_p,
 +   SRC_TOP3, 8, 1, m_sub_aclk266),
 +   MUX(none, mout_aclk_300_gscl, mout_aclk_300_gscl_p,
 +   SRC_TOP0, 25, 1),
 +   MUX(none, mout_aclk_300_gscl_mid, mout_aclk_300_gscl_mid_p,
 +   SRC_TOP0, 24, 1),
 +   MUX(none, mout_aclk_300_gscl_mid1, mout_aclk_300_gscl_mid1_p,
 +   SRC_TOP1, 12, 1),
 +   MUX_A(none, mout_sub_aclk300, mout_sub_aclk300_p,
 +   SRC_TOP3, 10, 1, m_sub_aclk300),
 +   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
 +   MUX_A(none, mout_sub_aclk333, mout_sub_aclk333_p,
 +   SRC_TOP3, 24, 1, m_sub_aclk333),
 MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
 MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
 MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
 @@ -257,10 +280,12 @@ struct samsung_div_clock

[PATCH] i2c: s3c2410: Add SMBus emulation for block read

[Prasanna Kumar]

From: Jaemin Yoo jmin@samsung.com

SMBus read and write are supported by the emulation layer of i2c
framework if the controller doesn't have SMBus features.

I2C_M_RECV_LEN flag is used to let i2c drivers know rx length is not
yet determined but will be read to the first byte in rx buffer.

s3c2410 doesn't handle this flag. So only one byte is read from slave.
There fore following two features are added to the driver code.

1. skip rx length check if I2C_M_RECV_LEN is set and the length is 1.
2. add actual bytes to the rx length after reading first bytes if
   I2C_M_RECV_LEN.

I2C_M_RECV_LEN is only set for SMBus command. So this code does not
affect legacy codes which only use i2c command for s3c2410.

Signed-off-by: Jaemin Yoo jmin@samsung.com
Tested-by: Prasanna Kumar prasanna...@samsung.com
---
 drivers/i2c/busses/i2c-s3c2410.c |9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 17c5c37..e4ab9ea 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -309,6 +309,12 @@ static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 
 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 {
+   /* msg-len is always 1 for the first byte of smbus block read.
+* Actual length will be read from slave. More bytes will be
+* read according to the length then. */
+   if (i2c-msg-flags  I2C_M_RECV_LEN  i2c-msg-len == 1)
+   return 0;
+
return i2c-msg_ptr == i2c-msg-len-1;
 }
 
@@ -448,6 +454,9 @@ static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, 
unsigned long iicstat)
byte = readb(i2c-regs + S3C2410_IICDS);
i2c-msg-buf[i2c-msg_ptr++] = byte;
 
+   /* Add actual length to read for smbus block read */
+   if (i2c-msg-flags  I2C_M_RECV_LEN  i2c-msg-len == 1)
+   i2c-msg-len += byte;
  prepare_read:
if (is_msglast(i2c)) {
/* last byte of buffer */
-- 
1.7.10.4

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[PATCH] clk: exynos5250: Added MUX, DIV and GATE clocks for Gscaler and MFC

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

Gscaler :

  1. For aclk_300_gscl,following clocks are added
  Mux clocks
mout_aclk_300_gscl_mid,
mout_aclk_300_gscl_mid1,
mout_aclk_300_gscl
  Divider clock
div_aclk300_gscl
  Sub-Mux clock ( driven from output of divider clock)
mout_sub_aclk300
  2. For aclk_266_gscl,
   Sub-Mux clock mout_sub_aclk266 added
   Divider clock has been modified to refer Sub-Mux clock

MFC :
   For aclk_333
Sub-Mux clock mout_sub_aclk333 added
   Divider clock has been modified to refer Sub-Mux clock
Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 drivers/clk/samsung/clk-exynos5250.c |   57 +
 1 files changed, 43 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c 
b/drivers/clk/samsung/clk-exynos5250.c
index e40d6af..40dff9d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -24,7 +24,9 @@
 #define DIV_CPU0   0x500
 #define SRC_CORE1  0x4204
 #define SRC_TOP0   0x10210
+#define SRC_TOP1   0x10214
 #define SRC_TOP2   0x10218
+#define SRC_TOP3   0x1021C
 #define SRC_GSCL   0x10220
 #define SRC_DISP1_00x1022c
 #define SRC_MAU0x10240
@@ -112,7 +114,9 @@ static __initdata unsigned long exynos5250_clk_regs[] = {
DIV_CPU0,
SRC_CORE1,
SRC_TOP0,
+   SRC_TOP1,
SRC_TOP2,
+   SRC_TOP3,
SRC_GSCL,
SRC_DISP1_0,
SRC_MAU,
@@ -167,6 +171,13 @@ PNAME(mout_mpll_user_p)= { fin_pll, sclk_mpll };
 PNAME(mout_bpll_user_p)= { fin_pll, sclk_bpll };
 PNAME(mout_aclk166_p)  = { sclk_cpll, sclk_mpll_user };
 PNAME(mout_aclk200_p)  = { sclk_mpll_user, sclk_bpll_user };
+PNAME(mout_sub_aclk266_p) = { fin_pll, div_aclk266 };
+PNAME(mout_aclk_300_gscl_mid_p) = { sclk_mpll_user, sclk_bpll_user};
+PNAME(mout_aclk_300_gscl_mid1_p) = { sclk_vpll, sclk_cpll};
+PNAME(mout_aclk_300_gscl_p) = { mout_aclk_300_gscl_mid,
+   mout_aclk_300_gscl_mid1 };
+PNAME(mout_sub_aclk300_p) = { fin_pll, div_aclk300_gscl };
+PNAME(mout_sub_aclk333_p) = { fin_pll, div_aclk333 };
 PNAME(mout_hdmi_p) = { div_hdmi_pixel, sclk_hdmiphy };
 PNAME(mout_usb3_p) = { sclk_mpll_user, sclk_cpll };
 PNAME(mout_group1_p)   = { fin_pll, fin_pll, sclk_hdmi27m,
@@ -220,8 +231,20 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata 
= {
MUX(none, sclk_mpll_user, mout_mpll_user_p, SRC_TOP2, 20, 1),
MUX(none, sclk_bpll_user, mout_bpll_user_p, SRC_TOP2, 24, 1),
MUX(none, mout_aclk166, mout_aclk166_p, SRC_TOP0, 8, 1),
-   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
MUX(none, mout_aclk200, mout_aclk200_p, SRC_TOP0, 12, 1),
+   MUX_A(none, mout_sub_aclk266, mout_sub_aclk266_p,
+   SRC_TOP3, 8, 1, m_sub_aclk266),
+   MUX(none, mout_aclk_300_gscl, mout_aclk_300_gscl_p,
+   SRC_TOP0, 25, 1),
+   MUX(none, mout_aclk_300_gscl_mid, mout_aclk_300_gscl_mid_p,
+   SRC_TOP0, 24, 1),
+   MUX(none, mout_aclk_300_gscl_mid1, mout_aclk_300_gscl_mid1_p,
+   SRC_TOP1, 12, 1),
+   MUX_A(none, mout_sub_aclk300, mout_sub_aclk300_p,
+   SRC_TOP3, 10, 1, m_sub_aclk300),
+   MUX(none, mout_aclk333, mout_aclk166_p, SRC_TOP0, 16, 1),
+   MUX_A(none, mout_sub_aclk333, mout_sub_aclk333_p,
+   SRC_TOP3, 24, 1, m_sub_aclk333),
MUX(none, mout_cam_bayer, mout_group1_p, SRC_GSCL, 12, 4),
MUX(none, mout_cam0, mout_group1_p, SRC_GSCL, 16, 4),
MUX(none, mout_cam1, mout_group1_p, SRC_GSCL, 20, 4),
@@ -257,10 +280,12 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata 
= {
DIV(none, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV(none, aclk66_pre, sclk_mpll_user, DIV_TOP1, 24, 3),
DIV(none, aclk66, aclk66_pre, DIV_TOP0, 0, 3),
-   DIV(none, aclk266, sclk_mpll_user, DIV_TOP0, 16, 3),
DIV(none, aclk166, mout_aclk166, DIV_TOP0, 8, 3),
-   DIV(none, aclk333, mout_aclk333, DIV_TOP0, 20, 3),
DIV(none, aclk200, mout_aclk200, DIV_TOP0, 12, 3),
+   DIV(none, div_aclk266, sclk_mpll_user, DIV_TOP0, 16, 3),
+   DIV(none, div_aclk300_gscl, mout_aclk_300_gscl,
+   DIV_TOP1, 14, 3),
+   DIV(none, div_aclk333, mout_aclk333, DIV_TOP0, 20, 3),
DIV(none, div_cam_bayer, mout_cam_bayer, DIV_GSCL, 12, 4),
DIV(none, div_cam0, mout_cam0, DIV_GSCL, 16, 4),
DIV(none, div_cam1, mout_cam1, DIV_GSCL, 20, 4),
@@ -313,19 +338,23 @@ struct samsung_div_clock

[PATCH] arm:exynos5250: Restore CLK_SRC_TOP3 register via CCF

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

This patch adds support for restoring CLK_SRC_TOP3 register
which gets modified while powergating corresponding power domains
after a cycle of Suspend-to-Resume.

Please refer below URL to know the background of this issue.
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14347.html.

This is based on Common Clock Framework defined for exynos5250 and 
patch mentioned here
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg16739.html

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/mach-exynos/pm_domains.c |   43 +
 1 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 9f1351d..b5ed384 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -21,8 +21,11 @@
 #include linux/of_address.h
 #include linux/of_platform.h
 #include linux/sched.h
+#include linux/clk.h
+#include linux/clk-private.h
 
 #include mach/regs-pmu.h
+#include plat/cpu.h
 #include plat/devs.h
 
 /*
@@ -35,6 +38,43 @@ struct exynos_pm_domain {
struct generic_pm_domain pd;
 };
 
+static int exynos_pdclk_restore(struct exynos_pm_domain *domain)
+{
+   int i = 0;
+   struct clk *p_clk;
+   struct clk_hw *hw_clk;
+   const struct clk_ops *p_ops;
+
+   const char *pdclks[][2] = {
+   { gsc-power-domain,
+   m_sub_aclk266 },
+   { gsc-power-domain,
+   m_sub_aclk300 },
+   { mfc-power-domain,
+   m_sub_aclk333 },
+   };
+
+   for (i = 0; i  ARRAY_SIZE(pdclks); i++) {
+   if (!strcmp(domain-name, pdclks[i][0])) {
+   p_clk = clk_get(NULL, pdclks[i][1]);
+   if (IS_ERR(p_clk)) {
+   pr_err(failed to get base clk\n);
+   return PTR_ERR(p_clk);
+   }
+
+   hw_clk = __clk_get_hw(p_clk);
+   if (IS_ERR(hw_clk)) {
+   pr_err(failed to get hw_clk\n);
+   return PTR_ERR(hw_clk);
+   }
+   p_ops = p_clk-ops;
+   if (p_ops != NULL  p_ops-set_parent != NULL)
+   p_clk-ops-set_parent(hw_clk, 1);
+   }
+   }
+   return 0;
+}
+
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 {
struct exynos_pm_domain *pd;
@@ -61,6 +101,9 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+   if (!power_on  soc_is_exynos5250())
+   exynos_pdclk_restore(pd);
return 0;
 }
 
-- 
1.7.5.4

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[PATCH] ARM : dts : Added clock definition for MFC as per Common clock framework

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

According to Common clock framework, clock definition is added
for exynos5250

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 24c52e6..652a63e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -128,6 +128,8 @@
reg = 0x1100 0x1;
interrupts = 0 96 0;
samsung,power-domain = pd_mfc;
+   clocks = clock 266;
+   clock-names = mfc;
};
 
rtc {
-- 
1.7.5.4

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[PATCH] [media] s5p-mfc: Change MFC clock reference w.r.t Common Clock Framework

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

According to Common Clock framework , modified the method of getting
clock for MFC Block.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 drivers/media/platform/s5p-mfc/s5p_mfc_pm.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c 
b/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
index 6aa38a5..b8ac8f6 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_pm.c
@@ -50,7 +50,7 @@ int s5p_mfc_init_pm(struct s5p_mfc_dev *dev)
goto err_p_ip_clk;
}
 
-   pm-clock = clk_get(dev-plat_dev-dev, dev-variant-mclk_name);
+   pm-clock = clk_get_parent(pm-clock_gate);
if (IS_ERR(pm-clock)) {
mfc_err(Failed to get MFC clock\n);
ret = PTR_ERR(pm-clock);
-- 
1.7.5.4

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Re: [PATCH RESEND v2] ARM: EXYNOS: dts: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

Hi kukjin,
I have put the above nodes by order of address.
Kindly review and ack the patch.

On Wed, Jan 30, 2013 at 10:19 AM, Prasanna Kumar
prasanna...@samsung.com wrote:
 This patch adds device tree nodes for MFC and G-scaler power
 domains of exynos5250.It binds these power-domain nodes to repsective
 device tree nodes

 It also adds support to enable PM generic domains for exynos5250.

 Signed-off-by: Prasanna Kumar prasanna...@samsung.com
 ---
  arch/arm/boot/dts/exynos5250.dtsi |   16 
  arch/arm/mach-exynos/Kconfig  |1 +
  2 files changed, 17 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 30485de..e282fde 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -46,6 +46,16 @@
 i2c8 = i2c_8;
 };

 +   pd_gsc: gsc-power-domain@0x10044000 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044000 0x20;
 +   };
 +
 +   pd_mfc: mfc-power-domain@0x10044040 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044040 0x20;
 +   };
 +
 gic:interrupt-controller@10481000 {
 compatible = arm,cortex-a9-gic;
 #interrupt-cells = 3;
 @@ -85,6 +95,7 @@
 compatible = samsung,mfc-v6;
 reg = 0x1100 0x1;
 interrupts = 0 96 0;
 +   samsung,power-domain = pd_mfc;
 };

 rtc {
 @@ -554,28 +565,33 @@
 };
 };

 +
 gsc_0:  gsc@0x13e0 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e0 0x1000;
 interrupts = 0 85 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_1:  gsc@0x13e1 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e1 0x1000;
 interrupts = 0 86 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_2:  gsc@0x13e2 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e2 0x1000;
 interrupts = 0 87 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_3:  gsc@0x13e3 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e3 0x1000;
 interrupts = 0 88 0;
 +   samsung,power-domain = pd_gsc;
 };

 hdmi {
 diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
 index e103c29..96f4a9f 100644
 --- a/arch/arm/mach-exynos/Kconfig
 +++ b/arch/arm/mach-exynos/Kconfig
 @@ -61,6 +61,7 @@ config SOC_EXYNOS5250
 bool SAMSUNG EXYNOS5250
 default y
 depends on ARCH_EXYNOS5
 +   select PM_GENERIC_DOMAINS if PM
 select S5P_PM if PM
 select S5P_SLEEP if PM
 select S5P_DEV_MFC
 --
 1.7.5.4

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[PATCH RESEND] ARM: EXYNOS: dts: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

This patch adds device tree nodes for MFC and G-scaler power
domains of exynos5250.It binds these power-domain nodes to repsective
device tree nodes

It also adds support to enable PM generic domains for exynos5250.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   15 +++
 arch/arm/mach-exynos/Kconfig  |1 +
 2 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..6d0e87c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -85,6 +85,7 @@
compatible = samsung,mfc-v6;
reg = 0x1100 0x1;
interrupts = 0 96 0;
+   samsung,power-domain = pd_mfc;
};
 
rtc {
@@ -554,28 +555,42 @@
};
};
 
+   pd_gsc: gsc-power-domain@0x10044000 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044000 0x20;
+   };
+
+   pd_mfc: mfc-power-domain@0x10044040 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044040 0x20;
+   };
+
gsc_0:  gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_1:  gsc@0x13e1 {
compatible = samsung,exynos5-gsc;
reg = 0x13e1 0x1000;
interrupts = 0 86 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_2:  gsc@0x13e2 {
compatible = samsung,exynos5-gsc;
reg = 0x13e2 0x1000;
interrupts = 0 87 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_3:  gsc@0x13e3 {
compatible = samsung,exynos5-gsc;
reg = 0x13e3 0x1000;
interrupts = 0 88 0;
+   samsung,power-domain = pd_gsc;
};
 
hdmi {
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e103c29..96f4a9f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
bool SAMSUNG EXYNOS5250
default y
depends on ARCH_EXYNOS5
+   select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM
select S5P_SLEEP if PM
select S5P_DEV_MFC
-- 
1.7.5.4

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[PATCH RESEND v2] ARM: EXYNOS: dts: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

This patch adds device tree nodes for MFC and G-scaler power
domains of exynos5250.It binds these power-domain nodes to repsective
device tree nodes

It also adds support to enable PM generic domains for exynos5250.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   16 
 arch/arm/mach-exynos/Kconfig  |1 +
 2 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..e282fde 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,6 +46,16 @@
i2c8 = i2c_8;
};
 
+   pd_gsc: gsc-power-domain@0x10044000 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044000 0x20;
+   };
+
+   pd_mfc: mfc-power-domain@0x10044040 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044040 0x20;
+   };
+
gic:interrupt-controller@10481000 {
compatible = arm,cortex-a9-gic;
#interrupt-cells = 3;
@@ -85,6 +95,7 @@
compatible = samsung,mfc-v6;
reg = 0x1100 0x1;
interrupts = 0 96 0;
+   samsung,power-domain = pd_mfc;
};
 
rtc {
@@ -554,28 +565,33 @@
};
};
 
+
gsc_0:  gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_1:  gsc@0x13e1 {
compatible = samsung,exynos5-gsc;
reg = 0x13e1 0x1000;
interrupts = 0 86 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_2:  gsc@0x13e2 {
compatible = samsung,exynos5-gsc;
reg = 0x13e2 0x1000;
interrupts = 0 87 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_3:  gsc@0x13e3 {
compatible = samsung,exynos5-gsc;
reg = 0x13e3 0x1000;
interrupts = 0 88 0;
+   samsung,power-domain = pd_gsc;
};
 
hdmi {
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e103c29..96f4a9f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -61,6 +61,7 @@ config SOC_EXYNOS5250
bool SAMSUNG EXYNOS5250
default y
depends on ARCH_EXYNOS5
+   select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM
select S5P_SLEEP if PM
select S5P_DEV_MFC
-- 
1.7.5.4

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Re: [PATCH 2/2] ARM: dts: exynos5: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

Hi Kukjin,

Kindly review this patch.

On Wed, Jan 9, 2013 at 5:45 PM, Prasanna Kumar prasanna...@samsung.com wrote:
 This patch adds device tree nodes for MFC and G-scaler power domains
 of exynos5.It binds these power-domain nodes to repsective device tree nodes.

 Signed-off-by: Prasanna Kumar prasanna...@samsung.com
 ---
  arch/arm/boot/dts/exynos5250.dtsi |   15 +++
  1 files changed, 15 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 30485de..6d0e87c 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -85,6 +85,7 @@
 compatible = samsung,mfc-v6;
 reg = 0x1100 0x1;
 interrupts = 0 96 0;
 +   samsung,power-domain = pd_mfc;
 };

 rtc {
 @@ -554,28 +555,42 @@
 };
 };

 +   pd_gsc: gsc-power-domain@0x10044000 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044000 0x20;
 +   };
 +
 +   pd_mfc: mfc-power-domain@0x10044040 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044040 0x20;
 +   };
 +
 gsc_0:  gsc@0x13e0 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e0 0x1000;
 interrupts = 0 85 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_1:  gsc@0x13e1 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e1 0x1000;
 interrupts = 0 86 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_2:  gsc@0x13e2 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e2 0x1000;
 interrupts = 0 87 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_3:  gsc@0x13e3 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e3 0x1000;
 interrupts = 0 88 0;
 +   samsung,power-domain = pd_gsc;
 };

 hdmi {
 --
 1.7.5.4

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Re: [PATCH 0/2] ARM: Exynos5 : Add Power domain device tree support for MFC and GSC

[Prasanna Kumar]

Hello ,

Any comments for this patch set ?

 On Wed, Jan 9, 2013 at 5:45 PM, Prasanna Kumar prasanna...@samsung.com 
 wrote:

 Hello all,

 This patch set adds device tree support for power domains (Gscaler and
 MFC) of exynos5

 Prasanna Kumar (2):
   arm: exynos5: Enable PM generic domain support in Kconfig
   ARM: dts: exynos5: Set up power domain for  MFC and G-scaler

  arch/arm/boot/dts/exynos5250.dtsi |   15 +++
  arch/arm/mach-exynos/Kconfig  |1 +
  2 files changed, 16 insertions(+), 0 deletions(-)

 --
 1.7.5.4

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 Thanks
 Prasanna Kumar




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[PATCH 0/2] ARM: Exynos5 : Add Power domain device tree support for MFC and GSC

[Prasanna Kumar]

Hello all,

This patch set adds device tree support for power domains (Gscaler and
MFC) of exynos5

Prasanna Kumar (2):
  arm: exynos5: Enable PM generic domain support in Kconfig
  ARM: dts: exynos5: Set up power domain for  MFC and G-scaler

 arch/arm/boot/dts/exynos5250.dtsi |   15 +++
 arch/arm/mach-exynos/Kconfig  |1 +
 2 files changed, 16 insertions(+), 0 deletions(-)

-- 
1.7.5.4

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[PATCH 1/2] arm: exynos5: Enable PM generic domain support in Kconfig

[Prasanna Kumar]

This patch adds support to enable PM generic domains
under Exynos5 family

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/mach-exynos/Kconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index e103c29..871be97 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
depends on ARCH_EXYNOS5
select S5P_PM if PM
select S5P_SLEEP if PM
+   select PM_GENERIC_DOMAINS if PM
select S5P_DEV_MFC
select SAMSUNG_DMADEV
help
-- 
1.7.5.4

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[PATCH 2/2] ARM: dts: exynos5: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

This patch adds device tree nodes for MFC and G-scaler power domains
of exynos5.It binds these power-domain nodes to repsective device tree nodes.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   15 +++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..6d0e87c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -85,6 +85,7 @@
compatible = samsung,mfc-v6;
reg = 0x1100 0x1;
interrupts = 0 96 0;
+   samsung,power-domain = pd_mfc;
};
 
rtc {
@@ -554,28 +555,42 @@
};
};
 
+   pd_gsc: gsc-power-domain@0x10044000 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044000 0x20;
+   };
+
+   pd_mfc: mfc-power-domain@0x10044040 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044040 0x20;
+   };
+
gsc_0:  gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_1:  gsc@0x13e1 {
compatible = samsung,exynos5-gsc;
reg = 0x13e1 0x1000;
interrupts = 0 86 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_2:  gsc@0x13e2 {
compatible = samsung,exynos5-gsc;
reg = 0x13e2 0x1000;
interrupts = 0 87 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_3:  gsc@0x13e3 {
compatible = samsung,exynos5-gsc;
reg = 0x13e3 0x1000;
interrupts = 0 88 0;
+   samsung,power-domain = pd_gsc;
};
 
hdmi {
-- 
1.7.5.4

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[PATCH 0/3] ARM:exynos5:power-domain: Save and restore CLK_TOP_SRC3 via clock framework.

[Prasanna Kumar]

After Suspend-Resume operation of exynos5, CLK_TOP_SRC3 register modified
while power gating G-scaler and MFC power domains.This is seen only after
suspend and resume.

The solution to this problem is to save CLK_SRC_TOP3 register and restore
it while powergating. But CLK_SRC_TOP3 register cannot accessed directly 
by power domain code.
Please refer below URL to know the background of this issue.
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14347.html.

This patch set adds clock framework support for save and restore
clock register (CLK_SRC_TOP3)  for G-scaler and MFC power domains.

This patch set depends on
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14648.html

Prasanna Kumar (3):
  ARM: dts: exynos5: Add power domain clocks to pd node of Gscaler and MFC
  ARM:exynos5:dts: Bindings for clock definitions are added.
  ARM: exynos5: Add clock save and restore operation(CLK_SRC_TOP3) using clock 
framework.

 .../bindings/arm/exynos/power_domain.txt   |   14 ++
 arch/arm/boot/dts/exynos5250.dtsi  |2 +
 arch/arm/mach-exynos/pm_domains.c  |  125 
 3 files changed, 141 insertions(+), 0 deletions(-)

-- 
1.7.5.4

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[PATCH 2/3] ARM:exynos5:dts: Bindings for clock definitions are added.

[Prasanna Kumar]

The details of samsung,exynos-pd-clks property is added.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 .../bindings/arm/exynos/power_domain.txt   |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt 
b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index 5216b41..dc1e89bd 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -12,6 +12,12 @@ Required Properties:
 Node of a device using power domains must have a samsung,power-domain property
 defined with a phandle to respective power domain.
 
+Optional Properties:
+samsung,exynos-pd-clks: After suspend-resume of system ,the clock sources of
+   few devices forming part of power domain need to be saved as they get
+   modified during power domain On-Off operation.Such clock defintions
+   are added via samsung,exynos-pd-clks property as strings.
+
 Example:
 
lcd0: power-domain-lcd0 {
@@ -26,3 +32,11 @@ Example of the node using power domain:
samsung,power-domain = lcd0;
/* ... */
};
+
+Example of the node using power domain clock defintions:
+
+   node {
+   /* ... */
+   samsung,exynos-pd-clks = aclk_333;
+   /* ... */
+   };
-- 
1.7.5.4

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[PATCH 3/3] ARM: exynos5: Add clock save and restore

[Prasanna Kumar]

After Suspend-Resume operation, it is observed that CLK_TOP_SRC3 register
gets modified if the G-Scaler/MFC devices are power gated.

The clock for G-Scaler gets set to XXTI which results in the device
running very slow.This issue also seen for MFC.

To solve above issue, the existing clock framework of exynos5 is used
to save and restore clocks while power gating instead of accessing
CLK_SRC_TOP3 register directly.The clock names are read from DT file.

Please refer below URL to know the background of this issue.
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg14347.html.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/mach-exynos/pm_domains.c |  125 +
 1 files changed, 125 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 9f1351d..2f49de9 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -21,9 +21,14 @@
 #include linux/of_address.h
 #include linux/of_platform.h
 #include linux/sched.h
+#include linux/clk.h
+#include linux/list.h
 
 #include mach/regs-pmu.h
 #include plat/devs.h
+#include plat/clock.h
+#include plat/clock-clksrc.h
+
 
 /*
  * Exynos specific wrapper around the generic power domain
@@ -33,7 +38,69 @@ struct exynos_pm_domain {
char const *name;
bool is_off;
struct generic_pm_domain pd;
+   struct list_head list_pdclks;
+   struct list_head saved_list_pdclks;
+   int pd_clks;
+};
+
+struct exynos_pd_clk {
+   struct list_head node;
+   struct clk *clk;
 };
+static int exynos_pdclk_save(struct exynos_pm_domain *epd)
+{
+   struct exynos_pd_clk *pdclk;
+   struct exynos_pd_clk *saved_pdclk;
+
+   list_for_each_entry(pdclk, epd-list_pdclks, node) {
+   if (pdclk) {
+   saved_pdclk = kzalloc(sizeof(struct exynos_pd_clk),
+   GFP_KERNEL);
+   if (!saved_pdclk) {
+   pr_err(%s: failed to allocate memory\n,
+   __func__);
+   return -ENOMEM;
+   }
+   saved_pdclk-clk = clk_get_parent(pdclk-clk);
+   if (IS_ERR(saved_pdclk-clk)) {
+   pr_err( Cannot get parent for %s\n,
+   pdclk-clk-name);
+   return PTR_ERR(saved_pdclk-clk);
+   }
+   list_add_tail(saved_pdclk-node,
+   epd-saved_list_pdclks);
+   }
+   }
+   return 0;
+}
+
+static void exynos_pdclk_restore(struct exynos_pm_domain *epd)
+{
+   struct exynos_pd_clk *pdclk;
+   struct exynos_pd_clk *saved_pdclk;
+   struct list_head *p_clk;
+   struct list_head *p_saved_clk;
+   int ret;
+
+   p_saved_clk = epd-saved_list_pdclks.next;
+   p_clk = epd-list_pdclks.next;
+
+   for ( ; p_saved_clk != epd-saved_list_pdclks 
+   p_clk != epd-list_pdclks;
+   p_clk = p_clk-next, p_saved_clk = p_saved_clk-next) {
+
+   saved_pdclk = list_entry(p_saved_clk,
+   struct exynos_pd_clk, node);
+   pdclk = list_entry(p_clk, struct exynos_pd_clk, node);
+   if (saved_pdclk  pdclk) {
+   ret = clk_set_parent(pdclk-clk, saved_pdclk-clk);
+   if (ret)
+   pr_err(Failed to set %s as parent of %s\n,
+saved_pdclk-clk-name, pdclk-clk-name);
+   }
+   }
+   return;
+}
 
 static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
 {
@@ -45,6 +112,13 @@ static int exynos_pd_power(struct generic_pm_domain 
*domain, bool power_on)
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd-base;
 
+   if (!power_on) {
+   if (pd-pd_clks  0)
+   if (exynos_pdclk_save(pd))
+   pr_err(Failed to save pdclks for %s\n,
+   domain-name);
+   }
+
pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
__raw_writel(pwr, base);
 
@@ -61,6 +135,11 @@ static int exynos_pd_power(struct generic_pm_domain 
*domain, bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+   if (!power_on) {
+   if (pd-pd_clks  0)
+   exynos_pdclk_restore(pd);
+   }
return 0;
 }
 
@@ -157,10 +236,48 @@ static struct notifier_block platform_nb = {
.notifier_call = exynos_pm_notifier_call,
 };
 
+static int exynos_read_pdclk_from_dt(struct device_node *dev_node,
+   struct

Re: [PATCH v2 1/3] ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP

[Prasanna Kumar]

Hi all,

Any comments on this patch ?

Thanks,
Prasanna

On Thu, Dec 20, 2012 at 5:56 PM, Prasanna Kumar prasanna...@samsung.com wrote:
 This patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains
 of exynos5.It binds these power-domain nodes to repsective device tree nodes.

 Signed-off-by: Prasanna Kumar prasanna...@samsung.com
 ---
  arch/arm/boot/dts/exynos5250.dtsi |   25 +
  1 files changed, 25 insertions(+), 0 deletions(-)

 diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
 b/arch/arm/boot/dts/exynos5250.dtsi
 index 581e57a..71a37bd 100644
 --- a/arch/arm/boot/dts/exynos5250.dtsi
 +++ b/arch/arm/boot/dts/exynos5250.dtsi
 @@ -83,6 +83,7 @@
 compatible = samsung,mfc-v6;
 reg = 0x1100 0x1;
 interrupts = 0 96 0;
 +   samsung,power-domain = pd_mfc;
 };

 rtc {
 @@ -283,6 +284,7 @@
 samsung,supports-rstclr;
 samsung,supports-secdai;
 samsung,idma-addr = 0x0300;
 +   samsung,power-domain = pd_mau;
 };

 i2s_1: i2s@12D6 {
 @@ -578,28 +580,51 @@
 };
 };

 +   pd_gsc: gsc-power-domain@0x10044000 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044000 0x20;
 +   };
 +
 +   pd_isp: isp-power-domain@0x10044020 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044020 0x20;
 +   };
 +
 +   pd_mfc: mfc-power-domain@0x10044040 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x10044040 0x20;
 +   };
 +
 +   pd_mau: mau-power-domain@0x100440C0 {
 +   compatible = samsung,exynos4210-pd;
 +   reg = 0x100440C0 0x20;
 +   };
 gsc_0:  gsc@0x13e0 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e0 0x1000;
 interrupts = 0 85 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_1:  gsc@0x13e1 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e1 0x1000;
 interrupts = 0 86 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_2:  gsc@0x13e2 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e2 0x1000;
 interrupts = 0 87 0;
 +   samsung,power-domain = pd_gsc;
 };

 gsc_3:  gsc@0x13e3 {
 compatible = samsung,exynos5-gsc;
 reg = 0x13e3 0x1000;
 interrupts = 0 88 0;
 +   samsung,power-domain = pd_gsc;
 };

 hdmi {
 --
 1.7.0.4


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Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Choi,

The method Save/restore clock source register - CLK_SRC_TOP3 was
suggested as well as preferred by our hardware team.

Would it be possible to give more information on this  alternate method ?


On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi jhbird.c...@gmail.com wrote:
 Hi~

 This code should be changed.

 I insert  this code (save/restore clock source register - CLK_SRC_TOP3)
 temporary.

 But we removed this code. And we use another  method to fix it.

 I think this is not right way.

 Thanks.



 On Fri, Dec 21, 2012 at 6:06 AM, tomasz.f...@gmail.com wrote:

 Hi Prasanna,

 On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
  This patch adds a software workaround to the hardware
  problem found in exynos5 while powergating.
 
  It is observed that CLK_TOP_SRC3 register gets modified if
  the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
  set to XXTI which results in the device running very slow .
  A big drop in performance is noticed whilerunning the video.
  This issue also occurs while powergating MFC.
 
  The value of clock source register is restored once the powergating
  operation is completed.

 Is the problem really related to power gating at all? From what you
 described in comment in the code, it seems like it's a problem with
 suspend/resume, not power gating, so it should be rather saved on suspend
 and restored on resume. Please recheck clock save/restore part of power
 management code.

 Altering clock configuration registers from power domain code looks really
 ugly...

 Best regards,
 Tomasz Figa

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Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi tomasz,

On Fri, Dec 21, 2012 at 2:36 AM,  tomasz.f...@gmail.com wrote:
 Hi Prasanna,

 On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
 This patch adds a software workaround to the hardware
 problem found in exynos5 while powergating.

 It is observed that CLK_TOP_SRC3 register gets modified if
 the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
 set to XXTI which results in the device running very slow .
 A big drop in performance is noticed whilerunning the video.
 This issue also occurs while powergating MFC.

 The value of clock source register is restored once the powergating
 operation is completed.

 Is the problem really related to power gating at all? From what you
 described in comment in the code, it seems like it's a problem with
 suspend/resume, not power gating, so it should be rather saved on suspend
 and restored on resume. Please recheck clock save/restore part of power
 management code.

The problem is only seen in following sequence.
1. Suspend and then Resume the system
2. Power Gating ( On- Off ) of the associated power domain ( Gscaler , MFC ...)

I rechecked clock save/restore part of power
management code.The register is already being saved clock save/restore
part of power
management code. ( exynos5_clock_save. in clock-exynos5.c).

I hope you have understood the situation here.

 Best regards,
 Tomasz Figa


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Re: [PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Choi,

On Mon, Dec 24, 2012 at 9:56 AM, Prasanna Kumar
prasannapadubi...@gmail.com wrote:
 Hi Choi,

 The method Save/restore clock source register - CLK_SRC_TOP3 was
 suggested as well as preferred by our hardware team.

 Would it be possible to give more information on this  alternate method ?

   I just wanted to be more clear on the last sentence of my previous email.
   Here alternate method means, the method you have used to fix the issue.
   Kindly share information on that.
   --
Thanks


 On Fri, Dec 21, 2012 at 7:07 AM, jonghwan Choi jhbird.c...@gmail.com wrote:
 Hi~

 This code should be changed.

 I insert  this code (save/restore clock source register - CLK_SRC_TOP3)
 temporary.

 But we removed this code. And we use another  method to fix it.

 I think this is not right way.

 Thanks.



 On Fri, Dec 21, 2012 at 6:06 AM, tomasz.f...@gmail.com wrote:

 Hi Prasanna,

 On Thursday 20 of December 2012 17:56:18 Prasanna Kumar wrote:
  This patch adds a software workaround to the hardware
  problem found in exynos5 while powergating.
 
  It is observed that CLK_TOP_SRC3 register gets modified if
  the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
  set to XXTI which results in the device running very slow .
  A big drop in performance is noticed whilerunning the video.
  This issue also occurs while powergating MFC.
 
  The value of clock source register is restored once the powergating
  operation is completed.

 Is the problem really related to power gating at all? From what you
 described in comment in the code, it seems like it's a problem with
 suspend/resume, not power gating, so it should be rather saved on suspend
 and restored on resume. Please recheck clock save/restore part of power
 management code.

 Altering clock configuration registers from power domain code looks really
 ugly...

 Best regards,
 Tomasz Figa

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[PATCH v2 0/3] ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue

[Prasanna Kumar]

Hello,
This patch set is for for-next branch.

Changes since v1:
[exynos5250.dtsi]
Added power domain support for MAU and ISP power domains in exynos5 dts
[pm_domains.c]
CLKSRC register is saved before PMU register is programmed
Replaced soc_is_exynos5250 with  of_machine_is_compatible 

Prasanna Kumar (3):
  ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP
  arm: exynos5: Enable PM generic domain support in Kconfig
  ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

 arch/arm/boot/dts/exynos5250.dtsi |   25 +
 arch/arm/mach-exynos/Kconfig  |1 +
 arch/arm/mach-exynos/pm_domains.c |   27 +++
 3 files changed, 53 insertions(+), 0 deletions(-)

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[PATCH v2 1/3] ARM: dts: exynos5: Set up power domain for MFC,G-scaler,MAU and ISP

[Prasanna Kumar]

This patch adds device tree nodes for MFC,G-scaler,MAU and ISP power domains
of exynos5.It binds these power-domain nodes to repsective device tree nodes.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   25 +
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 581e57a..71a37bd 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -83,6 +83,7 @@
compatible = samsung,mfc-v6;
reg = 0x1100 0x1;
interrupts = 0 96 0;
+   samsung,power-domain = pd_mfc;
};
 
rtc {
@@ -283,6 +284,7 @@
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = 0x0300;
+   samsung,power-domain = pd_mau;
};
 
i2s_1: i2s@12D6 {
@@ -578,28 +580,51 @@
};
};
 
+   pd_gsc: gsc-power-domain@0x10044000 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044000 0x20;
+   };
+
+   pd_isp: isp-power-domain@0x10044020 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044020 0x20;
+   };
+
+   pd_mfc: mfc-power-domain@0x10044040 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044040 0x20;
+   };
+
+   pd_mau: mau-power-domain@0x100440C0 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x100440C0 0x20;
+   };
gsc_0:  gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_1:  gsc@0x13e1 {
compatible = samsung,exynos5-gsc;
reg = 0x13e1 0x1000;
interrupts = 0 86 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_2:  gsc@0x13e2 {
compatible = samsung,exynos5-gsc;
reg = 0x13e2 0x1000;
interrupts = 0 87 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_3:  gsc@0x13e3 {
compatible = samsung,exynos5-gsc;
reg = 0x13e3 0x1000;
interrupts = 0 88 0;
+   samsung,power-domain = pd_gsc;
};
 
hdmi {
-- 
1.7.0.4

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[PATCH v2 2/3] arm: exynos5: Enable PM generic domain support in Kconfig

[Prasanna Kumar]

This patch adds support to enable PM generic domains
under Exynos5 family

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 This patch is same as v1
 arch/arm/mach-exynos/Kconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 91d5b6f..1c77f17 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
depends on ARCH_EXYNOS5
select S5P_PM if PM
select S5P_SLEEP if PM
+   select PM_GENERIC_DOMAINS if PM
select S5P_DEV_MFC
select SAMSUNG_DMADEV
help
-- 
1.7.0.4

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[PATCH v2 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

This patch adds a software workaround to the hardware
problem found in exynos5 while powergating.

It is observed that CLK_TOP_SRC3 register gets modified if
the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
set to XXTI which results in the device running very slow .
A big drop in performance is noticed whilerunning the video.
This issue also occurs while powergating MFC.

The value of clock source register is restored once the powergating
operation is completed.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/mach-exynos/pm_domains.c |   27 +++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/pm_domains.c 
b/arch/arm/mach-exynos/pm_domains.c
index 9f1351d..bd8a41e 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -24,6 +24,8 @@
 
 #include mach/regs-pmu.h
 #include plat/devs.h
+#include mach/regs-clock.h
+#include plat/cpu.h
 
 /*
  * Exynos specific wrapper around the generic power domain
@@ -41,6 +43,24 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
void __iomem *base;
u32 timeout, pwr;
char *op;
+   u32 tmp = 0;
+
+   /*
+*It is found that the CLK SRC register in exynos5
+*gets modified when power domain of gsc/mfc/isp/disp1
+*is powered off.This happens only after the system is
+*suspended and resumed and not before that.
+*The following fix adresses this hardware issue.
+*It saves the value of clock source register and
+*resores it later
+*/
+
+   if (of_machine_is_compatible(samsung,exynos5250)) {
+   if (!power_on) {
+   /* save clock source register */
+   tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
+   }
+   }
 
pd = container_of(domain, struct exynos_pm_domain, pd);
base = pd-base;
@@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, 
bool power_on)
cpu_relax();
usleep_range(80, 100);
}
+
+   if (of_machine_is_compatible(samsung,exynos5250)) {
+   if (!power_on) {
+   /* restore clock source register */
+   __raw_writel(tmp, EXYNOS5_CLKSRC_TOP3);
+   }
+   }
return 0;
 }
 
-- 
1.7.0.4

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Re: [PATCH 3/3] ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

[Prasanna Kumar]

Hi Thomas,

Thanks for the comments.Please find my reply inline.

On Tue, Dec 4, 2012 at 2:29 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:

 On 27 November 2012 17:52, Prasanna Kumar prasanna...@samsung.com wrote:
  From: Prasanna Kumar prasanna...@samsung.com
 
  This patch adds a software workaround to the hardware
  problem found in exynos5 while powergating.
 
  It is observed that CLK_TOP_SRC3 register gets modified if
  the G-Scaler/MFC devices are power gated. The clock for G-Scaler gets
  set to XXTI which results in the device running very slow .
  A big drop in performance is noticed whilerunning the video.
  This issue also occurs while powergating MFC.
 
  The value of clock source register is restored once the powergating
  operation is completed.
 
  Signed-off-by: Prasanna Kumar prasanna...@samsung.com
  ---
   arch/arm/mach-exynos/pm_domains.c |   27 +++
   1 files changed, 27 insertions(+), 0 deletions(-)
 
  diff --git a/arch/arm/mach-exynos/pm_domains.c
  b/arch/arm/mach-exynos/pm_domains.c
  index 9f1351d..955cbe3 100644
  --- a/arch/arm/mach-exynos/pm_domains.c
  +++ b/arch/arm/mach-exynos/pm_domains.c
  @@ -48,6 +51,23 @@ static int exynos_pd_power(struct generic_pm_domain
  *domain, bool power_on)
  pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0;
  __raw_writel(pwr, base);
 
  +   /*
  +*It is found that the CLK SRC register in exynos5
  +*gets modified when power domain of gsc/mfc/isp/disp1
  +*is powered off.This happens only after the system is
  +*suspended and resumed and not before that.
  +*The following fix adresses this hardware issue.
  +*It saves the value of clock source register and
  +*resores it later
  +*/
  +
  +   if (soc_is_exynos5250()) {
  +   if (!power_on) {
  +   /* save clock source register */
  +   tmp = __raw_readl(EXYNOS5_CLKSRC_TOP3);
  +   }
  +   }

 Does the value of EXYNOS5_CLKSRC_TOP3 register change as soon as the
 G-Scaler/MFC devices are power gated?

 - If yes, the value of CLKSRC register should be saved before the
 power domain register is programmed.

 - If not, as mentioned in the comment, if this issue occurs during a
 suspend-resume cycle, the value of this register can be saved and
 restored in the clock driver code itself.

During a normal power gating sequence, this problem is not seen
But Once the suspend-resume cycle is done,  if we try to turn on or
turn off domain,
this issue occurs.

I agree that CLKSRC register should be saved
before the power domain register is programmed.

Saving of CLKSRC_TOP3 register is already being done in clock driver
code.i.e in exynos5_clock_save[]. But the problem remains. So i feel
an exclusive saving of the register in pm_domain driver is required.

Kindly let me know your opinion

 The other thing that needs to be relooked into here is the use of
 EXYNOS5_CLKSRC_TOP3 register address. Currently, the clock registers
 are statically io-remapped. With the upcoming migration to common
 clock for Exynos5, the clock registers will not be statically
 io-remapped but instead remapped during clock initialization. So the
 use of EXYNOS5_CLKSRC_TOP3 will not hold and so we need to relook into
 this.

Yes , we can look into this, once the clock migration happens for Exynos5
Until then, can it be used as statically io-remapped ?


  @@ -61,6 +81,13 @@ static int exynos_pd_power(struct generic_pm_domain
  *domain, bool power_on)
  cpu_relax();
  usleep_range(80, 100);
  }
  +
  +   if (soc_is_exynos5250()) {

 We could use the of_machine_is_compatible api here instead of
 soc_is_exynos5250() macro.


Yes, of_machine_is_compatible function will be used
instead of soc_is_exynos5250()


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[PATCH 0/3]ARM: Exynos5 : Add Power domain device tree support and fix for hardware issue

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

Hello all,

This patch set is for for-next branch.

In this patch set, the first patch adds device tree support for
G-Scaler and MFC power domains of Exynos5. 

The second patch enables power domain support for exynos5 in Kconfig

The last patch provides a software fix for hardware issue found in exynos5
while powergating the power domains.

Prasanna Kumar (3):
  ARM: dts: exynos5: Set up power domain for MFC and G-scaler
  arm: exynos5: Enable PM generic domain support in Kconfig
  ARM: EXYNOS5: save CLK_TOP_SRC3 register before powergating

 arch/arm/boot/dts/exynos5250.dtsi |   15 +++
 arch/arm/mach-exynos/Kconfig  |1 +
 arch/arm/mach-exynos/pm_domains.c |   27 +++
 3 files changed, 43 insertions(+), 0 deletions(-)

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[PATCH 1/3] ARM: dts: exynos5: Set up power domain for MFC and G-scaler

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

This patch adds device tree nodes for MFC and G-scaler power domains of exynos5.
It binds these power-domain nodes to repsective device tree nodes.

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/boot/dts/exynos5250.dtsi |   15 +++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi 
b/arch/arm/boot/dts/exynos5250.dtsi
index 8f46227..23f9bf1 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -83,6 +83,7 @@
compatible = samsung,mfc-v6;
reg = 0x1100 0x1;
interrupts = 0 96 0;
+   samsung,power-domain = pd_mfc;
};
 
rtc {
@@ -578,28 +579,42 @@
};
};
 
+   pd_gsc: gsc-power-domain@0x10044000 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044000 0x20;
+   };
+
+   pd_mfc: mfc-power-domain@0x10044040 {
+   compatible = samsung,exynos4210-pd;
+   reg = 0x10044040 0x20;
+   };
+
gsc_0:  gsc@0x13e0 {
compatible = samsung,exynos5-gsc;
reg = 0x13e0 0x1000;
interrupts = 0 85 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_1:  gsc@0x13e1 {
compatible = samsung,exynos5-gsc;
reg = 0x13e1 0x1000;
interrupts = 0 86 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_2:  gsc@0x13e2 {
compatible = samsung,exynos5-gsc;
reg = 0x13e2 0x1000;
interrupts = 0 87 0;
+   samsung,power-domain = pd_gsc;
};
 
gsc_3:  gsc@0x13e3 {
compatible = samsung,exynos5-gsc;
reg = 0x13e3 0x1000;
interrupts = 0 88 0;
+   samsung,power-domain = pd_gsc;
};
 
hdmi {
-- 
1.7.0.4

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[PATCH 2/3] arm: exynos5: Enable PM generic domain support in Kconfig

[Prasanna Kumar]

From: Prasanna Kumar prasanna...@samsung.com

This patch adds support to enable PM generic domains
under Exynos5 family

Signed-off-by: Prasanna Kumar prasanna...@samsung.com
---
 arch/arm/mach-exynos/Kconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 945ce49..c07a29c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -63,6 +63,7 @@ config SOC_EXYNOS5250
depends on ARCH_EXYNOS5
select S5P_PM if PM
select S5P_SLEEP if PM
+   select PM_GENERIC_DOMAINS if PM
select S5P_DEV_MFC
select SAMSUNG_DMADEV
help
-- 
1.7.0.4

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