[PATCH v12 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v11: - Rebased on top of git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This series is based on the following branch. git://linuxtv.org/snawrocki/samsung.git for-v3.19-exynos-clk This series depends on the following patch which can be picked from git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git samsung/dt e540920cf21c (ARM: dts: add CPU nodes for Exynos4 SoCs). This patch series has been tested on Exynos4210/5250/5420 based boards. Tomasz Figa had plans to take this in the Samsung clock tree for v3.19 (http://www.spinics.net/lists/linux-samsung-soc/msg37933.html). Sylwester, could you consider to merge this in your tree? Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |4 + arch/arm/boot/dts/exynos4210-trats.dts |4 + arch/arm/boot/dts/exynos4210-universal_c210.dts |4 + arch/arm/boot/dts/exynos4210.dtsi | 14 ++- arch/arm/boot/dts/exynos5250-arndale.dts|4 + arch/arm/boot/dts/exynos5250-smdk5250.dts |4 + arch/arm/boot/dts/exynos5250-snow.dts |4 + arch/arm/boot/dts/exynos5250.dtsi | 25 +++- arch/arm/boot/dts/exynos5420.dtsi | 38 arch/arm/mach-exynos/exynos.c | 26 +++- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-exynos4.c | 63 +--- drivers/clk/samsung/clk-exynos5250.c| 44 - drivers/clk/samsung/clk-exynos5420.c| 72 +++- drivers/cpufreq/Kconfig.arm | 22 --- drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 --- include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 20 files changed, 266 insertions(+), 463 deletions(-) delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v12 1/6] clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335 +
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 006c6f2..04acd70 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) mux_pos) MUX_MASK) == mux_value)
+ return;
+ } while
[PATCH v12 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210,
Exynos5250 and Exynos5420.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 15 ++
drivers/clk/samsung/clk-exynos5250.c | 25 +
drivers/clk/samsung/clk-exynos5420.c | 45
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 +
5 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 940f028..9af5767 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS0x4200
@@ -1354,6 +1355,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
{
unsigned int tmp;
@@ -1457,6 +1468,10 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..e19e365 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst =
{
+ { 170, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 160, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 150, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 140, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 130, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 120, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 110, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 100, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 90, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 80, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 70, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 60, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 50, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 40, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 30, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 20, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks
[PATCH v12 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Andreas Farber afaer...@suse.de
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 ++
arch/arm/boot/dts/exynos4210-trats.dts |4 ++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 ++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 ++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 ++
arch/arm/boot/dts/exynos5250-snow.dts |4 ++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3acd97e..da2b3e1 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -563,3 +563,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6a0f4c0..0eedb88 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -406,3 +406,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index e51fcef..865f68a 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -345,6 +345,10 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
i2c_0 {
status = okay;
samsung,i2c-sda-delay = 100;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index f21b9aa..d4b418e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
+
+ operating-points
[PATCH v12 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 26 +-
1 files changed, 25 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6b283eb..402a2ae 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -282,6 +282,30 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5422, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5800, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5250, .data = cpufreq-dt },
+ { .compatible = samsung,exynos4210, .data = cpufreq-dt },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+ struct device_node *root = of_find_node_by_path(/);
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_cpufreq_matches, root);
+ if (!match) {
+ platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ return;
+ }
+
+ platform_device_register_simple(match-data, -1, NULL, 0);
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -321,7 +345,7 @@ static void __init exynos_dt_machine_init(void)
of_machine_is_compatible(samsung,exynos5250))
platform_device_register(exynos_cpuidle);
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.6.6.rc2
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[PATCH v12 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 0 insertions(+), 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 83a75dc..701f5ca 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 40c53dc..74e55f9 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 843ec82..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq
[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 48 +-
drivers/clk/samsung/clk-exynos5250.c | 19 -
drivers/clk/samsung/clk-exynos5420.c | 27 --
3 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 9af5767..3731fc7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(0, mout_hpm, mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
- DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
- DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3),
- DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
- DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem0, div_core2, DIV_CPU0, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem1, div_core2, DIV_CPU0, 8, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_periph, div_core2, DIV_CPU0, 12, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_atb, mout_core, DIV_CPU0, 16, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_copy, mout_hpm, DIV_CPU1, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_hpm, div_copy, DIV_CPU1, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -769,7 +779,8 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1186,17 +1197,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
0),
};
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
- ALIAS(CLK_SCLK_MPLL, NULL, mout_mpll),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, mout_mpll),
};
@@ -1463,8 +1467,6 @@ static void __init
Re: [PATCH v11 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Kevin, On Thu, Nov 20, 2014 at 2:30 AM, Kevin Hilman khil...@kernel.org wrote: Hi Thomas, On Mon, Oct 20, 2014 at 4:41 AM, Thomas Abraham thomas...@samsung.com wrote: The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver. Suggested-by: Tomasz Figa tomasz.f...@gmail.com Cc: Kukjin Kim kgene@samsung.com Signed-off-by: Thomas Abraham thomas...@samsung.com Reviewed-by: Tomasz Figa tomasz.f...@gmail.com Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Tested-by: Chander Kashyap k.chan...@samsung.com What's the status of the exynos5 CPUfreq support for upstream? This was pretty broadly reviewed and tested, but I still don't see this either in linux-next or Kukjin's for-next. The rebased version of the patches have been posted [1]. My apologies for the delay in following up on this patch series. Thanks, Thomas. [1] http://www.spinics.net/lists/arm-kernel/msg380011.html Kevin ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Amit,
On Wed, Nov 12, 2014 at 3:03 PM, Amit Kucheria amit.kuche...@linaro.org wrote:
Hi Thomas,
On Mon, Oct 20, 2014 at 5:11 PM, Thomas Abraham thomas...@samsung.com wrote:
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6b283eb..a1be294 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
While you're at it, can you add this to so we don't have to patch
kernels for the Chromebook2 and Odroid-XU3?
{ .compatible = samsung,exynos5422, .data = arm-bL-cpufreq-dt },
{ .compatible = samsung,exynos5800, .data = arm-bL-cpufreq-dt },
Okay, I this has been included in the updated patches [1]
[1] http://www.spinics.net/lists/arm-kernel/msg380011.html
Thanks,
Thomas.
+ { .compatible = samsung,exynos5250, .data = cpufreq-dt },
+ { .compatible = samsung,exynos4210, .data = cpufreq-dt },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
___
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[PATCH v11 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v10: - Rebased on top of v3.18-rc1 This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is based and tested on v3.18-rc1 and depends on the patch - clk: exynos4: remove duplicate div_core2 divider clock instantiation (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html) This patch has been merged in arm-soc/samsung/dt3 branch of arm-soc tree. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 1/6] clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335 +
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..8909c93 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) mux_pos) MUX_MASK) == mux_value)
+ return;
+ } while
[PATCH v11 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210,
Exynos5250 and Exynos5420.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 15 ++
drivers/clk/samsung/clk-exynos5250.c | 25 +
drivers/clk/samsung/clk-exynos5420.c | 45
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 +
5 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 940f028..9af5767 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS0x4200
@@ -1354,6 +1355,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
{
unsigned int tmp;
@@ -1457,6 +1468,10 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..e19e365 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst =
{
+ { 170, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 160, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 150, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 140, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 130, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 120, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 110, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 100, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 90, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 80, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 70, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 60, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 50, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 40, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 30, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 20, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks
[PATCH v11 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Andreas Farber afaer...@suse.de
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 ++
arch/arm/boot/dts/exynos4210-trats.dts |4 ++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 ++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 ++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 ++
arch/arm/boot/dts/exynos5250-snow.dts |4 ++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 7e728a1..ac07cdf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -548,6 +548,10 @@
cap-sd-highspeed;
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
rtc {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index bc27cc2..d91db82 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -410,3 +410,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f9bc04b..8459fb6 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -599,6 +599,10 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
rtc {
status = okay;
clocks = clock CLK_RTC, max77686 MAX77686_CLK_AP;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 012b021..bccdd22 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency
[PATCH v11 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 6b283eb..a1be294 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -282,6 +282,28 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5250, .data = cpufreq-dt },
+ { .compatible = samsung,exynos4210, .data = cpufreq-dt },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+ struct device_node *root = of_find_node_by_path(/);
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_cpufreq_matches, root);
+ if (!match) {
+ platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ return;
+ }
+
+ platform_device_register_simple(match-data, -1, NULL, 0);
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -321,7 +343,7 @@ static void __init exynos_dt_machine_init(void)
of_machine_is_compatible(samsung,exynos5250))
platform_device_register(exynos_cpuidle);
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.6.6.rc2
--
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[PATCH v11 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Signed-off-by: Thomas Abraham thomas...@samsung.com Acked-by: Viresh Kumar viresh.ku...@linaro.org Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Tested-by: Chander Kashyap k.chan...@samsung.com --- drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 -- 2 files changed, 0 insertions(+), 24 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 83a75dc..701f5ca 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ config ARM_EXYNOS_CPUFREQ bool -config ARM_EXYNOS4210_CPUFREQ - bool SAMSUNG EXYNOS4210 - depends on CPU_EXYNOS4210 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4210 - SoC (S5PV310 or S5PC210). - - If in doubt, say N. - config ARM_EXYNOS4X12_CPUFREQ bool SAMSUNG EXYNOS4x12 depends on SOC_EXYNOS4212 || SOC_EXYNOS4412 @@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ If in doubt, say N. -config ARM_EXYNOS5250_CPUFREQ - bool SAMSUNG EXYNOS5250 - depends on SOC_EXYNOS5250 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS5250 - SoC. - - If in doubt, say N. - config ARM_EXYNOS5440_CPUFREQ bool SAMSUNG EXYNOS5440 depends on SOC_EXYNOS5440 diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 40c53dc..74e55f9 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o -- 1.6.6.rc2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 6/6] clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 48 +-
drivers/clk/samsung/clk-exynos5250.c | 19 -
drivers/clk/samsung/clk-exynos5420.c | 27 --
3 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 9af5767..3731fc7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(0, mout_hpm, mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
- DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
- DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3),
- DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
- DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem0, div_core2, DIV_CPU0, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem1, div_core2, DIV_CPU0, 8, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_periph, div_core2, DIV_CPU0, 12, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_atb, mout_core, DIV_CPU0, 16, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_copy, mout_hpm, DIV_CPU1, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_hpm, div_copy, DIV_CPU1, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -769,7 +779,8 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1186,17 +1197,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
0),
};
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
- ALIAS(CLK_SCLK_MPLL, NULL, mout_mpll),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, mout_mpll),
};
@@ -1463,8 +1467,6 @@ static void __init
Re: [PATCH v11 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
On Mon, Oct 20, 2014 at 5:02 PM, Viresh Kumar viresh.ku...@linaro.org wrote: On 20 October 2014 17:11, Thomas Abraham thomas...@samsung.com wrote: Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Signed-off-by: Thomas Abraham thomas...@samsung.com Acked-by: Viresh Kumar viresh.ku...@linaro.org Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Tested-by: Chander Kashyap k.chan...@samsung.com --- drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 -- 2 files changed, 0 insertions(+), 24 deletions(-) Looks like you forgot removing drivers ;) Sorry, missed it while doing the rebase. I will fix and send an updated patch. Thanks, Thomas. -- To unsubscribe from this list: send the line unsubscribe linux-pm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v11 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Tomasz, On Mon, Oct 20, 2014 at 5:05 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On 20.10.2014 13:41, Thomas Abraham wrote: Changes since v10: - Rebased on top of v3.18-rc1 This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-dt driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is based and tested on v3.18-rc1 and depends on the patch - clk: exynos4: remove duplicate div_core2 divider clock instantiation (http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html) This patch has been merged in arm-soc/samsung/dt3 branch of arm-soc tree. That patch actually went through clock tree, but it doesn't matter, because AFAIK all the dependencies for this series are already in 3.18-rc1. I'll try to apply it in next days Thanks. The patch clk: exynos4: remove duplicate div_core2 divider clock instantiation is not available in 3.18-rc1. So for testing, I picked this patch from samsung/dt3 branch from arm-soc tree. Regards, Thomas. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v11 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 0 insertions(+), 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 83a75dc..701f5ca 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 40c53dc..74e55f9 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 843ec82..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq
Re: exynos5420/arndale-octa: imprecise external aborts on exynos_defconfig
Hi Bartlomiej, On Tue, Sep 30, 2014 at 11:47 PM, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: Hi, On Wednesday, September 17, 2014 05:39:29 PM Kevin Hilman wrote: Thomas Abraham ta.oma...@gmail.com writes: On Thu, Sep 11, 2014 at 12:16 AM, Kevin Hilman khil...@kernel.org wrote: Tyler Baker tyler.ba...@linaro.org writes: Exynos5420-based Arndale octa boards have recently started failing boot tests due to imprecise external aborts. This only appears to happen when using exynos_defconfig and boots fine with multi_v7_defconfig. The issue seems to be intermittent, so is not reliably reproducable and difficult to bisect. Here are a few boot logs from recent mainline/linux-next kernels that are failing: FYI, I'm seeing the same periodic aborts. For example, here's my boot of next-20140910: http://images.armcloud.us/kernel-ci/next/next-20140910/arm-exynos_defconfig/boot-exynos5420-arndale-octa.html However, my userspace is much simpler and doesn't seem to cause a panic, so my boot tests report passing. (I should fixup my scripts so these imprecise aborts are reported as a FAIL.) I'm glad you pointed out that it happens only with exynos_defconfig and not multi_v7_defconfig because I noticed that too. I haven't had the time to track it any further than that, so maybe the exynos folks can help track it down from here. Thanks for reporting this, Kevin Hi Tyler, Kevin, From the bootlog you have shared, [1.060016] CPU4: failed to come online [2.070031] CPU5: failed to come online [3.080049] CPU6: failed to come online [4.090066] CPU7: failed to come online [4.090099] Brought up 4 CPUs [4.090109] SMP: Total of 4 processors activated. [4.090119] CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13) [4.090128] CPU: This may indicate a broken bootloader or firmware. Would it be possible to set max cpus to 1, disable switcher and try Which max cpus do you mean? For NR_CPUS the lower limit is 2. The maxcpus=1 kernel parameter could be used here. The reason for trying with this option was to understand the probable location of this imprecise abort (mcpm init or secondary cpu boot). Thanks, Thomas. again. I don't have a arndale octa board but I have tested mainline kernel with smdk5420 board. It boots all eight CPUs, switcher works fine and there are no imprecise aborts seen. Sorry for the delay, I'm travelling this week. FWIW, the same CPU boot failures you hilight above are happening on multi_v7_defconfig[1] which is not getting the imprecise abort. This is only happening on exynos_defconfig[2], so I'm curious why you think the switcher or NR_CPUS might be the issues. Anyways, I narrowed this down a bit and discovered it's CONFIG_EXYNOS5420_MCPM=y that's the root cause. If I use exynos_defconfig and then disable that option, I don't get any more imprecise aborts. I have exactly the same issue with Exynos5420 Arndale Octa. CONFIG_EXYNOS5420_MCPM was enabled by commit fc3791f3a95d (ARM: exynos_defconfig: Update exynos_defconfig) which get merged into v3.17-rc1. It seems that this part of the patch should be reverted for the final v3.17 kernel. Kevin [1] http://images.armcloud.us/kernel-ci/mainline/v3.17-rc5-25-g8ba4caf/arm-multi_v7_defconfig/boot-exynos5420-arndale-octa.html [2] http://images.armcloud.us/kernel-ci/mainline/v3.17-rc5-25-g8ba4caf/arm-exynos_defconfig/boot-exynos5420-arndale-octa.html Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v10 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Tomasz, On Wed, Sep 24, 2014 at 4:38 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On 24.09.2014 09:34, Kukjin Kim wrote: Thomas Abraham wrote: This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html I have applied 2) to Samsung clock tree. Ok. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |4 + arch/arm/boot/dts/exynos4210-trats.dts |4 + arch/arm/boot/dts/exynos4210-universal_c210.dts |4 + arch/arm/boot/dts/exynos4210.dtsi | 14 +- arch/arm/boot/dts/exynos5250-arndale.dts|4 + arch/arm/boot/dts/exynos5250-smdk5250.dts |4 + arch/arm/boot/dts/exynos5250-snow.dts |4 + arch/arm/boot/dts/exynos5250.dtsi | 25 ++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ arch/arm/mach-exynos/exynos.c | 24 ++- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 335 +++ drivers/clk/samsung/clk-cpu.h | 91 ++ drivers/clk/samsung/clk-exynos4.c | 63 +++-- drivers/clk/samsung/clk-exynos5250.c| 44 +++- drivers/clk/samsung/clk-exynos5420.c| 72 +- drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + Looks good to me, Acked-by: Kukjin Kim kgene@samsung.com BTW, who will handle this series? I think this is already ready for v3.18. I believe Viresh already acked this series too and since it does quite a lot of shuffling in clock code, I'd prefer to take this through clock tree, but apparently there is a dependency on patch 1), which already went through another tree? Not yet. The v2 version of the patch does not cleanly apply and needs to be refreshed. Bartlomiej, would be posting an updated version of this patch? Thanks, Thomas. Best regards, Tomasz ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 1/6] clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335 +
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletions(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..8909c93 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) mux_pos) MUX_MASK) == mux_value)
+ return;
+ } while
[PATCH v10 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Andreas Farber afaer...@suse.de
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 ++
arch/arm/boot/dts/exynos4210-trats.dts |4 ++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 ++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 ++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 ++
arch/arm/boot/dts/exynos5250-snow.dts |4 ++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 3acd97e..da2b3e1 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -563,3 +563,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 6a0f4c0..0eedb88 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -406,3 +406,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index e51fcef..f954e82 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -624,4 +624,8 @@
num-cs = 1;
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index f21b9aa..d4b418e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
+
+ operating-points
[PATCH v10 6/6] clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 48 +-
drivers/clk/samsung/clk-exynos5250.c | 19 -
drivers/clk/samsung/clk-exynos5420.c | 27 --
3 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 101f549..04619a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(0, mout_hpm, mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
- DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
- DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3),
- DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
- DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem0, div_core2, DIV_CPU0, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem1, div_core2, DIV_CPU0, 8, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_periph, div_core2, DIV_CPU0, 12, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_atb, mout_core, DIV_CPU0, 16, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_copy, mout_hpm, DIV_CPU1, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_hpm, div_copy, DIV_CPU1, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -770,7 +780,8 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1187,17 +1198,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
0),
};
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
- ALIAS(CLK_SCLK_MPLL, NULL, mout_mpll),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, mout_mpll),
};
@@ -1464,8 +1468,6 @@ static void __init
[PATCH v10 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com Signed-off-by: Thomas Abraham thomas...@samsung.com Acked-by: Viresh Kumar viresh.ku...@linaro.org Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Tested-by: Chander Kashyap k.chan...@samsung.com --- drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 -- 2 files changed, 0 insertions(+), 24 deletions(-) diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 193a137..78df4e6 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ config ARM_EXYNOS_CPUFREQ bool -config ARM_EXYNOS4210_CPUFREQ - bool SAMSUNG EXYNOS4210 - depends on CPU_EXYNOS4210 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS4210 - SoC (S5PV310 or S5PC210). - - If in doubt, say N. - config ARM_EXYNOS4X12_CPUFREQ bool SAMSUNG EXYNOS4x12 depends on SOC_EXYNOS4212 || SOC_EXYNOS4412 @@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ If in doubt, say N. -config ARM_EXYNOS5250_CPUFREQ - bool SAMSUNG EXYNOS5250 - depends on SOC_EXYNOS5250 - default y - select ARM_EXYNOS_CPUFREQ - help - This adds the CPUFreq driver for Samsung EXYNOS5250 - SoC. - - If in doubt, say N. - config ARM_EXYNOS5440_CPUFREQ bool SAMSUNG EXYNOS5440 depends on SOC_EXYNOS5440 diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 40c53dc..74e55f9 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o -obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o -- 1.6.6.rc2 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |4 + arch/arm/boot/dts/exynos4210-trats.dts |4 + arch/arm/boot/dts/exynos4210-universal_c210.dts |4 + arch/arm/boot/dts/exynos4210.dtsi | 14 +- arch/arm/boot/dts/exynos5250-arndale.dts|4 + arch/arm/boot/dts/exynos5250-smdk5250.dts |4 + arch/arm/boot/dts/exynos5250-snow.dts |4 + arch/arm/boot/dts/exynos5250.dtsi | 25 ++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ arch/arm/mach-exynos/exynos.c | 24 ++- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 335 +++ drivers/clk/samsung/clk-cpu.h | 91 ++ drivers/clk/samsung/clk-exynos4.c | 63 +++-- drivers/clk/samsung/clk-exynos5250.c| 44 +++- drivers/clk/samsung/clk-exynos5420.c| 72 +- drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v10 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210,
Exynos5250 and Exynos5420.
Cc: Tomasz Figa tomasz.f...@gmail.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 15 ++
drivers/clk/samsung/clk-exynos5250.c | 25 +
drivers/clk/samsung/clk-exynos5420.c | 45
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 +
5 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 8617f49..101f549 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS0x4200
@@ -1355,6 +1356,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
{
unsigned int tmp;
@@ -1458,6 +1469,10 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..e19e365 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst =
{
+ { 170, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 160, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 150, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 140, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 130, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 120, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 110, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 100, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 90, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 80, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 70, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 60, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 50, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 40, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 30, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 20, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks
[PATCH v10 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa tomasz.f...@gmail.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa tomasz.f...@gmail.com
Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Chander Kashyap k.chan...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b89e5f3..c3b6b5d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -280,6 +280,28 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5250, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos4210, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+ struct device_node *root = of_find_node_by_path(/);
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_cpufreq_matches, root);
+ if (!match) {
+ platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ return;
+ }
+
+ platform_device_register_simple(match-data, -1, NULL, 0);
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -319,7 +341,7 @@ static void __init exynos_dt_machine_init(void)
of_machine_is_compatible(samsung,exynos5250))
platform_device_register(exynos_cpuidle);
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.6.6.rc2
--
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Re: [PATCH 00/14] Support 64bit Cortex A57 based Exynos7 SoC
Hi Tomasz, On Sat, Sep 13, 2014 at 4:27 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On 27.08.2014 13:34, Tomasz Figa wrote: Hi Naveen, On 27.08.2014 11:44, Naveen Krishna Chatradhi wrote: This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. A general issue with this series is that it introduces a very generic name for a very specific single SoC. We remember exactly the same cases for Exynos4 (original name used for Exynos5250) and Exynos5 (Exynos5250) and we should have learned that it is better to use a specific name first and only then try to make things common if it turns out to be appropriate. Any comments on this? The name of the SoC is Exynos7 and so all these patches are using Exynos7 in dt compatible string and file names. If there are any variants of Exynos7 SoC in future, support those variants will be based on what is already merged for Exynos7 SoC. There is no specific generalization targeted in this series by using Exynos7 name. Thanks, Thomas. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/4] pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts
Hi Abhilash,
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote:
Exynos7 uses different offsets for wakeup interrupt configuration registers.
So a new irq_chip instance for Exynos7 wakeup interrupts is added. The
irq_chip
selection is now based on the wakeup interrupt controller compatible string.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Cc: Thomas Abraham thomas...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Linus Walleij linus.wall...@linaro.org
---
.../bindings/pinctrl/samsung-pinctrl.txt |2 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 42
+++-
drivers/pinctrl/samsung/pinctrl-exynos.h |3 ++
3 files changed, 38 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf4..f80519a 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -136,6 +136,8 @@ B. External Wakeup Interrupts: For supporting external
wakeup interrupts, a
found on Samsung S3C64xx SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
+ - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
+ found on Samsung Exynos7 SoC.
- interrupt-parent: phandle of the interrupt parent to which the external
wakeup interrupts are forwarded to.
- interrupts: interrupt used by multiplexed wakeup interrupts.
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index 3133a1e..fe15ab8 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -56,12 +56,6 @@ static struct samsung_pin_bank_type bank_type_alive = {
.reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
};
-/* list of external wakeup controllers supported */
-static const struct of_device_id exynos_wkup_irq_ids[] = {
- { .compatible = samsung,exynos4210-wakeup-eint, },
- { }
-};
-
static void exynos_irq_mask(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
@@ -328,9 +322,11 @@ static int exynos_wkup_irq_set_wake(struct irq_data
*irqd, unsigned int on)
/*
* irq_chip for wakeup interrupts
*/
-static struct exynos_irq_chip exynos_wkup_irq_chip = {
+static struct exynos_irq_chip exynos_wkup_irq_chip;
+
+static struct exynos_irq_chip exynos4210_wkup_irq_chip = {
This should be marked as initdata.
.chip = {
- .name = exynos_wkup_irq_chip,
+ .name = exynos4210_wkup_irq_chip,
.irq_unmask = exynos_irq_unmask,
.irq_mask = exynos_irq_mask,
.irq_ack = exynos_irq_ack,
@@ -342,6 +338,29 @@ static struct exynos_irq_chip exynos_wkup_irq_chip = {
.eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
};
+static struct exynos_irq_chip exynos7_wkup_irq_chip = {
this as well.
+ .chip = {
+ .name = exynos7_wkup_irq_chip,
+ .irq_unmask = exynos_irq_unmask,
+ .irq_mask = exynos_irq_mask,
+ .irq_ack = exynos_irq_ack,
+ .irq_set_type = exynos_irq_set_type,
+ .irq_set_wake = exynos_wkup_irq_set_wake,
+ },
+ .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
+ .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
+ .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
+};
+
+/* list of external wakeup controllers supported */
+static const struct of_device_id exynos_wkup_irq_ids[] = {
+ { .compatible = samsung,exynos4210-wakeup-eint,
+ .data = exynos4210_wkup_irq_chip },
+ { .compatible = samsung,exynos7-wakeup-eint,
+ .data = exynos7_wkup_irq_chip },
+ { }
+};
+
/* interrupt handler for wakeup interrupts 0..15 */
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
@@ -434,7 +453,12 @@ static int exynos_eint_wkup_init(struct
samsung_pinctrl_drv_data *d)
int idx, irq;
for_each_child_of_node(dev-of_node, np) {
- if (of_match_node(exynos_wkup_irq_ids, np)) {
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_wkup_irq_ids, np);
+ if (match) {
+ memcpy(exynos_wkup_irq_chip, match-data,
+ sizeof(struct exynos_irq_chip));
wkup_np = np;
break;
}
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h
b/drivers/pinctrl/samsung/pinctrl-exynos.h
index e060722..0db1e52 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -25,6
Re: [PATCH 4/4] arm64: dts: Add initial pinctrl support to EXYNOS7
Hi Abhilash,
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote:
From: Naveen Krishna Chatradhi ch.nav...@samsung.com
Add intial pin configuration nodes for EXYNOS7.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Cc: Rob Herring r...@kernel.org
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: Thomas Abraham thomas...@samsung.com
---
arch/arm64/Kconfig |2 +
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 560
+++
arch/arm64/boot/dts/exynos/exynos7.dtsi | 66 +++
3 files changed, 628 insertions(+)
create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index b4d1dc2..0dcf6f5 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -143,6 +143,8 @@ config ARCH_EXYNOS7
bool ARMv8 based Samsung Exynos7
select ARCH_EXYNOS
select COMMON_CLK_SAMSUNG
+ select PINCTRL
+ select PINCTRL_EXYNOS
It would be good if the this change is moved to a different patch and
keep this only for dts updates. Rest of the patch looks fine.
Regards,
Thomas.
help
This enables support for Samsung Exynos7 SoC family
diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
new file mode 100644
index 000..d858805
--- /dev/null
+++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi
@@ -0,0 +1,560 @@
+/*
+ * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
+ * device tree nodes in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+pinctrl_alive {
+ gpa0: gpa0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 0 0, 0 1 0, 0 2 0, 0 3 0,
+0 4 0, 0 5 0, 0 6 0, 0 7 0;
+ };
+
+ gpa1: gpa1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ interrupt-parent = gic;
+ #interrupt-cells = 2;
+ interrupts = 0 8 0, 0 9 0, 0 10 0, 0 11 0,
+0 12 0, 0 13 0, 0 14 0, 0 15 0;
+ };
+
+ gpa2: gpa2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpa3: gpa3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+};
+
+pinctrl_bus0 {
+ gpb0: gpb0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc0: gpc0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc1: gpc1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc2: gpc2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpc3: gpc3 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd0: gpd0 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd1: gpd1 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd2: gpd2 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd4: gpd4 {
+ gpio-controller;
+ #gpio-cells = 2;
+
+ interrupt-controller;
+ #interrupt-cells = 2;
+ };
+
+ gpd5: gpd5 {
+ gpio-controller
Re: [PATCH 0/4] Add initial support for pinctrl on Exynos7
On Sat, Sep 13, 2014 at 2:20 PM, Abhilash Kesavan a.kesa...@samsung.com wrote: The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next Following patches are required for this series: 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg36208.html 2- dts, kbuild: Implement support for dtb vendor subdirs patchset http://comments.gmane.org/gmane.linux.kbuild.devel/12131 3- arch: arm64: enable support for Samsung Exynos7 SoC patchset http://www.spinics.net/lists/linux-samsung-soc/msg36728.html Abhilash Kesavan (2): pinctrl: exynos: Generalize the eint16_31 demux code pinctrl: exynos: Add irq_chip instance for Exynos7 wakeup interrupts Naveen Krishna Chatradhi (2): pinctrl: exynos: Add initial driver data for Exynos7 arm64: dts: Add initial pinctrl support to EXYNOS7 .../bindings/pinctrl/samsung-pinctrl.txt |3 + arch/arm64/Kconfig |2 + arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi| 560 arch/arm64/boot/dts/exynos/exynos7.dtsi| 66 +++ drivers/pinctrl/samsung/pinctrl-exynos.c | 161 +- drivers/pinctrl/samsung/pinctrl-exynos.h |4 + drivers/pinctrl/samsung/pinctrl-samsung.c |2 + drivers/pinctrl/samsung/pinctrl-samsung.h |1 + 8 files changed, 788 insertions(+), 11 deletions(-) create mode 100644 arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi Tested GPIO and Wakeup interrupts. After fixing comments for patches in this series, this series Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: exynos5420/arndale-octa: imprecise external aborts on exynos_defconfig
On Thu, Sep 11, 2014 at 12:16 AM, Kevin Hilman khil...@kernel.org wrote: Tyler Baker tyler.ba...@linaro.org writes: Exynos5420-based Arndale octa boards have recently started failing boot tests due to imprecise external aborts. This only appears to happen when using exynos_defconfig and boots fine with multi_v7_defconfig. The issue seems to be intermittent, so is not reliably reproducable and difficult to bisect. Here are a few boot logs from recent mainline/linux-next kernels that are failing: FYI, I'm seeing the same periodic aborts. For example, here's my boot of next-20140910: http://images.armcloud.us/kernel-ci/next/next-20140910/arm-exynos_defconfig/boot-exynos5420-arndale-octa.html However, my userspace is much simpler and doesn't seem to cause a panic, so my boot tests report passing. (I should fixup my scripts so these imprecise aborts are reported as a FAIL.) I'm glad you pointed out that it happens only with exynos_defconfig and not multi_v7_defconfig because I noticed that too. I haven't had the time to track it any further than that, so maybe the exynos folks can help track it down from here. Thanks for reporting this, Kevin Hi Tyler, Kevin, From the bootlog you have shared, [1.060016] CPU4: failed to come online [2.070031] CPU5: failed to come online [3.080049] CPU6: failed to come online [4.090066] CPU7: failed to come online [4.090099] Brought up 4 CPUs [4.090109] SMP: Total of 4 processors activated. [4.090119] CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x13) [4.090128] CPU: This may indicate a broken bootloader or firmware. Would it be possible to set max cpus to 1, disable switcher and try again. I don't have a arndale octa board but I have tested mainline kernel with smdk5420 board. It boots all eight CPUs, switcher works fine and there are no imprecise aborts seen. Thanks, Thomas. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v4 0/8] arch: arm64: enable support for Samsung Exynos7 SoC
On Fri, Sep 12, 2014 at 8:56 PM, Naveen Krishna Chatradhi ch.nav...@samsung.com wrote: Changes since v3: - Removed aliases for serial controllers from dtsi file and moved it into board specific dts file as suggested by Arnd. - Based this series on Robert Richter's patches for adding vendor device tree sub-directories for arm64. http://comments.gmane.org/gmane.linux.kbuild.devel/12131 This patchset supports new Exynos7 Samsung SoC based on Cortex-A57. Exynos7 is a System-On-Chip (SoC) that is based on 64-bit ARMv8 RISC processor. The following patches are tested based on Kgene's for-next tree. https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next The following patches are required for this series. 1- tty/serial: fix config dependencies for samsung serial https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg36208.html 2- dts, kbuild: Implement support for dtb vendor subdirs patch set http://comments.gmane.org/gmane.linux.kbuild.devel/12131 Alim Akhtar (1): arm64: exynos7: Enable ARMv8 based Exynos7 (SoC) support Naveen Krishna Chatradhi (6): clk: samsung: add support for 145xx and 1460x PLLs clk: samsung: Factor out the common code to clk.c clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info clk: samsung: add initial clock support for Exynos7 SoC arm64: dts: Add initial device tree support for EXYNOS7 tty/serial: samsung: enable usage for 64-bit Exynos platforms Pankaj Dubey (1): arm64: dts: add dt-bindings/ symlink .../devicetree/bindings/clock/exynos7-clock.txt| 37 ++ arch/arm64/Kconfig | 12 + arch/arm64/boot/dts/Makefile |1 + arch/arm64/boot/dts/exynos/Makefile|5 + arch/arm64/boot/dts/exynos/exynos7-espresso.dts| 39 ++ arch/arm64/boot/dts/exynos/exynos7.dtsi| 160 arch/arm64/boot/dts/include/dt-bindings|1 + drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5260.c | 185 ++--- drivers/clk/samsung/clk-exynos7.c | 417 drivers/clk/samsung/clk-pll.c | 25 +- drivers/clk/samsung/clk-pll.h |4 + drivers/clk/samsung/clk.c | 98 + drivers/clk/samsung/clk.h | 37 ++ drivers/tty/serial/Kconfig |2 +- include/dt-bindings/clock/exynos7-clk.h| 39 ++ 16 files changed, 898 insertions(+), 165 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos7-clock.txt create mode 100644 arch/arm64/boot/dts/exynos/Makefile create mode 100644 arch/arm64/boot/dts/exynos/exynos7-espresso.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos7.dtsi create mode 12 arch/arm64/boot/dts/include/dt-bindings create mode 100644 drivers/clk/samsung/clk-exynos7.c create mode 100644 include/dt-bindings/clock/exynos7-clk.h For this series: Reviewed-by: Thomas Abraham thomas...@samsung.com Tested-by: Thomas Abraham thomas...@samsung.com -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe devicetree in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
On Thu, Sep 4, 2014 at 7:00 PM, Kevin Hilman khil...@kernel.org wrote:
Thomas Abraham ta.oma...@gmail.com writes:
On Thu, Sep 4, 2014 at 4:45 AM, Kevin Hilman khil...@kernel.org wrote:
Hi Thomas,
Thomas Abraham ta.oma...@gmail.com writes:
[...]
A new branch [1] has been created using commits from exynos5-v3.17-rc1
branch + cpufreq + regulator + temp fixes. I have tested this branch
on Exynos5800 Chromebook2 and cpufreq works fine with both ondemand
and performance governors. Please let me know if there are any issues
with this new branch. It is based on v3.17-rc3.
Excellent! Thank you.
The only thing missing now is the CPUidle support for 5800, and all
that's needed for that is the compatible string patch[1] which Daniel
has queued up.
With that patch, display + CPUidle + CPUfreq are working pretty well on
my exynos5800/chromebook2 with the big.LITTLE switcher disabled. If I
turn on the switcher, it boots OK, but as soon as I try to run powertop
(upstream v2.6.1) it gets stuck. Have you tried this branch with the
switcher enabled?
Yes, I have tested switcher + cpufreq + cpuidle with this branch and
there are no issues found. I haven't tested with powertop yet. I will
try and do that and let you know the result.
You mentioned that when you run powertop, it gets stuck. When that
happens, is there any log on the console or does system just turn
unresponsive?
The console is not responsive, but kernel seems busy because I see
periodic timeout messages from the samsung clock driver.
Ok, I haven't tried to recreate this issue. I will try and do that.
Note that I see these messages when things are functioning normally
also.
I did notice this a few times before but today I was able to reproduce
this consistently with other test cases. This timeout is because the
CPU clock blocks of the cluster that has been turned down are being
reconfigured, which on Exynos will not work. The following is a
temporary patch which solves this issue.
From b0c4057d428134fe12446431ede1d9a579fd1d05 Mon Sep 17 00:00:00 2001
From: Thomas Abraham thomas...@samsung.com
Date: Fri, 5 Sep 2014 17:11:10 +0530
Subject: [PATCH] TEMP: cpufreq/bL: let the CPU switch complete before
scaling frequency
On Exynos5420/Exyons5800, the clock blocks that make up the CPU clock
supply do no operate when the cluster in which they belong is powered off.
The CPU clock supply path is PLL - Mux/Dividers - CPU_clock.
In the arm_big_little CPUfreq driver, the frequency is scaled first and
then the CPU is switched to the new cluster. In case the switch was for
the first-man CPU in that new cluster, the frequency scaling step in
arm_big_little CPUfreq driver would not work for Exynos since the
in-bound cluster is powered off at that point. Note: On Exynos, the
cluster is powered off when all the CPUs in that cluster are powered off
which implies that the CPU clock blocks for that cluster do not operate
anymore.
So when using arm_big_little CPUfreq driver for Exynos, two changes are
required. The first change is to let the CPU to switch to the new cluster
before scaling the frequency. The second change is to ensure that the
switch has been completed before scaling the frequency.
With these changes, the message wait_until_divider_stable: timeout in
divider stabilization is not seen anymore.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/include/asm/bL_switcher.h | 15 ++-
drivers/cpufreq/arm_big_little.c |9 -
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/bL_switcher.h
b/arch/arm/include/asm/bL_switcher.h
index 1714800..d609b86 100644
--- a/arch/arm/include/asm/bL_switcher.h
+++ b/arch/arm/include/asm/bL_switcher.h
@@ -20,9 +20,22 @@ typedef void (*bL_switch_completion_handler)(void *cookie);
int bL_switch_request_cb(unsigned int cpu, unsigned int new_cluster_id,
bL_switch_completion_handler completer,
void *completer_cookie);
+
+static void bL_switch_complete_cb(void *cookie)
+{
+struct completion *switch_complete = (struct completion *) cookie;
+complete(switch_complete);
+}
+
static inline int bL_switch_request(unsigned int cpu, unsigned int
new_cluster_id)
{
- return bL_switch_request_cb(cpu, new_cluster_id, NULL, NULL);
+ struct completion complete;
+
+ init_completion(complete);
+ bL_switch_request_cb(cpu, new_cluster_id, bL_switch_complete_cb,
+ complete);
+ wait_for_completion(complete);
+ return 0;
}
/*
diff --git a/drivers/cpufreq/arm_big_little.c b/drivers/cpufreq/arm_big_little.c
index a46c223..baeff47 100644
--- a/drivers/cpufreq/arm_big_little.c
+++ b/drivers/cpufreq/arm_big_little.c
@@ -129,6 +129,13 @@ bL_cpufreq_set_rate(u32 cpu, u32 old_cluster, u32
new_cluster, u32 rate)
int ret;
bool bLs = is_bL_switching_enabled();
+ /* Switch cluster
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
On Thu, Sep 4, 2014 at 4:45 AM, Kevin Hilman khil...@kernel.org wrote: Hi Thomas, Thomas Abraham ta.oma...@gmail.com writes: [...] A new branch [1] has been created using commits from exynos5-v3.17-rc1 branch + cpufreq + regulator + temp fixes. I have tested this branch on Exynos5800 Chromebook2 and cpufreq works fine with both ondemand and performance governors. Please let me know if there are any issues with this new branch. It is based on v3.17-rc3. Excellent! Thank you. The only thing missing now is the CPUidle support for 5800, and all that's needed for that is the compatible string patch[1] which Daniel has queued up. With that patch, display + CPUidle + CPUfreq are working pretty well on my exynos5800/chromebook2 with the big.LITTLE switcher disabled. If I turn on the switcher, it boots OK, but as soon as I try to run powertop (upstream v2.6.1) it gets stuck. Have you tried this branch with the switcher enabled? Yes, I have tested switcher + cpufreq + cpuidle with this branch and there are no issues found. I haven't tested with powertop yet. I will try and do that and let you know the result. You mentioned that when you run powertop, it gets stuck. When that happens, is there any log on the console or does system just turn unresponsive? Thanks, Thomas. Thanks again for your work on this, we're getting close! Kevin [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-August/279028.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
On Wed, Sep 3, 2014 at 9:56 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Kevin, On Wed, Sep 3, 2014 at 1:02 AM, Kevin Hilman khil...@kernel.org wrote: HI Thomas, Thomas Abraham ta.oma...@gmail.com writes: On Fri, Aug 29, 2014 at 8:33 PM, Kevin Hilman khil...@kernel.org wrote: Hi Thomas, On Fri, Aug 29, 2014 at 5:52 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Kevin, On Wed, Aug 27, 2014 at 3:55 AM, Kevin Hilman khil...@linaro.org wrote: On Tue, Aug 26, 2014 at 8:15 AM, Kevin Hilman khil...@linaro.org wrote: On Mon, Aug 25, 2014 at 10:25 PM, Chander Kashyap k.chan...@samsung.com wrote: [...] Can you clarify how you're setting the voltages to ensure stability? below is the diff : wip/exynos/integ Thanks. I've applied your patch, and bootup shows vdd_arm and vdd_kfc at 1500mV, but still when booting with cpuidle enabled (bL switcher disabled), I'm seeing lockups with no kernel output. With CPUidle disabled, things are pretty stable. What tree are you using to test this out on 5420? I'm using mainline v3.17-rc1 + DT patch for CPUidle and this cpufreq series. See my wip/exynos/integ branch at git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git. I mis-stated this. Actually my tree is based on the v3.17-rc1 branch of the exynos-reference tree[1] + the above mentioned patches for cpuidle and cpufreq. Also, I've narrowed down the instability a bit, and it's not related to CPUidle. I can now trigger a boot hang even without CPUidle enabled. Here's a quick way to cause a boot lockup. With the switcher disabled, I enable CPUfreq and set the default governor to performance. As soon as cpufreq driver loads, it tries to use the top frequences for both clusters, and it hangs. Selectively disabling frequencies, I narrowed it down to the 1.3GHz and 1.2GHz frequencies of the little cluster. With these commented out in the DT, it will fully boot with the performance governor enabled. So that leads to the question. Are all of the operating points in exynos5420.dtsi valid for exynos5800, and have they been validated? I tried to recreate the boot lockup issue using the same steps you listed above for the Exynos5800 peach-pi platform (Chromebook2), but I do not see any issues. I can see both clusters with max clock speed after boot (1.8GHz and 1.3GHz). I am using v3.17-rc2 + CPUFreq Patches + max77802 regulator support patches for Chromebook2 + temp hack to set A15 voltage to 1.35V and A7 voltage to 1.3V. Can you share your branch and temp hack(s) as well as your defconfig? I'm using the v3.17-rc1 branch from the exynos tree (which includes the max77802 series) but also has a bunch of other stuff which may be causing the issue. It would be good if I can reproduce your exact tree/branch and see if I still have the same problem. The branch with the patches that have been used to test cpufreq on Exynos5800 is available at https://github.com/exynos-reference/kernel/tree/exynos5-v3.17-rc3-temp-cpufreq Please let me know if this works or if there are any issues. Yes, your branch works fine, but it's because of the last (unposted) patch on your branch[1]: ARM: dts: remove all supplies sourced from tps65090 PMIC I must have explicitly stated that I am using local changes to get vdd_arm and vdd_kfc to required levels. I apologize for that. These are local temporary changes which I did not want to post. I am working on adding voltage scaling support in arm bL cpufreq driver with which these local hacks would not be necessary. That patch had not been posted, so I hadn't seen it before, but based on the changelog, it's pretty clear you had the same problems that I had without it, so I'm not sure why it wasn't mentioned earlier in this thread. At the time of posting, this patch series was only tested on Exynos5420 based smdk5420 board. There was no regulator support for peach-pit and peach-pi at that time and so I had not tested this series on Exynos5800 Chromebook2. But the code was written to be fully compatible for Exynos5800 as well. It was when you reported a problem with Exynos5800 that I tested this series on Exynos5800 with the regulator patches from Javier. I also noticed that the force vdd_arm and vdd_kfc to max voltage patch is not actually using the max voltage, which appears to be 1.5V from the DT, but actually using 1.35 V, however the changelog has no explanation for this. This also is a temporary patch and by max voltage I actually meant max voltage required to operate the cpus and not the max voltage that the buck can supply. One other thing, your temp-cpufreq branch has conflicts with max77802 stuff in the v3.17-rc1 branch of the exynos-reference tree (which I'm using for CPUidle dependencies, on the PMU series IIRC.) I haven't checked but probably there is an older version of Javier's regulator patches in the v3.17-rc1 branch. Are there any plans to update the main
Re: [PATCH v9 1/6] clk: samsung: add infrastructure to register cpu clocks
On Tue, Sep 2, 2014 at 3:59 AM, Mike Turquette mturque...@linaro.org wrote:
Quoting Thomas Abraham (2014-07-30 01:07:38)
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Acked-by: Mike Turquette mturque...@linaro.org
Thank you Mike.
Regards,
Thomas.
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335
+
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..8909c93 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or
a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of
clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and
AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to
the
+ * CPU clock rate and this relation is usually specified in the hardware
manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the
CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the
CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock
hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU
domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While
the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is
divided
+ * down in order to keep the output clock rate within the previous OPP
limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the
divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Kevin, On Wed, Sep 3, 2014 at 1:02 AM, Kevin Hilman khil...@kernel.org wrote: HI Thomas, Thomas Abraham ta.oma...@gmail.com writes: On Fri, Aug 29, 2014 at 8:33 PM, Kevin Hilman khil...@kernel.org wrote: Hi Thomas, On Fri, Aug 29, 2014 at 5:52 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Kevin, On Wed, Aug 27, 2014 at 3:55 AM, Kevin Hilman khil...@linaro.org wrote: On Tue, Aug 26, 2014 at 8:15 AM, Kevin Hilman khil...@linaro.org wrote: On Mon, Aug 25, 2014 at 10:25 PM, Chander Kashyap k.chan...@samsung.com wrote: [...] Can you clarify how you're setting the voltages to ensure stability? below is the diff : wip/exynos/integ Thanks. I've applied your patch, and bootup shows vdd_arm and vdd_kfc at 1500mV, but still when booting with cpuidle enabled (bL switcher disabled), I'm seeing lockups with no kernel output. With CPUidle disabled, things are pretty stable. What tree are you using to test this out on 5420? I'm using mainline v3.17-rc1 + DT patch for CPUidle and this cpufreq series. See my wip/exynos/integ branch at git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git. I mis-stated this. Actually my tree is based on the v3.17-rc1 branch of the exynos-reference tree[1] + the above mentioned patches for cpuidle and cpufreq. Also, I've narrowed down the instability a bit, and it's not related to CPUidle. I can now trigger a boot hang even without CPUidle enabled. Here's a quick way to cause a boot lockup. With the switcher disabled, I enable CPUfreq and set the default governor to performance. As soon as cpufreq driver loads, it tries to use the top frequences for both clusters, and it hangs. Selectively disabling frequencies, I narrowed it down to the 1.3GHz and 1.2GHz frequencies of the little cluster. With these commented out in the DT, it will fully boot with the performance governor enabled. So that leads to the question. Are all of the operating points in exynos5420.dtsi valid for exynos5800, and have they been validated? I tried to recreate the boot lockup issue using the same steps you listed above for the Exynos5800 peach-pi platform (Chromebook2), but I do not see any issues. I can see both clusters with max clock speed after boot (1.8GHz and 1.3GHz). I am using v3.17-rc2 + CPUFreq Patches + max77802 regulator support patches for Chromebook2 + temp hack to set A15 voltage to 1.35V and A7 voltage to 1.3V. Can you share your branch and temp hack(s) as well as your defconfig? I'm using the v3.17-rc1 branch from the exynos tree (which includes the max77802 series) but also has a bunch of other stuff which may be causing the issue. It would be good if I can reproduce your exact tree/branch and see if I still have the same problem. The branch with the patches that have been used to test cpufreq on Exynos5800 is available at https://github.com/exynos-reference/kernel/tree/exynos5-v3.17-rc3-temp-cpufreq Please let me know if this works or if there are any issues. Yes, your branch works fine, but it's because of the last (unposted) patch on your branch[1]: ARM: dts: remove all supplies sourced from tps65090 PMIC I must have explicitly stated that I am using local changes to get vdd_arm and vdd_kfc to required levels. I apologize for that. These are local temporary changes which I did not want to post. I am working on adding voltage scaling support in arm bL cpufreq driver with which these local hacks would not be necessary. That patch had not been posted, so I hadn't seen it before, but based on the changelog, it's pretty clear you had the same problems that I had without it, so I'm not sure why it wasn't mentioned earlier in this thread. At the time of posting, this patch series was only tested on Exynos5420 based smdk5420 board. There was no regulator support for peach-pit and peach-pi at that time and so I had not tested this series on Exynos5800 Chromebook2. But the code was written to be fully compatible for Exynos5800 as well. It was when you reported a problem with Exynos5800 that I tested this series on Exynos5800 with the regulator patches from Javier. I also noticed that the force vdd_arm and vdd_kfc to max voltage patch is not actually using the max voltage, which appears to be 1.5V from the DT, but actually using 1.35 V, however the changelog has no explanation for this. This also is a temporary patch and by max voltage I actually meant max voltage required to operate the cpus and not the max voltage that the buck can supply. One other thing, your temp-cpufreq branch has conflicts with max77802 stuff in the v3.17-rc1 branch of the exynos-reference tree (which I'm using for CPUidle dependencies, on the PMU series IIRC.) I haven't checked but probably there is an older version of Javier's regulator patches in the v3.17-rc1 branch. Are there any plans to update the main referece branch and include cpufreq? Yes, a new branch with all the latest patches (cpufreq
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Kevin, On Fri, Aug 29, 2014 at 8:33 PM, Kevin Hilman khil...@kernel.org wrote: Hi Thomas, On Fri, Aug 29, 2014 at 5:52 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Kevin, On Wed, Aug 27, 2014 at 3:55 AM, Kevin Hilman khil...@linaro.org wrote: On Tue, Aug 26, 2014 at 8:15 AM, Kevin Hilman khil...@linaro.org wrote: On Mon, Aug 25, 2014 at 10:25 PM, Chander Kashyap k.chan...@samsung.com wrote: [...] Can you clarify how you're setting the voltages to ensure stability? below is the diff : wip/exynos/integ Thanks. I've applied your patch, and bootup shows vdd_arm and vdd_kfc at 1500mV, but still when booting with cpuidle enabled (bL switcher disabled), I'm seeing lockups with no kernel output. With CPUidle disabled, things are pretty stable. What tree are you using to test this out on 5420? I'm using mainline v3.17-rc1 + DT patch for CPUidle and this cpufreq series. See my wip/exynos/integ branch at git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git. I mis-stated this. Actually my tree is based on the v3.17-rc1 branch of the exynos-reference tree[1] + the above mentioned patches for cpuidle and cpufreq. Also, I've narrowed down the instability a bit, and it's not related to CPUidle. I can now trigger a boot hang even without CPUidle enabled. Here's a quick way to cause a boot lockup. With the switcher disabled, I enable CPUfreq and set the default governor to performance. As soon as cpufreq driver loads, it tries to use the top frequences for both clusters, and it hangs. Selectively disabling frequencies, I narrowed it down to the 1.3GHz and 1.2GHz frequencies of the little cluster. With these commented out in the DT, it will fully boot with the performance governor enabled. So that leads to the question. Are all of the operating points in exynos5420.dtsi valid for exynos5800, and have they been validated? I tried to recreate the boot lockup issue using the same steps you listed above for the Exynos5800 peach-pi platform (Chromebook2), but I do not see any issues. I can see both clusters with max clock speed after boot (1.8GHz and 1.3GHz). I am using v3.17-rc2 + CPUFreq Patches + max77802 regulator support patches for Chromebook2 + temp hack to set A15 voltage to 1.35V and A7 voltage to 1.3V. Can you share your branch and temp hack(s) as well as your defconfig? I'm using the v3.17-rc1 branch from the exynos tree (which includes the max77802 series) but also has a bunch of other stuff which may be causing the issue. It would be good if I can reproduce your exact tree/branch and see if I still have the same problem. The branch with the patches that have been used to test cpufreq on Exynos5800 is available at https://github.com/exynos-reference/kernel/tree/exynos5-v3.17-rc3-temp-cpufreq Please let me know if this works or if there are any issues. Thanks, Thomas. Thanks for looking into this, Kevin -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Kevin, On Wed, Aug 27, 2014 at 3:55 AM, Kevin Hilman khil...@linaro.org wrote: On Tue, Aug 26, 2014 at 8:15 AM, Kevin Hilman khil...@linaro.org wrote: On Mon, Aug 25, 2014 at 10:25 PM, Chander Kashyap k.chan...@samsung.com wrote: [...] Can you clarify how you're setting the voltages to ensure stability? below is the diff : wip/exynos/integ Thanks. I've applied your patch, and bootup shows vdd_arm and vdd_kfc at 1500mV, but still when booting with cpuidle enabled (bL switcher disabled), I'm seeing lockups with no kernel output. With CPUidle disabled, things are pretty stable. What tree are you using to test this out on 5420? I'm using mainline v3.17-rc1 + DT patch for CPUidle and this cpufreq series. See my wip/exynos/integ branch at git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git. I mis-stated this. Actually my tree is based on the v3.17-rc1 branch of the exynos-reference tree[1] + the above mentioned patches for cpuidle and cpufreq. Also, I've narrowed down the instability a bit, and it's not related to CPUidle. I can now trigger a boot hang even without CPUidle enabled. Here's a quick way to cause a boot lockup. With the switcher disabled, I enable CPUfreq and set the default governor to performance. As soon as cpufreq driver loads, it tries to use the top frequences for both clusters, and it hangs. Selectively disabling frequencies, I narrowed it down to the 1.3GHz and 1.2GHz frequencies of the little cluster. With these commented out in the DT, it will fully boot with the performance governor enabled. So that leads to the question. Are all of the operating points in exynos5420.dtsi valid for exynos5800, and have they been validated? I tried to recreate the boot lockup issue using the same steps you listed above for the Exynos5800 peach-pi platform (Chromebook2), but I do not see any issues. I can see both clusters with max clock speed after boot (1.8GHz and 1.3GHz). I am using v3.17-rc2 + CPUFreq Patches + max77802 regulator support patches for Chromebook2 + temp hack to set A15 voltage to 1.35V and A7 voltage to 1.3V. Sorry for the delaying in following up. Thanks, Thomas. Kevin [1]https://github.com/exynos-reference/kernel.git -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2] ARM: EXYNOS: Refactor the pm code to use DT based lookup
,
+ .pm_prepare = exynos5250_pm_prepare,
+ .cpu_suspend= exynos5250_cpu_suspend,
+};
+
+static struct of_device_id exynos_pmu_of_device_ids[] = {
+ {
+ .compatible = samsung,exynos4210-pmu,
+ .data = (void *)exynos4_pm_data,
+ }, {
+ .compatible = samsung,exynos4212-pmu,
+ .data = (void *)exynos4_pm_data,
+ }, {
+ .compatible = samsung,exynos4412-pmu,
+ .data = (void *)exynos4_pm_data,
+ }, {
+ .compatible = samsung,exynos5250-pmu,
+ .data = (void *)exynos5250_pm_data,
+ },
+ { /*sentinel*/ },
+};
+
void __init exynos_pm_init(void)
{
u32 tmp;
+ const struct of_device_id *match;
cpu_pm_register_notifier(exynos_cpu_pm_notifier_block);
+ of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids,
match);
+
+ if (!match) {
+ pr_err(Failed to find PMU node\n);
+ return;
+ }
+ pm_data = (struct exynos_pm_data *) match-data;
+
/* Platform-specific GIC callback */
gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
/* All wakeup disable */
tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
- tmp |= ((0xFF 8) | (0x1F 1));
+ tmp |= pm_data-wake_disable_mask;
pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
register_syscore_ops(exynos_pm_syscore_ops);
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 96a1569..30c0301 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -21,6 +21,7 @@
#define S5P_USE_STANDBY_WFI0 (1 16)
#define S5P_USE_STANDBY_WFE0 (1 24)
+#define EXYNOS_WAKEUP_FROM_LOWPWR (1 28)
#define EXYNOS_SWRESET 0x0400
#define EXYNOS5440_SWRESET 0x00C4
Rest of the patch looks fine. With the fix for comment above,
Reviewed-by: Thomas Abraham thomas...@samsung.com
--
1.7.9.5
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Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hi Javier, On Sat, Aug 2, 2014 at 9:19 AM, Javier Martinez Canillas javier.marti...@collabora.co.uk wrote: Hello Thomas, On 07/30/2014 10:07 AM, Thomas Abraham wrote: For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU regulator supply properties for migrating from Exynos specific cpufreq driver to using generic cpufreq drivers. Cc: Kukjin Kim kgene@samsung.com Cc: Doug Anderson diand...@chromium.org Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk Cc: Andreas Faerber afaer...@suse.de Cc: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Thomas Abraham thomas...@samsung.com --- arch/arm/boot/dts/exynos4210-origen.dts |4 +++ arch/arm/boot/dts/exynos4210-trats.dts |4 +++ arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++ arch/arm/boot/dts/exynos4210.dtsi | 14 - arch/arm/boot/dts/exynos5250-arndale.dts|4 +++ arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++ arch/arm/boot/dts/exynos5250-snow.dts |4 +++ arch/arm/boot/dts/exynos5250.dtsi | 25 ++- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ 9 files changed, 99 insertions(+), 2 deletions(-) Tested the series on a Exynos5420 based Peach Pit Chromebook by doing the following for CPU0-3: 1) Verified that the big.LITTLE CPUFreq (arm-big-little) driver was reported as used in /sys/devices/system/cpu/cpu*/cpufreq/scaling_driver. 2) Set all available governors (conservative, ondemand, userspace, powersave and performance). 3) Confirmed that cpuinfo_cur_freq and scaling_cur_freq values were fixed or changing according to the selected governor policy. 4) Verified that the statistics in /sys/devices/system/cpu/cpu*/cpufreq/stats/* were filled. Everything is working correctly so please feel free to add for the whole series: Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk Thank you for using this series and the details of what has worked. This is very helpful. Regards, Thomas. Best regards, Javier -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
Hi Tomasz, On Fri, Aug 1, 2014 at 1:00 AM, Tomasz Figa tomasz.f...@gmail.com wrote: On 31.07.2014 21:25, Thomas Abraham wrote: On Fri, Aug 1, 2014 at 12:24 AM, Tomasz Figa tomasz.f...@gmail.com wrote: On 31.07.2014 20:40, Tomasz Figa wrote: Kukjin, On 31.07.2014 20:32, Kukjin Kim wrote: On 07/30/14 17:07, Thomas Abraham wrote: The new CPU clock type allows the use of generic CPUfreq drivers. So for Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420, which did not have CPUfreq driver support, enable the use of generic CPUfreq driver. Suggested-by: Tomasz Figat.f...@samsung.com Cc: Kukjin Kimkgene@samsung.com Looks good to me, Acked-by: Kukjin Kim kgene@samsung.com BTW, who will handle this series? I hope see this series in 3.17. This series consists mostly of clock changes and it likely depends on patches already in my for-next, so I would be inclined toward taking it through samsung-clk tree. However, for this I would need Acks for patch 5/6 from Viresh and for patches [1] and [2] (which are dependencies of this series) from you. I also need to make sure that the two mentioned patches don't have any dependencies already in your tree. [1] ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 [2] ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html Aha, I'm not quite sure we really want to hurry with this series for 3.17. I'd prefer it to be picked up early after 3.17-rc1 shows up to sit in linux-next for a while an be thoroughly tested on a number of boards. The v9 revision of this series has completed about 2 days of testing now on 4210/5250/5420 boards. I will let it run for few more days. For v8 and previous versions, the tests had completed 3 or more days. So I really don't think there is anything fundamentally wrong with this series. It would be nice to have this series merged and we start migrating other Exynos based boards to use generic cpufreq drivers. We have 22 Exynos-based boards currently supported in mainline. Is the testing running on all of them? This is the purpose of linux-next and This series replaces existing cpufreq driver for Exynos4210 and Exynos5250 which impact 7 Exynos boards - Exynos4210 (smdk, origen, trats, universal), Exynos5250 (smdk, arndale, snow). Out of these, it is trats and universal that have not been tested. Which other 15 Exynos boards did you feel this series needs to be tested on? Sanity testing for Exynos4x12 cpufreq support was done on Exynos4412 Origen board. for series that completely replace one driver with another I'd consider this as the only reasonable choice, if not keeping the old driver for a release. Of course we have never good testing traditions on Samsung SoC (see OMAP and Tegra baseline tests), but does it mean that we shouldn't start doing the right thing? Aren't Tegra/OMAP baseline tests for upstream kernel versions only, not for linux-next? Thanks, Thomas. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/3] clk: exynos5410: Add the definitions of new clock registers
Hi Humberto, On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote: Added clock register definitions for the majority of the relevant clocks inside the SoC, including the definitions of all PLL's clocks. The definitions are now ordered by name, in order to make the It would be good not to mix name ordering and addition of new definitions. Also, it would be better if the new definitions are ordered on the register address offset and not the name. It is easier to check if a definition is available based on register offset than the name. driver more readable and reduce the chances of potential conflicts when adding new entries. The different register groups (SRC, DIV, PLL, GATE, etc) are separated by a blank line. Signed-off-by: Humberto Silva Naves hsna...@gmail.com --- drivers/clk/samsung/clk-exynos5410.c | 144 -- 1 file changed, 122 insertions(+), 22 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 231475b..72a533e 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -19,39 +19,139 @@ #include clk.h -#define APLL_LOCK 0x0 -#define APLL_CON0 0x100 -#define CPLL_LOCK 0x10020 -#define CPLL_CON0 0x10120 -#define MPLL_LOCK 0x4000 -#define MPLL_CON0 0x4100 -#define BPLL_LOCK 0x20010 -#define BPLL_CON0 0x20110 -#define KPLL_LOCK 0x28000 -#define KPLL_CON0 0x28100 +#define APLL_CON0 0x100 +#define APLL_LOCK 0x0 +#define BPLL_CON0 0x20110 +#define BPLL_LOCK 0x20010 +#define CPLL_CON0 0x10120 +#define CPLL_CON1 0x10124 +#define CPLL_LOCK 0x10020 +#define DPLL_CON0 0x10128 +#define DPLL_CON1 0x1012C +#define DPLL_LOCK 0x10030 +#define EPLL_CON0 0x10130 +#define EPLL_CON1 0x10134 +#define EPLL_CON2 0x10138 +#define EPLL_LOCK 0x10040 +#define IPLL_CON0 0x10150 +#define IPLL_CON1 0x10154 +#define IPLL_LOCK 0x10060 +#define KPLL_CON0 0x28100 +#define KPLL_LOCK 0x28000 +#define MPLL_CON0 0x4100 +#define MPLL_LOCK 0x4000 +#define VPLL_CON0 0x10140 +#define VPLL_CON1 0x10144 +#define VPLL_CON2 0x10148 +#define VPLL_LOCK 0x10050 -#define SRC_CPU0x200 -#define DIV_CPU0 0x500 +#define SRC_CDREX 0x20200 +#define SRC_CPERI0 0x4200 #define SRC_CPERI1 0x4204 -#define DIV_TOP0 0x10510 -#define DIV_TOP1 0x10514 -#define DIV_FSYS1 0x1054c -#define DIV_FSYS2 0x10550 -#define DIV_PERIC0 0x10558 +#define SRC_CPU0x200 +#define SRC_DISP0_00x10224 +#define SRC_DISP0_10x10228 +#define SRC_DISP1_00x1022C +#define SRC_DISP1_10x10230 +#define SRC_FSYS 0x10244 +#define SRC_GSCL 0x10220 +#define SRC_KFC0x28200 +#define SRC_MAU0x10240 +#define SRC_PERIC0 0x10250 +#define SRC_PERIC1 0x10254 #define SRC_TOP0 0x10210 #define SRC_TOP1 0x10214 #define SRC_TOP2 0x10218 -#define SRC_FSYS 0x10244 -#define SRC_PERIC0 0x10250 +#define SRC_TOP3 0x1021C + +#define SRC_MASK_DISP0_0 0x10324 +#define SRC_MASK_DISP0_1 0x10328 +#define SRC_MASK_DISP1_0 0x1032C +#define SRC_MASK_DISP1_1 0x10330 #define SRC_MASK_FSYS 0x10340 +#define SRC_MASK_GEN 0x10344 +#define SRC_MASK_GSCL 0x10320 +#define SRC_MASK_MAU 0x10334 #define SRC_MASK_PERIC00x10350 +#define SRC_MASK_PERIC10x10354 +#define SRC_MASK_TOP 0x10310 + +#define DIV_CDREX 0x20500 +#define DIV_CDREX2 0x20504 +#define DIV_CPERI0 0x4500 +#define DIV_CPERI1 0x4504 +#define DIV_CPU0 0x500 +#define DIV_CPU1 0x504 +#define DIV_DISP0_00x10524 +#define DIV_DISP0_10x10528 +#define DIV_DISP1_00x1052C +#define DIV_DISP1_10x10530 +#define DIV_FSYS0 0x10548 +#define DIV_FSYS1 0x1054C +#define DIV_FSYS2 0x10550 +#define DIV_FSYS3 0x10554 +#define DIV_GEN0x1053C +#define DIV_GSCL 0x10520 +#define DIV_G2D0x8500 +#define DIV_ISP0 0x0C300 +#define
Re: [PATCH 2/3] clk: exynos5410: Add suspend/resume handling
Hi Humberto,
On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote:
This patch implements all the necessary code that handles register
saving and restoring during a suspend/resume cycle.
To make this possible, the local variable reg_base from the function
exynos5410_clk_init was changed to global.
Signed-off-by: Humberto Silva Naves hsna...@gmail.com
---
drivers/clk/samsung/clk-exynos5410.c | 132
+-
1 file changed, 131 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
index 72a533e..aaca65d 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -16,6 +16,7 @@
#include linux/clk-provider.h
#include linux/of.h
#include linux/of_address.h
+#include linux/syscore_ops.h
#include clk.h
@@ -160,6 +161,134 @@ enum exynos5410_plls {
nr_plls /* number of PLLs */
};
+static void __iomem *reg_base;
+
+#ifdef CONFIG_PM_SLEEP
+static struct samsung_clk_reg_dump *exynos5410_save;
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspend/resume cycle.
+ */
+static unsigned long exynos5410_clk_regs[] __initdata = {
+ SRC_CDREX,
+ SRC_CPERI0,
+ SRC_CPERI1,
+ SRC_CPU,
+ SRC_DISP0_0,
+ SRC_DISP0_1,
+ SRC_DISP1_0,
+ SRC_DISP1_1,
+ SRC_FSYS,
+ SRC_GSCL,
+ SRC_KFC,
+ SRC_MAU,
+ SRC_PERIC0,
+ SRC_PERIC1,
+ SRC_TOP0,
+ SRC_TOP1,
+ SRC_TOP2,
+ SRC_TOP3,
+
+ DIV_CDREX,
+ DIV_CDREX2,
+ DIV_CPU0,
+ DIV_CPERI1,
+ DIV_DISP0_0,
+ DIV_DISP0_1,
+ DIV_DISP1_0,
+ DIV_DISP1_1,
+ DIV_FSYS0,
+ DIV_FSYS1,
+ DIV_FSYS2,
+ DIV_GEN,
+ DIV_GSCL,
+ DIV_G2D,
+ DIV_KFC0,
+ DIV_MAU,
+ DIV_PERIC0,
+ DIV_PERIC1,
+ DIV_PERIC2,
+ DIV_PERIC3,
+ DIV_PERIC4,
+ DIV_PERIC5,
+ DIV_TOP0,
+ DIV_TOP1,
+ DIV_TOP2,
+ DIV_TOP3,
+
+ GATE_BUS_DISP1,
+ GATE_BUS_FSYS0,
+
+ GATE_IP_CDREX,
+ GATE_IP_CORE,
+ GATE_IP_DISP0,
+ GATE_IP_DISP1,
+ GATE_IP_FSYS,
+ GATE_IP_GEN,
+ GATE_IP_GSCL0,
+ GATE_IP_GSCL1,
+ GATE_IP_G2D,
+ GATE_IP_G3D,
+ GATE_IP_MFC,
+ GATE_IP_PERIC,
+ GATE_IP_PERIS,
+
+ GATE_TOP_SCLK_DISP1,
+ GATE_TOP_SCLK_FSYS,
+ GATE_TOP_SCLK_GSCL,
+ GATE_TOP_SCLK_MAU,
+ GATE_TOP_SCLK_PERIC,
+
+ GATE_BUS_DISP1,
+ GATE_BUS_FSYS0,
+
+ GATE_SCLK_CPU,
+
+ SRC_MASK_DISP0_0,
+ SRC_MASK_DISP1_0,
+ SRC_MASK_FSYS,
+ SRC_MASK_MAU,
+ SRC_MASK_PERIC0,
+ SRC_MASK_PERIC1,
+};
+
+static int exynos5410_clk_suspend(void)
+{
+ samsung_clk_save(reg_base, exynos5410_save,
+ ARRAY_SIZE(exynos5410_clk_regs));
+
+ return 0;
+}
+
+static void exynos5410_clk_resume(void)
+{
+ samsung_clk_restore(reg_base, exynos5410_save,
+ ARRAY_SIZE(exynos5410_clk_regs));
+}
+
+static struct syscore_ops exynos5410_clk_syscore_ops = {
+ .suspend = exynos5410_clk_suspend,
+ .resume = exynos5410_clk_resume,
+};
+
+static void exynos5410_clk_sleep_init(void)
+{
+ exynos5410_save = samsung_clk_alloc_reg_dump(exynos5410_clk_regs,
+ ARRAY_SIZE(exynos5410_clk_regs));
+ if (!exynos5410_save) {
+ pr_warn(%s: failed to allocate sleep save data, no sleep
support!\n,
+ __func__);
+ return;
+ }
+
+ register_syscore_ops(exynos5410_clk_syscore_ops);
+}
+#else
+static void exynos5410_clk_sleep_init(void) {}
+#endif
+
+
Extra new line here can be removed.
/* list of all parent clocks */
PNAME(apll_p) = { fin_pll, fout_apll, };
PNAME(bpll_p) = { fin_pll, fout_bpll, };
@@ -286,7 +415,6 @@ static struct samsung_pll_clock exynos5410_plls[nr_plls]
__initdata = {
static void __init exynos5410_clk_init(struct device_node *np)
{
struct samsung_clk_provider *ctx;
- void __iomem *reg_base;
reg_base = of_iomap(np, 0);
if (!reg_base)
@@ -304,6 +432,8 @@ static void __init exynos5410_clk_init(struct device_node
*np)
samsung_clk_register_gate(ctx, exynos5410_gate_clks,
ARRAY_SIZE(exynos5410_gate_clks));
+ exynos5410_clk_sleep_init();
+
samsung_clk_of_add_provider(np, ctx);
pr_debug(Exynos5410: clock setup completed.\n);
--
1.7.10.4
Reviewed-by: Thomas Abraham thomas...@samsung.com
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Re: [PATCH 3/3] clk: exynos5410: Added clocks BPLL, DPLL, EPLL, IPLL, MPLL, and VPLL
Hi Humberto,
On Wed, Jul 30, 2014 at 8:06 PM, Humberto Silva Naves hsna...@gmail.com wrote:
Added the remaining PLL clocks, and also registered the configuration
tables with the PLL coefficients for the supported frequencies.
These frequency tables are valid when a 24MHz clock is supplied as the
input clock source (which I believe is always the case). Furthermore,
the corresponding constants for these PLL clocks were addded to the
dt-bindings header file. While at it, the constant definitions were
reordered alphabetically.
Signed-off-by: Humberto Silva Naves hsna...@gmail.com
---
drivers/clk/samsung/clk-exynos5410.c | 128
+---
include/dt-bindings/clock/exynos5410.h | 12 ++-
2 files changed, 127 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
index aaca65d..7f4b3ea 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -156,9 +156,10 @@
/* list of PLLs */
enum exynos5410_plls {
- apll, cpll, mpll,
- bpll, kpll,
- nr_plls /* number of PLLs */
+ apll, bpll, cpll,
+ dpll, epll, ipll,
+ kpll, mpll, vpll,
+ nr_plls /* number of PLLs */
};
static void __iomem *reg_base;
@@ -398,17 +399,126 @@ static struct samsung_gate_clock
exynos5410_gate_clks[] __initdata = {
SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
};
+static struct samsung_pll_rate_table apll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(21, 175, 2, 0),
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(19, 475, 6, 0),
+ PLL_35XX_RATE(18, 225, 3, 0),
+ PLL_35XX_RATE(17, 425, 6, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 100, 2, 0),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 100, 2, 1),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 100, 2, 2),
+ PLL_35XX_RATE(2, 200, 3, 3),
+ { },
+};
+
+static struct samsung_pll_rate_table cpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(66600, 222, 4, 1),
+ PLL_35XX_RATE(64000, 160, 3, 1),
+ PLL_35XX_RATE(32000, 160, 3, 2),
+ { },
+};
+
+static struct samsung_pll_rate_table dpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(6, 200, 4, 1),
+ { },
+};
+
+static struct samsung_pll_rate_table epll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_36XX_RATE(rate, m, p, s, k) */
+ PLL_36XX_RATE(6, 100, 2, 1, 0),
+ PLL_36XX_RATE(4, 200, 3, 2, 0),
+ PLL_36XX_RATE(2, 200, 3, 3, 0),
+ PLL_36XX_RATE(180633600, 301, 5, 3, -3670),
+ PLL_36XX_RATE( 67737600, 452, 5, 5, -27263),
+ PLL_36XX_RATE( 49152000, 197, 3, 5, -25690),
+ PLL_36XX_RATE( 45158401, 181, 3, 5, -24012),
+ { },
+};
+
+static struct samsung_pll_rate_table ipll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s, k) */
+ PLL_35XX_RATE(86400, 288, 4, 1),
+ PLL_35XX_RATE(66600, 222, 4, 1),
+ PLL_35XX_RATE(43200, 288, 4, 2),
+ { },
+};
+
+static struct samsung_pll_rate_table kpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+ /* PLL_35XX_RATE(rate, m, p, s) */
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 100, 2, 0),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 100, 2, 1),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 100, 2, 2),
+ PLL_35XX_RATE(2, 200, 3, 3),
+ { },
+};
+
+static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
+ /* sorted in descending order */
+
Re: [PATCH v9 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
On Thu, Jul 31, 2014 at 11:50 AM, Chander M. Kashyap chander.kash...@gmail.com wrote: On Wed, Jul 30, 2014 at 1:37 PM, Thomas Abraham thomas...@samsung.com wrote: Changes since v8: - Fixes suggested by Tomasz Figa. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html 3. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |4 + arch/arm/boot/dts/exynos4210-trats.dts |4 + arch/arm/boot/dts/exynos4210-universal_c210.dts |4 + arch/arm/boot/dts/exynos4210.dtsi | 14 +- arch/arm/boot/dts/exynos5250-arndale.dts|4 + arch/arm/boot/dts/exynos5250-smdk5250.dts |4 + arch/arm/boot/dts/exynos5250-snow.dts |4 + arch/arm/boot/dts/exynos5250.dtsi | 25 +- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ arch/arm/mach-exynos/exynos.c | 24 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 335 +++ drivers/clk/samsung/clk-cpu.h | 91 ++ drivers/clk/samsung/clk-exynos4.c | 63 +++-- drivers/clk/samsung/clk-exynos5250.c| 44 ++- drivers/clk/samsung/clk-exynos5420.c| 72 - drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 - drivers/cpufreq/exynos5250-cpufreq.c| 210 -- include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 22 files changed, 690 insertions(+), 463 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c create mode 100644 drivers/clk/samsung/clk-cpu.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 Working great. tested on smdk5420, and arndale-5250 Hi Chander, Thanks for testing this series. Can I add a Tested-by tag for this series? Thanks, Thomas. ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- thanks and regards, Chander M. Kashyap Contact Number: +918123738320 --- TENSION LENE KA NAHI, DENE KE- ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 6/6] clk: samsung: remove unused clock aliases and update clock flags
Hi Tomasz, On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On 30.07.2014 10:07, Thomas Abraham wrote: With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags. [snip] @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? Exynos4210 : Exynos4x12, _get_rate(sclk_apll), _get_rate(sclk_mpll), _get_rate(sclk_epll), _get_rate(sclk_vpll), + exynos4_soc == EXYNOS4210 ? _get_rate(armclk) : _get_rate(div_core2)); I believe div_core2 should work fine here for all SoCs without the need for this if. The following patch is a pre-requisite for this patch. http://www.spinics.net/lists/arm-kernel/msg351540.html The rate can be obtained from div_core2 as well but with the cpu clock now registered, the rate can be obtained from the cpu clock instance instead of the div_core2 divider. And when Exynos4412 also add cpu clock instance, the 'if' above will be removed. } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e19e365..1d958f1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c [snip] @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_of_add_provider(np, ctx); pr_info(Exynos5250: clock setup completed, armclk=%ld\n, - _get_rate(div_arm2)); + _get_rate(armclk)); Similarly here, no need for this change. Same here. Instead of getting the rate from div_core2 divider block, the cpu clock instance is used to find the rate. I would prefer to use cpu clock here. Is there any reason to prefer div_core2 over the cpu clock instance? Thanks, Thomas. Best regards, Tomasz ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
On Thu, Jul 31, 2014 at 7:45 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Thomas, On 30.07.2014 10:07, Thomas Abraham wrote: Changes since v8: - Fixes suggested by Tomasz Figa. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html 3. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html I think we are at final stage of works on this series. Thanks for your cooperation. After addressing remaining minor comments from this thread, feel free to add: Reviewed-by: Tomasz Figa t.f...@samsung.com Hi Tomasz, Thanks for your review of this series. Your review comments has helped to make this series better. Regards, Thomas. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-pm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Viresh, On Thu, Jul 31, 2014 at 11:55 PM, Thomas Abraham ta.oma...@gmail.com wrote: On Thu, Jul 31, 2014 at 7:45 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Thomas, On 30.07.2014 10:07, Thomas Abraham wrote: Changes since v8: - Fixes suggested by Tomasz Figa. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html 3. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html I think we are at final stage of works on this series. Thanks for your cooperation. After addressing remaining minor comments from this thread, feel free to add: Reviewed-by: Tomasz Figa t.f...@samsung.com You had acked the cpufreq related changes in v7 of this series. But there were some changes in v8 and so I have not included your Ack for v8 and v9. Could you please have one more look at the patches 4/6 [1] and 5/6 [2] of this v9 series and let me know if it looks okay. [1] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34865.html [2] http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34864.html Thanks, Thomas. Hi Tomasz, Thanks for your review of this series. Your review comments has helped to make this series better. Regards, Thomas. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-pm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v9 6/6] clk: samsung: remove unused clock aliases and update clock flags
On Fri, Aug 1, 2014 at 12:16 AM, Tomasz Figa tomasz.f...@gmail.com wrote: On 31.07.2014 20:41, Thomas Abraham wrote: On Fri, Aug 1, 2014 at 12:05 AM, Tomasz Figa tomasz.f...@gmail.com wrote: On 31.07.2014 20:24, Thomas Abraham wrote: Hi Tomasz, On Thu, Jul 31, 2014 at 7:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote: On 30.07.2014 10:07, Thomas Abraham wrote: With some of the Exynos SoCs switched over to use the generic CPUfreq drivers, the unused clock aliases can be removed. In addition to this, the individual clock blocks which are now encapsulated with the consolidate CPU clock type can now be marked with read-only flags. [snip] @@ -1500,6 +1499,7 @@ static void __init exynos4_clk_init(struct device_node *np, exynos4_soc == EXYNOS4210 ? Exynos4210 : Exynos4x12, _get_rate(sclk_apll), _get_rate(sclk_mpll), _get_rate(sclk_epll), _get_rate(sclk_vpll), + exynos4_soc == EXYNOS4210 ? _get_rate(armclk) : _get_rate(div_core2)); I believe div_core2 should work fine here for all SoCs without the need for this if. The following patch is a pre-requisite for this patch. http://www.spinics.net/lists/arm-kernel/msg351540.html The rate can be obtained from div_core2 as well but with the cpu clock now registered, the rate can be obtained from the cpu clock instance instead of the div_core2 divider. And when Exynos4412 also add cpu clock instance, the 'if' above will be removed. } diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e19e365..1d958f1 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c [snip] @@ -848,6 +851,6 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_of_add_provider(np, ctx); pr_info(Exynos5250: clock setup completed, armclk=%ld\n, - _get_rate(div_arm2)); + _get_rate(armclk)); Similarly here, no need for this change. Same here. Instead of getting the rate from div_core2 divider block, the cpu clock instance is used to find the rate. I would prefer to use cpu clock here. Is there any reason to prefer div_core2 over the cpu clock instance? Well, the reason is simple: if you don't need to change something (i.e. the change doesn't have any advantages), don't change it. The advantage with using cpu clock would be that get_rate can obtain the cached rate whereas when reading div_core2 rate, the clock tree will have to be traversed to determine the rate. This is just one time printk at initialization, so still no real benefits. :) Well anyway, if you really don't want to undo this change, then I guess I can live with it. Thanks Tomasz. Probably, I would just use cpu clock for now. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] clk: exynos4: remove duplicate div_core2 divider clock instantiation
The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
This patch is based on for-next branch of Samsung clock tree.
drivers/clk/samsung/clk-exynos4.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ac163d7..8617f49 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -719,7 +719,7 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
+ DIV(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3),
DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
@@ -769,7 +769,6 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
@@ -1486,7 +1485,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_soc == EXYNOS4210 ? Exynos4210 : Exynos4x12,
_get_rate(sclk_apll), _get_rate(sclk_mpll),
_get_rate(sclk_epll), _get_rate(sclk_vpll),
- _get_rate(arm_clk));
+ _get_rate(div_core2));
}
--
1.7.9.5
--
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[PATCH v9 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v8: - Fixes suggested by Tomasz Figa. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html 3. clk: exynos4: remove duplicate div_core2 divider clock instantiation - http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg34859.html Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |4 + arch/arm/boot/dts/exynos4210-trats.dts |4 + arch/arm/boot/dts/exynos4210-universal_c210.dts |4 + arch/arm/boot/dts/exynos4210.dtsi | 14 +- arch/arm/boot/dts/exynos5250-arndale.dts|4 + arch/arm/boot/dts/exynos5250-smdk5250.dts |4 + arch/arm/boot/dts/exynos5250-snow.dts |4 + arch/arm/boot/dts/exynos5250.dtsi | 25 +- arch/arm/boot/dts/exynos5420.dtsi | 38 +++ arch/arm/mach-exynos/exynos.c | 24 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 335 +++ drivers/clk/samsung/clk-cpu.h | 91 ++ drivers/clk/samsung/clk-exynos4.c | 63 +++-- drivers/clk/samsung/clk-exynos5250.c| 44 ++- drivers/clk/samsung/clk-exynos5420.c| 72 - drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 - drivers/cpufreq/exynos5250-cpufreq.c| 210 -- include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 22 files changed, 690 insertions(+), 463 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c create mode 100644 drivers/clk/samsung/clk-cpu.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v9 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210,
Exynos5250 and Exynos5420.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 15 +++
drivers/clk/samsung/clk-exynos5250.c | 25 ++
drivers/clk/samsung/clk-exynos5420.c | 45
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 ++
5 files changed, 88 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 8617f49..101f549 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS0x4200
@@ -1355,6 +1356,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
{
unsigned int tmp;
@@ -1458,6 +1469,10 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..e19e365 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst =
{
+ { 170, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 160, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 150, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 140, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 130, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 120, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 110, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 100, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 90, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 80, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 70, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 60, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 50, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 40, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 30, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 20, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5250_armclk_d, ARRAY_SIZE
[PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 +++
arch/arm/boot/dts/exynos4210-trats.dts |4 +++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250-snow.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
+
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
[PATCH v9 1/6] clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335 +
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..8909c93 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) mux_pos) MUX_MASK) == mux_value)
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: re-parenting mux timed-out\n, __func__);
+}
+
+/* common round rate callback useable for all types of CPU clocks
[PATCH v9 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Cc: Viresh Kumar viresh.ku...@linaro.org
Cc: Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 7364a53..f81fc3e 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..fac36ef 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 61a5431..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq-cmu_regs + EXYNOS4_CLKDIV_CPU);
-
- do {
- tmp = __raw_readl(cpufreq-cmu_regs + EXYNOS4_CLKDIV_STATCPU);
- } while
[PATCH v9 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa t.f...@samsung.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 493dbc2..e61bb36 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -281,6 +281,28 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5250, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos4210, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+ struct device_node *root = of_find_node_by_path(/);
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_cpufreq_matches, root);
+ if (!match) {
+ platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ return;
+ }
+
+ platform_device_register_simple(match-data, -1, NULL, 0);
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -320,7 +342,7 @@ static void __init exynos_dt_machine_init(void)
of_machine_is_compatible(samsung,exynos5250))
platform_device_register(exynos_cpuidle);
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.7.9.5
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[PATCH v9 6/6] clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 48 +-
drivers/clk/samsung/clk-exynos5250.c | 19 --
drivers/clk/samsung/clk-exynos5420.c | 27 ---
3 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 101f549..04619a1 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(0, mout_hpm, mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
- DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
- DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3),
- DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
- DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem0, div_core2, DIV_CPU0, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem1, div_core2, DIV_CPU0, 8, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_periph, div_core2, DIV_CPU0, 12, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_atb, mout_core, DIV_CPU0, 16, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_ARM_CLK, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_copy, mout_hpm, DIV_CPU1, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_hpm, div_copy, DIV_CPU1, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -770,7 +780,8 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1187,17 +1198,10 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
0),
};
-static struct samsung_clock_alias exynos4_aliases[] __initdata = {
+static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
-};
-
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
- ALIAS(CLK_SCLK_MPLL, NULL, mout_mpll),
-};
-
-static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, mout_mpll),
};
@@ -1464,8 +1468,6 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
ARRAY_SIZE
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Wed, Jul 30, 2014 at 4:58 PM, Andreas Färber afaer...@suse.de wrote:
Am 30.07.2014 10:07, schrieb Thomas Abraham:
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Cc: Doug Anderson diand...@chromium.org
Cc: Javier Martinez Canillas javier.marti...@collabora.co.uk
Cc: Andreas Faerber afaer...@suse.de
Cc: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |4 +++
arch/arm/boot/dts/exynos4210-trats.dts |4 +++
arch/arm/boot/dts/exynos4210-universal_c210.dts |4 +++
arch/arm/boot/dts/exynos4210.dtsi | 14 -
arch/arm/boot/dts/exynos5250-arndale.dts|4 +++
arch/arm/boot/dts/exynos5250-smdk5250.dts |4 +++
arch/arm/boot/dts/exynos5250-snow.dts |4 +++
arch/arm/boot/dts/exynos5250.dtsi | 25 ++-
arch/arm/boot/dts/exynos5420.dtsi | 38
+++
9 files changed, 99 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..887dded 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -334,3 +334,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck1_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..66119dd 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -446,3 +446,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = varm_breg;
+};
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..bf0a39c 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -492,3 +492,7 @@
mdma1 {
reg = 0x1284 0x1000;
};
+
+cpu0 {
+ cpu0-supply = vdd_arm_reg;
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..69bac07 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,10 +35,22 @@
#address-cells = 1;
#size-cells = 0;
- cpu@900 {
+ cpu0: cpu@900 {
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 16;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
Nit: Here you left-align the columns ...
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Thu, Jul 31, 2014 at 9:23 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
In your calculation, only the PLL lock time is being considered. But
the 140us latency is for the whole clk_set_rate() call.
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
+ 100 987500
+90 962500
+80 937500
+70 912500
Re: [PATCH v9 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
On Thu, Jul 31, 2014 at 9:38 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 9:06 PM, Thomas Abraham ta.oma...@gmail.com wrote:
On Thu, Jul 31, 2014 at 9:23 AM, Doug Anderson diand...@chromium.org wrote:
Thomas,
On Wed, Jul 30, 2014 at 8:21 PM, Thomas Abraham ta.oma...@gmail.com wrote:
Hi Doug,
On Thu, Jul 31, 2014 at 6:07 AM, Doug Anderson diand...@chromium.org
wrote:
Thomas,
On Wed, Jul 30, 2014 at 1:07 AM, Thomas Abraham thomas...@samsung.com
wrote:
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..3b12a97 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -575,3 +575,7 @@
usb-phy = usb2_phy;
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..f07e834 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -414,3 +414,7 @@
};
};
};
+
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts
b/arch/arm/boot/dts/exynos5250-snow.dts
index f2b8c41..91acca7 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -509,4 +509,8 @@
};
};
+cpu0 {
+ cpu0-supply = buck2_reg;
+};
+
#include cros-ec-keyboard.dtsi
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..97b282c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -58,11 +58,34 @@
#address-cells = 1;
#size-cells = 0;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 14;
Where did the 14 number come from? My old calculations show that
with lock time of 270 ad P up to 6 we were at 67.5us lock time.
I measured the time taken by clk_set_rate call in the cpufreq driver
using do_gettimeofday(). The time taken to change the clock speed was
between 87us to 134us for Exynos5420. So I just took the worst case
time of 140us. Also, the time taken to change the CPU clock speed
includes the settling time for changes to dividers and mux clock
blocks.
Interesting. I wonder why the difference between my earlier
calculations. It seems just about double. :-/
In your calculation, only the PLL lock time is being considered. But
the 140us latency is for the whole clk_set_rate() call.
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+90 105
+80 1025000
+70 1012500
+60 100
+50 975000
+40 95
+30 937500
+20 925000
+ ;
};
cpu@1 {
device_type = cpu;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..3154b4c 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -59,8 +59,26 @@
device_type = cpu;
compatible = arm,cortex-a15;
reg = 0x0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu-cluster.0;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 14;
+
+ operating-points =
+ 180 125
+ 170 1212500
+ 160 1175000
+ 150 1137500
+ 140 1112500
+ 130 1062500
+ 120 1037500
+ 110 1012500
Re: [PATCH v8 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
Hi Tomasz,
On Tue, Jul 29, 2014 at 3:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
Just few minor comments for things I probably missed before.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock
exynos4x12_plls[nr_plls] __initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
I have noticed that the old driver does not have this operating point.
While it is probably OK to add this one and even few more for all
possible APLL settings, I am interested in how you obtained the values
for DIV0 and DIV1 registers for this configuration.
I found these values from an old internal repo. So far no trouble seen
with these values in all the testing.
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
[snip]
diff --git a/include/dt-bindings/clock/exynos5250.h
b/include/dt-bindings/clock/exynos5250.h
index 4273891..855d809 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -21,6 +21,7 @@
#define CLK_FOUT_CPLL6
#define CLK_FOUT_EPLL7
#define CLK_FOUT_VPLL8
+#define CLK_ARM_CLK 12
Why 12 not 9?
Exynos4 uses 12 and so just wanted to keep it same for Exynos5250 as well.
Thanks,
Thomas.
Best regards,
Tomasz
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Re: [PATCH v8 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hi Tomasz,
On Tue, Jul 29, 2014 at 4:01 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
Other than the same question about 400 MHz OPP for Exynos4210, I have
also few more inline.
On 29.07.2014 07:28, Thomas Abraham wrote:
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6
arch/arm/boot/dts/exynos4210-trats.dts |6
arch/arm/boot/dts/exynos4210-universal_c210.dts |6
arch/arm/boot/dts/exynos4210.dtsi | 12 +++
arch/arm/boot/dts/exynos5250-arndale.dts|6
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6
arch/arm/boot/dts/exynos5250-smdk5250.dts |6
arch/arm/boot/dts/exynos5250.dtsi | 23 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts |6
There are more Exynos5420-based boards supported in mainline. If you do
not have necessary data and/or hardware to fully enable the new driver
on them, you should add responsible people on Cc list, so at least they
know they have one more item on their TODO list. Added them for you.
Thanks!. Will do that next time.
arch/arm/boot/dts/exynos5420.dtsi | 38
+++
10 files changed, 115 insertions(+)
[snip]
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 492e1ef..876247a 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -63,6 +63,29 @@
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 20;
Where does this latency value comes from? How did you calculate it?
For example, on Exynos4210, for all operating points added by your
patches, the highest PLL locking latency will be 60uS, because the
highest PDIV value would be 6 and PLL lock time is PDIV*240 ticks of 24
MHz reference clock.
Since the CPU clock is a composite clock with dividers and muxes, the
latency includes the settling time for these clock blocks as well. I
have not made any measurements of the clock transition latency.
+
+ operating-points =
+ 170 130
+ 160 125
[snip]
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 6052aa9..084e587 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -24,6 +24,12 @@
bootargs = console=ttySAC2,115200 init=/linuxrc;
};
+ cpus {
Is there no regulator for cpu0?
This was a mistake. I did not intend to add regulator for cpu4 as well
but somehow I missed it. I will remove it in the next version.
+ cpu@4 {
+ cpu0-supply = buck6_reg;
+ };
+ };
+
fixed-rate-clocks {
oscclk {
compatible = samsung,exynos5420-oscclk;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi
b/arch/arm/boot/dts/exynos5420.dtsi
index cb2b70e..1116d55 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
[snip]
cpu1: cpu@1 {
@@ -69,6 +87,7 @@
reg = 0x1;
clock-frequency = 18;
cci-control-port = cci_control1;
+ clock-latency = 20;
Do you need to specify this property for every CPU or rather just for
those which have operating points specified?
The big.little cpufreq driver expects each CPU to have the clock
latency specified.
Thanks,
Thomas.
Best regards,
Tomasz
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Re: [PATCH v8 6/6] clk: samsung: remove unused clock aliases and update clock flags
Hi Tomasz,
On Tue, Jul 29, 2014 at 4:14 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
You can find few comments inline.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
^^^
Keep in mind that following clocks are common for Exynos4210 and
Exynos4x12. Have you tested this series on a board based on Exynos4212
or 4412 to verify that it does not break the legacy driver? (I would
test it myself, but I am on holidays at the moment.)
Thanks for taking time to have a look at this series. I have tested
this series with the old cpufreq driver for Exynos4412 on an
Origen4412 board and it works fine. These divider clocks are not
directly used or referenced by the legacy cpufreq driver. So I marked
them as read-only here.
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
[snip]
@@ -1501,7 +1507,7 @@ static void __init exynos4_clk_init(struct device_node
*np,
exynos4_soc == EXYNOS4210 ? Exynos4210 : Exynos4x12,
_get_rate(sclk_apll), _get_rate(sclk_mpll),
_get_rate(sclk_epll), _get_rate(sclk_vpll),
- _get_rate(arm_clk));
+ _get_rate(armclk));
This will not work on Exynos4412, because there is no armclk added for
this SoC. My suggestion is to simply keep name of the clock as is, move
current arm_clk divider to Exynos4x12-specific clocks and register
Exynos4210 CPU clock as arm_clk.
Ok. Will do this in the next version.
Thanks,
Thomas.
Best regards,
Tomasz
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Re: [PATCH v8 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
On Tue, Jul 29, 2014 at 5:34 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 29.07.2014 13:46, Thomas Abraham wrote:
Hi Tomasz,
On Tue, Jul 29, 2014 at 3:43 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
Just few minor comments for things I probably missed before.
On 29.07.2014 07:28, Thomas Abraham wrote:
[snip]
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock
exynos4x12_plls[nr_plls] __initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst =
{
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
I have noticed that the old driver does not have this operating point.
While it is probably OK to add this one and even few more for all
possible APLL settings, I am interested in how you obtained the values
for DIV0 and DIV1 registers for this configuration.
I found these values from an old internal repo. So far no trouble seen
with these values in all the testing.
OK.
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
[snip]
diff --git a/include/dt-bindings/clock/exynos5250.h
b/include/dt-bindings/clock/exynos5250.h
index 4273891..855d809 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -21,6 +21,7 @@
#define CLK_FOUT_CPLL6
#define CLK_FOUT_EPLL7
#define CLK_FOUT_VPLL8
+#define CLK_ARM_CLK 12
Why 12 not 9?
Exynos4 uses 12 and so just wanted to keep it same for Exynos5250 as well.
There is no need to align those numbers between different bindings,
because preprocessor macros are used anyway and leaving holes between
clocks only makes the namespace harder to maintain.
Ok. I will fix this.
Thanks,
Thomas.
Best regards,
Tomasz
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Re: [PATCH v8 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hi Andreas,
On Tue, Jul 29, 2014 at 5:38 PM, Andreas Färber afaer...@suse.de wrote:
Hi Thomas,
Am 29.07.2014 07:28, schrieb Thomas Abraham:
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
pinctrl@1140 {
/*
* Disabled pullups since external part has its own pullups and
I've been instructed to dismantle this .dtsi file, so please place this
into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
doesn't use the max77686 but an s5m6787 PMIC.
Ok, I will move this to exynos5250-snow.dts.
How do I find out which -supply to specify here for Spring?
This information can be found in the Spring board schematic.
Also, wouldn't it make sense to assign a cpu0 label in exynos.dtsi
to override it via cpu0 { ... };?
Sorry, I did not understand the question.
Thanks,
Thomas.
Regards,
Andreas
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Re: [PATCH v8 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
Hi Andreas,
On Tue, Jul 29, 2014 at 6:12 PM, Andreas Färber afaer...@suse.de wrote:
Hi Thomas,
Am 29.07.2014 14:35, schrieb Thomas Abraham:
On Tue, Jul 29, 2014 at 5:38 PM, Andreas Färber afaer...@suse.de wrote:
Am 29.07.2014 07:28, schrieb Thomas Abraham:
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
pinctrl@1140 {
/*
* Disabled pullups since external part has its own pullups
and
I've been instructed to dismantle this .dtsi file, so please place this
into exynos5250-snow.dts. It's probably wrong here anyway, since Spring
doesn't use the max77686 but an s5m6787 PMIC.
Ok, I will move this to exynos5250-snow.dts.
How do I find out which -supply to specify here for Spring?
This information can be found in the Spring board schematic.
Are those available publicly somewhere? I guess not...
I am not sure if it is available publicly. Doug (Cc'ed on this email)
might have it.
Also, wouldn't it make sense to assign a cpu0 label in exynos.dtsi
to override it via cpu0 { ... };?
Sorry, I did not understand the question.
Instead of adding
cpus { cpu@0 { ... }; };
to the board's / node, I am suggesting you do in the SoC's .dtsi:
- cpu@0 {
+ cpu0: cpu@0 {
and then in the board's file after / { ... }; add the following:
cpu0 {
cpu0-supply = buck2_reg;
};
This is the new preferred way to override or extend inherited nodes, I
am told. (cpu0 should be inserted in alphabetical order then.)
Okay, thanks for the clarification. I will update as per the preferred way.
Thanks,
Thomas.
Cheers,
Andreas
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[PATCH] ARM: dts: smdk5250: Specify MAX77686 pmic interrupt
The IRQB interrupt pin of MAX77686 PMIC is connected to GPX3[2] pin of
Exynos5250 on the Exynos5250 SMDK board. Specify this connection using
interrupts property for the max77686 pmic node.
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 695f5ad..cf38808 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -50,6 +50,8 @@
max77686@09 {
compatible = maxim,max77686;
reg = 0x09;
+ interrupt-parent = gpx3;
+ interrupts = 2 0;
voltage-regulators {
ldo1_reg: LDO1 {
--
1.7.9.5
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[PATCH v8 2/6] clk: samsung: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210,
Exynos5250 and Exynos5420.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 15 +++
drivers/clk/samsung/clk-exynos5250.c | 25 ++
drivers/clk/samsung/clk-exynos5420.c | 45
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 ++
5 files changed, 88 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index ac163d7..5388806 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
/* Exynos4 clock controller register offsets */
#define SRC_LEFTBUS0x4200
@@ -1356,6 +1357,16 @@ static struct samsung_pll_clock exynos4x12_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
+ { 120, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 5), },
+ { 100, E4210_CPU_DIV0(7, 1, 4, 3, 7, 3), E4210_CPU_DIV1(0, 4), },
+ { 80, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 50, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 40, E4210_CPU_DIV0(7, 1, 3, 3, 7, 3), E4210_CPU_DIV1(0, 3), },
+ { 20, E4210_CPU_DIV0(0, 1, 1, 1, 3, 1), E4210_CPU_DIV1(0, 3), },
+ { 0 },
+};
+
static void __init exynos4_core_down_clock(enum exynos4_soc soc)
{
unsigned int tmp;
@@ -1459,6 +1470,10 @@ static void __init exynos4_clk_init(struct device_node
*np,
samsung_clk_register_fixed_factor(ctx,
exynos4210_fixed_factor_clks,
ARRAY_SIZE(exynos4210_fixed_factor_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], 0x14200,
+ e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-exynos5250.c
index 70ec3d2..e19e365 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -19,6 +19,7 @@
#include linux/syscore_ops.h
#include clk.h
+#include clk-cpu.h
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -748,6 +749,26 @@ static struct samsung_pll_clock exynos5250_plls[nr_plls]
__initdata = {
VPLL_LOCK, VPLL_CON0, NULL),
};
+static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst =
{
+ { 170, E5250_CPU_DIV0(5, 3, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 160, E5250_CPU_DIV0(4, 1, 7, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 150, E5250_CPU_DIV0(4, 1, 7, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 140, E5250_CPU_DIV0(4, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 130, E5250_CPU_DIV0(3, 1, 6, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 120, E5250_CPU_DIV0(3, 1, 5, 7, 7, 2), E5250_CPU_DIV1(2, 0), },
+ { 110, E5250_CPU_DIV0(3, 1, 5, 7, 7, 3), E5250_CPU_DIV1(2, 0), },
+ { 100, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 90, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 80, E5250_CPU_DIV0(2, 1, 4, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 70, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 60, E5250_CPU_DIV0(1, 1, 3, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 50, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 40, E5250_CPU_DIV0(1, 1, 2, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 30, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 20, E5250_CPU_DIV0(1, 1, 1, 7, 7, 1), E5250_CPU_DIV1(2, 0), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = samsung,clock-xxti, .data = (void *)0, },
{ },
@@ -797,6 +818,10 @@ static void __init exynos5250_clk_init(struct device_node
*np)
ARRAY_SIZE(exynos5250_div_clks));
samsung_clk_register_gate(ctx, exynos5250_gate_clks,
ARRAY_SIZE(exynos5250_gate_clks));
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, armclk,
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5250_armclk_d, ARRAY_SIZE
[PATCH v8 1/6] clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 335 +
drivers/clk/samsung/clk-cpu.h | 91 +++
3 files changed, 427 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
create mode 100644 drivers/clk/samsung/clk-cpu.h
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 6fb4bc6..8909c93 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..009a21b
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility function to register CPU clock for Samsung
+ * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
+ * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
+ * blocks which includes mux and divider blocks. There are a number of other
+ * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
+ * clock for CPU domain. The rates of these auxiliary clocks are related to the
+ * CPU clock rate and this relation is usually specified in the hardware manual
+ * of the SoC or supplied after the SoC characterization.
+ *
+ * The below implementation of the CPU clock allows the rate changes of the CPU
+ * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * domain. The platform clock driver provides a clock register configuration
+ * for each configurable rate which is then used to program the clock hardware
+ * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * clocks.
+ *
+ * On a rate change request for the CPU clock, the rate change is propagated
+ * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
+ * alternate clock source. If required, the alternate clock source is divided
+ * down in order to keep the output clock rate within the previous OPP limits.
+*/
+
+#include linux/errno.h
+#include clk-cpu.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK(0x7 4)
+#define E4210_DIV1_COPY_MASK (0x7 0)
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+/*
+ * Helper function to wait until divider(s) have stabilized after the divider
+ * value has changed.
+ */
+static void wait_until_divider_stable(void __iomem *div_reg, unsigned long
mask)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (!(readl(div_reg) mask))
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: timeout in divider stablization\n, __func__);
+}
+
+/*
+ * Helper function to wait until mux has stabilized after the mux selection
+ * value was changed.
+ */
+static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
+ unsigned long mux_value)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+
+ do {
+ if (((readl(mux_reg) mux_pos) MUX_MASK) == mux_value)
+ return;
+ } while (time_before(jiffies, timeout));
+
+ pr_err(%s: re-parenting mux timed-out\n, __func__);
+}
+
+/* common round rate callback useable for all types of CPU clocks */
+static long
[PATCH v8 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v7: - Fixes suggested by Tomasz Figa. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enables cpufreq support for Exynos5420 using arm_big_little cpufreq driver. This patch series is dependent on two other patches 1. ARM: dts: add CPU nodes for Exynos4 SoCs - https://lkml.org/lkml/2014/7/21/315 2. ARM: dts: smdk5250: Specify MAX77686 pmic interrupt - http://www.spinics.net/lists/arm-kernel/msg351134.html Since there are significant changes since v7, the Tested-by and Acked-by tags for all the patches in this series have been dropped. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: add cpu clock configuration data and instantiate cpu clock ARM: dts: Exynos: add CPU OPP and regulator supply property ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support clk: samsung: remove unused clock aliases and update clock flags arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 12 + arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 ++ arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 38 +++ arch/arm/mach-exynos/exynos.c | 24 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 335 +++ drivers/clk/samsung/clk-cpu.h | 91 ++ drivers/clk/samsung/clk-exynos4.c | 59 ++-- drivers/clk/samsung/clk-exynos5250.c| 44 ++- drivers/clk/samsung/clk-exynos5420.c| 72 - drivers/cpufreq/Kconfig.arm | 22 -- drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 - drivers/cpufreq/exynos5250-cpufreq.c| 210 -- include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 707 insertions(+), 456 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c create mode 100644 drivers/clk/samsung/clk-cpu.h delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 3/6] ARM: dts: Exynos: add CPU OPP and regulator supply property
For Exynos 4210/5250/5420 based platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific cpufreq driver
to using generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6
arch/arm/boot/dts/exynos4210-trats.dts |6
arch/arm/boot/dts/exynos4210-universal_c210.dts |6
arch/arm/boot/dts/exynos4210.dtsi | 12 +++
arch/arm/boot/dts/exynos5250-arndale.dts|6
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6
arch/arm/boot/dts/exynos5250-smdk5250.dts |6
arch/arm/boot/dts/exynos5250.dtsi | 23 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts |6
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
10 files changed, 115 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..49a97fc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -33,6 +33,12 @@
bootargs =root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck1_reg;
+ };
+ };
+
regulators {
compatible = simple-bus;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..fe32b6a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,6 +30,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5
rootwait earlyprintk panic=5;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = varm_breg;
+ };
+ };
+
regulators {
compatible = simple-bus;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..8ab12d6 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw
rootwait earlyprintk panic=5 maxcpus=1;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = vdd_arm_reg;
+ };
+ };
+
sysram@0202 {
smp-sysram@0 {
status = disabled;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63..cd68030 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -39,6 +39,18 @@
device_type = cpu;
compatible = arm,cortex-a9;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+ clock-latency = 20;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
};
cpu@901 {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..d9b803b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -26,6 +26,12 @@
bootargs = console=ttySAC2,115200;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
rtc@101E {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
pinctrl@1140 {
/*
* Disabled pullups since external part has its own pullups and
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index b4b35ad..cf38808 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -27,6 +27,12 @@
bootargs = root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc
[PATCH v8 4/6] ARM: Exynos: switch to using generic cpufreq driver for Exynos4210/5250/5420
The new CPU clock type allows the use of generic CPUfreq drivers. So for
Exynos4210/5250, switch to using generic cpufreq driver. For Exynos5420,
which did not have CPUfreq driver support, enable the use of generic
CPUfreq driver.
Suggested-by: Tomasz Figa t.f...@samsung.com
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index df41bd1..4d7be5e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -279,6 +279,28 @@ static void __init exynos_init_irq(void)
exynos_map_pmu();
}
+static const struct of_device_id exynos_cpufreq_matches[] = {
+ { .compatible = samsung,exynos5420, .data = arm-bL-cpufreq-dt },
+ { .compatible = samsung,exynos5250, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos4210, .data = cpufreq-cpu0 },
+ { .compatible = samsung,exynos5440, .data = exynos5440-cpufreq },
+ { /* sentinel */ }
+};
+
+static void __init exynos_cpufreq_init(void)
+{
+ struct device_node *root = of_find_node_by_path(/);
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos_cpufreq_matches, root);
+ if (!match) {
+ platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ return;
+ }
+
+ platform_device_register_simple(match-data, -1, NULL, 0);
+}
+
static void __init exynos_dt_machine_init(void)
{
struct device_node *i2c_np;
@@ -318,7 +340,7 @@ static void __init exynos_dt_machine_init(void)
of_machine_is_compatible(samsung,exynos5250))
platform_device_register(exynos_cpuidle);
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ exynos_cpufreq_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
--
1.7.9.5
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[PATCH v8 6/6] clk: samsung: remove unused clock aliases and update clock flags
With some of the Exynos SoCs switched over to use the generic CPUfreq drivers,
the unused clock aliases can be removed. In addition to this, the individual
clock blocks which are now encapsulated with the consolidate CPU clock type
can now be marked with read-only flags.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c| 44 +++---
drivers/clk/samsung/clk-exynos5250.c | 19 ---
drivers/clk/samsung/clk-exynos5420.c | 27 ++---
3 files changed, 54 insertions(+), 36 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 5388806..b482e39 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -578,7 +578,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(0, mout_hpm, mout_core_p4210, SRC_CPU, 20, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
@@ -714,15 +715,24 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_clkout_rightbus, mout_clkout_rightbus,
CLKOUT_CMU_RIGHTBUS, 8, 6),
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_corem0, div_core2, DIV_CPU0, 4, 3),
- DIV(0, div_corem1, div_core2, DIV_CPU0, 8, 3),
- DIV(0, div_periph, div_core2, DIV_CPU0, 12, 3),
- DIV(0, div_atb, mout_core, DIV_CPU0, 16, 3),
- DIV(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
- DIV(0, div_copy, mout_hpm, DIV_CPU1, 0, 3),
- DIV(0, div_hpm, div_copy, DIV_CPU1, 4, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem0, div_core2, DIV_CPU0, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_corem1, div_core2, DIV_CPU0, 8, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_periph, div_core2, DIV_CPU0, 12, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_atb, mout_core, DIV_CPU0, 16, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_pclk_dbg, div_atb, DIV_CPU0, 20, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_copy, mout_hpm, DIV_CPU1, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_hpm, div_copy, DIV_CPU1, 4, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_clkout_cpu, mout_clkout_cpu, CLKOUT_CMU_CPU, 8, 6),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
@@ -770,8 +780,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1194,10 +1206,6 @@ static struct samsung_clock_alias exynos4_aliases[]
__initdata = {
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
};
-static struct samsung_clock_alias exynos4210_aliases[] __initdata = {
- ALIAS(CLK_SCLK_MPLL, NULL, mout_mpll),
-};
-
static struct samsung_clock_alias exynos4x12_aliases[] __initdata = {
ALIAS(CLK_MOUT_MPLL_USER_C, NULL, mout_mpll),
};
@@ -1465,8 +1473,6 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_div_clks));
samsung_clk_register_gate(ctx, exynos4210_gate_clks,
ARRAY_SIZE(exynos4210_gate_clks));
- samsung_clk_register_alias(ctx
[PATCH v8 5/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Cc: Viresh Kumar viresh.ku...@linaro.org
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 7364a53..f81fc3e 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..fac36ef 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 61a5431..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq-cmu_regs + EXYNOS4_CLKDIV_CPU);
-
- do {
- tmp = __raw_readl(cpufreq-cmu_regs + EXYNOS4_CLKDIV_STATCPU);
- } while (tmp 0x111);
-
- /* Change Divider - CPU1
Re: [PATCH v7 1/6] clk: samsung: add infrastructure to register cpu clocks
Hi Tomasz,
Thanks for your review comments. I have made most of the changes you
have suggested. The suggested modifications which I did not include is
marked below.
On Sat, Jul 19, 2014 at 6:25 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
Please see my comments inline.
On 14.07.2014 15:38, Thomas Abraham wrote:
[snip]
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..0d62968
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the CPU clocks
+ * for Samsung platforms.
I'd expect few words here or in separate comment on how the code works,
i.e. assumptions made, most important procedures, etc. This is a complex
piece of code for quite complex hardware, so proper documentation is
essential.
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define E4210_SRC_CPU0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU0 0x400
+#define E4210_DIV_STAT_CPU1 0x404
+
+#define MAX_DIV 8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK ((0x7 4) | (0x7 0))
This mask contains two fields, doesn't it? I'd say it would be better
for readability if you split it.
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK (DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0) \
+ (((apll) 24) | ((pclk_dbg) 20) | ((atb) 16) | \
+ ((periph) 12) | ((corem1) 8) | ((corem0) 4))
+#define E4210_CPU_DIV1(hpm, copy)\
+ (((hpm) 4) | ((copy) 0))
+
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud)
\
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+ (periph 12) | (acp 8) | (cpud 4)))
+#define E5250_CPU_DIV1(hpm, copy)\
+ (((hpm) 4) | (copy))
+
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud)\
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+ (cpud 4)))
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ (((kpll 24) | (pclk 20) | (aclk 4)))
Again, used macro arguments should always be surrounded with parentheses.
+
+enum cpuclk_type {
+ EXYNOS4210,
+ EXYNOS5250,
+ EXYNOS5420,
+};
+
+/**
+ * struct exynos4210_cpuclk_data: config data to setup cpu clocks.
It seems like this could be used for all Exynos SoCs, so probably should
be called exynos_cpuclk_data.
+ * @prate: frequency of the primary parent clock (in KHz).
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for dividers in the
CPU
+ * clock domain. The parent frequency at which these divider values are
valid is
+ * specified in @prate. The @prate is the frequency of the primary parent
clock.
+ * For CPU clock domains that do not have a DIV1 register, the @div1 member
+ * is optional.
+ */
+struct exynos4210_cpuclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw: handle between CCF and CPU clock.
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset: offset from the ctrl_base address where the CPU clock div/mux
+ * registers can be accessed.
+ * @lock: cpu clock domain register access lock.
+ * @type: type of the CPU clock.
+ * @data: optional data which the actual instantiation of this clock
+ * can use.
+ * @clk_nb: clock notifier registered for changes in clock speed of the
+ * primary parent clock.
+ * @pre_rate_cb: callback function to handle PRE_RATE_CHANGE notification
+ * of the primary parent clock.
+ * @post_rate_cb: callback function to handle POST_RATE_CHANGE notification
+ * of the primary parent clock.
+ *
+ * This structure holds information required for programming the cpu clock
for
+ * various clock speeds.
nit: s/cpu/CPU
Re: [PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
Hi Tomasz,
On Sat, Jul 19, 2014 at 6:48 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
Hi Thomas,
Please see my comments inline.
On 14.07.2014 15:38, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
For Exynos 4210/5250/5420 based platforms, add CPU nodes, operating points
and
cpu clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq drivers.
[snip]
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..c3a73bf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,33 @@
pinctrl2 = pinctrl_2;
};
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+ cpu@0 {
nit: Missing blank line after last property.
The cluster ID field of MPIDR on Exynos4210 is 0x9 not zero, which means
that this should be cpu@900.
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
reg = 0x900;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
+ };
+
+ cpu@1 {
cpu@901
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
reg = 0x901;
+ };
In general this wouldn't have even booted, because there were several
places where code relied on CPUs being 0, 1, 2... However I have sent
necessary fixes and they should hit linux-next in few days.
+ };
+
sysram@0202 {
compatible = mmio-sram;
reg = 0x0202 0x2;
[snip]
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..66b0f98 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -63,6 +63,29 @@
compatible = arm,cortex-a15;
reg = 0;
clock-frequency = 17;
+
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+
+ operating-points =
+ 170 130
+ 160 125
+ 150 1225000
+ 140 120
+ 130 115
+ 120 1125000
+ 110 110
+ 100 1075000
+ 90 105
+ 80 1025000
+ 70 1012500
+ 60 100
+ 50 975000
+ 40 95
+ 30 937500
+ 20 925000
+ ;
+ clock-latency = 20;
I don't see this property specified for Exynos4210. Have you missed it
there?
Okay, I have specified this for Exynos4210 as well.
Thanks,
Thomas.
Best regards,
Tomasz
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Re: [PATCH v7 5/6] ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250/5420
On Sat, Jul 19, 2014 at 6:57 PM, Tomasz Figa tomasz.f...@gmail.com wrote:
On 14.07.2014 15:38, Thomas Abraham wrote:
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for exynos cpufreq driver and add
the
platform device for generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2a43a17..5028b35 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -183,7 +183,20 @@ void __init exynos_cpuidle_init(void)
void __init exynos_cpufreq_init(void)
{
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ char *dev_name;
+
+ if (of_machine_is_compatible(samsung,exynos5440))
+ return;
The original code registers the device unconditionally. Why Exynos5440
is excluded now?
+ if (of_machine_is_compatible(samsung,exynos5420))
+ dev_name = arm-bL-cpufreq-dt;
+ else
+ if (of_machine_is_compatible(samsung,exynos4412) ||
+ of_machine_is_compatible(samsung,exynos4212))
+ dev_name = exynos-cpufreq;
+ else
+ dev_name = cpufreq-cpu0;
+
+ platform_device_register_simple(dev_name, -1, NULL, 0);
}
How about rewriting this to:
static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = samsung,exynos5420,
.data = arm-bL-cpufreq-dt },
{ .compatible = samsung,exynos5250,
.data = cpufreq-cpu0 },
{ .compatible = samsung,exynos4210,
.data = cpufreq-cpu0 },
{ /* sentinel */ }
};
void __init exynos_cpufreq_init(void)
{
struct device_node *root = of_find_node_by_path(/);
const struct of_device_id *match;
match = of_match_node(exynos_cpufreq_matches, root);
if (!match) {
platform_device_register_simple(exynos-cpufreq, -1,
NULL, 0);
return;
}
platform_device_register_simple(match-data, -1, NULL, 0);
}
This way it is much more readable and original behavior is preserved for
any SoCs not supported by new drivers.
Thanks for the suggestion Tomasz.
Best regards,
Tomasz
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Re: [PATCH v7 6/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
Hi Tomasz, On Sat, Jul 19, 2014 at 6:59 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi, On 14.07.2014 15:38, Thomas Abraham wrote: From: Thomas Abraham thomas...@samsung.com Exynos4210 and Exynos5250 based platforms have switched over to use generic cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq drivers for these platforms can be removed. Signed-off-by: Thomas Abraham thomas...@samsung.com Acked-by: Viresh Kumar viresh.ku...@linaro.org Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com Tested-by: Arjun K.V arjun...@samsung.com --- drivers/cpufreq/Kconfig.arm | 22 drivers/cpufreq/Makefile |2 - drivers/cpufreq/exynos4210-cpufreq.c | 184 - drivers/cpufreq/exynos5250-cpufreq.c | 210 -- 4 files changed, 418 deletions(-) delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c I would hesitate with removing this driver straightaway and replacing it with a new one that isn't yet well tested. For at least one release I would keep the old code in place with the possibility of switching between old and new one in Kconfig. The new drivers have been tested for three days on Exynos4210/5250/5420 based boards. So I am fairly confident that there will be no issues in switching to the generic drivers and the old drivers have not been retained in the next version. Thanks, Thomas. Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-pm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] ARM: dts: add CPU nodes for Exynos4 SoCs
On Mon, Jul 21, 2014 at 6:40 PM, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: Hi, On Monday, July 21, 2014 01:43:53 PM Daniel Drake wrote: On Fri, Jul 18, 2014 at 5:00 PM, Bartlomiej Zolnierkiewicz b.zolnier...@samsung.com wrote: Recent patch by Tomasz Figa (irqchip: gic: Fix core ID calculation when topology is read from DT) fixed GIC driver to filter cluster ID from values returned by cpu_logical_map() for SoCs having registers mapped without per-CPU banking making it is possible to add CPU nodes for Exynos4 SoCs. In case of Exynos SoCs these CPU nodes are also required by future changes adding initialization of cpuidle states in Exynos cpuidle driver through DT. This conflicts with work in the thread cpufreq: use generic cpufreq drivers for exynos platforms which is already in its 7th iteration. Perhaps best to work directly with Thomas to help him finish that series? Patch [PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data from Thomas needs another revision anyway since it lacks cluster ID in Exynos4210 CPU node. It also mixes addition of CPU nodes with cpufreq specific changes and IMHO addition of CPU nodes should be in separate patch to ease bisection if any later problems turn up. Therefore I think that it would be the best if Thomas would rebase his work on top of irqchip: gic: Fix core ID calculation when topology is read from DT patch and this one. Thomas, are you okay with this? Hi Bartlomiej, Yes, I am okay with this. Regards, Thomas. Best regards, -- Bartlomiej Zolnierkiewicz Samsung RD Institute Poland Samsung Electronics -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
On Fri, Jul 18, 2014 at 6:14 AM, Chanwoo Choi cw00.c...@samsung.com wrote: Hi Thomas, On 07/17/2014 02:58 PM, Thomas Abraham wrote: Hi Mike, On Tue, Jul 15, 2014 at 9:20 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Tomasz, On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham thomas...@samsung.com wrote: Changes since v6: - Fixes suggested by Amit Daniel amit.dan...@samsung.com. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support In this series, support for Exynos5420 has been included. If there are any more changes required, could you please let me know. This patch series migrates exynos cpufreq support to use generic cpufreq drivers. For this, cpu clock blocks are encapsulated into a cpu clock type and cpufreq driver operates the cpu clock type. We had discussed in the [1] about using coordinated clocks. This series is not using the concept of coordinated clocks but the code in this series can be migrated to use coordinated clocks when it is available. Is it okay to consider this series for v3.17-rc1. I will update this code to use coordinated clocks when it is available. This series helps with cpufreq support for newer Exynos SoCs such as Exynos5420/3250. [1] http://www.spinics.net/lists/cpufreq/msg10042.html I tested this patchset with Exynos3250 cpufreq patchset[1] on Exynos3250 SoC. [1] https://lkml.org/lkml/2014/6/18/126 Tested-by: Chanwoo Choi cw00.c...@samsung.com Hi Chanwoo, Thanks for using these patches for Exynos3250 cpufreq support. Regards, Thomas. Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Mike, On Tue, Jul 15, 2014 at 9:20 AM, Thomas Abraham ta.oma...@gmail.com wrote: Hi Tomasz, On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham thomas...@samsung.com wrote: Changes since v6: - Fixes suggested by Amit Daniel amit.dan...@samsung.com. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support In this series, support for Exynos5420 has been included. If there are any more changes required, could you please let me know. This patch series migrates exynos cpufreq support to use generic cpufreq drivers. For this, cpu clock blocks are encapsulated into a cpu clock type and cpufreq driver operates the cpu clock type. We had discussed in the [1] about using coordinated clocks. This series is not using the concept of coordinated clocks but the code in this series can be migrated to use coordinated clocks when it is available. Is it okay to consider this series for v3.17-rc1. I will update this code to use coordinated clocks when it is available. This series helps with cpufreq support for newer Exynos SoCs such as Exynos5420/3250. [1] http://www.spinics.net/lists/cpufreq/msg10042.html Thanks, Thomas Thanks, Thomas. arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 27 ++ arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 + arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 32 ++ arch/arm/mach-exynos/exynos.c | 15 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 576 +++ drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c| 16 +- drivers/clk/samsung/clk-exynos5420.c| 60 ++- drivers/clk/samsung/clk.h |5 + drivers/cpufreq/Kconfig.arm | 22 - drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 802 insertions(+), 442 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v6: - Fixes suggested by Amit Daniel amit.dan...@samsung.com. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 27 ++ arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 + arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 32 ++ arch/arm/mach-exynos/exynos.c | 15 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 576 +++ drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c| 16 +- drivers/clk/samsung/clk-exynos5420.c| 60 ++- drivers/clk/samsung/clk.h |5 + drivers/cpufreq/Kconfig.arm | 22 - drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 802 insertions(+), 442 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
From: Thomas Abraham thomas...@samsung.com
For Exynos 4210/5250/5420 based platforms, add CPU nodes, operating points and
cpu clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6
arch/arm/boot/dts/exynos4210-trats.dts |6
arch/arm/boot/dts/exynos4210-universal_c210.dts |6
arch/arm/boot/dts/exynos4210.dtsi | 27
arch/arm/boot/dts/exynos5250-arndale.dts|6
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6
arch/arm/boot/dts/exynos5250-smdk5250.dts |6
arch/arm/boot/dts/exynos5250.dtsi | 23 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts |6
arch/arm/boot/dts/exynos5420.dtsi | 38 +++
10 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..49a97fc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -33,6 +33,12 @@
bootargs =root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck1_reg;
+ };
+ };
+
regulators {
compatible = simple-bus;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..fe32b6a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,6 +30,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5
rootwait earlyprintk panic=5;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = varm_breg;
+ };
+ };
+
regulators {
compatible = simple-bus;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..8ab12d6 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw
rootwait earlyprintk panic=5 maxcpus=1;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = vdd_arm_reg;
+ };
+ };
+
sysram@0202 {
smp-sysram@0 {
status = disabled;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..c3a73bf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,33 @@
pinctrl2 = pinctrl_2;
};
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ };
+ };
+
sysram@0202 {
compatible = mmio-sram;
reg = 0x0202 0x2;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..d9b803b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -26,6 +26,12 @@
bootargs = console=ttySAC2,115200;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
rtc@101E {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg
[PATCH v7 3/6] clk: exynos: use cpu-clock provider type to represent arm clock
From: Thomas Abraham thomas...@samsung.com
Register cpu clocks using the new cpu-clock provider type for exynos platforms.
The differnt clock blocks that are now encapsulated within the cpu-clock can be
marked with read-only attribute.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 25 +
drivers/clk/samsung/clk-exynos5250.c | 16 +++-
drivers/clk/samsung/clk-exynos5420.c | 32 +++-
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 ++
5 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 75573a4..10f1818 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -471,7 +471,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4210, SRC_CAM, 4, 4),
@@ -530,7 +531,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(0, mout_jpeg, mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, mout_vpll_p, SRC_TOP0, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, mout_fimc2, group1_p4x12, SRC_CAM, 8, 4),
@@ -572,8 +574,10 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
DIV(0, div_fimc1, mout_fimc1, DIV_CAM, 4, 4),
DIV(0, div_fimc2, mout_fimc2, DIV_CAM, 8, 4),
@@ -619,8 +623,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1016,7 +1022,6 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
static struct samsung_clock_alias exynos4_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
- ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
};
@@ -1255,6 +1260,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
+ exynos_register_cpu_clock(ctx, 0, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], np);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1264,6 +1271,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_alias(ctx
[PATCH v7 1/6] clk: samsung: add infrastructure to register cpu clocks
From: Thomas Abraham thomas...@samsung.com
This patch defines a new clock type for CPU clock provider and adds
infrastructure to register the CPU clock providers for Samsung platforms.
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs and so this new clock type provides a way to encapsulate these
blocks into CPU clock type.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 576 +
drivers/clk/samsung/clk.h |5 +
3 files changed, 582 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69e8177..f4edd31 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..0d62968
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the CPU clocks
+ * for Samsung platforms.
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK((0x7 4) | (0x7 0))
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)\
+ (((apll) 24) | ((pclk_dbg) 20) | ((atb) 16) | \
+ ((periph) 12) | ((corem1) 8) | ((corem0) 4))
+#define E4210_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | ((copy) 0))
+
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(periph 12) | (acp 8) | (cpud 4)))
+#define E5250_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | (copy))
+
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(cpud 4)))
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ (((kpll 24) | (pclk 20) | (aclk 4)))
+
+enum cpuclk_type {
+ EXYNOS4210,
+ EXYNOS5250,
+ EXYNOS5420,
+};
+
+/**
+ * struct exynos4210_cpuclk_data: config data to setup cpu clocks.
+ * @prate: frequency of the primary parent clock (in KHz).
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for dividers in the CPU
+ * clock domain. The parent frequency at which these divider values are valid
is
+ * specified in @prate. The @prate is the frequency of the primary parent
clock.
+ * For CPU clock domains that do not have a DIV1 register, the @div1 member
+ * is optional.
+ */
+struct exynos4210_cpuclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw:handle between CCF and CPU clock.
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset: offset from the ctrl_base address where the CPU clock div/mux
+ * registers can be accessed.
+ * @lock: cpu clock domain register access lock.
+ * @type: type of the CPU clock.
+ * @data: optional data which the actual instantiation of this clock
+ * can use.
+ * @clk_nb: clock
[PATCH v7 6/6] cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support
From: Thomas Abraham thomas...@samsung.com
Exynos4210 and Exynos5250 based platforms have switched over to use generic
cpufreq drivers for cpufreq functionality. So the Exynos specific cpufreq
drivers for these platforms can be removed.
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/cpufreq/Kconfig.arm | 22
drivers/cpufreq/Makefile |2 -
drivers/cpufreq/exynos4210-cpufreq.c | 184 -
drivers/cpufreq/exynos5250-cpufreq.c | 210 --
4 files changed, 418 deletions(-)
delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c
delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index ebac671..7a2f289 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -28,17 +28,6 @@ config ARM_VEXPRESS_SPC_CPUFREQ
config ARM_EXYNOS_CPUFREQ
bool
-config ARM_EXYNOS4210_CPUFREQ
- bool SAMSUNG EXYNOS4210
- depends on CPU_EXYNOS4210
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS4210
- SoC (S5PV310 or S5PC210).
-
- If in doubt, say N.
-
config ARM_EXYNOS4X12_CPUFREQ
bool SAMSUNG EXYNOS4x12
depends on SOC_EXYNOS4212 || SOC_EXYNOS4412
@@ -50,17 +39,6 @@ config ARM_EXYNOS4X12_CPUFREQ
If in doubt, say N.
-config ARM_EXYNOS5250_CPUFREQ
- bool SAMSUNG EXYNOS5250
- depends on SOC_EXYNOS5250
- default y
- select ARM_EXYNOS_CPUFREQ
- help
- This adds the CPUFreq driver for Samsung EXYNOS5250
- SoC.
-
- If in doubt, say N.
-
config ARM_EXYNOS5440_CPUFREQ
bool SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index db6d9a2..fac36ef 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,9 +52,7 @@ obj-$(CONFIG_ARM_DT_BL_CPUFREQ) +=
arm_big_little_dt.o
obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS_CPUFREQ) += exynos-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ) += exynos4x12-cpufreq.o
-obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ) += exynos5250-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c
b/drivers/cpufreq/exynos4210-cpufreq.c
deleted file mode 100644
index 61a5431..000
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4210 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include linux/module.h
-#include linux/kernel.h
-#include linux/err.h
-#include linux/clk.h
-#include linux/io.h
-#include linux/slab.h
-#include linux/cpufreq.h
-#include linux/of.h
-#include linux/of_address.h
-
-#include exynos-cpufreq.h
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-static struct exynos_dvfs_info *cpufreq;
-
-static unsigned int exynos4210_volt_table[] = {
- 125, 115, 105, 975000, 95,
-};
-
-static struct cpufreq_frequency_table exynos4210_freq_table[] = {
- {0, L0, 1200 * 1000},
- {0, L1, 1000 * 1000},
- {0, L2, 800 * 1000},
- {0, L3, 500 * 1000},
- {0, L4, 200 * 1000},
- {0, 0, CPUFREQ_TABLE_END},
-};
-
-static struct apll_freq apll_freq_4210[] = {
- /*
-* values:
-* freq
-* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL,
RESERVED
-* clock divider for COPY, HPM, RESERVED
-* PLL M, P, S
-*/
- APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
- APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
- APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
- APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
- APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
-};
-
-static void exynos4210_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = apll_freq_4210[div_index].clk_div_cpu0;
-
- __raw_writel(tmp, cpufreq-cmu_regs + EXYNOS4_CLKDIV_CPU);
-
- do
[PATCH v7 5/6] ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250/5420
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for exynos cpufreq driver and add the
platform device for generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Acked-by: Viresh Kumar viresh.ku...@linaro.org
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 2a43a17..5028b35 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -183,7 +183,20 @@ void __init exynos_cpuidle_init(void)
void __init exynos_cpufreq_init(void)
{
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ char *dev_name;
+
+ if (of_machine_is_compatible(samsung,exynos5440))
+ return;
+ if (of_machine_is_compatible(samsung,exynos5420))
+ dev_name = arm-bL-cpufreq-dt;
+ else
+ if (of_machine_is_compatible(samsung,exynos4412) ||
+ of_machine_is_compatible(samsung,exynos4212))
+ dev_name = exynos-cpufreq;
+ else
+ dev_name = cpufreq-cpu0;
+
+ platform_device_register_simple(dev_name, -1, NULL, 0);
}
void __iomem *sysram_base_addr;
--
1.7.9.5
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[PATCH v7 2/6] clk: samsung: register exynos5420 apll/kpll configuration data
From: Thomas Abraham thomas...@samsung.com
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
Reviewed-by: Amit Daniel Kachhap amit.dan...@samsung.com
Tested-by: Arjun K.V arjun...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index cc14ac8..95f83be 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1169,6 +1169,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
GATE(CLK_G3D, g3d, mout_user_aclk_g3d, GATE_IP_G3D, 9, 0, 0),
};
+static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(19, 475, 6, 0),
+ PLL_35XX_RATE(18, 225, 3, 0),
+ PLL_35XX_RATE(17, 425, 6, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, fout_apll, fin_pll, APLL_LOCK,
APLL_CON0, NULL),
@@ -1222,6 +1244,12 @@ static void __init exynos5x_clk_init(struct device_node
*np,
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
ext_clk_match);
+
+ if (_get_rate(fin_pll) == 24 * MHZ) {
+ exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ }
+
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
--
1.7.9.5
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Re: [PATCH v7 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Hi Tomasz, On Mon, Jul 14, 2014 at 7:08 PM, Thomas Abraham thomas...@samsung.com wrote: Changes since v6: - Fixes suggested by Amit Daniel amit.dan...@samsung.com. This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support In this series, support for Exynos5420 has been included. If there are any more changes required, could you please let me know. Thanks, Thomas. arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 27 ++ arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 + arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 32 ++ arch/arm/mach-exynos/exynos.c | 15 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 576 +++ drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c| 16 +- drivers/clk/samsung/clk-exynos5420.c| 60 ++- drivers/clk/samsung/clk.h |5 + drivers/cpufreq/Kconfig.arm | 22 - drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 802 insertions(+), 442 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v6 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
On Wed, Jun 18, 2014 at 1:21 PM, Viresh Kumar viresh.ku...@linaro.org wrote: On 17 June 2014 20:55, Thomas Abraham thomas...@samsung.com wrote: Changes since v5: - Configuration data for cpu clock block is embedded with the code. The cpu clock logic can later to extended to obtain this data from DT. - Excluded the support for Exynos4x12 SoC since the work on boost OPP bindings is still incomplete. - Included cpufreq support for Exynos5420 SoC. - Many other minor changes (and so dropped Ack's for some of the patches in v5) This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. cpuf...@vger.kernel.org list is deprecated now: dec102a, use linux-pm instead. Ok. Will take care next time. For patch 5 and 6: Acked-by: Viresh Kumar viresh.ku...@linaro.org Thanks Viresh. Regards, Thomas. -- To unsubscribe from this list: send the line unsubscribe cpufreq in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 0/3] cpufreq: Use cpufreq-cpu0 driver for Exynos3250
On Wed, Jun 18, 2014 at 2:09 PM, Chanwoo Choi cw00.c...@samsung.com wrote: This patchset use cpufreq-cpu0 driver to support Exynos3250 cpufreq. So, this patchset is based on following patchset[1] by Thomas Abraham. [1] http://www.spinics.net/lists/arm-kernel/msg339392.html Changes from v1: - Rebased on new patchset[1] by Thomas Abraham - Modify clk-cpu.c to support Exynos3250 - Drop documentation patch on previous patchset[2] [2] http://www.spinics.net/lists/cpufreq/msg10265.html - Add only operating-points for Exynos3250 without armclk-divider-table Chanwoo Choi (3): clk: samsung: cpu: Add support for cpu clocks of Exynos3250 clk: samsung: exynos3250: Use cpu-clock provider type to support cpufreq ARM: dts: Exynos: Add cpu clock table for Exynos3250 arch/arm/boot/dts/exynos3250.dtsi| 15 +++ drivers/clk/samsung/clk-cpu.c| 31 +++ drivers/clk/samsung/clk-exynos3250.c | 14 ++ 3 files changed, 56 insertions(+), 4 deletions(-) Hi Chanwoo, I have reviewed this series and it looks fine. If the cpu clock type is merged without any further changes, please add Reviewed-by: Thomas Abraham thomas...@samsung.com Thanks, Thomas. -- 1.8.0 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 0/6] cpufreq: use generic cpufreq drivers for exynos platforms
Changes since v5: - Configuration data for cpu clock block is embedded with the code. The cpu clock logic can later to extended to obtain this data from DT. - Excluded the support for Exynos4x12 SoC since the work on boost OPP bindings is still incomplete. - Included cpufreq support for Exynos5420 SoC. - Many other minor changes (and so dropped Ack's for some of the patches in v5) This patch series removes the use of Exynos4210 and Exynos5250 specific cpufreq drivers and enables the use of cpufreq-cpu0 driver for these platforms. This series also enabled cpufreq support for Exynos5420 using arm_big_little cpufreq driver. Thomas Abraham (6): clk: samsung: add infrastructure to register cpu clocks clk: samsung: register exynos5420 apll/kpll configuration data clk: exynos: use cpu-clock provider type to represent arm clock ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250 cpufreq: exynos: remove exynos4210/5250 specific cpufreq driver support arch/arm/boot/dts/exynos4210-origen.dts |6 + arch/arm/boot/dts/exynos4210-trats.dts |6 + arch/arm/boot/dts/exynos4210-universal_c210.dts |6 + arch/arm/boot/dts/exynos4210.dtsi | 27 ++ arch/arm/boot/dts/exynos5250-arndale.dts|6 + arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 + arch/arm/boot/dts/exynos5250-smdk5250.dts |6 + arch/arm/boot/dts/exynos5250.dtsi | 23 + arch/arm/boot/dts/exynos5420-smdk5420.dts |6 + arch/arm/boot/dts/exynos5420.dtsi | 32 ++ arch/arm/mach-exynos/exynos.c | 15 +- drivers/clk/samsung/Makefile|2 +- drivers/clk/samsung/clk-cpu.c | 577 +++ drivers/clk/samsung/clk-exynos4.c | 25 +- drivers/clk/samsung/clk-exynos5250.c| 16 +- drivers/clk/samsung/clk-exynos5420.c| 59 ++- drivers/clk/samsung/clk.h |5 + drivers/cpufreq/Kconfig.arm | 22 - drivers/cpufreq/Makefile|2 - drivers/cpufreq/exynos4210-cpufreq.c| 184 drivers/cpufreq/exynos5250-cpufreq.c| 210 - include/dt-bindings/clock/exynos5250.h |1 + include/dt-bindings/clock/exynos5420.h |2 + 23 files changed, 802 insertions(+), 442 deletions(-) create mode 100644 drivers/clk/samsung/clk-cpu.c delete mode 100644 drivers/cpufreq/exynos4210-cpufreq.c delete mode 100644 drivers/cpufreq/exynos5250-cpufreq.c -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v6 1/6] clk: samsung: add infrastructure to register cpu clocks
From: Thomas Abraham thomas...@samsung.com
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/Makefile |2 +-
drivers/clk/samsung/clk-cpu.c | 577 +
drivers/clk/samsung/clk.h |5 +
3 files changed, 583 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/samsung/clk-cpu.c
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 69e8177..f4edd31 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -2,7 +2,7 @@
# Samsung Clock specific Makefile
#
-obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
+obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
new file mode 100644
index 000..c40f7b5
--- /dev/null
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -0,0 +1,577 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Thomas Abraham thomas...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the utility functions to register the CPU clocks
+ * for Samsung platforms.
+*/
+
+#include linux/errno.h
+#include clk.h
+
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU00x400
+#define E4210_DIV_STAT_CPU10x404
+
+#define MAX_DIV8
+#define DIV_MASK 7
+#define DIV_MASK_ALL 0x
+#define MUX_MASK 7
+
+#define E4210_DIV0_RATIO0_MASK 0x7
+#define E4210_DIV1_HPM_MASK((0x7 4) | (0x7 0))
+#define E4210_MUX_HPM_MASK (1 20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK(DIV_MASK E4210_DIV0_ATB_SHIFT)
+
+#define E4210_CPU_DIV0(apll, pclk_dbg, atb, periph, corem1, corem0)\
+ (((apll) 24) | ((pclk_dbg) 20) | ((atb) 16) | \
+ ((periph) 12) | ((corem1) 8) | ((corem0) 4))
+#define E4210_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | ((copy) 0))
+
+#define E5250_CPU_DIV0(apll, pclk_dbg, atb, periph, acp, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(periph 12) | (acp 8) | (cpud 4)))
+#define E5250_CPU_DIV1(hpm, copy) \
+ (((hpm) 4) | (copy))
+
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ (((apll 24) | (pclk_dbg 20) | (atb 16) | \
+(cpud 4)))
+#define E5420_KFC_DIV(kpll, pclk, aclk)
\
+ (((kpll 24) | (pclk 20) | (aclk 4)))
+
+enum cpuclk_type {
+ EXYNOS4210,
+ EXYNOS5250,
+ EXYNOS5420,
+};
+
+/**
+ * struct exynos4210_cpuclk_data: config data to setup cpu clocks.
+ * @prate: frequency of the primary parent clock (in KHz).
+ * @div0: value to be programmed in the div_cpu0 register.
+ * @div1: value to be programmed in the div_cpu1 register.
+ *
+ * This structure holds the divider configuration data for dividers in the CPU
+ * clock domain. The parent frequency at which these divider values are valid
is
+ * specified in @prate. The @prate is the frequency of the primary parent
clock.
+ * For CPU clock domains that do not have a DIV1 register, the @div1 member
+ * is optional.
+ */
+struct exynos4210_cpuclk_data {
+ unsigned long prate;
+ unsigned intdiv0;
+ unsigned intdiv1;
+};
+
+/**
+ * struct exynos_cpuclk: information about clock supplied to a CPU core.
+ * @hw:handle between CCF and CPU clock.
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock.
+ * @ctrl_base: base address of the clock controller.
+ * @offset: offset from the ctrl_base address where the CPU clock div/mux
+ * registers can be accessed.
+ * @lock: cpu clock domain register access lock.
+ * @type: type of the CPU clock.
+ * @data: optional data which the actual instantiation of this clock
+ * can use.
+ * @clk_nb: clock notifier registered for changes in clock speed of the
+ * primary parent clock.
+ * @pre_rate_cb: callback function
[PATCH v6 5/6] ARM: Exynos: switch to using generic cpufreq driver for exynos4210/5250
From: Thomas Abraham thomas...@samsung.com
Remove the platform device instantiation for Exynos4210/5250 cpufreq
driver and add the platform device for generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/mach-exynos/exynos.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index f38cf7c..cfcfe02 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -181,7 +181,20 @@ void __init exynos_cpuidle_init(void)
void __init exynos_cpufreq_init(void)
{
- platform_device_register_simple(exynos-cpufreq, -1, NULL, 0);
+ char *dev_name;
+
+ if (of_machine_is_compatible(samsung,exynos5440))
+ return;
+ if (of_machine_is_compatible(samsung,exynos5420))
+ dev_name = arm-bL-cpufreq-dt;
+ else
+ if (of_machine_is_compatible(samsung,exynos4412) ||
+ of_machine_is_compatible(samsung,exynos4212))
+ dev_name = exynos-cpufreq;
+ else
+ dev_name = cpufreq-cpu0;
+
+ platform_device_register_simple(dev_name, -1, NULL, 0);
}
void __iomem *sysram_base_addr;
--
1.7.9.5
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[PATCH v6 3/6] clk: exynos: use cpu-clock provider type to represent arm clock
From: Thomas Abraham thomas...@samsung.com
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type and the independent
clock blocks that made up the arm clock can be removed.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos4.c | 25 +
drivers/clk/samsung/clk-exynos5250.c | 16 +++-
drivers/clk/samsung/clk-exynos5420.c | 31 ++-
include/dt-bindings/clock/exynos5250.h |1 +
include/dt-bindings/clock/exynos5420.h |2 ++
5 files changed, 53 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos4.c
b/drivers/clk/samsung/clk-exynos4.c
index 4f150c9..04cbcb6 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -471,7 +471,8 @@ static struct samsung_mux_clock exynos4210_mux_clks[]
__initdata = {
MUX(0, mout_fimd1, group1_p4210, E4210_SRC_LCD1, 0, 4),
MUX(0, mout_mipi1, group1_p4210, E4210_SRC_LCD1, 12, 4),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_CPU, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4210, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_SCLK_VPLL, sclk_vpll, sclk_vpll_p4210, SRC_TOP0, 8, 1),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4210, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4210, SRC_CAM, 4, 4),
@@ -530,7 +531,8 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
MUX(0, mout_jpeg, mout_jpeg_p, E4X12_SRC_CAM1, 8, 1),
MUX(CLK_SCLK_MPLL, sclk_mpll, mout_mpll_p, SRC_DMC, 12, 1),
MUX(CLK_SCLK_VPLL, sclk_vpll, mout_vpll_p, SRC_TOP0, 8, 1),
- MUX(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1),
+ MUX_F(CLK_MOUT_CORE, mout_core, mout_core_p4x12, SRC_CPU, 16, 1, 0,
+ CLK_MUX_READ_ONLY),
MUX(CLK_MOUT_FIMC0, mout_fimc0, group1_p4x12, SRC_CAM, 0, 4),
MUX(CLK_MOUT_FIMC1, mout_fimc1, group1_p4x12, SRC_CAM, 4, 4),
MUX(CLK_MOUT_FIMC2, mout_fimc2, group1_p4x12, SRC_CAM, 8, 4),
@@ -572,8 +574,10 @@ static struct samsung_mux_clock exynos4x12_mux_clks[]
__initdata = {
/* list of divider clocks supported in all exynos4 soc's */
static struct samsung_div_clock exynos4_div_clks[] __initdata = {
- DIV(0, div_core, mout_core, DIV_CPU0, 0, 3),
- DIV(0, div_core2, div_core, DIV_CPU0, 28, 3),
+ DIV_F(0, div_core, mout_core, DIV_CPU0, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(0, div_core2, div_core, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV(0, div_fimc0, mout_fimc0, DIV_CAM, 0, 4),
DIV(0, div_fimc1, mout_fimc1, DIV_CAM, 4, 4),
DIV(0, div_fimc2, mout_fimc2, DIV_CAM, 8, 4),
@@ -619,8 +623,10 @@ static struct samsung_div_clock exynos4_div_clks[]
__initdata = {
DIV(0, div_spi_pre2, div_spi2, DIV_PERIL2, 8, 8),
DIV(0, div_audio1, mout_audio1, DIV_PERIL4, 0, 4),
DIV(0, div_audio2, mout_audio2, DIV_PERIL4, 16, 4),
- DIV(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3),
- DIV(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3),
+ DIV_F(CLK_ARM_CLK, arm_clk, div_core2, DIV_CPU0, 28, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_SCLK_APLL, sclk_apll, mout_apll, DIV_CPU0, 24, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
DIV_F(0, div_mipi_pre0, div_mipi0, DIV_LCD0, 20, 4,
CLK_SET_RATE_PARENT, 0),
DIV_F(0, div_mmc_pre0, div_mmc0, DIV_FSYS1, 8, 8,
@@ -1005,7 +1011,6 @@ static struct samsung_gate_clock exynos4x12_gate_clks[]
__initdata = {
static struct samsung_clock_alias exynos4_aliases[] __initdata = {
ALIAS(CLK_MOUT_CORE, NULL, moutcore),
- ALIAS(CLK_ARM_CLK, NULL, armclk),
ALIAS(CLK_SCLK_APLL, NULL, mout_apll),
};
@@ -1244,6 +1249,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4210_gate_clks));
samsung_clk_register_alias(ctx, exynos4210_aliases,
ARRAY_SIZE(exynos4210_aliases));
+ exynos_register_cpu_clock(ctx, 0, CLK_ARM_CLK, armclk,
+ mout_core_p4210[0], mout_core_p4210[1], np);
} else {
samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
ARRAY_SIZE(exynos4x12_mux_clks));
@@ -1253,6 +1260,8 @@ static void __init exynos4_clk_init(struct device_node
*np,
ARRAY_SIZE(exynos4x12_gate_clks));
samsung_clk_register_alias(ctx, exynos4x12_aliases,
ARRAY_SIZE(exynos4x12_aliases
[PATCH v6 4/6] ARM: dts: Exynos: add cpu nodes, opp and cpu clock configuration data
From: Thomas Abraham thomas...@samsung.com
For Exynos 4210/5250/5420 based platforms, add CPU nodes, operating points and
cpu clock data for migrating from Exynos specific cpufreq driver to using
generic cpufreq drivers.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
arch/arm/boot/dts/exynos4210-origen.dts |6 +
arch/arm/boot/dts/exynos4210-trats.dts |6 +
arch/arm/boot/dts/exynos4210-universal_c210.dts |6 +
arch/arm/boot/dts/exynos4210.dtsi | 27 +++
arch/arm/boot/dts/exynos5250-arndale.dts|6 +
arch/arm/boot/dts/exynos5250-cros-common.dtsi |6 +
arch/arm/boot/dts/exynos5250-smdk5250.dts |6 +
arch/arm/boot/dts/exynos5250.dtsi | 23
arch/arm/boot/dts/exynos5420-smdk5420.dts |6 +
arch/arm/boot/dts/exynos5420.dtsi | 32 +++
10 files changed, 124 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts
b/arch/arm/boot/dts/exynos4210-origen.dts
index f767c42..49a97fc 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -33,6 +33,12 @@
bootargs =root=/dev/ram0 rw ramdisk=8192 initrd=0x4100,8M
console=ttySAC2,115200 init=/linuxrc;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck1_reg;
+ };
+ };
+
regulators {
compatible = simple-bus;
#address-cells = 1;
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts
b/arch/arm/boot/dts/exynos4210-trats.dts
index f516da9..fe32b6a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,6 +30,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5
rootwait earlyprintk panic=5;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = varm_breg;
+ };
+ };
+
regulators {
compatible = simple-bus;
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts
b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index d50eb3a..8ab12d6 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,12 @@
bootargs = console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw
rootwait earlyprintk panic=5 maxcpus=1;
};
+ cpus {
+ cpu: cpu@0 {
+ cpu0-supply = vdd_arm_reg;
+ };
+ };
+
sysram@0202 {
smp-sysram@0 {
status = disabled;
diff --git a/arch/arm/boot/dts/exynos4210.dtsi
b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..c3a73bf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,33 @@
pinctrl2 = pinctrl_2;
};
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+ clocks = clock CLK_ARM_CLK;
+ clock-names = cpu;
+
+ operating-points =
+ 120 125
+ 100 115
+ 80 1075000
+ 50 975000
+ 40 975000
+ 20 95
+ ;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ };
+ };
+
sysram@0202 {
compatible = mmio-sram;
reg = 0x0202 0x2;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index d0de1f5..d9b803b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -26,6 +26,12 @@
bootargs = console=ttySAC2,115200;
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
rtc@101E {
status = okay;
};
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f..34bb31c 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -19,6 +19,12 @@
chosen {
};
+ cpus {
+ cpu@0 {
+ cpu0-supply = buck2_reg;
+ };
+ };
+
pinctrl@1140
[PATCH v6 2/6] clk: samsung: register exynos5420 apll/kpll configuration data
From: Thomas Abraham thomas...@samsung.com
Register the PLL configuration data for APLL and KPLL on Exynos5420. This
configuration data table specifies PLL coefficients for supported PLL
clock speeds when a 24MHz clock is supplied as the input clock source
for these PLLs.
Cc: Tomasz Figa t.f...@samsung.com
Signed-off-by: Thomas Abraham thomas...@samsung.com
---
drivers/clk/samsung/clk-exynos5420.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7ee..51cff4a 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1142,6 +1142,28 @@ static struct samsung_gate_clock exynos5x_gate_clks[]
__initdata = {
GATE(CLK_G3D, g3d, mout_user_aclk_g3d, GATE_IP_G3D, 9, 0, 0),
};
+static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] = {
+ PLL_35XX_RATE(20, 250, 3, 0),
+ PLL_35XX_RATE(19, 475, 6, 0),
+ PLL_35XX_RATE(18, 225, 3, 0),
+ PLL_35XX_RATE(17, 425, 6, 0),
+ PLL_35XX_RATE(16, 200, 3, 0),
+ PLL_35XX_RATE(15, 250, 4, 0),
+ PLL_35XX_RATE(14, 175, 3, 0),
+ PLL_35XX_RATE(13, 325, 6, 0),
+ PLL_35XX_RATE(12, 200, 2, 1),
+ PLL_35XX_RATE(11, 275, 3, 1),
+ PLL_35XX_RATE(10, 250, 3, 1),
+ PLL_35XX_RATE(9, 150, 2, 1),
+ PLL_35XX_RATE(8, 200, 3, 1),
+ PLL_35XX_RATE(7, 175, 3, 1),
+ PLL_35XX_RATE(6, 200, 2, 2),
+ PLL_35XX_RATE(5, 250, 3, 2),
+ PLL_35XX_RATE(4, 200, 3, 2),
+ PLL_35XX_RATE(3, 200, 2, 3),
+ PLL_35XX_RATE(2, 200, 3, 3),
+};
+
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, fout_apll, fin_pll, APLL_LOCK,
APLL_CON0, NULL),
@@ -1195,6 +1217,12 @@ static void __init exynos5x_clk_init(struct device_node
*np,
samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
ext_clk_match);
+
+ if (_get_rate(fin_pll) == 24 * MHZ) {
+ exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ }
+
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
reg_base);
samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
--
1.7.9.5
--
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