Re: [PATCH v9 1/2] regulator: Add driver for max77802 PMIC PMIC regulators
On Sat, Aug 23, 2014 at 3:45 AM, Doug Anderson diand...@chromium.org wrote:
Hi,
On Fri, Aug 22, 2014 at 3:02 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Mark,
On 08/22/2014 08:30 PM, Mark Brown wrote:
The problem is that one of these regulators is used as the vqmmc-supply
(VCCQ/VDD_IO) so the mmc host controller driver disables it on
MMC_POWER_OFF. Now AFAIK (Yuvaraj can correct me what I got wrong) this
shouldn't be an issue since on card detection, the vqmmc supply should be
enabled again but on Exynos the built-in card detect line is on the same
power rail as vqmmc. That means that disabling the regulator prevents card
insertions to be detected.
If the MMC host controller needs a supply enabling in order to do card
detection and it's supposed to be doing card detection I'd expect it to
be enabling that supply. Why is it not doing that?
Good question. I'm not that familiar with the dw_mmc host controller nor
its driver implementation so I'll let Yuvaraj or Doug to answer that.
Well,here it goes!
1. Power ON the board LDO4CTRL1[7:6] 11b
2. dw_mmc driver enable the vqmmc.
3. checks for UHS support, complete the voltage switching t0 1.8V
4. Does warm reset by reboot command.
5. mmc core calls mmc_set_ios() with MMC_POWER_OFF.
6. dw_mmc driver cut-off the regulator with LDO4CTRL1[7:6] is 00b
7.dw_mmc driver enable the vqmmc.
But after step 7 also, LD4CTRL[7:6] is 00b.
I haven't seen the issue that Yuvaraj is reporting (but I also haven't
picked up all of the relevant patches and tried to reproduce), so I'm
going to have to leave it to Yuvaraj to answer.
static int max77802_enable(struct regulator_dev *rdev)
{
struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev);
int id = rdev_get_id(rdev);
int shift = max77802_get_opmode_shift(id);
return regmap_update_bits(rdev-regmap,
rdev-desc-enable_reg,rdev-desc-enable_mask,max77802-opmode[id]
shift);
}
I think in the above code snippet, the val is what we got it during
the probe.We always write that value for enabling this regulator(which
is LDO4CTRL1[7:6] 00b after warm reset) which is not correct according
the MAX77802 manual.
As far as I know the dw_mmc driver ought to be enabling vqmmc when it
needs it. Perhaps there's a bug in your patch series that adds vqmmc
support to dw_mmc?
-Doug
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Re: [PATCH v9 1/2] regulator: Add driver for max77802 PMIC PMIC regulators
On Mon, Aug 25, 2014 at 2:37 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
Hello Yuvaraj,
On 08/25/2014 10:22 AM, Yuvaraj Cd wrote:
Good question. I'm not that familiar with the dw_mmc host controller nor
its driver implementation so I'll let Yuvaraj or Doug to answer that.
Well,here it goes!
1. Power ON the board LDO4CTRL1[7:6] 11b
2. dw_mmc driver enable the vqmmc.
3. checks for UHS support, complete the voltage switching t0 1.8V
4. Does warm reset by reboot command.
5. mmc core calls mmc_set_ios() with MMC_POWER_OFF.
6. dw_mmc driver cut-off the regulator with LDO4CTRL1[7:6] is 00b
7.dw_mmc driver enable the vqmmc.
But after step 7 also, LD4CTRL[7:6] is 00b.
Ok, so the dw_mmc driver is enabling vqmmc, that's good.
I haven't seen the issue that Yuvaraj is reporting (but I also haven't
picked up all of the relevant patches and tried to reproduce), so I'm
going to have to leave it to Yuvaraj to answer.
static int max77802_enable(struct regulator_dev *rdev)
{
struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev);
int id = rdev_get_id(rdev);
int shift = max77802_get_opmode_shift(id);
return regmap_update_bits(rdev-regmap,
rdev-desc-enable_reg,rdev-desc-enable_mask,max77802-opmode[id]
shift);
}
I think in the above code snippet, the val is what we got it during
the probe.We always write that value for enabling this regulator(which
is LDO4CTRL1[7:6] 00b after warm reset) which is not correct according
the MAX77802 manual.
I see, so probably until we have a way to define the operating mode for
each regulator using DT we should set the opmode to normal when enabling a
regulator independently of the value the hardware register reported on probe.
Can you please test the following change [0] so I can post as a proper
patch? Doug, Mark do you think that forcing the regulator to opmode normal
when enabling is the right solution here?
Best regards,
Javier
[0]
diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c
index ad1caa9..917b5ab 100644
--- a/drivers/regulator/max77802.c
+++ b/drivers/regulator/max77802.c
@@ -180,7 +180,7 @@ static int max77802_enable(struct regulator_dev *rdev)
return regmap_update_bits(rdev-regmap, rdev-desc-enable_reg,
rdev-desc-enable_mask,
- max77802-opmode[id] shift);
+ MAX77802_OPMODE_NORMAL shift);
}
It works.
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Re: [PATCH v9 1/2] regulator: Add driver for max77802 PMIC PMIC regulators
On Mon, Aug 18, 2014 at 2:02 PM, Javier Martinez Canillas
javier.marti...@collabora.co.uk wrote:
The MAX77802 PMIC has 10 high-efficiency Buck and 32 Low-dropout
(LDO) regulators. This patch adds support for all these regulators
found on the MAX77802 PMIC and is based on a driver added by Simon
Glass to the Chrome OS kernel 3.8 tree.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
Tested-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v7:
- Remove DVS support since that can be added as a follow up.
Changes since v6: None
Changes since v5:
- Take out the mfd changes from v4 that were squashed by mistake.
Suggested by Lee Jones.
Changes since v4: None
Changes since v3:
- Set the supply_name for regulators to lookup their parent supply node.
Suggested by Mark Brown.
- Change Exyno5 for Exynos5420/Exynos5800 in regulator driver Kconfig.
Suggested by Doug Anderson.
---
drivers/regulator/Kconfig| 9 +
drivers/regulator/Makefile | 1 +
drivers/regulator/max77802.c | 578
+++
3 files changed, 588 insertions(+)
create mode 100644 drivers/regulator/max77802.c
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 2dc8289..8134a99 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -387,6 +387,15 @@ config REGULATOR_MAX77693
and one current regulator 'CHARGER'. This is suitable for
Exynos-4x12 chips.
+config REGULATOR_MAX77802
+ tristate Maxim 77802 regulator
+ depends on MFD_MAX77686
+ help
+ This driver controls a Maxim 77802 regulator
+ via I2C bus. The provided regulator is suitable for
+ Exynos5420/Exynos5800 SoCs to control various voltages.
+ It includes support for control of voltage and ramp speed.
+
config REGULATOR_MC13XXX_CORE
tristate
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index aa4a6aa..b4ec6c8 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_REGULATOR_MAX8997) += max8997.o
obj-$(CONFIG_REGULATOR_MAX8998) += max8998.o
obj-$(CONFIG_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_REGULATOR_MAX77693) += max77693.o
+obj-$(CONFIG_REGULATOR_MAX77802) += max77802.o
obj-$(CONFIG_REGULATOR_MC13783) += mc13783-regulator.o
obj-$(CONFIG_REGULATOR_MC13892) += mc13892-regulator.o
obj-$(CONFIG_REGULATOR_MC13XXX_CORE) += mc13xxx-regulator-core.o
diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c
new file mode 100644
index 000..5f022f8
--- /dev/null
+++ b/drivers/regulator/max77802.c
@@ -0,0 +1,578 @@
+/*
+ * max77802.c - Regulator driver for the Maxim 77802
+ *
+ * Copyright (C) 2013-2014 Google, Inc
+ * Simon Glass s...@chromium.org
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ * Chiwoong Byun woong.b...@smasung.com
+ * Jonghwa Lee jonghwa3@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This driver is based on max8997.c
+ */
+
+#include linux/kernel.h
+#include linux/bug.h
+#include linux/err.h
+#include linux/gpio.h
+#include linux/slab.h
+#include linux/gpio/consumer.h
+#include linux/platform_device.h
+#include linux/regulator/driver.h
+#include linux/regulator/machine.h
+#include linux/regulator/of_regulator.h
+#include linux/mfd/max77686.h
+#include linux/mfd/max77686-private.h
+
+/* Default ramp delay in case it is not manually set */
+#define MAX77802_RAMP_DELAY10 /* uV/us */
+
+#define MAX77802_OPMODE_SHIFT_LDO 6
+#define MAX77802_OPMODE_BUCK234_SHIFT 4
+#define MAX77802_OPMODE_MASK 0x3
+
+#define MAX77802_VSEL_MASK 0x3F
+#define MAX77802_DVS_VSEL_MASK 0xFF
+
+#define MAX77802_RAMP_RATE_MASK_2BIT 0xC0
+#define MAX77802_RAMP_RATE_SHIFT_2BIT 6
+#define MAX77802_RAMP_RATE_MASK_4BIT 0xF0
+#define MAX77802_RAMP_RATE_SHIFT_4BIT 4
+
+/* MAX77802 has two register formats: 2-bit and 4-bit */
+static const unsigned int ramp_table_77802_2bit[] = {
+ 12500,
+ 25000,
+ 5,
+ 10,
+};
+
+static unsigned int ramp_table_77802_4bit[] = {
+ 1000, 2000, 3030, 4000,
+ 5000, 5880, 7140, 8330,
+ 9090, 1, 0, 12500,
+ 16670, 25000, 5, 10,
+};
+
+struct max77802_regulator_prv {
+ int num_regulators;
+
Re: mwifiex card reset
On Tue, Jul 1, 2014 at 12:27 PM, James Cameron qu...@laptop.org wrote: On Mon, Jun 30, 2014 at 11:44:29PM -0700, Bing Zhao wrote: I may have missed something, but doesn't the MMC_POWER_OFF and MMC_POWER_ON|UP handling in controller driver help? Anyway the clocks/GPIOs/regulators are sort of platform dependent. Would it be better putting it in /arch/arm/mach-x/? Wouldn't device tree for mmc be better? I have come across same problem.Below is the thread in which more discussions happened on this. http://patchwork.ozlabs.org/patch/312444/ I am adding few more those who are interested in this solution. -- James Cameron http://quozl.linux.org.au/ -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] mmc: dw_mmc: exynos: Turn SDIO interrupts on
On Wed, Apr 23, 2014 at 9:42 AM, Alim Akhtar alim.akh...@gmail.com wrote: Hi Yuvaraj, On Mon, Mar 24, 2014 at 10:12 AM, Yuvaraj Kumar yuvaraj...@gmail.com wrote: On Mon, Mar 24, 2014 at 9:59 AM, Jaehoon Chung jh80.ch...@samsung.com wrote: Hi, Yuvaraj. NACK. we can use mmc_of_parese(). Thanks Jaehoon for the pointer.I will use mmc_of_parse(). Are you planning to re-spin this patch? Now Jaehoon's changes for using mmc_of_parse() is landed in mmc-next. As its already added mmc_of_parse(),no respin of this. Just we need to use it in DT. Thanks!! I have sent the patch that use mmc_of_parse(). https://patchwork.kernel.org/patch/3750681/ Best Regards, Jaehoon Chung On 03/24/2014 01:23 PM, Yuvaraj Kumar C D wrote: The mmc part in exynos supports SDIO interrupts and they work fine, so turn the capability on. With this I see download speeds increase about 10x. This V1 of this patch is posted to LKML at https://patchwork.kernel.org/patch/2429661/) by Doug Anderson. Signed-off-by: Doug Anderson diand...@chromium.org Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com --- drivers/mmc/host/dw_mmc.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c index 0c56faa..240949d 100644 --- a/drivers/mmc/host/dw_mmc.c +++ b/drivers/mmc/host/dw_mmc.c @@ -2417,6 +2417,9 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) if (of_get_property(np, cd-inverted, NULL)) pdata-caps2 |= MMC_CAP2_CD_ACTIVE_HIGH; + if (of_find_property(np, cap-sdio-irq, NULL)) + pdata-caps |= MMC_CAP_SDIO_IRQ; + return pdata; } -- To unsubscribe from this list: send the line unsubscribe linux-mmc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Alim ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] i2c: s3c2410 : Add polling mode support
On Fri, Jan 3, 2014 at 9:40 PM, Wolfram Sang w...@the-dreams.de wrote: Hi, On Mon, Nov 11, 2013 at 04:50:20PM +0530, Yuvaraj Kumar C D wrote: From: Vasanth Ananthan vasanthanant...@gmail.com This patch adds polling mode support for i2c-s3c2410 driver.The SATA PHY controller's CMU and TRSV block's are of I2C register map in exynos5250.These blocks can be configured using i2c. But i2c controller instance on which these block's sits lacks an interrupt line.Also the current i2c-s3c2410 driver is only interrupt driven, thus a polling mode support is required in the driver for supporting this controller. This patch adds this support to the driver. Changes from V1: 1.Changed the is_ack() to have even period b/w polls and used usleep_range() instead of udelay(). Mileages vary, but I'd like to see revision changes after the ---. ret = devm_request_irq(pdev-dev, i2c-irq, s3c24xx_i2c_irq, 0, -dev_name(pdev-dev), i2c); + dev_name(pdev-dev), i2c); Unrelated change. Rest looks good, so I'll fix up the things for you and apply to for-next, thanks! Thanks Wolfram. ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH V2] i2c: s3c2410 : Add polling mode support
Ping..
On Fri, Dec 13, 2013 at 2:51 PM, Yuvaraj Kumar yuvaraj...@gmail.com wrote:
Dear Wolfram,
Can you take this into your tree?
On Fri, Nov 22, 2013 at 11:32 AM, Yuvaraj Kumar yuvaraj...@gmail.com wrote:
Any comments on this patch?
On Mon, Nov 11, 2013 at 4:50 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com
wrote:
From: Vasanth Ananthan vasanthanant...@gmail.com
This patch adds polling mode support for i2c-s3c2410 driver.The
SATA PHY controller's CMU and TRSV block's are of I2C register
map in exynos5250.These blocks can be configured using i2c.
But i2c controller instance on which these block's sits lacks an
interrupt line.Also the current i2c-s3c2410 driver is only interrupt
driven, thus a polling mode support is required in the driver for
supporting this controller. This patch adds this support to the driver.
Changes from V1:
1.Changed the is_ack() to have even period b/w polls and
used usleep_range() instead of udelay().
Signed-off-by: Vasanth Ananthan vasant...@samsung.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/i2c/i2c-s3c2410.txt|2 +
drivers/i2c/busses/i2c-s3c2410.c | 66
+---
2 files changed, 58 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
index 296eb45..278de8e 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt
@@ -10,6 +10,8 @@ Required properties:
inside HDMIPHY block found on several samsung SoCs
(d) samsung, exynos5440-i2c, for s3c2440-like i2c used
on EXYNOS5440 which does not need GPIO configuration.
+ (e) samsung, exynos5-sata-phy-i2c, for s3c2440-like i2c used as
+ a host to SATA PHY controller on an internal bus.
- reg: physical base address of the controller and length of memory
mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-s3c2410.c
b/drivers/i2c/busses/i2c-s3c2410.c
index 3747b9b..08ed126 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -85,6 +85,7 @@
#define QUIRK_S3C2440 (1 0)
#define QUIRK_HDMIPHY (1 1)
#define QUIRK_NO_GPIO (1 2)
+#define QUIRK_POLL (1 3)
/* Max time to wait for bus to become idle after a xfer (in us) */
#define S3C2410_IDLE_TIMEOUT 5000
@@ -141,6 +142,8 @@ static struct platform_device_id s3c24xx_driver_ids[] =
{
};
MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
+static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long
iicstat);
+
#ifdef CONFIG_OF
static const struct of_device_id s3c24xx_i2c_match[] = {
{ .compatible = samsung,s3c2410-i2c, .data = (void *)0 },
@@ -149,6 +152,8 @@ static const struct of_device_id s3c24xx_i2c_match[] = {
.data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
{ .compatible = samsung,exynos5440-i2c,
.data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
+ { .compatible = samsung,exynos5-sata-phy-i2c,
+ .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
@@ -187,7 +192,8 @@ static inline void s3c24xx_i2c_master_complete(struct
s3c24xx_i2c *i2c, int ret)
if (ret)
i2c-msg_idx = ret;
- wake_up(i2c-wait);
+ if (!(i2c-quirks QUIRK_POLL))
+ wake_up(i2c-wait);
}
static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
@@ -224,6 +230,22 @@ static inline void s3c24xx_i2c_enable_irq(struct
s3c24xx_i2c *i2c)
writel(tmp | S3C2410_IICCON_IRQEN, i2c-regs + S3C2410_IICCON);
}
+static bool is_ack(struct s3c24xx_i2c *i2c)
+{
+ int tries;
+
+ for (tries = 50; tries; --tries) {
+ if (readl(i2c-regs + S3C2410_IICCON)
+S3C2410_IICCON_IRQPEND) {
+ if (!(readl(i2c-regs + S3C2410_IICSTAT)
+S3C2410_IICSTAT_LASTBIT))
+ return true;
+ }
+ usleep_range(1000, 2000);
+ }
+ dev_err(i2c-dev, ack was not recieved\n);
+ return false;
+}
/* s3c24xx_i2c_message_start
*
@@ -268,6 +290,16 @@ static void s3c24xx_i2c_message_start(struct
s3c24xx_i2c *i2c,
stat |= S3C2410_IICSTAT_START;
writel(stat, i2c-regs + S3C2410_IICSTAT);
+
+ if (i2c-quirks QUIRK_POLL) {
+ while ((i2c-msg_num != 0) is_ack(i2c)) {
+ i2c_s3c_irq_nextbyte(i2c, stat);
+ stat = readl(i2c-regs + S3C2410_IICSTAT);
+
+ if (stat S3C2410_IICSTAT_ARBITR)
+
Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
On Thu, Oct 31, 2013 at 1:15 PM, Vivek Gautam gautam.vi...@samsung.com wrote: Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs. The new driver uses the generic PHY framework and will interact with DWC3 controller present on Exynos5 series of SoCs. Signed-off-by: Vivek Gautam gautam.vi...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt| 20 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5-usb3.c | 562 4 files changed, 590 insertions(+), 0 deletions(-) create mode 100644 drivers/phy/phy-exynos5-usb3.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index c0fccaa..9b5c111 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -20,3 +20,23 @@ Required properties: - compatible : should be samsung,exynos5250-dp-video-phy; - reg : offset and length of the Display Port PHY register set; - #phy-cells : from the generic PHY bindings, must be 0; + +Samsung Exynos5 SoC seiries USB 3.0 PHY controller +-- + +Required properties: +- compatible : + should be samsung,exynos5250-usb3phy for exynos5250 SoC + should be samsung,exynos5420-usb3phy for exynos5420 SoC +- reg : Register offset and length array + - first field corresponds to USB 3.0 PHY register set; + - second field corresponds to PHY power isolation register + present in PMU; +- clocks: Clock IDs array as required by the controller +- clock-names: names of clocks correseponding to IDs in the clock property; + Required clocks: + - first clock is main PHY clock (same as USB 3.0 controller IP clock) + - second clock is reference clock (usually crystal clock) + optional clock: + - third clock is special clock used by PHY for operation +- #phy-cells : from the generic PHY bindings, must be 0; diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..9a100c6 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -51,4 +51,11 @@ config PHY_EXYNOS_DP_VIDEO help Support for Display Port PHY found on Samsung EXYNOS SoCs. +config PHY_EXYNOS5_USB3 + tristate Exynos5 SoC series USB 3.0 PHY driver + depends on ARCH_EXYNOS5 + select GENERIC_PHY + help + Enable USB 3.0 PHY support for Exynos 5 SoC series + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d0caae9..9c06a61 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_EXYNOS5_USB3) += phy-exynos5-usb3.o diff --git a/drivers/phy/phy-exynos5-usb3.c b/drivers/phy/phy-exynos5-usb3.c new file mode 100644 index 000..b9a2674 --- /dev/null +++ b/drivers/phy/phy-exynos5-usb3.c @@ -0,0 +1,562 @@ +/* + * Samsung EXYNOS5 SoC series USB 3.0 PHY driver + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Vivek Gautam gautam.vi...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/mutex.h + +/* Exynos USB PHY registers */ +#define EXYNOS5_FSEL_9MHZ6 0x0 +#define EXYNOS5_FSEL_10MHZ 0x1 +#define EXYNOS5_FSEL_12MHZ 0x2 +#define EXYNOS5_FSEL_19MHZ20x3 +#define EXYNOS5_FSEL_20MHZ 0x4 +#define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_50MHZ 0x7 + +/* EXYNOS5: USB 3.0 DRD PHY registers */ +#define EXYNOS5_DRD_LINKSYSTEM (0x04) + +#define LINKSYSTEM_FLADJ_MASK (0x3f 1) +#define LINKSYSTEM_FLADJ(_x) ((_x) 1) +#define LINKSYSTEM_XHCI_VERSION_CONTROL(0x1 27) + +#define EXYNOS5_DRD_PHYUTMI(0x08) + +#define PHYUTMI_OTGDISABLE (0x1 6) +#define PHYUTMI_FORCESUSPEND (0x1 1) +#define PHYUTMI_FORCESLEEP (0x1 0) + +#define EXYNOS5_DRD_PHYPIPE(0x0c) + +#define EXYNOS5_DRD_PHYCLKRST (0x10) + +#define
Re: [PATCH v3 1/3] phy: Add new Exynos USB PHY driver
On Tue, Nov 5, 2013 at 9:43 PM, Kamil Debski k.deb...@samsung.com wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/phy/samsung-usbphy.txt | 52
drivers/phy/Kconfig| 23 +-
drivers/phy/Makefile |4 +
drivers/phy/phy-exynos-usb2.c | 234 ++
drivers/phy/phy-exynos-usb2.h | 87 ++
drivers/phy/phy-exynos4210-usb2.c | 272
drivers/phy/phy-exynos4212-usb2.c | 324
7 files changed, 995 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt
create mode 100644 drivers/phy/phy-exynos-usb2.c
create mode 100644 drivers/phy/phy-exynos-usb2.h
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4212-usb2.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
new file mode 100644
index 000..c8fbc70
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
@@ -0,0 +1,52 @@
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usbphy
+ - samsung,exynos4212-usbphy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+ - second and also required is the location of isolation registers
+ (isolation registers control the physical connection between the in
+ SoC modules and outside of the SoC, this also can be called enable
+ control in the documentation of the SoC)
+ - third is the location of the mode switch register, this only applies
+ to SoCs that have such a feature; mode switching enables to have
+ both host and device used the same SoC pins and is commonly used
+ when OTG is supported
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clocks is required by the phy module
+ - other clocks are associated by name with their respective phys and
+ are used to determine the value of the clock settings register
+
+The second cell in the PHY specifier identifies the PHY, its meaning is
+compatible dependent. For the currently supported SoCs (Exynos 4210 and
+Exynos 4212) it is as follows:
+ 0 - USB device,
+ 1 - USB host,
+ 2 - HSIC0,
+ 3 - HSIC1,
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+exynos_usbphy: exynos-usbphy@125B {
+ compatible = samsung,exynos4212-usbphy;
+ reg = 0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4;
+ clocks = clock 305, clock 2, clock 2, clock 2,
+ clock 2;
+ clock-names = phy, device, host, hsic0, hsic1;
+ status = okay;
+ #phy-cells = 1;
+};
+
+Then the PHY can be used in other nodes such as:
+
+ehci@1258 {
+ status = okay;
+ phys = exynos_usbphy 2;
+ phy-names = hsic0;
+};
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..bdf0fab 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -14,7 +14,7 @@ config GENERIC_PHY
API by which phy drivers can create PHY using the phy framework and
phy users can obtain reference to the PHY. All the users of this
framework should select this config.
-
+
config PHY_EXYNOS_MIPI_VIDEO
tristate S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver
help
@@ -51,4 +51,25 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_EXYNOS_USB2
+ tristate Samsung USB 2.0 PHY driver
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung
SoCs.
+ This driver provides common interface to interact, for Samsung
+ USB 2.0 PHY driver.
+
+config PHY_EXYNOS4210_USB2
+ bool Support for Exynos 4210
+ depends on PHY_EXYNOS_USB2
+ depends on CPU_EXYNOS4210
+ help
+ Enable USB PHY support for Exynos 4210
+
+config PHY_EXYNOS4212_USB2
+ bool Support for Exynos 4212
+ depends on PHY_EXYNOS_USB2
+ depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
+ help
+ Enable USB PHY support for Exynos 4212
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..c87bc65 100644
---
Re: [PATCH 1/2] i2c: exynos5: add support for HSI2C on Exynos5260 SoC
On Fri, Nov 22, 2013 at 11:42 AM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
This patch adds new compatible to support HSI2C module on Exynos5260
HSI2C module on Exynos5260 needs to be reset during during initialization.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
.../devicetree/bindings/i2c/i2c-exynos5.txt|6 +++-
drivers/i2c/busses/i2c-exynos5.c | 31
++--
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
index 056732c..704ab92 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -5,7 +5,11 @@ at various speeds ranging from 100khz to 3.4Mhz.
Required properties:
- compatible: value should be.
- - samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - samsung,exynos5-hsi2c, for i2c compatible with HSI2C available on
+ Exynos5250/5420 SoCs.
+ - samsung,exynos5260-hsi2c, for i2c compatible with HSI2C available
+ on Exynos5260 SoCs.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
diff --git a/drivers/i2c/busses/i2c-exynos5.c
b/drivers/i2c/busses/i2c-exynos5.c
index aca3991..cbb49e2 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -184,14 +184,35 @@ struct exynos5_i2c {
* 2. Fast speed upto 1Mbps
*/
int speed_mode;
+
+ /* Version of HS-I2C Hardware */
+ unsigned intversion;
+};
+
+enum hsi2c_version {
+ EXYNOS_5,
+ EXYNOS_5260
};
static const struct of_device_id exynos5_i2c_match[] = {
- { .compatible = samsung,exynos5-hsi2c },
+ {
+ .compatible = samsung,exynos5-hsi2c,
+ .data = (void *)EXYNOS_5 },
+ {
+ .compatible = samsung,exynos5260-hsi2c,
+ .data = (void *)EXYNOS_5260 },
{},
};
MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
+static inline unsigned int exynos5_i2c_get_version(struct platform_device
*pdev)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(exynos5_i2c_match, pdev-dev.of_node);
+ return (unsigned int)match-data;
+}
+
static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
{
writel(readl(i2c-regs + HSI2C_INT_STATUS),
@@ -692,7 +713,13 @@ static int exynos5_i2c_probe(struct platform_device
*pdev)
if (ret)
goto err_clk;
- exynos5_i2c_init(i2c);
+ i2c-version = exynos5_i2c_get_version(pdev);
+
+ /* The HS-I2C core on Exynos5260 needs a reset to start with */
+ if (i2c-version == EXYNOS_5260)
Is there is any change in the HSI2C IP for EXYNOS5260?
Can you let me know whats the change w.r.t IP and
why it needs reset to start,which was not needed in earlier SOC?
+ exynos5_i2c_reset(i2c);
+ else
+ exynos5_i2c_init(i2c);
ret = i2c_add_adapter(i2c-adap);
if (ret 0) {
--
1.7.10.4
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Re: [PATCH 2/3] Phy: Exynos: Add Exynos5250 sata phy driver
On Tue, Oct 1, 2013 at 6:21 PM, Kishon Vijay Abraham I kis...@ti.com wrote:
On Tuesday 01 October 2013 12:03 PM, Yuvaraj Kumar C D wrote:
This patch adds the sata phy driver for Exynos5250.Exynos5250 sata
phy comprises of CMU and TRSV blocks which are of I2C register Map.
So this patch also adds a i2c client driver, which is used configure
the CMU and TRSV block of exynos5250 SATA PHY.
Why not make the Exynos5250 sata phy as a i2c client driver instead?
This patch incorporates the generic phy framework to deal with sata
phy.
This patch depends on the below patch
[1].drivers: phy: add generic PHY framework
by Kishon Vijay Abraham Ikis...@ti.com
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
Signed-off-by: Girish K S ks.g...@samsung.com
Signed-off-by: Vasanth Ananthan vasant...@samsung.com
---
drivers/phy/Kconfig |6 +
drivers/phy/Makefile |1 +
drivers/phy/exynos/Kconfig |5 +
drivers/phy/exynos/Makefile |5 +
drivers/phy/exynos/exynos5250_phy_i2c.c | 53 +++
drivers/phy/exynos/sata_phy_exynos5250.c | 248
++
drivers/phy/exynos/sata_phy_exynos5250.h | 33
7 files changed, 351 insertions(+)
create mode 100644 drivers/phy/exynos/Kconfig
create mode 100644 drivers/phy/exynos/Makefile
create mode 100644 drivers/phy/exynos/exynos5250_phy_i2c.c
create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.c
create mode 100644 drivers/phy/exynos/sata_phy_exynos5250.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5f85909..ab3d1c6 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -11,3 +11,9 @@ menuconfig GENERIC_PHY
devices present in the kernel. This layer will have the generic
API by which phy drivers can create PHY using the phy framework and
phy users can obtain reference to the PHY.
+
+if GENERIC_PHY
NAK. Just select GENERIC_PHY from your driver Kconfig.
+
+source drivers/phy/exynos/Kconfig
+
+endif
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 9e9560f..e0223d7 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,3 +3,4 @@
#
obj-$(CONFIG_GENERIC_PHY)+= phy-core.o
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += exynos/
simply have phy-exynos5250 in drivers/phy.
ok.
diff --git a/drivers/phy/exynos/Kconfig b/drivers/phy/exynos/Kconfig
new file mode 100644
index 000..fa125fb
--- /dev/null
+++ b/drivers/phy/exynos/Kconfig
@@ -0,0 +1,5 @@
+config PHY_SAMSUNG_SATA
+ tristate Samsung Sata SerDes/PHY driver
+ help
+ Support for Samsung sata SerDes/Phy found on Samsung
+ SoCs.
diff --git a/drivers/phy/exynos/Makefile b/drivers/phy/exynos/Makefile
new file mode 100644
index 000..50dc7eb
--- /dev/null
+++ b/drivers/phy/exynos/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the exynos phy drivers.
+#
+ccflags-y := -Idrivers/phy/exynos
+obj-$(CONFIG_PHY_SAMSUNG_SATA) += sata_phy_exynos5250.o
exynos5250_phy_i2c.o
diff --git a/drivers/phy/exynos/exynos5250_phy_i2c.c
b/drivers/phy/exynos/exynos5250_phy_i2c.c
new file mode 100644
index 000..9c75d3b
--- /dev/null
+++ b/drivers/phy/exynos/exynos5250_phy_i2c.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013 Samsung Electronics Co.Ltd
+ * Author:
+ * Yuvaraj C D yuvaraj...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include linux/kernel.h
+#include linux/i2c.h
+#include linux/module.h
+#include sata_phy_exynos5250.h
+
+static int exynos_sata_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *i2c_id)
+{
+ sataphy_attach_i2c_client(client);
+
+ dev_info(client-adapter-dev,
+ attached %s into i2c adapter successfully\n,
+ client-name);
+
+ return 0;
+}
+
+static int exynos_sata_i2c_remove(struct i2c_client *client)
+{
+ dev_info(client-adapter-dev,
+ detached %s from i2c adapter successfully\n,
+ client-name);
+
+ return 0;
+}
+
+static const struct i2c_device_id phy_i2c_device_match[] = {
+ { sata-phy-i2c, 0 },
+};
+MODULE_DEVICE_TABLE(of, phy_i2c_device_match);
+
+struct i2c_driver sataphy_i2c_driver = {
+ .probe= exynos_sata_i2c_probe,
+ .id_table = phy_i2c_device_match,
+ .remove = exynos_sata_i2c_remove,
+ .driver = {
+ .name = sata-phy-i2c,
+ .owner = THIS_MODULE,
+ .of_match_table = (void *)phy_i2c_device_match,
+ },
+};
As I just mentioned above, we can merge this driver with the below one.
True, Initially it was merged.But already existing
Re: [PATCH V4 0/4] exynos dwmmc device tree node cleanup
Hi Kukjin, Can you please take this series to your tree? Best Regards Yuvaraj On Tue, Sep 3, 2013 at 1:41 PM, Tomasz Figa tomasz.f...@gmail.com wrote: Hi Yuvaraj, On Tuesday 03 of September 2013 11:34:20 Yuvaraj Kumar C D wrote: changes from V3: 1.Added two new patch in the series [1] ARM: dts: Move fifo-depth property from board dts [2] ARM: dts: rename mmc dts node for exynos5 series changes from V2: 1.remove from exynos5.dtsi and add in exynos5250.dtsi in single patch.Suggested by Tomasz Figa. 2.Separate patch for changing status property of dwmmc node in smdk5250 and arndale board dts file. V1 Patches: 1.[PATCH 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file. http://www.spinics.net/lists/linux-samsung-soc/msg21602.html 2.[PATCH 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file http://www.spinics.net/lists/linux-samsung-soc/msg21603.html Yuvaraj Kumar C D (4): ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi ARM: dts: exynos: change status property of dwmmc nodes ARM: dts: Move fifo-depth property from board dts ARM: dts: rename mmc dts node for exynos5 series arch/arm/boot/dts/cros5250-common.dtsi|8 +++ arch/arm/boot/dts/exynos5.dtsi| 21 - arch/arm/boot/dts/exynos5250-arndale.dts | 16 - arch/arm/boot/dts/exynos5250-smdk5250.dts | 16 - arch/arm/boot/dts/exynos5250-snow.dts |2 +- arch/arm/boot/dts/exynos5250.dtsi | 36 ++--- 6 files changed, 41 insertions(+), 58 deletions(-) Reviewed-by: Tomasz Figa t.f...@samsung.com Best regards, Tomasz -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: Re: [PATCH V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
--- Original Message ---
Sender : Doug Andersondiand...@google.com
Date : Aug 24, 2013 09:18 (GMT+05:30)
Title : Re: [PATCH V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
Yuvaraj,
On Thu, Aug 22, 2013 at 11:25 PM, Yuvaraj Cd wrote:
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
OK, so I don't know about card-detect-delay, but here's my belief
about the others. Feel free to tell me I'm wrong, since I'm not an EE
by training and also the stuff below has been cobbled together from
lots of different docs. I also haven't experimented enough to know
100% that it's correct. I also know nothing about the actual
signaling protocols of SD/MMC... Enough caveats?
sdr-timing / ddr-timing:
* First number (I think) allows you to drive data related lines at a
phase offset from the clock line. So if you have crazy routing on
your board and the data lines are much longer than the clock lines you
might want to do this. This is not common, so usually you want 0
here. Note that some other docs I have disagree with this and claim
that this number has to do with hold time requirements.
* Second number allows you to sample signals from the card at a phase
offset from the clock line. This number might depend on the card, but
hopefully not much. It's supposed to depend more on the length of the
lines (AKA depends on the board), though it might also depend on
pullup values as well and somewhat on the card? This number needs to
be tuned (like link training) when you operate a card at 50MHz.
* For ciu-div:
With a ciu-div of 3 (really 3+1 = 4) you get phase offsets of 45 degrees.
With a ciu-div of 1 (really 1+1 = 2) you get phase offsets of 90 degrees.
WIth a ciu-div of 0 (really 0+1 = 1) you get no phase offsets (I would
have guessed 180, but manual says otherwise)
So ciu-div intimately affects the sdr-timing and ddr-timing. Thus if
those are board-specific then so is ciu-div.
---
All of the above suggests to me the following untested things:
* If you happened to have a situation where you had a ciu-div of 3
and all of your sdr-timing/ddr-timing values were even, you could cut
the input clock in half, change ciu-div to 1, and cut all your
timings in half. I'd imagine that would save you power (better to
slow clocks down higher in the clock tree?). It would be sorta nice
if this was done automatically (assuming that you have full control of
input clock).
* I'm a little unclear exactly how the CLKDIV register interacts with
all of the above. I guess I'd be under the assumption that the CLKDIV
applies to the main clock, the sample clock, and the drive clock.
...but maybe I'm confused. I think you also get different results (in
terms of how many ns the drive and sample are delayed) depending on
whether the CLKDIV applies _after_ ciu-div or before. My guess is
that it applies after.
---
Anyway, not sure that helps a whole lot, but that's a summary of what
I've come to understand. I'm happy to be enlightened. I'm still
trying to figure how how these numbers were picked for our hardware
and whether those numbers are actually right.
Thanks Doug.It was very informative and I'm enlightened.
I will incorporate these changes in next version and post soon.
-DougN‹§²æìr¸›yúèšØb²X¬¶Ç§vØ^–)Þº{.nÇ+‰·¥Š{±±©¬ºx,¡È§¶›¡Ü¨}©ž²Æ
zÚj:+v‰¨¾«‘êçzZ+€Ê+zf£¢·hšˆ§~††Ûiÿûàz¹ ®w¥¢¸?™¨èÚ¢)ߢf
Re: [PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
On Fri, Aug 23, 2013 at 4:36 AM, Tomasz Figa tomasz.f...@gmail.com wrote:
On Thursday 22 of August 2013 12:24:58 Yuvaraj Kumar wrote:
On Wed, Aug 21, 2013 at 4:00 PM, Tomasz Figa t.f...@samsung.com wrote:
Hi Yuvaraj,
On Wednesday 21 of August 2013 12:13:53 Yuvaraj Kumar C D wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
What are the difference between both versions? Is there a patch adding
the new compatible to the driver somewhere?
Exynos5250 has DWMMC controller of IP version 2.41a
Exynos5420 has DWMMC controller of IP version 2.50a
In addition Exynos5420 has Security Management Unit for eMMC.
OK. What about my second question?
Below is the link.
http://permalink.gmane.org/gmane.linux.kernel.mmc/21060
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Ahh, so you fixed this already in this version, thanks. Haven't
noticed
this patch at first and commented on previous one. Sorry for the
noise.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
.../devicetree/bindings/mmc/exynos-dw-mshc.txt |2 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 38
arch/arm/boot/dts/exynos5420.dtsi
| 36 +++ 3 files changed, 76 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index
6d1c098..84cd56f 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -16,6 +16,8 @@ Required Properties:
specific extensions.
- samsung,exynos5250-dw-mshc: for controllers with Samsung
Exynos5250
specific extensions.
+ - samsung,exynos5420-dw-mshc: for controllers with Samsung
Exynos5420 + specific extensions.
* samsung,dw-mshc-ciu-div: Specifies the divider value for the card
interface unit (ciu) clock. This property is applicable only for
Exynos5 SoC's and diff --git
a/arch/arm/boot/dts/exynos5420-smdk5420.dts
b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..6e65278
100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -31,6 +31,44 @@
};
};
+ dwmmc0@1220 {
+ status = okay;
+ num-slots = 1;
You don't have to specify this property if there is only one slot.
Also are you sure that this is a board specific property?
Yes,If num-slots property is not defined dw_mmc driver assumes 1 slot
is available.
I think yes,its a board specific property as number of card slots is
board dependent.
+ broken-cd;
+ bypass-smu;
This property doesn't seem to be documented nor used anywhere.
Sorry. I missed to add in binding document.Will add in next version.
Is there a patch adding support for this property to the driver?
Yes.You can find here http://permalink.gmane.org/gmane.linux.kernel.mmc/21060
+ supports-highspeed;
Is it a board specific property?
+ fifo-depth = 0x80;
Ditto.
Ideally this can be move to SOC specific dts.But I am just following
,already merged smdk5250 board
dts convensions.
This means that Exynos5250 board dts files need to be fixed as well.
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 0 4;
+ samsung,dw-mshc-ddr-timing = 0 2;
Are the above three properties really board-specific?
Hmm?
I am not sure about this. But Doug Anderson has pointed out these as
board specific properties.
Best regards,
Tomasz
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Re: [PATCH V3] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
On Fri, Aug 23, 2013 at 5:23 AM, Doug Anderson diand...@google.com wrote:
Hi,
Thanks for adding my Thomasz,
On Thu, Aug 22, 2013 at 4:51 AM, Yuvaraj Kumar C D yuvaraj...@gmail.com
wrote:
This patch adds the device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
changes since V2:
1.dropped num-slots property from node as its not required
if number of card slots available is 1.
Just to mention: this is actually not board specific. No exynos
products support more than one slot. ...and in fact apparently NOBODY
supports more than one slot. I have a plan to post up a patch
removing multislot support whenever I have a free moment.
Anyway, what you did is fine.
2.Move the below properties
a.fifo-depth
Right, not board-specific. This is SoC specific. Interestingly
enough you appear to have it wrong. I have it on good authority that
5420 has a FIFO depth of 0x40 not 0x80. Apparently the FIFO is 0x40
deep and 64 wide whereas the old FIFO is 0x80 deep and 32 wide.
Ok.I will change fifo-depth to 0x40.
b.card-detect-delay
c.samsung,dw-mshc-ciu-div
d.samsung,dw-mshc-sdr-timing
e.samsung,dw-mshc-ddr-timing
These ARE board specific, actually. ...and Tomasz has pointed out.
I am not sure, why these properties are not SOC specific?How these
properties value
will change in other variants(boards) of exynos5420?
+ dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5420-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
+ reg = 0x1222 0x2000;
+ clocks = clock 353, clock 134;
+ clock-names = biu, ciu;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
Note: I have information that says that these timings are not correct
and that nearly always the drive timing should be 0 and the sample
timing 4. ...but we haven't landed that change ourselves yet, so
maybe keeping the timings you have is right.
-Doug
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[PATCH V2 2/2] ARM: dts: Add dwmmc nodes in SOC specific dts file
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's have different versions of DWMMC controller.
So dwmmc device nodes moved from Exynos5 SOC's common dts file to
SOC specific dts file.
changes since V1:
1.disable node by status = disabled in SOC file
2.enable node by status = okay in board specific file
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 10 ++
arch/arm/boot/dts/exynos5250.dtsi | 16
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts
b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 2538b32..bd19d55d 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -141,6 +141,7 @@
};
dwmmc0@1220 {
+ status = okay;
num-slots = 1;
supports-highspeed;
broken-cd;
@@ -158,11 +159,8 @@
};
};
- dwmmc1@1221 {
- status = disabled;
- };
-
dwmmc2@1222 {
+ status = okay;
num-slots = 1;
supports-highspeed;
fifo-depth = 0x80;
@@ -180,10 +178,6 @@
};
};
- dwmmc3@1223 {
- status = disabled;
- };
-
spi_0: spi@12d2 {
status = disabled;
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 1eec646..b1b6f61 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -387,21 +387,36 @@
};
dwmmc_0: dwmmc0@1220 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 75 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1220 0x1000;
clocks = clock 280, clock 139;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_1: dwmmc1@1221 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 76 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1221 0x1000;
clocks = clock 281, clock 140;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_2: dwmmc2@1222 {
+ compatible = samsung,exynos5250-dw-mshc;
+ interrupts = 0 77 0;
+ #address-cells = 1;
+ #size-cells = 0;
reg = 0x1222 0x1000;
clocks = clock 282, clock 141;
clock-names = biu, ciu;
+ status = disabled;
};
dwmmc_3: dwmmc3@1223 {
@@ -412,6 +427,7 @@
#size-cells = 0;
clocks = clock 283, clock 142;
clock-names = biu, ciu;
+ status = disabled;
};
i2s0: i2s@0383 {
--
1.7.9.5
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[PATCH V2 1/2] ARM: dts: remove dwmmc nodes from exynos5 common dts file.
From: Yuvaraj Kumar C D yuvaraj...@samsung.com
Exynos5 series SOC's 5250 and 5420 have different versions of
DWMMC controller.So there is a new compatible string to distinguish
between them.So these nodes should be moved out of Exynos5 series
common device tree source.
Changes since V1: none
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi | 21 -
1 file changed, 21 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d..24140f0 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -50,27 +50,6 @@
interrupts = 1 9 0xf04;
};
- dwmmc_0: dwmmc0@1220 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 75 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_1: dwmmc1@1221 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 76 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
- dwmmc_2: dwmmc2@1222 {
- compatible = samsung,exynos5250-dw-mshc;
- interrupts = 0 77 0;
- #address-cells = 1;
- #size-cells = 0;
- };
-
serial@12C0 {
compatible = samsung,exynos4210-uart;
reg = 0x12C0 0x100;
--
1.7.9.5
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Re: [RFC: PATCH v5] i2c: exynos5: add High Speed I2C controller driver
On Wed, Mar 20, 2013 at 9:54 PM, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Adds support for High Speed I2C driver found in Exynos5 and later
SoCs from Samsung. This driver currently supports Auto mode.
Driver only supports Device Tree method.
Note: Added debugfs support for registers view, not tested.
Signed-off-by: Taekgyun Ko taeggyun...@samsung.com
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
---
Changes since v4:
1. Fixed ISR routine to handle interrupt and fifo status registers
2. Handle the error return
3. Split the exynos5_i2c_set_timing to report error
4. Added description for the static functions and modes of operation
5. implemented TX fifo and RX fifo usage
.../devicetree/bindings/i2c/i2c-exynos5.txt| 50 ++
drivers/i2c/busses/Kconfig |7 +
drivers/i2c/busses/Makefile|1 +
drivers/i2c/busses/i2c-exynos5.c | 871
4 files changed, 929 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
create mode 100644 drivers/i2c/busses/i2c-exynos5.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
new file mode 100644
index 000..0bc9347
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
@@ -0,0 +1,50 @@
+* Samsung's High Speed I2C controller
+
+The Samsung's High Speed I2C controller is used to interface with I2C devices
+at various speeds ranging from 100khz to 3.4Mhz.
+
+Required properties:
+ - compatible: value should be.
+ (a) samsung,exynos5-hsi2c, for i2c compatible with exynos5 hsi2c.
+ - reg: physical base address of the controller and length of memory mapped
+region.
+ - interrupts: interrupt number to the cpu.
+
+ - Samsung GPIO variant (deprecated):
+- gpios: The order of the gpios should be the following: SDA, SCL.
+ The gpio specifier depends on the gpio controller.
+ - Pinctrl variant (preferred, if available):
+- pinctrl-0: Pin control group to be used for this controller.
+- pinctrl-names: Should contain only one value - default.
+
+Optional properties:
+ - samsung,hs-mode: Mode of operation, High speed or Fast speed mode. If not
+specified, default value is 0.
+ - samsung,hs-clock-freq: Desired operating frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+ - samsung,fs-clock-freq: Desired operarting frequency in Hz of the bus.
+If not specified, the default value in Hz is 10.
+
+Example:
+
+ hsi2c@12ca {
+ compatible = samsung,exynos5-hsi2c;
+ reg = 0x12ca 0x100;
+ interrupts = 56;
+ samsung,fs-clock-freq = 10;
+ /* Samsung GPIO variant begins here */
+ gpios = gpd1 2 0 /* SDA */
+gpd1 3 0 /* SCL */;
+ /* Samsung GPIO variant ends here */
+ /* Pinctrl variant begins here */
+ pinctrl-0 = i2c4_bus;
+ pinctrl-names = default;
+ /* Pinctrl variant ends here */
+ #address-cells = 1;
+ #size-cells = 0;
+
+ s2mps11_pmic@66 {
+ compatible = samsung,s2mps11-pmic;
+ reg = 0x66;
+ };
+ };
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3725de..78b4936 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -434,6 +434,13 @@ config I2C_EG20T
ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
+config I2C_EXYNOS5
+ tristate Exynos5 high-speed I2C driver
+ depends on ARCH_EXYNOS5 OF
+ help
+ Say Y here to include support for High-speed I2C controller in the
+ Exynos5 based Samsung SoCs.
+
config I2C_GPIO
tristate GPIO-based bitbanging I2C
depends on GENERIC_GPIO
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..b19366c 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ i2c-designware-platform-objs := i2c-designware-platdrv.o
obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
i2c-designware-pci-objs := i2c-designware-pcidrv.o
obj-$(CONFIG_I2C_EG20T)+= i2c-eg20t.o
+obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
diff --git a/drivers/i2c/busses/i2c-exynos5.c
b/drivers/i2c/busses/i2c-exynos5.c
new file mode 100644
index 000..e8e6483
--- /dev/null
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@
Re: [PATCH] mmc: dw_mmc: enable controller interrupt before calling mmc_start_host
Yes,its legal name.Yuvaraj C D. On Wed, Oct 24, 2012 at 2:49 AM, Chris Ball c...@laptop.org wrote: Hi, On Mon, Oct 08 2012, Yuvaraj CD wrote: As mmc_start_host is getting called before enabling the dw_mmc controller interrupt, there is a problem of missing the SDMMC_INT_CMD_DONE for the very first command sent by the sdio_reset. This problem occurs only when we disable MMC debugging i.e, MMC_DEBUG [=n]. Hence this patch enables the dw_mmc controller interrupt before mmc_start_host. Signed-off-by: Yuvaraj CD yuvaraj...@samsung.com Is Yuvaraj CD your legal name? We should use your full name so that we can track copyright attribution properly. Thanks! - Chris. -- Chris Ball c...@laptop.org http://printf.net/ One Laptop Per Child -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] mmc: dw_mmc: enable controller interrupt before calling mmc_start_host
As mmc_start_host is getting called before enabling the dw_mmc controller
interrupt, there is a problem of missing the SDMMC_INT_CMD_DONE for the
very first command sent by the sdio_reset.
This problem occurs only when we disable MMC debugging i.e, MMC_DEBUG [=n].
Hence this patch enables the dw_mmc controller interrupt before mmc_start_host.
Signed-off-by: Yuvaraj CD yuvaraj...@samsung.com
---
drivers/mmc/host/dw_mmc.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index a23af77..729c031 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -2233,6 +2233,21 @@ int dw_mci_probe(struct dw_mci *host)
else
host-num_slots = ((mci_readl(host, HCON) 1) 0x1F) + 1;
+ /*
+* Enable interrupts for command done, data over, data empty, card det,
+* receive ready and error such as transmit, receive timeout, crc error
+*/
+ mci_writel(host, RINTSTS, 0x);
+ mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
+ SDMMC_INT_TXDR | SDMMC_INT_RXDR |
+ DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
+ mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt
*/
+
+ dev_info(host-dev, DW MMC controller at irq %d,
+%d bit host data width,
+%u deep fifo\n,
+host-irq, width, fifo_size);
+
/* We need at least one slot to succeed */
for (i = 0; i host-num_slots; i++) {
ret = dw_mci_init_slot(host, i);
@@ -2262,20 +2277,6 @@ int dw_mci_probe(struct dw_mci *host)
else
host-data_offset = DATA_240A_OFFSET;
- /*
-* Enable interrupts for command done, data over, data empty, card det,
-* receive ready and error such as transmit, receive timeout, crc error
-*/
- mci_writel(host, RINTSTS, 0x);
- mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
- SDMMC_INT_TXDR | SDMMC_INT_RXDR |
- DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
- mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt
*/
-
- dev_info(host-dev, DW MMC controller at irq %d,
-%d bit host data width,
-%u deep fifo\n,
-host-irq, width, fifo_size);
if (host-quirks DW_MCI_QUIRK_IDMAC_DTO)
dev_info(host-dev, Internal DMAC interrupt fix enabled.\n);
--
1.7.9.5
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