Re: [PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
On 08/01/2012 06:39 PM, Padma Venkat wrote:
Hi,
On Wed, Aug 1, 2012 at 9:21 AM, Kukjin Kim kgene@samsung.com wrote:
Padmavathi Venna wrote:
Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
board specific. So this patch adds a function to set the required
audio codec clk frequency from machine file.
This patch also adds all the required clock instances for audio
subsystem and adds the clock alias names for i2sclk and busclk.
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: sangsu4u.park sangsu4u.p...@samsung.com
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 129
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/include/mach/regs-audss.h | 12 ++
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
4 files changed, 143 insertions(+), 0 deletions(-)
[...]
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -69,6 +69,7 @@ static void __init exynos5250_dt_machine_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
+ exynos5_set_audiocdclk_rate(16934400);
As you commented, the value of clock can be changed according to the board,
and this file, mach-exynos5-dt.c is not only for smdk5250, now there is no
board for exynos5250 though.
Please suggest me some file where I can call this function then.
Will it be a good idea to split this into two patches, one adding basic
audio subsystem defines and another one adding specific support for EXYNOS5?
[...]
Thanks.
Best regards,
Kgene.
Thanks for your review.
Best Regards
Padma
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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Re: [PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
Hi,
On Wed, Aug 1, 2012 at 9:21 AM, Kukjin Kim kgene@samsung.com wrote:
Padmavathi Venna wrote:
Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
board specific. So this patch adds a function to set the required
audio codec clk frequency from machine file.
This patch also adds all the required clock instances for audio
subsystem and adds the clock alias names for i2sclk and busclk.
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: sangsu4u.park sangsu4u.p...@samsung.com
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 129
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/include/mach/regs-audss.h | 12 ++
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
4 files changed, 143 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
exynos/clock-exynos5.c
index 774533c..681450a 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -20,10 +20,13 @@
#include plat/pll.h
#include plat/s5p-clock.h
#include plat/clock-clksrc.h
+#include plat/devs.h
Why do we need above on this patch?
It's by mistake. I will remove this line in the next patch set.
#include plat/pm.h
+#include plat/cpu.h
Same as above.
It's by mistake. I will remove this line in the next patch set.
#include mach/map.h
#include mach/regs-clock.h
+#include mach/regs-audss.h
See below my comment.
#include mach/sysmmu.h
#include common.h
@@ -106,6 +109,16 @@ static struct clk exynos5_clk_sclk_usbphy = {
.rate = 4800,
};
+struct clk exynos5_clk_audiocdclk0 = {
+ .id = -1,
+ .name = audiocdclk,
+};
+
+void exynos5_set_audiocdclk_rate(unsigned long rate)
+{
+ clk_default_setrate(exynos5_clk_audiocdclk0, rate);
+}
+
static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
@@ -171,6 +184,16 @@ static int exynos5_clk_ip_gps_ctrl(struct clk *clk,
int enable)
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
}
+static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+static int exynos5_clk_audss_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS_CLKGATE_AUDSS, clk, enable);
+}
+
static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -635,6 +658,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 3),
}, {
.name = iis,
+ .devname= samsung-i2s.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 2),
+ }, {
+ .name = iis,
.devname= samsung-i2s.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 20),
@@ -645,6 +673,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 21),
}, {
.name = pcm,
+ .devname= samsung-pcm.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 4),
+ }, {
+ .name = pcm,
.devname= samsung-pcm.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 22),
@@ -870,6 +903,95 @@ static struct clk exynos5_init_clocks_on[] = {
}
};
+static struct clk *clkset_sclk_audio0_list[] = {
+ [0] = exynos5_clk_audiocdclk0,
+ [1] = clk_ext_xtal_mux,
+ [2] = exynos5_clk_sclk_hdmi27m,
+ [3] = exynos5_clk_sclk_dptxphy,
+ [4] = exynos5_clk_sclk_usbphy,
+ [5] = exynos5_clk_sclk_hdmiphy,
+ [6] = exynos5_clk_mout_mpll.clk,
+ [7] = exynos5_clk_mout_epll.clk,
+ [8] = exynos5_clk_sclk_vpll.clk,
+ [9] = exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio0 = {
+ .sources= clkset_sclk_audio0_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio0 = {
+ .clk= {
+ .name = audio-bus,
sclk_audio?
Yes. The name of this clock instance can be changed to sclk_audio for
better understanding.
+ .enable = exynos5_clksrc_mask_maudio_ctrl,
+ .ctrlbit= (1 0),
+ },
+ .sources = exynos5_clkset_sclk_audio0,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_mout_audss_list[] = {
+
[PATCH] ARM: EXYNOS: Add clocks for EXYNOS Audio Subsystem.
Audiocdclk frequency is 16.9344MHz in SMDK5250 and this clock is
board specific. So this patch adds a function to set the required
audio codec clk frequency from machine file.
This patch also adds all the required clock instances for audio
subsystem and adds the clock alias names for i2sclk and busclk.
Signed-off-by: Taylor Hutt th...@chromium.org
Signed-off-by: sangsu4u.park sangsu4u.p...@samsung.com
Signed-off-by: Padmavathi Venna padm...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 129
arch/arm/mach-exynos/common.h |1 +
arch/arm/mach-exynos/include/mach/regs-audss.h | 12 ++
arch/arm/mach-exynos/mach-exynos5-dt.c |1 +
4 files changed, 143 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..681450a 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -20,10 +20,13 @@
#include plat/pll.h
#include plat/s5p-clock.h
#include plat/clock-clksrc.h
+#include plat/devs.h
#include plat/pm.h
+#include plat/cpu.h
#include mach/map.h
#include mach/regs-clock.h
+#include mach/regs-audss.h
#include mach/sysmmu.h
#include common.h
@@ -106,6 +109,16 @@ static struct clk exynos5_clk_sclk_usbphy = {
.rate = 4800,
};
+struct clk exynos5_clk_audiocdclk0 = {
+ .id = -1,
+ .name = audiocdclk,
+};
+
+void exynos5_set_audiocdclk_rate(unsigned long rate)
+{
+ clk_default_setrate(exynos5_clk_audiocdclk0, rate);
+}
+
static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
@@ -171,6 +184,16 @@ static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int
enable)
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
}
+static int exynos5_clksrc_mask_maudio_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_MAUDIO, clk, enable);
+}
+
+static int exynos5_clk_audss_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS_CLKGATE_AUDSS, clk, enable);
+}
+
static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -635,6 +658,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 3),
}, {
.name = iis,
+ .devname= samsung-i2s.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 2),
+ }, {
+ .name = iis,
.devname= samsung-i2s.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 20),
@@ -645,6 +673,11 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit= (1 21),
}, {
.name = pcm,
+ .devname= samsung-pcm.0,
+ .enable = exynos5_clk_audss_ctrl,
+ .ctrlbit= (3 4),
+ }, {
+ .name = pcm,
.devname= samsung-pcm.1,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 22),
@@ -870,6 +903,95 @@ static struct clk exynos5_init_clocks_on[] = {
}
};
+static struct clk *clkset_sclk_audio0_list[] = {
+ [0] = exynos5_clk_audiocdclk0,
+ [1] = clk_ext_xtal_mux,
+ [2] = exynos5_clk_sclk_hdmi27m,
+ [3] = exynos5_clk_sclk_dptxphy,
+ [4] = exynos5_clk_sclk_usbphy,
+ [5] = exynos5_clk_sclk_hdmiphy,
+ [6] = exynos5_clk_mout_mpll.clk,
+ [7] = exynos5_clk_mout_epll.clk,
+ [8] = exynos5_clk_sclk_vpll.clk,
+ [9] = exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_audio0 = {
+ .sources= clkset_sclk_audio0_list,
+ .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_audio0 = {
+ .clk= {
+ .name = audio-bus,
+ .enable = exynos5_clksrc_mask_maudio_ctrl,
+ .ctrlbit= (1 0),
+ },
+ .sources = exynos5_clkset_sclk_audio0,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_MAUDIO, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_MAUDIO, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_mout_audss_list[] = {
+ clk_ext_xtal_mux,
+ clk_fout_epll,
+};
+
+static struct clksrc_sources clkset_mout_audss = {
+ .sources= exynos5_clkset_mout_audss_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_audss_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_audss = {
+ .clk= {
+ .name = mout_audss,
+ },
+ .sources = clkset_mout_audss,
+ .reg_src = { .reg =
