[PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 2 +-
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5410.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi| 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi| 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi| 2 +-
arch/arm/boot/dts/tegra114.dtsi | 2 +-
arch/arm/boot/dts/tegra124.dtsi | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
arch/arm64/boot/dts/apm-storm.dtsi | 2 +-
arch/arm64/boot/dts/foundation-v8.dts | 2 +-
arch/arm64/boot/dts/rtsm_ve-aemv8a.dts | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
index ea288f0..40aacc9 100644
--- a/arch/arm/boot/dts/axm55xx.dtsi
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -62,7 +62,7 @@
#address-cells = 0;
interrupt-controller;
reg = 0x20 0x01001000 0 0x1000,
- 0x20 0x01002000 0 0x1000,
+ 0x20 0x01002000 0 0x2000,
0x20 0x01004000 0 0x2000,
0x20 0x01006000 0 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c29945e..65329ff 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -46,7 +46,7 @@
interrupt-controller;
#interrupt-cells = 3;
reg = 0x48211000 0x1000,
- 0x48212000 0x1000,
+ 0x48212000 0x2000,
0x48214000 0x2000,
0x48216000 0x2000;
interrupts = GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH);
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
index 2ccbb57f..c15e7e0 100644
--- a/arch/arm/boot/dts/ecx-2000.dts
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -99,7 +99,7 @@
interrupt-controller;
interrupts = 1 9 0xf04;
reg = 0xfff11000 0x1000,
- 0xfff12000 0x1000,
+ 0xfff12000 0x2000,
0xfff14000 0x2000,
0xfff16000 0x2000;
};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 3e678fa..bbd177a 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -173,7 +173,7 @@
#interrupt-cells = 3;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000 0x2000;
interrupts = 1 9 0xf04;
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 79d0608..15fdc3b 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -44,7 +44,7 @@
#interrupt-cells = 3;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000 0x2000;
interrupts = 1 9 0xf04;
diff --git a/arch/arm/boot/dts/exynos5260.dtsi
b/arch/arm/boot/dts/exynos5260.dtsi
index 5398a60..c0e2341 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -161,7 +161,7 @@
#size-cells = 0;
interrupt-controller;
reg = 0x10481000 0x1000,
- 0x10482000 0x1000,
+ 0x10482000 0x2000,
0x10484000 0x2000,
0x10486000
Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
arch/arm/boot/dts/exynos3250.dtsi | 2 +-
arch/arm/boot/dts/exynos5.dtsi | 2 +-
arch/arm/boot/dts/exynos5260.dtsi | 2 +-
arch/arm/boot/dts/exynos5410.dtsi | 2 +-
arch/arm/boot/dts/exynos5440.dtsi | 2 +-
arch/arm/boot/dts/omap5.dtsi| 2 +-
arch/arm/boot/dts/r8a73a4.dtsi | 2 +-
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi| 2 +-
arch/arm/boot/dts/sun7i-a20.dtsi| 2 +-
arch/arm/boot/dts/tegra114.dtsi | 2 +-
arch/arm/boot/dts/tegra124.dtsi | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 2 +-
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
arch/arm64/boot/dts/apm-storm.dtsi | 2 +-
arch/arm64/boot/dts/foundation-v8.dts | 2 +-
arch/arm64/boot/dts/rtsm_ve-aemv8a.dts | 2 +-
21 files changed, 21 insertions(+), 21 deletions(-)
For the Tegra114 and Tegra124 patches:
Tested-by: Thierry Reding tred...@nvidia.com
Acked-by: Thierry Reding tred...@nvidia.com
pgpOr175p_rJn.pgp
Description: PGP signature
Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
What's your plan for making the kernel change? Updating the dts files
is good, but that doesn't immediately help you if you have old dtbs.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
Acked-by: Rob Herring r...@kernel.org
Rob
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Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
On Wed, Jun 25 2014 at 01:21:17 PM, Rob Herring robherri...@gmail.com wrote:
On Wed, Jun 25, 2014 at 5:37 AM, Marc Zyngier marc.zyng...@arm.com wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
What's your plan for making the kernel change? Updating the dts files
is good, but that doesn't immediately help you if you have old dtbs.
See at the end of https://lkml.org/lkml/2014/6/25/243
Basically, we stay with a GICv1 behaviour if we detect the mess.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/axm55xx.dtsi | 2 +-
arch/arm/boot/dts/dra7.dtsi | 2 +-
arch/arm/boot/dts/ecx-2000.dts | 2 +-
Acked-by: Rob Herring r...@kernel.org
Thanks,
M.
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Re: [PATCH] arm/arm64: DT: Fix GICv2 CPU interface size
On Wed, Jun 25, 2014 at 11:37:54AM +0100, Marc Zyngier wrote:
All the Cortex-{A7,A15} implementations are using a GICv2. Same for
the current arm64 platforms.
Turns out that most of these platforms have described their GIC CPU
interface size as being 4kB. while it is actually 8kB (the GICC_DIR
register lives at offset 0x1000).
This was found when converting the GIC driver to use EOImode==1 on
GICv2-based systems. It uses the GICC_DIR register, and the result
is a very early firework...
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
Just tested this on an Allwinner A31.
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
Tested-by: Maxime Ripard maxime.rip...@free-electrons.com
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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