Re: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
On Wed, Aug 15, 2012 at 10:10 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
+ pinctrl@1140 {
+ uart0_data: uart0-data {
+ samsung,pins = gpa0-0, gpa0-1;
+ samsung,pin-function = 0x2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
Apart from the pin-pud and pin-drv stuff this patch looks fine. These two
things I want to discuss in the other mail thread (controller core) first.
Yours,
Linus Walleij
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Re: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
Re: samsung,pin-function samsung,pin-pud samsung,pin-drv - why can't
these be one property, why take the space to define them individually
instead of in an array of 3 values under one property name?
--
Matt Sealey m...@genesi-usa.com
Product Development Analyst, Genesi USA, Inc.
On Wed, Aug 15, 2012 at 3:10 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 457
+
arch/arm/boot/dts/exynos4210.dtsi | 37 +++
2 files changed, 494 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as
device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1140 {
+ uart0_data: uart0-data {
+ samsung,pins = gpa0-0, gpa0-1;
+ samsung,pin-function = 0x2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = gpa0-2, gpa0-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = gpa0-4, gpa0-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = gpb-0, gpb-2, gpb-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins =
Re: [PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
On 17 August 2012 00:26, Matt Sealey m...@genesi-usa.com wrote:
Re: samsung,pin-function samsung,pin-pud samsung,pin-drv - why can't
these be one property, why take the space to define them individually
instead of in an array of 3 values under one property name?
Samsung pinctrl driver was written to be usable on all of the Samsung
application processors starting from 24xx series to the latest
Exynos5.
The gpio/pinmux/pinconfig controllers on these SoC have varying
capabilities. Some of the banks in s3c24xx series support mux function
but do not support pull up/down (pud) or driver strength (drv).
s3c64xx soc's have banks that support pin mux and 'pud' but do not
support 'drv'. And there are banks that do not support mux function
but support 'pud' and 'drv'. Further, a given SoC can have multiple
combinations of different bank types.
In addition to this, there are two more properties for mux and pud
values in power down mode in some of the samsung SoC's.
To keep the bindings common across all the possible Samsung SoC's, the
mux, pud and drv properties were split so that the parsing code in the
Samsung pinctrl driver remains generic for all the possible
combinations of pin banks and SoC's.
Thanks,
Thomas.
--
Matt Sealey m...@genesi-usa.com
Product Development Analyst, Genesi USA, Inc.
On Wed, Aug 15, 2012 at 3:10 PM, Thomas Abraham
thomas.abra...@linaro.org wrote:
Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 457
+
arch/arm/boot/dts/exynos4210.dtsi | 37 +++
2 files changed, 494 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as
device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1140 {
+ uart0_data: uart0-data {
+ samsung,pins = gpa0-0, gpa0-1;
+ samsung,pin-function = 0x2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = gpa0-2, gpa0-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = gpa0-4, gpa0-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = gpa1-2, gpa1-3;
+
[PATCH 1/2] ARM: dts: Add pinctrl node entries for Samsung Exynos4210 SoC
Add pinctrl driver nodes for the three instances of pin controllers
in Samsung Exynos4210 SoC and add the pin group nodes available in the
each of those three instances.
Cc: Kukjin Kim kgene@samsung.com
Signed-off-by: Thomas Abraham thomas.abra...@linaro.org
---
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 457 +
arch/arm/boot/dts/exynos4210.dtsi | 37 +++
2 files changed, 494 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/exynos4210-pinctrl.dtsi
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
new file mode 100644
index 000..b12cf27
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ * Copyright (c) 2011-2012 Linaro Ltd.
+ * www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+ pinctrl@1140 {
+ uart0_data: uart0-data {
+ samsung,pins = gpa0-0, gpa0-1;
+ samsung,pin-function = 0x2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart0_fctl: uart0-fctl {
+ samsung,pins = gpa0-2, gpa0-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_data: uart1-data {
+ samsung,pins = gpa0-4, gpa0-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart1_fctl: uart1-fctl {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c2_bus: i2c2-bus {
+ samsung,pins = gpa0-6, gpa0-7;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_data: uart2-data {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart2_fctl: uart2-fctl {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_a: uart-audio-a {
+ samsung,pins = gpa1-0, gpa1-1;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ i2c3_bus: i2c3-bus {
+ samsung,pins = gpa1-2, gpa1-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ uart3_data: uart3-data {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ uart_audio_b: uart-audio-b {
+ samsung,pins = gpa1-4, gpa1-5;
+ samsung,pin-function = 4;
+ samsung,pin-pud = 0;
+ samsung,pin-drv = 0;
+ };
+
+ spi0_bus: spi0-bus {
+ samsung,pins = gpb-0, gpb-2, gpb-3;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ i2c4_bus: i2c4-bus {
+ samsung,pins = gpb-2, gpb-3;
+ samsung,pin-function = 3;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ spi1_bus: spi1-bus {
+ samsung,pins = gpb-4, gpb-6, gpb-7;
+ samsung,pin-function = 2;
+ samsung,pin-pud = 3;
+ samsung,pin-drv = 0;
+ };
+
+ i2c5_bus: i2c5-bus {
+
