Re: [PATCH 10/10] drm/exynos/decon5433: add support for DECON-TV

[Inki Dae]

Hi Andrzej,


2015년 10월 20일 18:22에 Andrzej Hajda 이(가) 쓴 글:

DECON-TV IP is responsible for generating video stream which is transferred
to HDMI IP. It is almost fully compatible with DECON IP.

The patch is based on initial work of Hyungwon Hwang.

Signed-off-by: Andrzej Hajda 
---
  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 154 --
  include/video/exynos5433_decon.h  |  29 +
  2 files changed, 122 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 3c9aa4e..fbe1b31 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -13,6 +13,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 

@@ -37,6 +38,12 @@ static const char * const decon_clks_name[] = {
"sclk_decon_eclk",
  };

+enum decon_iftype {
+   IFTYPE_RGB,
+   IFTYPE_I80,
+   IFTYPE_HDMI
+};
+
  enum decon_flag_bits {
BIT_CLKS_ENABLED,
BIT_IRQS_ENABLED,
@@ -53,7 +60,8 @@ struct decon_context {
struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
int pipe;
unsigned long   flags;
-   booli80_if;
+   enum decon_iftype   out_type;
+   int first_win;
  };

  static const uint32_t decon_formats[] = {
@@ -80,7 +88,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc)

if (test_and_set_bit(BIT_IRQS_ENABLED, >flags)) {
val = VIDINTCON0_INTEN;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDINTCON0_FRAMEDONE;
else
val |= VIDINTCON0_INTFRMEN;
@@ -104,8 +112,11 @@ static void decon_disable_vblank(struct exynos_drm_crtc 
*crtc)

  static void decon_setup_trigger(struct decon_context *ctx)
  {
-   u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
-   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
+   u32 val = (ctx->out_type != IFTYPE_HDMI)
+   ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
+   : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
writel(val, ctx->addr + DECON_TRIGCON);
  }

@@ -118,13 +129,22 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
if (test_bit(BIT_SUSPENDED, >flags))
return;

+   if (ctx->out_type == IFTYPE_HDMI) {
+   m->crtc_hsync_start = m->crtc_hdisplay + 10;
+   m->crtc_hsync_end = m->crtc_htotal - 92;
+   m->crtc_vsync_start = m->crtc_vdisplay + 1;
+   m->crtc_vsync_end = m->crtc_vsync_start + 1;
+   }
+
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
+
/* enable clock gate */
val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
writel(val, ctx->addr + DECON_CMU);

/* lcd on and use command if */
val = VIDOUT_LCD_ON;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDOUT_COMMAND_IF;
else
val |= VIDOUT_RGB_IF;
@@ -134,7 +154,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
VIDTCON2_HOZVAL(m->hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON2);

-   if (!ctx->i80_if) {
+   if (ctx->out_type != IFTYPE_I80) {
val = VIDTCON00_VBPD_F(
m->crtc_vtotal - m->crtc_vsync_end - 1) |
VIDTCON00_VFPD_F(
@@ -159,15 +179,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
decon_setup_trigger(ctx);

/* enable output and display signal */
-   val = VIDCON0_ENVID | VIDCON0_ENVID_F;
-   writel(val, ctx->addr + DECON_VIDCON0);
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
  }

-#define COORDINATE_X(x)(((x) & 0xfff) << 12)
-#define COORDINATE_Y(x)((x) & 0xfff)
-#define OFFSIZE(x) (((x) & 0x3fff) << 14)
-#define PAGEWIDTH(x)   ((x) & 0x3fff)
-
  static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 struct drm_framebuffer *fb)
  {
@@ -238,6 +252,10 @@ static void decon_atomic_begin(struct exynos_drm_crtc 
*crtc,
decon_shadow_protect_win(ctx, plane->zpos, true);
  }

+#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
+#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
+#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
+
  static void decon_update_plane(struct exynos_drm_crtc *crtc,
   struct exynos_drm_plane *plane)
  {
@@ -271,8 +289,12 @@ static void 

Re: [PATCH 10/10] drm/exynos/decon5433: add support for DECON-TV

[Andrzej Hajda]

On 10/23/2015 01:55 PM, Inki Dae wrote:
> Hi Andrzej,
>
>
> 2015년 10월 20일 18:22에 Andrzej Hajda 이(가) 쓴 글:
>> DECON-TV IP is responsible for generating video stream which is transferred
>> to HDMI IP. It is almost fully compatible with DECON IP.
>>
>> The patch is based on initial work of Hyungwon Hwang.
>>
>> Signed-off-by: Andrzej Hajda 
>> ---
>>   drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 154 
>> --
>>   include/video/exynos5433_decon.h  |  29 +
>>   2 files changed, 122 insertions(+), 61 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
>> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> index 3c9aa4e..fbe1b31 100644
>> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
>> @@ -13,6 +13,7 @@
>>   #include 
>>   #include 
>>   #include 
>> +#include 
>>   #include 
>>   #include 
>>
>> @@ -37,6 +38,12 @@ static const char * const decon_clks_name[] = {
>>  "sclk_decon_eclk",
>>   };
>>
>> +enum decon_iftype {
>> +IFTYPE_RGB,
>> +IFTYPE_I80,
>> +IFTYPE_HDMI
>> +};
>> +
>>   enum decon_flag_bits {
>>  BIT_CLKS_ENABLED,
>>  BIT_IRQS_ENABLED,
>> @@ -53,7 +60,8 @@ struct decon_context {
>>  struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
>>  int pipe;
>>  unsigned long   flags;
>> -booli80_if;
>> +enum decon_iftype   out_type;
>> +int first_win;
>>   };
>>
>>   static const uint32_t decon_formats[] = {
>> @@ -80,7 +88,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc 
>> *crtc)
>>
>>  if (test_and_set_bit(BIT_IRQS_ENABLED, >flags)) {
>>  val = VIDINTCON0_INTEN;
>> -if (ctx->i80_if)
>> +if (ctx->out_type == IFTYPE_I80)
>>  val |= VIDINTCON0_FRAMEDONE;
>>  else
>>  val |= VIDINTCON0_INTFRMEN;
>> @@ -104,8 +112,11 @@ static void decon_disable_vblank(struct exynos_drm_crtc 
>> *crtc)
>>
>>   static void decon_setup_trigger(struct decon_context *ctx)
>>   {
>> -u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
>> -TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
>> +u32 val = (ctx->out_type != IFTYPE_HDMI)
>> +? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
>> +  TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
>> +: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
>> +  TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
>>  writel(val, ctx->addr + DECON_TRIGCON);
>>   }
>>
>> @@ -118,13 +129,22 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
>>  if (test_bit(BIT_SUSPENDED, >flags))
>>  return;
>>
>> +if (ctx->out_type == IFTYPE_HDMI) {
>> +m->crtc_hsync_start = m->crtc_hdisplay + 10;
>> +m->crtc_hsync_end = m->crtc_htotal - 92;
>> +m->crtc_vsync_start = m->crtc_vdisplay + 1;
>> +m->crtc_vsync_end = m->crtc_vsync_start + 1;
>> +}
>> +
>> +decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
>> +
>>  /* enable clock gate */
>>  val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
>>  writel(val, ctx->addr + DECON_CMU);
>>
>>  /* lcd on and use command if */
>>  val = VIDOUT_LCD_ON;
>> -if (ctx->i80_if)
>> +if (ctx->out_type == IFTYPE_I80)
>>  val |= VIDOUT_COMMAND_IF;
>>  else
>>  val |= VIDOUT_RGB_IF;
>> @@ -134,7 +154,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
>>  VIDTCON2_HOZVAL(m->hdisplay - 1);
>>  writel(val, ctx->addr + DECON_VIDTCON2);
>>
>> -if (!ctx->i80_if) {
>> +if (ctx->out_type != IFTYPE_I80) {
>>  val = VIDTCON00_VBPD_F(
>>  m->crtc_vtotal - m->crtc_vsync_end - 1) |
>>  VIDTCON00_VFPD_F(
>> @@ -159,15 +179,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
>>  decon_setup_trigger(ctx);
>>
>>  /* enable output and display signal */
>> -val = VIDCON0_ENVID | VIDCON0_ENVID_F;
>> -writel(val, ctx->addr + DECON_VIDCON0);
>> +decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
>>   }
>>
>> -#define COORDINATE_X(x) (((x) & 0xfff) << 12)
>> -#define COORDINATE_Y(x) ((x) & 0xfff)
>> -#define OFFSIZE(x)  (((x) & 0x3fff) << 14)
>> -#define PAGEWIDTH(x)((x) & 0x3fff)
>> -
>>   static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int 
>> win,
>>   struct drm_framebuffer *fb)
>>   {
>> @@ -238,6 +252,10 @@ static void decon_atomic_begin(struct exynos_drm_crtc 
>> *crtc,
>>  decon_shadow_protect_win(ctx, plane->zpos, true);
>>   }
>>
>> +#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
>> +#define COORDINATE_X(x) BIT_VAL((x), 

Re: [PATCH 10/10] drm/exynos/decon5433: add support for DECON-TV

[Inki Dae]

2015-10-23 22:03 GMT+09:00 Andrzej Hajda :
>
> On 10/23/2015 01:55 PM, Inki Dae wrote:
> > Hi Andrzej,
> >
> >
> > 2015년 10월 20일 18:22에 Andrzej Hajda 이(가) 쓴 글:
> >> DECON-TV IP is responsible for generating video stream which is transferred
> >> to HDMI IP. It is almost fully compatible with DECON IP.
> >>
> >> The patch is based on initial work of Hyungwon Hwang.
> >>
> >> Signed-off-by: Andrzej Hajda 
> >> ---
> >>   drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 154 
> >> --
> >>   include/video/exynos5433_decon.h  |  29 +
> >>   2 files changed, 122 insertions(+), 61 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
> >> b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> >> index 3c9aa4e..fbe1b31 100644
> >> --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> >> +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
> >> @@ -13,6 +13,7 @@
> >>   #include 
> >>   #include 
> >>   #include 
> >> +#include 
> >>   #include 
> >>   #include 
> >>
> >> @@ -37,6 +38,12 @@ static const char * const decon_clks_name[] = {
> >>  "sclk_decon_eclk",
> >>   };
> >>
> >> +enum decon_iftype {
> >> +IFTYPE_RGB,
> >> +IFTYPE_I80,
> >> +IFTYPE_HDMI
> >> +};
> >> +
> >>   enum decon_flag_bits {
> >>  BIT_CLKS_ENABLED,
> >>  BIT_IRQS_ENABLED,
> >> @@ -53,7 +60,8 @@ struct decon_context {
> >>  struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
> >>  int pipe;
> >>  unsigned long   flags;
> >> -booli80_if;
> >> +enum decon_iftype   out_type;
> >> +int first_win;
> >>   };
> >>
> >>   static const uint32_t decon_formats[] = {
> >> @@ -80,7 +88,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc 
> >> *crtc)
> >>
> >>  if (test_and_set_bit(BIT_IRQS_ENABLED, >flags)) {
> >>  val = VIDINTCON0_INTEN;
> >> -if (ctx->i80_if)
> >> +if (ctx->out_type == IFTYPE_I80)
> >>  val |= VIDINTCON0_FRAMEDONE;
> >>  else
> >>  val |= VIDINTCON0_INTFRMEN;
> >> @@ -104,8 +112,11 @@ static void decon_disable_vblank(struct 
> >> exynos_drm_crtc *crtc)
> >>
> >>   static void decon_setup_trigger(struct decon_context *ctx)
> >>   {
> >> -u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
> >> -TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
> >> +u32 val = (ctx->out_type != IFTYPE_HDMI)
> >> +? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
> >> +  TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
> >> +: TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
> >> +  TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
> >>  writel(val, ctx->addr + DECON_TRIGCON);
> >>   }
> >>
> >> @@ -118,13 +129,22 @@ static void decon_commit(struct exynos_drm_crtc 
> >> *crtc)
> >>  if (test_bit(BIT_SUSPENDED, >flags))
> >>  return;
> >>
> >> +if (ctx->out_type == IFTYPE_HDMI) {
> >> +m->crtc_hsync_start = m->crtc_hdisplay + 10;
> >> +m->crtc_hsync_end = m->crtc_htotal - 92;
> >> +m->crtc_vsync_start = m->crtc_vdisplay + 1;
> >> +m->crtc_vsync_end = m->crtc_vsync_start + 1;
> >> +}
> >> +
> >> +decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
> >> +
> >>  /* enable clock gate */
> >>  val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
> >>  writel(val, ctx->addr + DECON_CMU);
> >>
> >>  /* lcd on and use command if */
> >>  val = VIDOUT_LCD_ON;
> >> -if (ctx->i80_if)
> >> +if (ctx->out_type == IFTYPE_I80)
> >>  val |= VIDOUT_COMMAND_IF;
> >>  else
> >>  val |= VIDOUT_RGB_IF;
> >> @@ -134,7 +154,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
> >>  VIDTCON2_HOZVAL(m->hdisplay - 1);
> >>  writel(val, ctx->addr + DECON_VIDTCON2);
> >>
> >> -if (!ctx->i80_if) {
> >> +if (ctx->out_type != IFTYPE_I80) {
> >>  val = VIDTCON00_VBPD_F(
> >>  m->crtc_vtotal - m->crtc_vsync_end - 1) |
> >>  VIDTCON00_VFPD_F(
> >> @@ -159,15 +179,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
> >>  decon_setup_trigger(ctx);
> >>
> >>  /* enable output and display signal */
> >> -val = VIDCON0_ENVID | VIDCON0_ENVID_F;
> >> -writel(val, ctx->addr + DECON_VIDCON0);
> >> +decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, 
> >> ~0);
> >>   }
> >>
> >> -#define COORDINATE_X(x) (((x) & 0xfff) << 12)
> >> -#define COORDINATE_Y(x) ((x) & 0xfff)
> >> -#define OFFSIZE(x)  (((x) & 0x3fff) << 14)
> >> -#define PAGEWIDTH(x)((x) & 0x3fff)
> >> -
> >>   static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int 
> >> win,
> >>  

[PATCH 10/10] drm/exynos/decon5433: add support for DECON-TV

[Andrzej Hajda]

DECON-TV IP is responsible for generating video stream which is transferred
to HDMI IP. It is almost fully compatible with DECON IP.

The patch is based on initial work of Hyungwon Hwang.

Signed-off-by: Andrzej Hajda 
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 154 --
 include/video/exynos5433_decon.h  |  29 +
 2 files changed, 122 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c 
b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 3c9aa4e..fbe1b31 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -13,6 +13,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -37,6 +38,12 @@ static const char * const decon_clks_name[] = {
"sclk_decon_eclk",
 };
 
+enum decon_iftype {
+   IFTYPE_RGB,
+   IFTYPE_I80,
+   IFTYPE_HDMI
+};
+
 enum decon_flag_bits {
BIT_CLKS_ENABLED,
BIT_IRQS_ENABLED,
@@ -53,7 +60,8 @@ struct decon_context {
struct clk  *clks[ARRAY_SIZE(decon_clks_name)];
int pipe;
unsigned long   flags;
-   booli80_if;
+   enum decon_iftype   out_type;
+   int first_win;
 };
 
 static const uint32_t decon_formats[] = {
@@ -80,7 +88,7 @@ static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
 
if (test_and_set_bit(BIT_IRQS_ENABLED, >flags)) {
val = VIDINTCON0_INTEN;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDINTCON0_FRAMEDONE;
else
val |= VIDINTCON0_INTFRMEN;
@@ -104,8 +112,11 @@ static void decon_disable_vblank(struct exynos_drm_crtc 
*crtc)
 
 static void decon_setup_trigger(struct decon_context *ctx)
 {
-   u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
-   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN;
+   u32 val = (ctx->out_type != IFTYPE_HDMI)
+   ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
+   : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
+ TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
writel(val, ctx->addr + DECON_TRIGCON);
 }
 
@@ -118,13 +129,22 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
if (test_bit(BIT_SUSPENDED, >flags))
return;
 
+   if (ctx->out_type == IFTYPE_HDMI) {
+   m->crtc_hsync_start = m->crtc_hdisplay + 10;
+   m->crtc_hsync_end = m->crtc_htotal - 92;
+   m->crtc_vsync_start = m->crtc_vdisplay + 1;
+   m->crtc_vsync_end = m->crtc_vsync_start + 1;
+   }
+
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
+
/* enable clock gate */
val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
writel(val, ctx->addr + DECON_CMU);
 
/* lcd on and use command if */
val = VIDOUT_LCD_ON;
-   if (ctx->i80_if)
+   if (ctx->out_type == IFTYPE_I80)
val |= VIDOUT_COMMAND_IF;
else
val |= VIDOUT_RGB_IF;
@@ -134,7 +154,7 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
VIDTCON2_HOZVAL(m->hdisplay - 1);
writel(val, ctx->addr + DECON_VIDTCON2);
 
-   if (!ctx->i80_if) {
+   if (ctx->out_type != IFTYPE_I80) {
val = VIDTCON00_VBPD_F(
m->crtc_vtotal - m->crtc_vsync_end - 1) |
VIDTCON00_VFPD_F(
@@ -159,15 +179,9 @@ static void decon_commit(struct exynos_drm_crtc *crtc)
decon_setup_trigger(ctx);
 
/* enable output and display signal */
-   val = VIDCON0_ENVID | VIDCON0_ENVID_F;
-   writel(val, ctx->addr + DECON_VIDCON0);
+   decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 }
 
-#define COORDINATE_X(x)(((x) & 0xfff) << 12)
-#define COORDINATE_Y(x)((x) & 0xfff)
-#define OFFSIZE(x) (((x) & 0x3fff) << 14)
-#define PAGEWIDTH(x)   ((x) & 0x3fff)
-
 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 struct drm_framebuffer *fb)
 {
@@ -238,6 +252,10 @@ static void decon_atomic_begin(struct exynos_drm_crtc 
*crtc,
decon_shadow_protect_win(ctx, plane->zpos, true);
 }
 
+#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
+#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
+#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
+
 static void decon_update_plane(struct exynos_drm_crtc *crtc,
   struct exynos_drm_plane *plane)
 {
@@ -271,8 +289,12 @@ static void decon_update_plane(struct exynos_drm_crtc 
*crtc,
val = plane->dma_addr[0] + pitch *