Re: [PATCH v2 06/10] clk: exynos5420: register clocks using common clock framework
On 14 June 2013 22:56, Andrew Bresticker wrote: > Hi Chander, > >> + [Core Clocks] >> + >> + ClockID >> + >> + >> + oscclk 1 > > I know the UM refers to this as 'oscclk', but could we instead call > this 'fin_pll' to be consistent with Exynos 4 and Exynos 5250? I will rename it to make consistent. Thanks. > > Thanks, > Andrew -- with warm regards, Chander Kashyap -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 06/10] clk: exynos5420: register clocks using common clock framework
Hi Chander, > + [Core Clocks] > + > + ClockID > + > + > + oscclk 1 I know the UM refers to this as 'oscclk', but could we instead call this 'fin_pll' to be consistent with Exynos 4 and Exynos 5250? Thanks, Andrew -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 06/10] clk: exynos5420: register clocks using common clock framework
The Exynos5420 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Chander Kashyap Signed-off-by: Thomas Abraham --- .../devicetree/bindings/clock/exynos5420-clock.txt | 201 ++ drivers/clk/samsung/Makefile |1 + drivers/clk/samsung/clk-exynos5420.c | 762 3 files changed, 964 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt create mode 100644 drivers/clk/samsung/clk-exynos5420.c diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt new file mode 100644 index 000..095d643 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -0,0 +1,201 @@ +* Samsung Exynos5420 Clock Controller + +The Exynos5420 clock controller generates and supplies clock to various +controllers within the Exynos5420 SoC. + +Required Properties: + +- comptible: should be one of the following. + - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC. + +- reg: physical base address of the controller and length of memory mapped + region. + +- #clock-cells: should be 1. + +The following is the list of clocks generated by the controller. Each clock is +assigned an identifier and client nodes use this identifier to specify the +clock which they consume. + + + [Core Clocks] + + ClockID + + + oscclk 1 + + [Clock Gate for Special Clocks] + + ClockID + + sclk_uart0 128 + sclk_uart1 129 + sclk_uart2 130 + sclk_uart3 131 + sclk_mmc0132 + sclk_mmc1133 + sclk_mmc2134 + sclk_spi0135 + sclk_spi1136 + sclk_spi2137 + sclk_i2s1138 + sclk_i2s2139 + sclk_pcm1140 + sclk_pcm2141 + sclk_spdif 142 + sclk_hdmi143 + sclk_pixel 144 + sclk_dp1 145 + sclk_mipi1 146 + sclk_fimd1 147 + sclk_maudio0 148 + sclk_maupcm0 149 + sclk_usbd300 150 + sclk_usbd301 151 + sclk_usbphy300 152 + sclk_usbphy301 153 + sclk_unipro 154 + sclk_pwm 155 + sclk_gscl_wa 156 + sclk_gscl_wb 157 + + [Peripheral Clock Gates] + + ClockID + + + aclk66_peric 256 + uart0257 + uart1258 + uart2259 + uart3260 + i2c0 261 + i2c1 262 + i2c2 263 + i2c3 264 + i2c4 265 + i2c5 266 + i2c6 267 + i2c7 268 + i2c_hdmi 269 + tsadc270 + spi0 271 + spi1 272 + spi2 273 + keyif274 + i2s1 275 + i2s2 276 + pcm1 277 + pcm2 278 + pwm 279 + spdif280 + i2c8 281 + i2c9 282 + i2c10283 + aclk66_psgen 300 + chipid 301 + sysreg 302 + tzpc0303 + tzpc1304 + tzpc2305 + tzpc3306 + tzpc4307 + tzpc5308 + tzpc6309 + tzpc7310 + tzpc8311 + tzpc9312 + hdmi_cec 313 + seckey 314 + mct 315 + wdt 316 + rtc 317 + tmu 318 + tmu_gpu 319 + pclk66_gpio 330 + aclk200_fsys2350 + mmc0 351 + mmc1 352 + mmc2 353 + sromc354 + ufs 355 + aclk200_fsys 360 + tsi 361 + pdma0362 + pdma1363 + rtic 364 + usbh20 365 + usbd300 366 + usbd301 377 + aclk400_mscl 380 + mscl0381 + mscl1382 + mscl2383 + smmu_mscl0 384 + smmu_mscl1 385 + smmu_mscl2 386 + aclk333 400 + mfc 401 + smmu_mfcl402 + smmu_mfcr403 + aclk200_disp1410 + dsim1411 + dp1 412
