Re: [PATCH v2 06/21] ARM: tegra: remove old LIC support
On 2015-01-08 11:29, Thierry Reding wrote: On Wed, Jan 07, 2015 at 05:42:41PM +, Marc Zyngier wrote: [...] diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c [...] void __init tegra_init_irq(void) { - int i; - void __iomem *distbase; - - if (of_find_matching_node(NULL, tegra_ictlr_match)) - goto skip_extn_setup; - - tegra_legacy_irq_syscore_init(); - - distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); - num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f; - - if (num_ictlrs ARRAY_SIZE(ictlr_reg_base)) { - WARN(1, Too many (%d) interrupt controllers found. Maximum is %d., - num_ictlrs, ARRAY_SIZE(ictlr_reg_base)); - num_ictlrs = ARRAY_SIZE(ictlr_reg_base); - } - - for (i = 0; i num_ictlrs; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(~0, ictlr + ICTLR_CPU_IER_CLR); - writel(0, ictlr + ICTLR_CPU_IEP_CLASS); - } - - gic_arch_extn.irq_ack = tegra_ack; - gic_arch_extn.irq_eoi = tegra_eoi; - gic_arch_extn.irq_mask = tegra_mask; - gic_arch_extn.irq_unmask = tegra_unmask; - gic_arch_extn.irq_retrigger = tegra_retrigger; - gic_arch_extn.irq_set_wake = tegra_set_wake; - gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; + if (!of_find_matching_node(NULL, tegra_ictlr_match)) + pr_warn(Outdated DT detected, suspend/resume will NOT work\n); I'm not very happy about the ABI breakage here, but I also realize that we need this change to properly describe the hardware. To make it more obvious that people really should update their DTBs, maybe turn this into a WARN()? Sure, done. -skip_extn_setup: tegra114_gic_cpu_pm_registration(); I'm not intimately familiar with the GIC, but is this really SoC specific? Doesn't anybody else need this? Comparing to the GIC spec the write of 0x1e0 to the GIC_CPU_CTRL register (which I assume corresponds to GICC_CTLR in the spec), this simply disables the IRQ and FIQ bypass signals for both group 0 and group 1. This seems to be a Tegra special, at least in mainline. But yes, I'd very much like to be able to remove this from platform code and make it part of the GIC driver if we can. Something for a subsequent patch series, I guess. Thanks, M. -- Fast, cheap, reliable. Pick two. -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 06/21] ARM: tegra: remove old LIC support
On Wed, Jan 07, 2015 at 05:42:41PM +, Marc Zyngier wrote: [...] diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c [...] void __init tegra_init_irq(void) { - int i; - void __iomem *distbase; - - if (of_find_matching_node(NULL, tegra_ictlr_match)) - goto skip_extn_setup; - - tegra_legacy_irq_syscore_init(); - - distbase = IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE); - num_ictlrs = readl_relaxed(distbase + GIC_DIST_CTR) 0x1f; - - if (num_ictlrs ARRAY_SIZE(ictlr_reg_base)) { - WARN(1, Too many (%d) interrupt controllers found. Maximum is %d., - num_ictlrs, ARRAY_SIZE(ictlr_reg_base)); - num_ictlrs = ARRAY_SIZE(ictlr_reg_base); - } - - for (i = 0; i num_ictlrs; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - writel(~0, ictlr + ICTLR_CPU_IER_CLR); - writel(0, ictlr + ICTLR_CPU_IEP_CLASS); - } - - gic_arch_extn.irq_ack = tegra_ack; - gic_arch_extn.irq_eoi = tegra_eoi; - gic_arch_extn.irq_mask = tegra_mask; - gic_arch_extn.irq_unmask = tegra_unmask; - gic_arch_extn.irq_retrigger = tegra_retrigger; - gic_arch_extn.irq_set_wake = tegra_set_wake; - gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; + if (!of_find_matching_node(NULL, tegra_ictlr_match)) + pr_warn(Outdated DT detected, suspend/resume will NOT work\n); I'm not very happy about the ABI breakage here, but I also realize that we need this change to properly describe the hardware. To make it more obvious that people really should update their DTBs, maybe turn this into a WARN()? -skip_extn_setup: tegra114_gic_cpu_pm_registration(); I'm not intimately familiar with the GIC, but is this really SoC specific? Doesn't anybody else need this? Comparing to the GIC spec the write of 0x1e0 to the GIC_CPU_CTRL register (which I assume corresponds to GICC_CTLR in the spec), this simply disables the IRQ and FIQ bypass signals for both group 0 and group 1. Thierry pgpVZ3oRmbaxp.pgp Description: PGP signature
[PATCH v2 06/21] ARM: tegra: remove old LIC support
Now that all DTs have been updated, entierely drop support for the non-DT code. This is likely to break platforms that do not update their DT, so print a warning at boot time. Signed-off-by: Marc Zyngier marc.zyng...@arm.com --- arch/arm/mach-tegra/iomap.h | 15 arch/arm/mach-tegra/irq.c | 201 +--- arch/arm/mach-tegra/irq.h | 6 -- 3 files changed, 2 insertions(+), 220 deletions(-) diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h index ee79808..81dc950 100644 --- a/arch/arm/mach-tegra/iomap.h +++ b/arch/arm/mach-tegra/iomap.h @@ -31,21 +31,6 @@ #define TEGRA_ARM_INT_DIST_BASE0x50041000 #define TEGRA_ARM_INT_DIST_SIZESZ_4K -#define TEGRA_PRIMARY_ICTLR_BASE 0x60004000 -#define TEGRA_PRIMARY_ICTLR_SIZE SZ_64 - -#define TEGRA_SECONDARY_ICTLR_BASE 0x60004100 -#define TEGRA_SECONDARY_ICTLR_SIZE SZ_64 - -#define TEGRA_TERTIARY_ICTLR_BASE 0x60004200 -#define TEGRA_TERTIARY_ICTLR_SIZE SZ_64 - -#define TEGRA_QUATERNARY_ICTLR_BASE0x60004300 -#define TEGRA_QUATERNARY_ICTLR_SIZESZ_64 - -#define TEGRA_QUINARY_ICTLR_BASE 0x60004400 -#define TEGRA_QUINARY_ICTLR_SIZE SZ_64 - #define TEGRA_TMR1_BASE0x60005000 #define TEGRA_TMR1_SIZESZ_8 diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index b37141d..a1befd3 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -30,43 +30,9 @@ #include board.h #include iomap.h -#define ICTLR_CPU_IEP_VFIQ 0x08 -#define ICTLR_CPU_IEP_FIR 0x14 -#define ICTLR_CPU_IEP_FIR_SET 0x18 -#define ICTLR_CPU_IEP_FIR_CLR 0x1c - -#define ICTLR_CPU_IER 0x20 -#define ICTLR_CPU_IER_SET 0x24 -#define ICTLR_CPU_IER_CLR 0x28 -#define ICTLR_CPU_IEP_CLASS0x2C - -#define ICTLR_COP_IER 0x30 -#define ICTLR_COP_IER_SET 0x34 -#define ICTLR_COP_IER_CLR 0x38 -#define ICTLR_COP_IEP_CLASS0x3c - -#define FIRST_LEGACY_IRQ 32 -#define TEGRA_MAX_NUM_ICTLRS 5 - #define SGI_MASK 0x -static int num_ictlrs; - -static void __iomem *ictlr_reg_base[] = { - IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE), - IO_ADDRESS(TEGRA_QUINARY_ICTLR_BASE), -}; - #ifdef CONFIG_PM_SLEEP -static u32 cop_ier[TEGRA_MAX_NUM_ICTLRS]; -static u32 cop_iep[TEGRA_MAX_NUM_ICTLRS]; -static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS]; -static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; - -static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; static void __iomem *tegra_gic_cpu_base; #endif @@ -83,140 +49,7 @@ bool tegra_pending_sgi(void) return false; } -static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg) -{ - void __iomem *base; - u32 mask; - - BUG_ON(irq FIRST_LEGACY_IRQ || - irq = FIRST_LEGACY_IRQ + num_ictlrs * 32); - - base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32]; - mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); - - __raw_writel(mask, base + reg); -} - -static void tegra_mask(struct irq_data *d) -{ - if (d-hwirq FIRST_LEGACY_IRQ) - return; - - tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_CLR); -} - -static void tegra_unmask(struct irq_data *d) -{ - if (d-hwirq FIRST_LEGACY_IRQ) - return; - - tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IER_SET); -} - -static void tegra_ack(struct irq_data *d) -{ - if (d-hwirq FIRST_LEGACY_IRQ) - return; - - tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR); -} - -static void tegra_eoi(struct irq_data *d) -{ - if (d-hwirq FIRST_LEGACY_IRQ) - return; - - tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_CLR); -} - -static int tegra_retrigger(struct irq_data *d) -{ - if (d-hwirq FIRST_LEGACY_IRQ) - return 0; - - tegra_irq_write_mask(d-hwirq, ICTLR_CPU_IEP_FIR_SET); - - return 1; -} - #ifdef CONFIG_PM_SLEEP -static int tegra_set_wake(struct irq_data *d, unsigned int enable) -{ - u32 irq = d-hwirq; - u32 index, mask; - - if (irq FIRST_LEGACY_IRQ || - irq = FIRST_LEGACY_IRQ + num_ictlrs * 32) - return -EINVAL; - - index = ((irq - FIRST_LEGACY_IRQ) / 32); - mask = BIT((irq - FIRST_LEGACY_IRQ) % 32); - if (enable) - ictlr_wake_mask[index] |= mask; - else - ictlr_wake_mask[index] = ~mask; - - return 0; -} - -static int tegra_legacy_irq_suspend(void) -{ - unsigned long flags; - int i; - - local_irq_save(flags); - for (i = 0; i num_ictlrs; i++) { - void __iomem *ictlr = ictlr_reg_base[i]; - /* Save interrupt state */ - cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); - cpu_iep[i] =