Re: [PATCH v3 1/2] ARM: EXYNOS: Add clock support for Gscaler
Hi Kukjin Kim,
thanks for the review comments.
On Wed, Aug 1, 2012 at 11:54 AM, Kukjin Kim kgene@samsung.com wrote:
Shaik Ameer Basha wrote:
Add required clock support for Gscaler for exynos5
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 100
++
1 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-
exynos/clock-exynos5.c
index 774533c..49a76b1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -552,6 +552,81 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
};
+/* for aclk_300_gscl_mid */
No need above comment which is certain.
Ok. I will remove all unnecessary comments.
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+ .clk = {
+ .name = mout_aclk_300_gscl_mid,
+ },
+ .sources = exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+/* for aclk_300_gscl_mid1 */
Same as above.
+static struct clk *exynos5_clkset_aclk_300_gscl_mid1_list[] = {
+ [0] = exynos5_clk_sclk_vpll.clk,
+ [1] = exynos5_clk_mout_cpll.clk,
+};
In this case, the above sources can be used for gscl_mid1 and disp1_mid as
well. So how about exynos5_clkset_mid1_list?
yes. you are right.
I will change the name as per your suggestion. (i.e., exynos5_clkset_mid1_list)
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+ .sources= exynos5_clkset_aclk_300_gscl_mid1_list,
+ .nr_sources =
ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_mid1_list),
+};
If so, need to update this.
Ok. I will update here too...
+
+
no need double empty lines.
ok. will remove the extra lines.
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+ .clk= {
+ .name = mout_aclk_300_gscl_mid1,
+ },
+ .sources = exynos5_clkset_aclk_300_gscl_mid1,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+/* for aclk_300_gscl */
no need useless comment.
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+ [0] = exynos5_clk_mout_aclk_300_gscl_mid.clk,
+ [1] = exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+ .sources= exynos5_clkset_aclk_300_gscl_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+ .clk= {
Tap please.
Ok. i will change that.
+ .name = mout_aclk_300_gscl,
+ },
+ .sources = exynos5_clkset_aclk_300_gscl,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
+ .clk= {
Same as above.
Ok. i will change that.
+ .name = dout_aclk_300_gscl,
+ .parent = exynos5_clk_mout_aclk_300_gscl.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
And I think, we don't need to define above 'clksrc_clk's?
Sorry. you are right. i will remove that.
+static struct clksrc_clk exynos5_clk_mdout_aclk_300_gscl = {
+ .clk= {
+ .name = mdout_aclk_300_gscl,
+ },
+ .sources = exynos5_clkset_aclk_300_gscl,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
[...]
Thanks.
Best regards,
Kgene.
--
Kukjin Kim kgene@samsung.com, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
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[PATCH v3 1/2] ARM: EXYNOS: Add clock support for Gscaler
Add required clock support for Gscaler for exynos5
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Signed-off-by: Prathyush K prathyus...@samsung.com
Signed-off-by: Shaik Ameer Basha shaik.am...@samsung.com
---
arch/arm/mach-exynos/clock-exynos5.c | 100 ++
1 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-exynos/clock-exynos5.c
b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c..49a76b1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -552,6 +552,81 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
};
+/* for aclk_300_gscl_mid */
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+ .clk = {
+ .name = mout_aclk_300_gscl_mid,
+ },
+ .sources = exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+/* for aclk_300_gscl_mid1 */
+static struct clk *exynos5_clkset_aclk_300_gscl_mid1_list[] = {
+ [0] = exynos5_clk_sclk_vpll.clk,
+ [1] = exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+ .sources= exynos5_clkset_aclk_300_gscl_mid1_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_mid1_list),
+};
+
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+ .clk= {
+ .name = mout_aclk_300_gscl_mid1,
+ },
+ .sources = exynos5_clkset_aclk_300_gscl_mid1,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+/* for aclk_300_gscl */
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+ [0] = exynos5_clk_mout_aclk_300_gscl_mid.clk,
+ [1] = exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+ .sources= exynos5_clkset_aclk_300_gscl_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+ .clk= {
+ .name = mout_aclk_300_gscl,
+ },
+ .sources = exynos5_clkset_aclk_300_gscl,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_aclk_300_gscl = {
+ .clk= {
+ .name = dout_aclk_300_gscl,
+ .parent = exynos5_clk_mout_aclk_300_gscl.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 12, .size = 3 },
+};
+
+/* for aclk_300_gscl_sub mux */
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+ [0] = clk_ext_xtal_mux,
+ [1] = exynos5_clk_dout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+ .sources= exynos5_clk_src_gscl_300_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+ .clk= {
+ .name = aclk_300_gscl,
+ },
+ .sources = exynos5_clk_src_gscl_300,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
static struct clk exynos5_init_clocks_off[] = {
{
.name = timers,
@@ -764,6 +839,26 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit= (1 18),
}, {
+ .name = gscl,
+ .devname= exynos-gsc.0,
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit= (1 0),
+ }, {
+ .name = gscl,
+ .devname= exynos-gsc.1,
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit= (1 1),
+ }, {
+ .name = gscl,
+ .devname= exynos-gsc.2,
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit= (1 2),
+ }, {
+ .name = gscl,
+ .devname= exynos-gsc.3,
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit= (1 3),
+ }, {
.name = SYSMMU_CLOCK_NAME,
.devname= SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
.enable = exynos5_clk_ip_mfc_ctrl,
@@ -1225,6 +1320,11 @@ static struct clksrc_clk *exynos5_sysclks[] = {
exynos5_clk_aclk_266,
exynos5_clk_aclk_200,
exynos5_clk_aclk_166,
+ exynos5_clk_aclk_300_gscl,
+ exynos5_clk_dout_aclk_300_gscl,
+ exynos5_clk_mout_aclk_300_gscl,
+ exynos5_clk_mout_aclk_300_gscl_mid,
+
