Re: [PATCH v3 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210

[Krzysztof Kozlowski]

On 11.12.2015 14:07, Chanwoo Choi wrote:
> This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
> one power line for all buses to translate data between DRAM and sub-blocks.
> 
> Following list specifies the detailed relation between DRAM and sub-blocks:
> - DMC/ACP clock for DMC (Dynamic Memory Controller)
> - ACLK200 clock for LCD0
> - ACLK100 clock for PERIL/PERIR/MFC(PCLK)
> - ACLK160 clock for CAM/TV/LCD0/LCD1
> - ACLK133 clock for FSYS/GPS
> - GDL/GDR clock for LEFTBUS/RIGHTBUS
> - SCLK_MFC clock for MFC
> 
> Signed-off-by: Chanwoo Choi 
> ---
>  arch/arm/boot/dts/exynos4210.dtsi | 159 
> ++
>  1 file changed, 159 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski 

Best regards,
Krzysztof


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[PATCH v3 16/20] ARM: dts: Add bus nodes using VDD_MIF for Exynos4210

[Chanwoo Choi]

This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has
one power line for all buses to translate data between DRAM and sub-blocks.

Following list specifies the detailed relation between DRAM and sub-blocks:
- DMC/ACP clock for DMC (Dynamic Memory Controller)
- ACLK200 clock for LCD0
- ACLK100 clock for PERIL/PERIR/MFC(PCLK)
- ACLK160 clock for CAM/TV/LCD0/LCD1
- ACLK133 clock for FSYS/GPS
- GDL/GDR clock for LEFTBUS/RIGHTBUS
- SCLK_MFC clock for MFC

Signed-off-by: Chanwoo Choi 
---
 arch/arm/boot/dts/exynos4210.dtsi | 159 ++
 1 file changed, 159 insertions(+)

diff --git a/arch/arm/boot/dts/exynos4210.dtsi 
b/arch/arm/boot/dts/exynos4210.dtsi
index c1cb8df6da07..2d9b02967105 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -257,6 +257,165 @@
power-domains = <_lcd1>;
#iommu-cells = <0>;
};
+
+   bus_dmc: bus_dmc {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_DMC>;
+   clock-names = "bus";
+   operating-points-v2 = <_dmc_opp_table>;
+   status = "disabled";
+   };
+
+   bus_acp: bus_acp {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_ACP>;
+   clock-names = "bus";
+   operating-points-v2 = <_acp_opp_table>;
+   status = "disabled";
+   };
+
+   bus_peri: bus_peri {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_ACLK100>;
+   clock-names = "bus";
+   operating-points-v2 = <_peri_opp_table>;
+   status = "disabled";
+   };
+
+   bus_fsys: bus_fsys {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_ACLK133>;
+   clock-names = "bus";
+   operating-points-v2 = <_fsys_opp_table>;
+   status = "disabled";
+   };
+
+   bus_display: bus_display {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_ACLK160>;
+   clock-names = "bus";
+   operating-points-v2 = <_display_opp_table>;
+   status = "disabled";
+   };
+
+   bus_lcd0: bus_lcd0 {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_ACLK200>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_leftbus: bus_leftbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDL>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_rightbus: bus_rightbus {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_DIV_GDR>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_mfc: bus_mfc {
+   compatible = "samsung,exynos-bus";
+   clocks = < CLK_SCLK_MFC>;
+   clock-names = "bus";
+   operating-points-v2 = <_leftbus_opp_table>;
+   status = "disabled";
+   };
+
+   bus_dmc_opp_table: opp_table1 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@13400 {
+   opp-hz = /bits/ 64 <13400>;
+   opp-microvolt = <1025000>;
+   };
+   opp@26700 {
+   opp-hz = /bits/ 64 <26700>;
+   opp-microvolt = <105>;
+   };
+   opp@4 {
+   opp-hz = /bits/ 64 <4>;
+   opp-microvolt = <115>;
+   };
+   };
+
+   bus_acp_opp_table: opp_table2 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@13400 {
+   opp-hz = /bits/ 64 <13400>;
+   };
+   opp@16000 {
+   opp-hz = /bits/ 64 <16000>;
+   };
+   opp@2 {
+   opp-hz = /bits/ 64 <2>;
+   };
+   };
+
+   bus_peri_opp_table: opp_table3 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@500 {
+   opp-hz = /bits/ 64 <500>;
+   };
+   opp@1 {
+   opp-hz = /bits/ 64 <1>;
+   };
+   };
+
+   bus_fsys_opp_table: opp_table4 {
+   compatible = "operating-points-v2";
+   opp-shared;
+
+   opp@1000 {
+   opp-hz = /bits/ 64 <1000>;
+