From: Hakjoo Kim ruppi@hardkernel.com
Add Samsung EXYNOS5410 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5410.
Signed-off-by: Hakjoo Kim ruppi@hardkernel.com
[AF: Rebased onto Exynos5260 and irq_chip consolidation]
Signed-off-by: Andreas Färber afaer...@suse.de
---
v2 - v3:
* Rebased (.svc, .{g,w}eint_{con,mask,pend} fields dropped)
v1 - v2:
* Filled in Sob from Hakjoo Kim
.../bindings/pinctrl/samsung-pinctrl.txt | 1 +
drivers/pinctrl/samsung/pinctrl-exynos.c | 107 +
drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
4 files changed, 111 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
index e82aaf492517..b87a176e730e 100644
--- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
@@ -17,6 +17,7 @@ Required Properties:
- samsung,exynos4x12-pinctrl: for Exynos4x12 compatible pin-controller.
- samsung,exynos5250-pinctrl: for Exynos5250 compatible pin-controller.
- samsung,exynos5260-pinctrl: for Exynos5260 compatible pin-controller.
+ - samsung,exynos5410-pinctrl: for Exynos5410 compatible pin-controller.
- samsung,exynos5420-pinctrl: for Exynos5420 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c
b/drivers/pinctrl/samsung/pinctrl-exynos.c
index d7154ed0b0eb..0580399a6587 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1084,6 +1084,113 @@ struct samsung_pin_ctrl exynos5260_pin_ctrl[] = {
},
};
+/* pin banks of exynos5410 pin-controller 0 */
+static struct samsung_pin_bank exynos5410_pin_banks0[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpa0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(6, 0x020, gpa1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpa2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(5, 0x060, gpb0, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(5, 0x080, gpb1, 0x10),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0A0, gpb2, 0x14),
+ EXYNOS_PIN_BANK_EINTG(4, 0x0C0, gpb3, 0x18),
+ EXYNOS_PIN_BANK_EINTG(7, 0x0E0, gpc0, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(4, 0x100, gpc3, 0x20),
+ EXYNOS_PIN_BANK_EINTG(7, 0x120, gpc1, 0x24),
+ EXYNOS_PIN_BANK_EINTG(7, 0x140, gpc2, 0x28),
+ EXYNOS_PIN_BANK_EINTN(2, 0x160, gpm5),
+ EXYNOS_PIN_BANK_EINTG(8, 0x180, gpd1, 0x2c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x1A0, gpe0, 0x30),
+ EXYNOS_PIN_BANK_EINTG(2, 0x1C0, gpe1, 0x34),
+ EXYNOS_PIN_BANK_EINTG(6, 0x1E0, gpf0, 0x38),
+ EXYNOS_PIN_BANK_EINTG(8, 0x200, gpf1, 0x3c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x220, gpg0, 0x40),
+ EXYNOS_PIN_BANK_EINTG(8, 0x240, gpg1, 0x44),
+ EXYNOS_PIN_BANK_EINTG(2, 0x260, gpg2, 0x48),
+ EXYNOS_PIN_BANK_EINTG(4, 0x280, gph0, 0x4c),
+ EXYNOS_PIN_BANK_EINTG(8, 0x2A0, gph1, 0x50),
+ EXYNOS_PIN_BANK_EINTN(8, 0x2C0, gpm7),
+ EXYNOS_PIN_BANK_EINTN(6, 0x2E0, gpy0),
+ EXYNOS_PIN_BANK_EINTN(4, 0x300, gpy1),
+ EXYNOS_PIN_BANK_EINTN(6, 0x320, gpy2),
+ EXYNOS_PIN_BANK_EINTN(8, 0x340, gpy3),
+ EXYNOS_PIN_BANK_EINTN(8, 0x360, gpy4),
+ EXYNOS_PIN_BANK_EINTN(8, 0x380, gpy5),
+ EXYNOS_PIN_BANK_EINTN(8, 0x3A0, gpy6),
+ EXYNOS_PIN_BANK_EINTN(8, 0x3C0, gpy7),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC00, gpx0, 0x00),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC20, gpx1, 0x04),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC40, gpx2, 0x08),
+ EXYNOS_PIN_BANK_EINTW(8, 0xC60, gpx3, 0x0c),
+};
+
+/* pin banks of exynos5410 pin-controller 1 */
+static struct samsung_pin_bank exynos5410_pin_banks1[] = {
+ EXYNOS_PIN_BANK_EINTG(5, 0x000, gpj0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpj1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x040, gpj2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpj3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x080, gpj4, 0x10),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0A0, gpk0, 0x14),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0C0, gpk1, 0x18),
+ EXYNOS_PIN_BANK_EINTG(8, 0x0E0, gpk2, 0x1c),
+ EXYNOS_PIN_BANK_EINTG(7, 0x100, gpk3, 0x20),
+};
+
+/* pin banks of exynos5410 pin-controller 2 */
+static struct samsung_pin_bank exynos5410_pin_banks2[] = {
+ EXYNOS_PIN_BANK_EINTG(8, 0x000, gpv0, 0x00),
+ EXYNOS_PIN_BANK_EINTG(8, 0x020, gpv1, 0x04),
+ EXYNOS_PIN_BANK_EINTG(8, 0x060, gpv2, 0x08),
+ EXYNOS_PIN_BANK_EINTG(8, 0x080, gpv3, 0x0c),
+ EXYNOS_PIN_BANK_EINTG(2, 0x0C0, gpv4, 0x10),
+};
+
+/* pin banks of exynos5410 pin-controller 3 */
+static struct samsung_pin_bank exynos5410_pin_banks3[] = {
+ EXYNOS_PIN_BANK_EINTG(7, 0x000, gpz, 0x00),
+};
+
+/*
+ * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
+ * four
