Re: [PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

2014-10-08 Thread Vikas Sajjan 
Hi Javier,

On Tue, Oct 7, 2014 at 6:17 PM, Javier Martinez Canillas
jav...@dowhile0.org wrote:
 Hellos Vikas,

 On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan vikas.saj...@samsung.com 
 wrote:
 From: Abhilash Kesavan a.kesa...@samsung.com

 Adds intial PMU settings for exynos5420. This is required for
 future S2R and Switching support.

 Signed-off-by: Thomas Abraham thomas...@samsung.com
 Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
 Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
 ---
  arch/arm/mach-exynos/pmu.c  |  287 
 +++
  arch/arm/mach-exynos/regs-pmu.h |  227 +++
  2 files changed, 514 insertions(+)

 S2R is working on my Exynos5420 Peach Pit Chromebook with your series:

 Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk



Thanks for testing.



 Best regards,
 Javier
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[PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

2014-10-07 Thread Vikas Sajjan 
From: Abhilash Kesavan a.kesa...@samsung.com

Adds intial PMU settings for exynos5420. This is required for
future S2R and Switching support.

Signed-off-by: Thomas Abraham thomas...@samsung.com
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
---
 arch/arm/mach-exynos/pmu.c  |  287 +++
 arch/arm/mach-exynos/regs-pmu.h |  227 +++
 2 files changed, 514 insertions(+)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index b68cd29a..4110281 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,6 +12,8 @@
 #include linux/io.h
 #include linux/of.h
 #include linux/platform_device.h
+#include linux/delay.h
+
 
 #include exynos-pmu.h
 #include regs-pmu.h
@@ -348,6 +350,151 @@ static const struct exynos_pmu_conf 
exynos5250_pmu_config[] = {
{ PMU_TABLE_END,},
 };
 
+static struct exynos_pmu_conf exynos5420_pmu_config[] = {
+   /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
+   { EXYNOS5_ARM_CORE0_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5_ARM_CORE1_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,  { 0x0, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 
0x0} },
+   { EXYNOS5_ISP_ARM_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,{ 0x1, 0x0, 
0x0} },
+   { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5420_ARM_COMMON_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_COMMON_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5_ARM_L2_SYS_PWR_REG,   { 0x0, 0x0, 
0x0} },
+   { EXYNOS5420_KFC_L2_SYS_PWR_REG,{ 0x0, 0x0, 
0x0} },
+   { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 
0x1} },
+   { EXYNOS5_CMU_RESET_SYS_PWR_REG,{ 0x1, 0x1, 
0x0} },
+   { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,  { 0x1, 0x0, 
0x1} },
+   { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 
0x0} },
+   { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,   { 0x1, 0x0, 
0x1} },
+   { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,{ 0x1, 0x1, 
0x1} },
+   { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,   { 0x1, 0x0, 
0x1} },
+   { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x1, 
0x0} },
+   { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,  { 0x1, 0x0, 
0x0} },
+   {

Re: [PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

2014-10-07 Thread Javier Martinez Canillas 
Hellos Vikas,

On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan vikas.saj...@samsung.com wrote:
 From: Abhilash Kesavan a.kesa...@samsung.com

 Adds intial PMU settings for exynos5420. This is required for
 future S2R and Switching support.

 Signed-off-by: Thomas Abraham thomas...@samsung.com
 Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
 Signed-off-by: Vikas Sajjan vikas.saj...@samsung.com
 ---
  arch/arm/mach-exynos/pmu.c  |  287 
 +++
  arch/arm/mach-exynos/regs-pmu.h |  227 +++
  2 files changed, 514 insertions(+)

S2R is working on my Exynos5420 Peach Pit Chromebook with your series:

Tested-by: Javier Martinez Canillas javier.marti...@collabora.co.uk

Best regards,
Javier
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
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