Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 30 August 2013 12:29, Rahul Sharma rahul.sha...@samsung.com wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
+static const struct i2c_device_id hdmiphy_id[] = {
+ { },
+};
+
[ snip ]
+ .id_table = hdmiphy_id,
This is fixing a regression on v3.12 kernel (same as patch 5/7 in this
series). Would you please split this and send it as a separate patch
for v3.12?
--
Tushar Behera
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RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: Sylwester Nawrocki [mailto:sylvester.nawro...@gmail.com]
Sent: Monday, September 30, 2013 7:09 AM
To: Inki Dae
Cc: Rahul Sharma; devicet...@vger.kernel.org; linux-samsung-soc;
sw0312.kim; sunil joshi; dri-devel; kgene.kim; Shirish S; Sylwester
Nawrocki; Rahul Sharma; Stephen Warren; Mark Rutland; Kumar Gala; Pawel
Moll; Rob Herring; Sean Paul
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 09/28/2013 06:10 PM, Inki Dae wrote:
Any opinion from Device-Tree folks?
IMO, we should have same consensus on Shirish patches before
proceeding.
Rahul, it seems that DT people have no interest in this issue. So let's
have a consensus about this issue internally.
To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
How about keeping hdmiphy config data in each board dts file?
Please don't use HTML and quote only relevant part of e-mails. Otherwise
there are good chances your messages end up in people's spam box.
Ah, I missed checking text mode. Sorry about this. :)
It often helps to Cc a DT binding maintainer directly.
Good idea.
Then, you consider moving the HDMI phy configuration to the device tree.
As Sean suggested in this thread:
Right.
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
+ },
+ },
[trimmed couple more entries]
+};
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them universally.
Shirish has uploaded a patch to the chromium review site to push these
into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
you can work that into your patch set?
The configuration data is 64 bytes of the register values IIUC. Would it
be
possible to figure out exact meaning of each byte ? Do all of these bytes
Right, but the user manual doesn't describe that enough so we might need to
inquire for what it means to design team.
need to be changed per board ? Perhaps we can have per SoC static tables
in
the PHY driver and be overwriting only some of the bytes with values read
from device tree ?
AFAIR firmware-like binary blobs (register address/value pairs) are not
supposed to be stored in DT.
If there is no detailed documentation for theese PHY configuration tables
I guess there is no choice but to put these raw 64 bytes in DT. Presumably
this should be a an required property defined only by board dts, since
those
values are PCB design dependent.
However, if not all boards need tweaking this configuration data, then it
could make sense to define recommended per-SoC tables in the driver and
overwrite from DT only if it is specified there for a specific board.
If we can come up with universal configuration for a SoC and selected
pixel
clock frequency then it could likely be better to store that in the driver
rather than in DT.
Thanks you your opinion. However, we need to make sure how we take care of
the PHY configuration values. So I will have two steps to merge this pages
set.
To Rahul,
Could you post only your patch set regardless of Shirish's patch? I will
merge your patch set first because as is, Exynos drm hdmi driver is broken.
And, we need more discussions about Shirish patch. So I will not merge this
patch until we have a consensus about it.
To Shirish,
For your patch, it seems that you need to make sure to figure out exact
meaning of each byte of the PHY configuration values first. Maybe you need
to inquire for that to hardware or design team. And please separate the
values into common and specific parts if needed.
Thanks,
Inki Dae
--
Thanks,
Sylwester
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RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Tomasz Figa
Sent: Monday, September 30, 2013 8:13 AM
To: Sylwester Nawrocki
Cc: Inki Dae; Rahul Sharma; devicet...@vger.kernel.org; linux-samsung-soc;
sw0312.kim; sunil joshi; dri-devel; kgene.kim; Shirish S; Sylwester
Nawrocki; Rahul Sharma; Stephen Warren; Mark Rutland; Kumar Gala; Pawel
Moll; Rob Herring; Sean Paul
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Monday 30 of September 2013 00:08:46 Sylwester Nawrocki wrote:
On 09/28/2013 06:10 PM, Inki Dae wrote:
Any opinion from Device-Tree folks?
IMO, we should have same consensus on Shirish patches before
proceeding.
Rahul, it seems that DT people have no interest in this issue. So
let's
have a consensus about this issue internally.
To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
How about keeping hdmiphy config data in each board dts file?
Please don't use HTML and quote only relevant part of e-mails. Otherwise
there are good chances your messages end up in people's spam box.
It often helps to Cc a DT binding maintainer directly.
Then, you consider moving the HDMI phy configuration to the device tree.
As Sean suggested in this thread:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
I'd like to only add that patches introducing or modifying a device tree
binding need to be acked by at least one DT binding maintainer to be
merged.
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
[trimmed couple more entries]
+};
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them universally.
Shirish has uploaded a patch to the chromium review site to push these
into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
you can work that into your patch set?
The configuration data is 64 bytes of the register values IIUC. Would it
be possible to figure out exact meaning of each byte ?
This is definitely something that I would go for. Then for board specific
data appropriate device tree properties could be defined, not just a
binary blob.
Agree. Thanks for your opinion.
Thanks,
Inki Dae
Best regards,
Tomasz
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Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 09/28/2013 06:10 PM, Inki Dae wrote:
Any opinion from Device-Tree folks?
IMO, we should have same consensus on Shirish patches before proceeding.
Rahul, it seems that DT people have no interest in this issue. So let's
have a consensus about this issue internally.
To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
How about keeping hdmiphy config data in each board dts file?
Please don't use HTML and quote only relevant part of e-mails. Otherwise
there are good chances your messages end up in people's spam box.
It often helps to Cc a DT binding maintainer directly.
Then, you consider moving the HDMI phy configuration to the device tree.
As Sean suggested in this thread:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
+ },
+ },
[trimmed couple more entries]
+};
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them universally.
Shirish has uploaded a patch to the chromium review site to push these
into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
you can work that into your patch set?
The configuration data is 64 bytes of the register values IIUC. Would it be
possible to figure out exact meaning of each byte ? Do all of these bytes
need to be changed per board ? Perhaps we can have per SoC static tables in
the PHY driver and be overwriting only some of the bytes with values read
from device tree ?
AFAIR firmware-like binary blobs (register address/value pairs) are not
supposed to be stored in DT.
If there is no detailed documentation for theese PHY configuration tables
I guess there is no choice but to put these raw 64 bytes in DT. Presumably
this should be a an required property defined only by board dts, since those
values are PCB design dependent.
However, if not all boards need tweaking this configuration data, then it
could make sense to define recommended per-SoC tables in the driver and
overwrite from DT only if it is specified there for a specific board.
If we can come up with universal configuration for a SoC and selected pixel
clock frequency then it could likely be better to store that in the driver
rather than in DT.
--
Thanks,
Sylwester
--
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Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Monday 30 of September 2013 00:08:46 Sylwester Nawrocki wrote:
On 09/28/2013 06:10 PM, Inki Dae wrote:
Any opinion from Device-Tree folks?
IMO, we should have same consensus on Shirish patches before
proceeding.
Rahul, it seems that DT people have no interest in this issue. So
let's
have a consensus about this issue internally.
To Mr. Kyungmin, Sylwester, Kukjin Kim, and Tomasz,
How about keeping hdmiphy config data in each board dts file?
Please don't use HTML and quote only relevant part of e-mails. Otherwise
there are good chances your messages end up in people's spam box.
It often helps to Cc a DT binding maintainer directly.
Then, you consider moving the HDMI phy configuration to the device tree.
As Sean suggested in this thread:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
I'd like to only add that patches introducing or modifying a device tree
binding need to be acked by at least one DT binding maintainer to be
merged.
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
[trimmed couple more entries]
+};
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them universally.
Shirish has uploaded a patch to the chromium review site to push these
into dt (https://chromium-review.googlesource.com/#/c/65581). Maybe
you can work that into your patch set?
The configuration data is 64 bytes of the register values IIUC. Would it
be possible to figure out exact meaning of each byte ?
This is definitely something that I would go for. Then for board specific
data appropriate device tree properties could be defined, not just a
binary blob.
Best regards,
Tomasz
--
To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in
the body of a message to majord...@vger.kernel.org
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Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 16 September 2013 18:10, Inki Dae inki@samsung.com wrote:
CCing devicetree,
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Tuesday, September 10, 2013 5:28 PM
To: Sean Paul
Cc: Inki Dae; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 6 September 2013 19:21, Sean Paul seanp...@chromium.org wrote:
On Thu, Sep 5, 2013 at 11:37 PM, Rahul Sharma r.sh.o...@gmail.com
wrote:
On 5 September 2013 19:20, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Sean Paul [mailto:seanp...@chromium.org]
Sent: Thursday, September 05, 2013 10:20 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel;
kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil
joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com
wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-
samsung-
soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel;
kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil
joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] =
{
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF,
0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10,
0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF,
0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef,
0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10,
0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff,
0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00,
0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff,
0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02,
0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since
these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review
site to
push
these
into dt
(https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy
setting
is same as the current board. But if changed, you need to
confirm
with
measurement of signals, because it may vary slightly by
resistance
of
board pattern
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
CCing devicetree,
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Tuesday, September 10, 2013 5:28 PM
To: Sean Paul
Cc: Inki Dae; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 6 September 2013 19:21, Sean Paul seanp...@chromium.org wrote:
On Thu, Sep 5, 2013 at 11:37 PM, Rahul Sharma r.sh.o...@gmail.com
wrote:
On 5 September 2013 19:20, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Sean Paul [mailto:seanp...@chromium.org]
Sent: Thursday, September 05, 2013 10:20 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel;
kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil
joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com
wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-
samsung-
soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel;
kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil
joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] =
{
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF,
0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10,
0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF,
0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef,
0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10,
0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff,
0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00,
0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01,
0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10,
0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff,
0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00,
0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02,
0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since
these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review
site to
push
these
into dt
(https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy
setting
is same as the current board. But if changed, you need to
confirm
with
measurement of signals, because it may vary slightly by
resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Thu, Sep 5, 2013 at 11:37 PM, Rahul Sharma r.sh.o...@gmail.com wrote:
On 5 September 2013 19:20, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Sean Paul [mailto:seanp...@chromium.org]
Sent: Thursday, September 05, 2013 10:20 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-
soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to
push
these
into dt
(https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy
setting
is same as the current board. But if changed, you need to confirm
with
measurement of signals, because it may vary slightly by
resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided
by
PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-
board
basis.
In the 5420 datasheet, there are a few register descriptions
available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch
set
should
be rebased on top of Rahul's patch set. Shirish
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to push
these
into dt (https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy setting
is same as the current board. But if changed, you need to confirm with
measurement of signals, because it may vary slightly by resistance of
board pattern
Right. it seems that the phy configuration should be adjusted according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided by PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-board
basis.
In the 5420 datasheet, there are a few register descriptions available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please re-
post
your patch set after discussing how to rebase these patch set.
Thanks,
Inki Dae
In that case, we need to test the phy confs for all the exynos boards,
supported in
mainline. Probably needs a analyser as well to precisely compare the
deviation.
Shirish patch adds phy config data only to arndale and smdk5250 boards, and
these config data should have each board specific values. Therefore, for
other boards, shouldn't correct phy config data suitable to their boards be
added to their board dts files? Is the above analyzer really needed?
Sorry, I had only seen his patches for chromium tree. In mainline
version, he added for 5250 as well. But both sets (for arndale and
smdk) are exactly same as original 5250 configs which also works
with 4412 origen.
Some problem has been identified during conformance testing for
5420 peach board, which happens with analyser. It was always
working fine on the TV sets that I have. @Shirish/Sean please
correct me if wrong.
Shirish patch is only for 5420 Peach board. Else, to start with we can
mark
phyconf as optional property which overrides the default Phy Confs for
given SoC.
Hm you mean that hdmiphy driver use the default phy config data in
driver; most boards use the same data, and only in special case; a board
uses
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to
push
these
into dt (https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy setting
is same as the current board. But if changed, you need to confirm
with
measurement of signals, because it may vary slightly by resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided by
PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-
board
basis.
In the 5420 datasheet, there are a few register descriptions
available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please re-
post
your patch set after discussing how to rebase these patch set.
Thanks,
Inki Dae
In that case, we need to test the phy confs for all the exynos boards,
supported in
mainline. Probably needs a analyser as well to precisely compare the
deviation.
Shirish patch adds phy config data only to arndale and smdk5250 boards,
and
these config data should have each board specific values. Therefore, for
other boards, shouldn't correct phy config data suitable to their boards
be
added to their board dts files? Is the above analyzer really needed?
Sorry, I had only seen his patches for chromium tree. In mainline
version, he added for 5250 as well. But both sets (for arndale and
smdk) are exactly
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to
push
these
into dt (https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy setting
is same as the current board. But if changed, you need to confirm
with
measurement of signals, because it may vary slightly by resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided by
PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-
board
basis.
In the 5420 datasheet, there are a few register descriptions
available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please re-
post
your patch set after discussing how to rebase these patch set.
Thanks,
Inki Dae
In that case, we need to test the phy confs for all the exynos boards,
supported in
mainline. Probably needs a analyser as well to precisely compare the
deviation.
Shirish patch adds phy config data only to arndale and smdk5250 boards,
and
these config data should have each board specific values. Therefore, for
other boards, shouldn't correct phy config data suitable to their boards
be
added to their board dts files? Is the above analyzer really needed?
Sorry, I had only seen his patches for chromium tree. In mainline
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: Sean Paul [mailto:seanp...@chromium.org]
Sent: Thursday, September 05, 2013 10:20 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-
soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to
push
these
into dt
(https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy
setting
is same as the current board. But if changed, you need to confirm
with
measurement of signals, because it may vary slightly by
resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided
by
PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-
board
basis.
In the 5420 datasheet, there are a few register descriptions
available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch
set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please
re-
post
your patch set after discussing how to rebase these patch set.
Thanks,
Inki Dae
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
Can you please quote only related part of e-mails when replying ? It discourages to read such discussions when you have to scroll through few pages of garbage before getting to the actual reply text. -- Thanks, Sylwester -- To unsubscribe from this list: send the line unsubscribe linux-samsung-soc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 5 September 2013 19:20, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Sean Paul [mailto:seanp...@chromium.org]
Sent: Thursday, September 05, 2013 10:20 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Thu, Sep 5, 2013 at 2:19 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-
soc-
ow...@vger.kernel.org] On Behalf Of Rahul Sharma
Sent: Thursday, September 05, 2013 3:04 PM
To: Inki Dae
Cc: Sean Paul; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
On 5 September 2013 10:52, Inki Dae inki@samsung.com wrote:
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C,
0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C,
0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2,
0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3,
0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c,
0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00,
0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C,
0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1,
0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08,
0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00,
0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these
are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to
push
these
into dt
(https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy
setting
is same as the current board. But if changed, you need to confirm
with
measurement of signals, because it may vary slightly by
resistance
of
board pattern
Right. it seems that the phy configuration should be adjusted
according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided
by
PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-
board
basis.
In the 5420 datasheet, there are a few register descriptions
available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch
set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please
re-
post
your patch set after discussing how
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Wednesday, September 04, 2013 2:48 PM
To: Sean Paul
Cc: Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim; sw0312.kim;
InKi Dae; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
shir...@chromium.org
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343
+++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and
mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6 @@ struct hdmi_context {
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
-/* list of phy config settings */
-static const struct hdmiphy_config hdmiphy_v13_configs[] = {
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Wed, Sep 4, 2013 at 3:37 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Wednesday, September 04, 2013 2:48 PM
To: Sean Paul
Cc: Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim; sw0312.kim;
InKi Dae; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
shir...@chromium.org
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343
+++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and
mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6 @@ struct hdmi_context {
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
-/* list of phy config settings */
-static const struct hdmiphy_config hdmiphy_v13_configs[] = {
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On Wed, Sep 4, 2013 at 1:47 AM, Rahul Sharma r.sh.o...@gmail.com wrote:
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343 +++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6 @@ struct hdmi_context {
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
-/* list of phy config settings */
-static const struct hdmiphy_config hdmiphy_v13_configs[] = {
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
- },
- },
- {
- .pixel_clock = 74176000,
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Sean Paul
Sent: Wednesday, September 04, 2013 11:52 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Wed, Sep 4, 2013 at 3:37 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Wednesday, September 04, 2013 2:48 PM
To: Sean Paul
Cc: Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim; sw0312.kim;
InKi Dae; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
shir...@chromium.org
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma
rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343
+++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock
IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and
mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6 @@ struct hdmi_context {
enum hdmi_type
Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
On 5 September 2013 09:46, Inki Dae inki@samsung.com wrote:
-Original Message-
From: linux-samsung-soc-ow...@vger.kernel.org [mailto:linux-samsung-soc-
ow...@vger.kernel.org] On Behalf Of Sean Paul
Sent: Wednesday, September 04, 2013 11:52 PM
To: Inki Dae
Cc: Rahul Sharma; Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim;
sw0312.kim; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
Shirish S
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy
driver
On Wed, Sep 4, 2013 at 3:37 AM, Inki Dae inki@samsung.com wrote:
-Original Message-
From: Rahul Sharma [mailto:r.sh.o...@gmail.com]
Sent: Wednesday, September 04, 2013 2:48 PM
To: Sean Paul
Cc: Rahul Sharma; linux-samsung-soc; dri-devel; kgene.kim; sw0312.kim;
InKi Dae; Lucas Stach; Tomasz Figa; Sylwester Nawrocki; sunil joshi;
shir...@chromium.org
Subject: Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to
hdmiphy
driver
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma
rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343
+++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock
IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and
mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6
RE: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
+static struct hdmiphy_config hdmiphy_4210_configs[] = {
+ {
+ .pixel_clock = 2700,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30,
0x40,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 27027000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09,
0x64,
+ 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54,
0x87,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 74176000,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef,
0x5B,
+ 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54,
0xb9,
+ 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 7425,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8,
0x40,
+ 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10,
0xe0,
+ 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00,
0x00,
+ },
+ },
+ {
+ .pixel_clock = 14850,
+ .conf = {
+ 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8,
0x40,
+ 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54,
0xba,
+ 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10,
0xE0,
+ 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00,
0x00,
+ },
+ },
+};
+
Are you aware of the effort to move these to dt? Since these are
board-specific values, it seems incorrect to apply them
universally.
Shirish has uploaded a patch to the chromium review site to push
these
into dt (https://chromium-review.googlesource.com/#/c/65581).
Maybe
you can work that into your patch set?
Are these really board-specific values?
According to your hardware people:
If the signal pattern doesn't change for new board, the phy setting
is same as the current board. But if changed, you need to confirm with
measurement of signals, because it may vary slightly by resistance of
board pattern
Right. it seems that the phy configuration should be adjusted according
to
PCB environment: OSC clock rate, 24MHz or 27MHz, could be decided by PCB
even though most PCBs use 27MHz.
That indicates to me that we might need to tweak these on a per-board
basis.
In the 5420 datasheet, there are a few register descriptions available
for the phy. 0x145D0004 is CLK_SEL which seems like it would be
board-specific, same with TX_* registers.
And we can select HDMI Tx PHY internal PLL input clock by setting
CLK_SEL.
Ok, Shirish's patch set is reasonable to me. However, that patch set
should
be rebased on top of Rahul's patch set. Shirish and Rahul, please re-
post
your patch set after discussing how to rebase these patch set.
Thanks,
Inki Dae
In that case, we need to test the phy confs for all the exynos boards,
supported in
mainline. Probably needs a analyser as well to precisely compare the
deviation.
Shirish patch adds phy config data only to arndale and smdk5250 boards, and
these config data should have each board specific values. Therefore, for
other boards, shouldn't correct phy config data suitable to their boards be
added to their board dts files? Is the above analyzer really needed?
Shirish patch is only for 5420 Peach board. Else, to start with we can
mark
phyconf as optional property which overrides the default Phy Confs for
given SoC.
Hm you mean that hdmiphy driver use the default phy config data in
driver; most boards use the same data, and only in special case; a board
uses different OSC clock rate, the hdmiphy driver use phy config data from
dts file checking hdmiphy-confs property?
regards,
Rahul Sharma.
Sean
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Re: [PATCH 1/7] drm/exynos: move hdmiphy related code to hdmiphy driver
Thanks Sean,
On 3 September 2013 20:15, Sean Paul seanp...@chromium.org wrote:
A few comments.
On Fri, Aug 30, 2013 at 2:59 AM, Rahul Sharma rahul.sha...@samsung.com
wrote:
Exynos hdmiphy operations and configs are kept inside
the hdmi driver. Hdmiphy related code is tightly coupled
with hdmi IP driver.
This patche moves hdmiphy related code to hdmiphy driver.
s/patche/patch
ok.
It will help in cleanly supporting the hdmiphy variations
in further SoCs.
Signed-off-by: Rahul Sharma rahul.sha...@samsung.com
---
.../devicetree/bindings/video/exynos_hdmi.txt |2 +
drivers/gpu/drm/exynos/exynos_drm_hdmi.h | 11 +
drivers/gpu/drm/exynos/exynos_hdmi.c | 343 +++
drivers/gpu/drm/exynos/exynos_hdmiphy.c| 438
+++-
drivers/gpu/drm/exynos/regs-hdmiphy.h | 35 ++
5 files changed, 533 insertions(+), 296 deletions(-)
create mode 100644 drivers/gpu/drm/exynos/regs-hdmiphy.h
diff --git a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
index 50decf8..240eca5 100644
--- a/Documentation/devicetree/bindings/video/exynos_hdmi.txt
+++ b/Documentation/devicetree/bindings/video/exynos_hdmi.txt
@@ -25,6 +25,7 @@ Required properties:
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
hdmi, sclk_hdmi, sclk_pixel, sclk_hdmiphy and mout_hdmi.
+- phy: it points to hdmiphy dt node.
Example:
hdmi {
@@ -32,4 +33,5 @@ Example:
reg = 0x1453 0x10;
interrupts = 0 95 0;
hpd-gpio = gpx3 7 1;
+ phy = hdmiphy;
};
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
index 724cab1..1c839f8 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h
@@ -64,4 +64,15 @@ void exynos_hdmi_drv_attach(struct
exynos_drm_hdmi_context *ctx);
void exynos_mixer_drv_attach(struct exynos_drm_hdmi_context *ctx);
void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops);
void exynos_mixer_ops_register(struct exynos_mixer_ops *ops);
+
+int exynos_hdmiphy_driver_register(void);
+void exynos_hdmiphy_driver_unregister(void);
+
+void exynos_hdmiphy_enable(struct device *dev);
+void exynos_hdmiphy_disable(struct device *dev);
+int exynos_hdmiphy_check_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_set_mode(struct device *dev,
+ struct drm_display_mode *mode);
+int exynos_hdmiphy_conf_apply(struct device *dev);
#endif
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c
b/drivers/gpu/drm/exynos/exynos_hdmi.c
index f67ffca..3af4e4c 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -34,6 +34,8 @@
#include linux/io.h
#include linux/of.h
#include linux/of_gpio.h
+#include linux/of_i2c.h
+#include linux/of_platform.h
#include drm/exynos_drm.h
@@ -172,7 +174,6 @@ struct hdmi_v14_conf {
};
struct hdmi_conf_regs {
- int pixel_clock;
int cea_video_id;
union {
struct hdmi_v13_conf v13_conf;
@@ -193,9 +194,9 @@ struct hdmi_context {
int irq;
struct i2c_client *ddc_port;
- struct i2c_client *hdmiphy_port;
+ struct device *hdmiphy_dev;
- /* current hdmiphy conf regs */
+ /* current hdmi ip configuration registers. */
struct hdmi_conf_regs mode_conf;
struct hdmi_resources res;
@@ -205,180 +206,6 @@ struct hdmi_context {
enum hdmi_type type;
};
-struct hdmiphy_config {
- int pixel_clock;
- u8 conf[32];
-};
-
-/* list of phy config settings */
-static const struct hdmiphy_config hdmiphy_v13_configs[] = {
- {
- .pixel_clock = 2700,
- .conf = {
- 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
- },
- },
- {
- .pixel_clock = 27027000,
- .conf = {
- 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
- 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
- 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
- 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
- },
- },
- {
- .pixel_clock = 74176000,
- .conf = {
- 0x01, 0x05, 0x00, 0xD8,
