Re: [PATCH 03/11] hpsa: add 5 second delay after doorbell reset
On 11/07/2013 05:45 PM, Stephen M. Cameron wrote:
From: Stephen M. Cameron scame...@beardog.cce.hp.com
The hardware guys tell us that after initiating a software
reset via the doorbell register we need to wait 5 seconds before
attempting to talk to the board *at all*. This means that we
cannot watch the board to verify it transitions from ready to
to not ready then back ready, since this transition will
most likely happen during those 5 seconds (though we can still
verify the reset happens by watching the driver version field
get cleared.)
Signed-off-by: Stephen M. Cameron scame...@beardog.cce.hp.com
---
drivers/scsi/hpsa.c | 32 +++-
1 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 20fc598..fff5fd3 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -3781,6 +3781,13 @@ static int hpsa_controller_hard_reset(struct pci_dev
*pdev,
*/
dev_info(pdev-dev, using doorbell to reset controller\n);
writel(use_doorbell, vaddr + SA5_DOORBELL);
+
+ /* PMC hardware guys tell us we need a 5 second delay after
+ * doorbell reset and before any attempt to talk to the board
+ * at all to ensure that this actually works and doesn't fall
+ * over in some weird corner cases.
+ */
+ msleep(5000);
} else { /* Try to do it the PCI power state way */
/* Quoting from the Open CISS Specification: The Power
@@ -3977,15 +3984,22 @@ static int hpsa_kdump_hard_reset_controller(struct
pci_dev *pdev)
need a little pause here */
msleep(HPSA_POST_RESET_PAUSE_MSECS);
I know it's complicated with a lot of different devices and fw versions,
but here^ we wait for 3sec - isn't the method - wait for 3s then wait for board
not ready
a bit fragile, what if a board comes up faster?
When the method watching the driver version works why don't you want to use
it
regardless of the reset method used?
- /* Wait for board to become not ready, then ready. */
- dev_info(pdev-dev, Waiting for board to reset.\n);
- rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
- if (rc) {
- dev_warn(pdev-dev,
- failed waiting for board to reset.
- Will try soft reset.\n);
- rc = -ENOTSUPP; /* Not expected, but try soft reset later */
- goto unmap_cfgtable;
+ if (!use_doorbell) {
+ /* Wait for board to become not ready, then ready.
+ * (if we used the doorbell, then we already waited 5 secs
+ * so the not ready state is already gone by so we
+ * won't catch it.)
+ */
+ dev_info(pdev-dev, Waiting for board to reset.\n);
+ rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
+ if (rc) {
+ dev_warn(pdev-dev,
+ failed waiting for board to reset.
+ Will try soft reset.\n);
+ /* Not expected, but try soft reset later */
+ rc = -ENOTSUPP;
+ goto unmap_cfgtable;
+ }
}
rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
if (rc) {
--
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Re: [PATCH 03/11] hpsa: add 5 second delay after doorbell reset
On Fri, Nov 08, 2013 at 02:51:37PM +0100, Tomas Henzl wrote:
On 11/07/2013 05:45 PM, Stephen M. Cameron wrote:
From: Stephen M. Cameron scame...@beardog.cce.hp.com
The hardware guys tell us that after initiating a software
reset via the doorbell register we need to wait 5 seconds before
attempting to talk to the board *at all*. This means that we
cannot watch the board to verify it transitions from ready to
to not ready then back ready, since this transition will
most likely happen during those 5 seconds (though we can still
verify the reset happens by watching the driver version field
get cleared.)
Signed-off-by: Stephen M. Cameron scame...@beardog.cce.hp.com
---
drivers/scsi/hpsa.c | 32 +++-
1 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 20fc598..fff5fd3 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -3781,6 +3781,13 @@ static int hpsa_controller_hard_reset(struct pci_dev
*pdev,
*/
dev_info(pdev-dev, using doorbell to reset controller\n);
writel(use_doorbell, vaddr + SA5_DOORBELL);
+
+ /* PMC hardware guys tell us we need a 5 second delay after
+* doorbell reset and before any attempt to talk to the board
+* at all to ensure that this actually works and doesn't fall
+* over in some weird corner cases.
+*/
+ msleep(5000);
} else { /* Try to do it the PCI power state way */
/* Quoting from the Open CISS Specification: The Power
@@ -3977,15 +3984,22 @@ static int hpsa_kdump_hard_reset_controller(struct
pci_dev *pdev)
need a little pause here */
msleep(HPSA_POST_RESET_PAUSE_MSECS);
I know it's complicated with a lot of different devices and fw versions,
but here^ we wait for 3sec - isn't the method - wait for 3s then wait for
board not ready
a bit fragile, what if a board comes up faster?
When the method watching the driver version works why don't you want to
use it
regardless of the reset method used?
The watching the driver version thing is only there to catch if
the firmware guys break things and turn the reset into a no-op
(which happened with the PCI power manaegment based reset and we
didn't catch it for a year or so because we didn't have that check)
We aren't supposed to look at the driver version field (or anything)
until we first verify the scratch pad register says the firmware is
ready. In the case of those boards that use the doorbell reset,
we aren't supposed to look at *anything* for the first five seconds.
I have been bugging the firmware/hardware guys for a sane reset
procedure that actually works reliably for years with no luck.
For the SCSI over PCIe driver, being tired of this crap, I simply
unconditionally reset the device on driver load every single time,
and did this from the beginning. This kind of forced the firmware
and hardware guys to make the reset on that thing work reliably
and quickly, and since I did that from the earliest days, they didn't
have a chance to screw it up without it being caught immediately.
For Smart Array, obviously it's too late for that approach.
-- steve
- /* Wait for board to become not ready, then ready. */
- dev_info(pdev-dev, Waiting for board to reset.\n);
- rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
- if (rc) {
- dev_warn(pdev-dev,
- failed waiting for board to reset.
-Will try soft reset.\n);
- rc = -ENOTSUPP; /* Not expected, but try soft reset later */
- goto unmap_cfgtable;
+ if (!use_doorbell) {
+ /* Wait for board to become not ready, then ready.
+* (if we used the doorbell, then we already waited 5 secs
+* so the not ready state is already gone by so we
+* won't catch it.)
+*/
+ dev_info(pdev-dev, Waiting for board to reset.\n);
+ rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
+ if (rc) {
+ dev_warn(pdev-dev,
+ failed waiting for board to reset.
+Will try soft reset.\n);
+ /* Not expected, but try soft reset later */
+ rc = -ENOTSUPP;
+ goto unmap_cfgtable;
+ }
}
rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
if (rc) {
--
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Re: [PATCH 03/11] hpsa: add 5 second delay after doorbell reset
On 11/08/2013 03:44 PM, scame...@beardog.cce.hp.com wrote:
On Fri, Nov 08, 2013 at 02:51:37PM +0100, Tomas Henzl wrote:
On 11/07/2013 05:45 PM, Stephen M. Cameron wrote:
From: Stephen M. Cameron scame...@beardog.cce.hp.com
The hardware guys tell us that after initiating a software
reset via the doorbell register we need to wait 5 seconds before
attempting to talk to the board *at all*. This means that we
cannot watch the board to verify it transitions from ready to
to not ready then back ready, since this transition will
most likely happen during those 5 seconds (though we can still
verify the reset happens by watching the driver version field
get cleared.)
Signed-off-by: Stephen M. Cameron scame...@beardog.cce.hp.com
---
drivers/scsi/hpsa.c | 32 +++-
1 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 20fc598..fff5fd3 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -3781,6 +3781,13 @@ static int hpsa_controller_hard_reset(struct pci_dev
*pdev,
*/
dev_info(pdev-dev, using doorbell to reset controller\n);
writel(use_doorbell, vaddr + SA5_DOORBELL);
+
+ /* PMC hardware guys tell us we need a 5 second delay after
+* doorbell reset and before any attempt to talk to the board
+* at all to ensure that this actually works and doesn't fall
+* over in some weird corner cases.
+*/
+ msleep(5000);
} else { /* Try to do it the PCI power state way */
/* Quoting from the Open CISS Specification: The Power
@@ -3977,15 +3984,22 @@ static int hpsa_kdump_hard_reset_controller(struct
pci_dev *pdev)
need a little pause here */
msleep(HPSA_POST_RESET_PAUSE_MSECS);
I know it's complicated with a lot of different devices and fw versions,
but here^ we wait for 3sec - isn't the method - wait for 3s then wait for
board not ready
a bit fragile, what if a board comes up faster?
When the method watching the driver version works why don't you want to
use it
regardless of the reset method used?
The watching the driver version thing is only there to catch if
the firmware guys break things and turn the reset into a no-op
(which happened with the PCI power manaegment based reset and we
didn't catch it for a year or so because we didn't have that check)
We aren't supposed to look at the driver version field (or anything)
until we first verify the scratch pad register says the firmware is
ready. In the case of those boards that use the doorbell reset,
we aren't supposed to look at *anything* for the first five seconds.
I have been bugging the firmware/hardware guys for a sane reset
procedure that actually works reliably for years with no luck.
For the SCSI over PCIe driver, being tired of this crap, I simply
unconditionally reset the device on driver load every single time,
and did this from the beginning. This kind of forced the firmware
and hardware guys to make the reset on that thing work reliably
and quickly, and since I did that from the earliest days, they didn't
have a chance to screw it up without it being caught immediately.
For Smart Array, obviously it's too late for that approach.
OK, my question was more or less if this:
msleep(HPSA_POST_RESET_PAUSE_MSECS);
just before waiting for the board to enter BOARD_NOT_READY state
isn't dangerous - when the board enters a ready state in the first 3sec
it will wait indefinitely for the not_ready state
thus whether the test for not ready state shouldn't be removed.
The mechanism now works somehow and maybe it's better
not to touch it, I just wanted to draw your attention to that
potential problem.
-- steve
- /* Wait for board to become not ready, then ready. */
- dev_info(pdev-dev, Waiting for board to reset.\n);
- rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
- if (rc) {
- dev_warn(pdev-dev,
- failed waiting for board to reset.
-Will try soft reset.\n);
- rc = -ENOTSUPP; /* Not expected, but try soft reset later */
- goto unmap_cfgtable;
+ if (!use_doorbell) {
+ /* Wait for board to become not ready, then ready.
+* (if we used the doorbell, then we already waited 5 secs
+* so the not ready state is already gone by so we
+* won't catch it.)
+*/
+ dev_info(pdev-dev, Waiting for board to reset.\n);
+ rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
+ if (rc) {
+ dev_warn(pdev-dev,
+ failed waiting for board to reset.
+Will try soft reset.\n);
+ /* Not expected, but try soft reset later */
+ rc = -ENOTSUPP;
+ goto unmap_cfgtable;
+
[Bug 60758] module scsi_wait_scan not found kernel panic on boot
https://bugzilla.kernel.org/show_bug.cgi?id=60758 --- Comment #45 from newbie kernel...@gmail.com --- If you do not like seeing the message, just comment out line number 165 in your /etc/rc.d/rc.sysinit file. seems no help, that message still exist, I don't know why. but really problem is: I use two SATA 200G(sda/sdb) build a soft RAID1 (md) three days ago, one disk error and off, but I just discovered today, after I mdadm add fix it then reboot, the bad disk show read error constantly, I can't use normally,so I use the other good one boot, then... FATAL: Module scsi_wait_scan not found then... message loop~ I use 3.10.17, 3.10.18, the same situation,I can't boot into system, so finally,I boot with CentOS 2.6 kernel into the system save data, then shutdown now... -- You are receiving this mail because: You are the assignee for the bug. -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 03/11] hpsa: add 5 second delay after doorbell reset
On Fri, Nov 08, 2013 at 04:02:20PM +0100, Tomas Henzl wrote:
On 11/08/2013 03:44 PM, scame...@beardog.cce.hp.com wrote:
On Fri, Nov 08, 2013 at 02:51:37PM +0100, Tomas Henzl wrote:
On 11/07/2013 05:45 PM, Stephen M. Cameron wrote:
From: Stephen M. Cameron scame...@beardog.cce.hp.com
The hardware guys tell us that after initiating a software
reset via the doorbell register we need to wait 5 seconds before
attempting to talk to the board *at all*. This means that we
cannot watch the board to verify it transitions from ready to
to not ready then back ready, since this transition will
most likely happen during those 5 seconds (though we can still
verify the reset happens by watching the driver version field
get cleared.)
Signed-off-by: Stephen M. Cameron scame...@beardog.cce.hp.com
---
drivers/scsi/hpsa.c | 32 +++-
1 files changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 20fc598..fff5fd3 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -3781,6 +3781,13 @@ static int hpsa_controller_hard_reset(struct
pci_dev *pdev,
*/
dev_info(pdev-dev, using doorbell to reset controller\n);
writel(use_doorbell, vaddr + SA5_DOORBELL);
+
+ /* PMC hardware guys tell us we need a 5 second delay after
+ * doorbell reset and before any attempt to talk to the board
+ * at all to ensure that this actually works and doesn't fall
+ * over in some weird corner cases.
+ */
+ msleep(5000);
} else { /* Try to do it the PCI power state way */
/* Quoting from the Open CISS Specification: The Power
@@ -3977,15 +3984,22 @@ static int
hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
need a little pause here */
msleep(HPSA_POST_RESET_PAUSE_MSECS);
I know it's complicated with a lot of different devices and fw versions,
but here^ we wait for 3sec - isn't the method - wait for 3s then wait for
board not ready
a bit fragile, what if a board comes up faster?
When the method watching the driver version works why don't you want
to use it
regardless of the reset method used?
The watching the driver version thing is only there to catch if
the firmware guys break things and turn the reset into a no-op
(which happened with the PCI power manaegment based reset and we
didn't catch it for a year or so because we didn't have that check)
We aren't supposed to look at the driver version field (or anything)
until we first verify the scratch pad register says the firmware is
ready. In the case of those boards that use the doorbell reset,
we aren't supposed to look at *anything* for the first five seconds.
I have been bugging the firmware/hardware guys for a sane reset
procedure that actually works reliably for years with no luck.
For the SCSI over PCIe driver, being tired of this crap, I simply
unconditionally reset the device on driver load every single time,
and did this from the beginning. This kind of forced the firmware
and hardware guys to make the reset on that thing work reliably
and quickly, and since I did that from the earliest days, they didn't
have a chance to screw it up without it being caught immediately.
For Smart Array, obviously it's too late for that approach.
OK, my question was more or less if this:
msleep(HPSA_POST_RESET_PAUSE_MSECS);
just before waiting for the board to enter BOARD_NOT_READY state
isn't dangerous - when the board enters a ready state in the first 3sec
it will wait indefinitely for the not_ready state
thus whether the test for not ready state shouldn't be removed.
The mechanism now works somehow and maybe it's better
not to touch it, I just wanted to draw your attention to that
potential problem.
Oh ok, I see. Thanks, yes that does look questionable. So you
are suggesting to skip the check for transition from NOT READY to
READY in the scratch pad register in all cases, since we have all
these ridiculous delay requirements preventing us from watching the
board closely enough and so that may mean that we would miss such a
transition.
Let me talk it over with Mike Miller, but it seems reasonable.
-- steve
-- steve
- /* Wait for board to become not ready, then ready. */
- dev_info(pdev-dev, Waiting for board to reset.\n);
- rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
- if (rc) {
- dev_warn(pdev-dev,
- failed waiting for board to reset.
- Will try soft reset.\n);
- rc = -ENOTSUPP; /* Not expected, but try soft reset later */
- goto unmap_cfgtable;
+ if (!use_doorbell) {
+ /* Wait for board to become not ready, then ready.
+ * (if we used the doorbell, then we already waited 5 secs
+ * so the not ready state is already gone
Re: [PATCH 2/5] scsi: improved eh timeout handler
On 11/07/2013 07:33 PM, Douglas Gilbert wrote: On 13-11-07 01:45 AM, Hannes Reinecke wrote: On 11/06/2013 06:23 PM, Mike Christie wrote: On 11/05/2013 10:48 PM, Hannes Reinecke wrote: On 11/05/2013 08:19 PM, Mike Christie wrote: On 11/04/2013 11:05 PM, Hannes Reinecke wrote: + +scmd-eh_eflags |= SCSI_EH_ABORT_SCHEDULED; +SCSI_LOG_ERROR_RECOVERY(3, +scmd_printk(KERN_INFO, scmd, +scmd %p abort scheduled\n, scmd)); +schedule_delayed_work(scmd-abort_work, HZ / 100); +return SUCCESS; +} Do we want to use our own workqueue_struct with WQ_MEM_RECLAIM set? Errm. Yes, why? I must admit I'm not _that_ familiar with workqueues ... Care to explain? We all share the above workqueue_structs pool of threads, so if we get stuck behind code doing GFP_KERNEL allocs that end up needing to write data to the disk we are now trying to aborts on, then we could get stuck. With WQ_MEM_RECLAIM, we have our own backup thread that gets created at workqueue_struct create time which can get used in cases like that so we can always make forward progress. Ah. Right. Yes, that makes sense. I guess I'll have to redo the patches _yet again_. I wonder if it might be useful to flag a LU (disk) with try really hard to recover me, perhaps at the expense of other LUs. Seems like a LU containing the rootfs or swap might qualify for setting such a flag. And LUs that have this flag cleared could be assumed to not get wedged in the fashion that Mike pointed out. While this would be a good idea in general, I would _very much_ see to have this patch accepted first. Without that proviso any discussion is pretty much moot anyway. So I would like to defer that until the patch has been accepted. Cheers, Hannes -- Dr. Hannes Reinecke zSeries Storage h...@suse.de +49 911 74053 688 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg GF: J. Hawn, J. Guild, F. Imendörffer, HRB 16746 (AG Nürnberg) -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[GIT PULL] delete decade+ obsolete aic7xxx_old driver
Hi James, We've got appropriate acks on this, and we've also established that it doesn't appear to even be enabled in any of the common distros, and nobody voiced any strong objections in the past month+ since posting, so please pull this driver deletion. Thanks, Paul. --- The following changes since commit 272b98c6455f00884f0350f775c5342358ebb73f: Linux 3.12-rc1 (2013-09-16 16:17:51 -0400) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux.git aic7xxx-delete for you to fetch changes up to 1ef2840c7207c8f22d0065d9149bad7dc5e3dca1: scsi: delete decade+ obsolete aic7xxx_old driver (2013-09-19 16:07:44 -0400) Paul Gortmaker (1): scsi: delete decade+ obsolete aic7xxx_old driver Documentation/scsi/00-INDEX | 2 - Documentation/scsi/aic7xxx_old.txt | 511 -- MAINTAINERS | 1 - drivers/scsi/Kconfig|41 - drivers/scsi/Makefile | 1 - drivers/scsi/aic7xxx_old.c | 11149 -- drivers/scsi/aic7xxx_old/aic7xxx.h |28 - drivers/scsi/aic7xxx_old/aic7xxx.reg| 1401 drivers/scsi/aic7xxx_old/aic7xxx.seq| 1539 - drivers/scsi/aic7xxx_old/aic7xxx_proc.c | 270 - drivers/scsi/aic7xxx_old/aic7xxx_reg.h | 629 -- drivers/scsi/aic7xxx_old/aic7xxx_seq.c | 817 --- drivers/scsi/aic7xxx_old/scsi_message.h |49 - drivers/scsi/aic7xxx_old/sequencer.h| 135 - 14 files changed, 16573 deletions(-) delete mode 100644 Documentation/scsi/aic7xxx_old.txt delete mode 100644 drivers/scsi/aic7xxx_old.c delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.h delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.reg delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.seq delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_proc.c delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_reg.h delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_seq.c delete mode 100644 drivers/scsi/aic7xxx_old/scsi_message.h delete mode 100644 drivers/scsi/aic7xxx_old/sequencer.h -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [GIT PULL] delete decade+ obsolete aic7xxx_old driver
On 11/08/2013 11:04 AM, Paul Gortmaker wrote: Paul Gortmaker (1): scsi: delete decade+ obsolete aic7xxx_old driver Documentation/scsi/00-INDEX | 2 - Documentation/scsi/aic7xxx_old.txt | 511 -- MAINTAINERS | 1 - drivers/scsi/Kconfig|41 - drivers/scsi/Makefile | 1 - drivers/scsi/aic7xxx_old.c | 11149 -- drivers/scsi/aic7xxx_old/aic7xxx.h |28 - drivers/scsi/aic7xxx_old/aic7xxx.reg| 1401 drivers/scsi/aic7xxx_old/aic7xxx.seq| 1539 - drivers/scsi/aic7xxx_old/aic7xxx_proc.c | 270 - drivers/scsi/aic7xxx_old/aic7xxx_reg.h | 629 -- drivers/scsi/aic7xxx_old/aic7xxx_seq.c | 817 --- drivers/scsi/aic7xxx_old/scsi_message.h |49 - drivers/scsi/aic7xxx_old/sequencer.h| 135 - 14 files changed, 16573 deletions(-) delete mode 100644 Documentation/scsi/aic7xxx_old.txt delete mode 100644 drivers/scsi/aic7xxx_old.c delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.h delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.reg delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx.seq delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_proc.c delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_reg.h delete mode 100644 drivers/scsi/aic7xxx_old/aic7xxx_seq.c delete mode 100644 drivers/scsi/aic7xxx_old/scsi_message.h delete mode 100644 drivers/scsi/aic7xxx_old/sequencer.h Farewell old friend...don't let the door hit you in the ass on the way out ;-) -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/1] scsi: hpsa correct gen9 PCI IDs
From: Mike Miller mike.mil...@hp.com
This patch deletes one ID that never should have in in hpsa. It also the PCI
ID's for two cancelled products.
Please consider this for inclusion.
Signed-off-by: Mike Miller mike.mil...@hp.com
---
drivers/scsi/hpsa.c |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/scsi/hpsa.c b/drivers/scsi/hpsa.c
index 891c86b..5ddf749 100644
--- a/drivers/scsi/hpsa.c
+++ b/drivers/scsi/hpsa.c
@@ -91,21 +91,18 @@ static const struct pci_device_id hpsa_pci_device_id[] = {
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
- {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
+ {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x334D},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
- {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x334D},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
- {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1920},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
- {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
{PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
@@ -140,11 +137,11 @@ static struct board_type products[] = {
{0x3249103C, Smart Array P812, SA5_access},
{0x324A103C, Smart Array P712m, SA5_access},
{0x324B103C, Smart Array P711m, SA5_access},
+ {0x334D103C, Smart Array P822se, SA5_access},
{0x3350103C, Smart Array P222, SA5_access},
{0x3351103C, Smart Array P420, SA5_access},
{0x3352103C, Smart Array P421, SA5_access},
{0x3353103C, Smart Array P822, SA5_access},
- {0x334D103C, Smart Array P822se, SA5_access},
{0x3354103C, Smart Array P420i, SA5_access},
{0x3355103C, Smart Array P220i, SA5_access},
{0x3356103C, Smart Array P721m, SA5_access},
--
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[PATCH 3/5] ata: Add APM X-Gene SATA driver
Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/ata/Kconfig |7 + drivers/ata/Makefile |2 + drivers/ata/sata_xgene.c | 1385 ++ drivers/ata/sata_xgene.h | 112 4 files changed, 1506 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/sata_xgene.c create mode 100644 drivers/ata/sata_xgene.h diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 4e73772..41b9da3 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -106,6 +106,13 @@ config AHCI_IMX If unsure, say N. +config SATA_XGENE + tristate APM X-Gene 6.0Gbps SATA support + depends on SATA_AHCI_PLATFORM + default y if ARM64 + help + This option enables support for APM X-Gene SoC SATA controller. + config SATA_FSL tristate Freescale 3.0Gbps SATA support depends on FSL_SOC diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 46518c6..022f9d1 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o obj-$(CONFIG_SATA_HIGHBANK)+= sata_highbank.o libahci.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o +sata-xgene-objs := sata_xgene.o sata_xgene_serdes.o +obj-$(CONFIG_SATA_XGENE) += sata-xgene.o # SFF w/ custom DMA obj-$(CONFIG_PDC_ADMA) += pdc_adma.o diff --git a/drivers/ata/sata_xgene.c b/drivers/ata/sata_xgene.c new file mode 100644 index 000..93ccf89 --- /dev/null +++ b/drivers/ata/sata_xgene.c @@ -0,0 +1,1385 @@ +/* + * AppliedMicro X-Gene SoC SATA Driver + * + * Copyright (c) 2013, Applied Micro Circuits Corporation + * Author: Loc Ho l...@apm.com + * Tuan Phan tp...@apm.com + * Suman Tripathi stripa...@apm.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + */ +#include linux/module.h +#include linux/platform_device.h +#include linux/of_address.h +#include linux/of_irq.h +#include linux/acpi.h +#include linux/efi.h +#include sata_xgene.h + +#undef XGENE_DBG_CSR /* Enable CSR read/write dumping */ +#ifdef XGENE_DBG_CSR +#define XGENE_CSRDBG(fmt, args...) \ + printk(KERN_INFO XGENESATA: fmt \n, ## args); +#else +#define XGENE_CSRDBG(fmt, args...) +#endif + +/* Max # of disk per a controller */ +#define MAX_AHCI_CHN_PERCTR2 + +#define SATA_DIAG_OFFSET 0xD000 +#define SATA_GLB_OFFSET0xD850 +#define SATA_SHIM_OFFSET 0xE000 +#define SATA_MASTER_OFFSET 0xF000 +#define SATA_PORT0_OFFSET 0x0100 +#define SATA_PORT1_OFFSET 0x0180 + +/* SATA host controller CSR */ +#define SLVRDERRATTRIBUTES_ADDR0x +#define SLVWRERRATTRIBUTES_ADDR0x0004 +#define MSTRDERRATTRIBUTES_ADDR0x0008 +#define MSTWRERRATTRIBUTES_ADDR0x000c +#define BUSCTLREG_ADDR 0x0014 +#define MSTAWAUX_COHERENT_BYPASS_SET(dst, src) \ + (((dst) ~0x0002) | (((u32)(src)1) 0x0002)) +#define MSTARAUX_COHERENT_BYPASS_SET(dst, src) \ + (((dst) ~0x0001) | (((u32)(src)) 0x0001)) +#define IOFMSTRWAUX_ADDR 0x0018 +#define INTSTATUSMASK_ADDR 0x002c +#define ERRINTSTATUS_ADDR 0x0030 +#define ERRINTSTATUSMASK_ADDR 0x0034 + +/* SATA host AHCI CSR */ +#define PORTCFG_ADDR 0x00a4 +#define PORTADDR_SET(dst, src) \ + (((dst) ~0x003f) | (((u32)(src)) 0x003f)) +#define PORTPHY1CFG_ADDR 0x00a8 +#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \ + (((dst) ~0x0010) | (((u32)(src) 0x14) 0x0010)) +#define PORTPHY2CFG_ADDR 0x00ac +#define PORTPHY3CFG_ADDR 0x00b0 +#define PORTPHY4CFG_ADDR 0x00b4 +#define PORTPHY5CFG_ADDR 0x00b8 +#define SCTL0_ADDR 0x012C +#define PORTPHY5CFG_RTCHG_SET(dst, src) \ + (((dst) ~0xfff0) | (((u32)(src) 0x14) 0xfff0)) +#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \ + (((dst) ~0x0100) | (((u32)(src) 0x18)
[PATCH 0/5] ata: Add APM X-Gene SATA controller support
Add APM X-Gene SATA controller support Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- Loc Ho (5): ata: Export AHCI library functions required by APM X-Gene SATA driver arm64: Add APM X-Gene SATA DTS binding ata: Add APM X-Gene SATA driver ata: Add APM X-Gene SATA serdes functions Documentation: Add documentation for APM X-Gene SATA binding .../devicetree/bindings/ata/apm-xgene.txt | 84 + arch/arm64/boot/dts/apm-storm.dtsi | 73 + drivers/ata/Kconfig|7 + drivers/ata/Makefile |2 + drivers/ata/ahci.h |6 + drivers/ata/libahci.c | 13 +- drivers/ata/sata_xgene.c | 1385 ++ drivers/ata/sata_xgene.h | 112 ++ drivers/ata/sata_xgene_serdes.c| 1982 9 files changed, 3659 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt create mode 100644 drivers/ata/sata_xgene.c create mode 100644 drivers/ata/sata_xgene.h create mode 100644 drivers/ata/sata_xgene_serdes.c -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/5] arm64: Add APM X-Gene SATA DTS binding
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 73
1 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index 359d7b6..09fc967 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -176,6 +176,36 @@
reg-names = csr-reg;
clock-output-names = eth8clk;
};
+
+ eth01clk: eth01clk@1f21c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = eth01clk;
+ reg = 0x0 0x1f21c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = eth01clk;
+ };
+
+ eth23clk: eth23clk@1f22c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = eth23clk;
+ reg = 0x0 0x1f22c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = eth23clk;
+ };
+
+ sata45clk: sata45clk@1f23c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = sata45clk;
+ reg = 0x0 0x1f23c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = sata45clk;
+ };
};
serial0: serial@1c02 {
@@ -193,5 +223,48 @@
reg = 0x0 0x1714 0x0 0x100;
mask = 0x1;
};
+
+ sata0: sata@1a00 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a00 0x0 0x10
+ 0x0 0x1f21 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x86 0x4;
+ #clock-cells = 1;
+ clocks = eth01clk 0;
+ clock-names = eth01clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata1: sata@1a40 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a40 0x0 0x10
+ 0x0 0x1f22 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x87 0x4;
+ #clock-cells = 1;
+ clocks = eth23clk 0;
+ clock-names = eth23clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata2: sata@1a80 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a80 0x0 0x10
+ 0x0 0x1f23 0x0 0x1
+ 0x0 0x1f2d 0x0 0x1 ;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x88 0x4;
+ #clock-cells = 1;
+ clocks = sata45clk 0;
+ clock-names = sata45clk;
+ status = ok;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
};
};
--
1.5.5
--
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[PATCH 1/5] ata: Export AHCI library functions required by APM X-Gene SATA driver
Export required functions by APM X-Gene SATA driver to avoid duplicate code.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/ata/ahci.h|6 ++
drivers/ata/libahci.c | 13 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 1145637..cf881e0 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -368,6 +368,12 @@ irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance);
irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
void ahci_print_info(struct ata_host *host, const char *scc_s);
int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
+void ahci_sw_activity(struct ata_link *link);
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat);
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+ struct ata_taskfile *tf, int is_cmd, u16 flags,
+ unsigned long timeout_msec);
static inline void __iomem *__ahci_port_base(struct ata_host *host,
unsigned int port_no)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index aaac4fb..de7e074 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -68,7 +68,6 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap,
u32 state,
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
static int ahci_port_start(struct ata_port *ap);
@@ -553,7 +552,7 @@ static int ahci_scr_read(struct ata_link *link, unsigned
int sc_reg, u32 *val)
return -EINVAL;
}
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
void __iomem *port_mmio = ahci_port_base(link-ap);
int offset = ahci_scr_offset(link-ap, sc_reg);
@@ -564,6 +563,7 @@ static int ahci_scr_write(struct ata_link *link, unsigned
int sc_reg, u32 val)
}
return -EINVAL;
}
+EXPORT_SYMBOL_GPL(ahci_scr_write);
void ahci_start_engine(struct ata_port *ap)
{
@@ -869,7 +869,7 @@ int ahci_reset_controller(struct ata_host *host)
}
EXPORT_SYMBOL_GPL(ahci_reset_controller);
-static void ahci_sw_activity(struct ata_link *link)
+void ahci_sw_activity(struct ata_link *link)
{
struct ata_port *ap = link-ap;
struct ahci_port_priv *pp = ap-private_data;
@@ -882,6 +882,7 @@ static void ahci_sw_activity(struct ata_link *link)
if (!timer_pending(emp-timer))
mod_timer(emp-timer, jiffies + msecs_to_jiffies(10));
}
+EXPORT_SYMBOL_GPL(ahci_sw_activity);
static void ahci_sw_activity_blink(unsigned long arg)
{
@@ -1239,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
}
EXPORT_SYMBOL_GPL(ahci_kick_engine);
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
struct ata_taskfile *tf, int is_cmd, u16 flags,
unsigned long timeout_msec)
{
@@ -1268,6 +1269,7 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int
pmp,
return 0;
}
+EXPORT_SYMBOL_GPL(ahci_exec_polled_cmd);
int ahci_do_softreset(struct ata_link *link, unsigned int *class,
int pmp, unsigned long deadline,
@@ -1552,7 +1554,7 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
dev_err(ap-host-dev, failed to clear device error\n);
}
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
{
struct ahci_host_priv *hpriv = ap-host-private_data;
struct ahci_port_priv *pp = ap-private_data;
@@ -1662,6 +1664,7 @@ static void ahci_error_intr(struct ata_port *ap, u32
irq_stat)
} else
ata_port_abort(ap);
}
+EXPORT_SYMBOL_GPL(ahci_error_intr);
static void ahci_handle_port_interrupt(struct ata_port *ap,
void __iomem *port_mmio, u32 status)
--
1.5.5
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[PATCH 5/5] Documentation: Add documentation for APM X-Gene SATA DTS binding
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
.../devicetree/bindings/ata/apm-xgene.txt | 84
1 files changed, 84 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt
b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644
index 000..cd52864
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,84 @@
+* APM X-Gene 6.0 Gb/s SATA nodes
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible : Shall be apm,xgene-ahci
+- reg : First memory resource shall be the AHCI memory
resource
+ Second memory resource shall be the Serdes memory
resource
+ Third memory resource shall be the optional Serdes
+ memory resource if mux'ed with another IP
+- interrupt-parent : Interrupt controller
+- interrupts : Interrupt mapping for SATA IRQ
+- #clock-cells : Shall be value of 1
+- clocks : Reference to the clock entry
+- clock-names : Shall be eth01clk, eth23clk, or eth45clk.
+
+Optional properties:
+- status : Shall be ok if enabled or na if disabled. Default
+ is ok.
+- serdes-diff-clk : Shall be 0 for external, 1 internal differential,
+ or 2 internal single ended clock. Default is 0.
+- gen-sel : Shall be 1 (force Gen1), 2 (Force Gen2, or 3 Gen3).
+ Default is 3.
+- EQA1 : Serdes EQ parameter for A1 chip. Default is 9.
+- EQ : Serdes EQ parameter for non-A1 chip. Default is 2.
+- GENAVG : Enable averaging Serdes calculation. Default is 0 for
+ A1 chip and 1 for non-A1 chip.
+- LBA1 : Serdes loopback buffer for A1 chip. Default is 1;
+- LB : Serdes loopback buffer for non-A1 chip. Default is 0;
+- LCA1 : Serdes loopback enable control for A1 chip. Default
+ is 1;
+- LC : Serdes loopback enable control for non-A1 chip.
+ Default is 0;
+- CDRA1: Serdes SPD select CDR for A1 chip. Default is
5.
+- CDR : Serdes SPD select CDR for non-A1 chip. Default is 5.
+- PQA1 : Serdes PQ for A1 chip. Default is 8.
+- PQ : Serdes PQ for non-A1 chip. Default is 0xA.
+- coherent : Enable coherent (1 = enable, 0 = disable).
+ Default is 1.
+
+Example:
+ sata0: sata@1a00 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a00 0x0 0x10
+ 0x0 0x1f21 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x86 0x4;
+ #clock-cells = 1;
+ clocks = eth01clk 0;
+ clock-names = eth01clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata1: sata@1a40 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a40 0x0 0x10
+ 0x0 0x1f22 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x87 0x4;
+ #clock-cells = 1;
+ clocks = eth23clk 0;
+ clock-names = eth23clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata2: sata@1a80 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a80 0x0 0x10
+ 0x0 0x1f23 0x0 0x1
+ 0x0 0x1f2d 0x0 0x1 ;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x88 0x4;
+ #clock-cells = 1;
+ clocks = sata45clk 0;
+ clock-names = sata45clk;
+ status = ok;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
--
1.5.5
--
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Re: [PATCH 2/5] arm64: Add APM X-Gene SATA DTS binding
On Fri, Nov 08, 2013 at 03:30:35PM -0700, Loc Ho wrote: Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- arch/arm64/boot/dts/apm-storm.dtsi | 73 1 files changed, 73 insertions(+), 0 deletions(-) Technically this patch doesn't add a binding (the binding is just the documentation part), it updates the device tree with the SATA devices. Also, again: Patch description! Not optional. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH/RESEND v2 0/2] SATA disk resume time optimization
I tested your patches and they do function. We tried a similar approach a few months back where instead of waking the scsi disks we just set them all to runtime_suspended and skipped the resume. Then we let them be awakened later by read/write access just as you have. It's a really tempting approach, in theory, since you're saving both time and power by only waking those disks you know you need. But in practice I've found that userspace doesn't play nice. In my experience the user layer almost always manages to wake up every mounted disk after resume, even if you didn't deliberately use them prior to suspend. The accesses can come from the file manager doing a scan after resume, or from any number of apps running on the system that decide they need to get even the smallest piece of information from the disks. A simple space check will wake them up. Thus when you leave all the disks stopped, user space ends up triggering a traffic jam when the OS wakes back up, which makes disk access take even longer. My patch works very similarly to yours but just triggers an asynchronous wakeup to all the disks in anticipation of userspace's needs. We've tested it pretty heavily on ubuntu machines of all types and it's done well. Ultimately I would be happy if either solution were accepted though, because this is a serious performance problem that needs to be addressed in some way. On Wed, Nov 06, 2013 at 08:53:11PM -0500, Phillip Susi wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 10/17/2013 03:33 PM, Todd E Brandt wrote: The essential issue behind hard disks' lengthy resume time is the ata port driver blocking until the ATA port hardware is finished coming online. So the kernel isn't really doing anything during all those seconds that the disks are resuming, it's just blocking until the hardware says it's ready to accept commands. Applying this patch set I have been working in a similar direction and have patches to follow. Instead of backgrounding the start in sd_resume, I have removed it entirely, and background the resume at the ata port layer, as well as avoid resuming Power on in Standby disks entirely. -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.14 (GNU/Linux) Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/ iQEcBAEBCgAGBQJSevKEAAoJEJrBOlT6nu75FFkIAL8mwXOuuNvY5GoppHVMcweC EOBz6t2Xmc/TsGYr9u4kRVXbf3G0trSM9dj/XSJ6p+Dj/su/vJ69yKxp7sUPidgz zqjfKlG+myMQIaAO+tPGXvMcmT74BXjgjobZw2lUyLyRPLD9elDGmrDA5ZXZ+hiz hzSx4gOC57j+sK/pmoZ7U/CWeWYEYQ+J9xBXm0hzbBbSTjpzVsR0T+7xU+WVkeX0 Ox++FFBZp2b1xJgaREurRv1mORx/GJ+PfSETb49P5BWaWW+QVwOEhWOX/JQNc/Pp ANJmttP4WPvlRV0X3hD6FvAYSnu1qbwwGOiP/j5g7mklyfm5alA0jcuahc1w5tI= =9KhA -END PGP SIGNATURE- -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 4/5] ata: Add APM X-Gene SATA serdes functions
Hi, Forgot to run checkpatch on this one. It will be fixed in the new version. -Loc On Fri, Nov 8, 2013 at 4:38 PM, Olof Johansson o...@lixom.net wrote: On Fri, Nov 08, 2013 at 03:30:37PM -0700, Loc Ho wrote: Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/ata/sata_xgene_serdes.c | 1982 +++ 1 files changed, 1982 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/sata_xgene_serdes.c To start with: This patch is riddled with checkpatch errors from whitespace stuff. It completely lacks any kind of patch description. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/5] arm64: Add APM X-Gene SATA DTS binding
Hi, I will add description on the next version. -Loc On Fri, Nov 8, 2013 at 4:39 PM, Olof Johansson o...@lixom.net wrote: On Fri, Nov 08, 2013 at 03:30:35PM -0700, Loc Ho wrote: Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- arch/arm64/boot/dts/apm-storm.dtsi | 73 1 files changed, 73 insertions(+), 0 deletions(-) Technically this patch doesn't add a binding (the binding is just the documentation part), it updates the device tree with the SATA devices. Also, again: Patch description! Not optional. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 1/5] ata: Export AHCI library functions required by APM X-Gene SATA driver
ata: Export required functions by APM X-Gene SATA driver to avoid duplicate
code.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/ata/ahci.h|6 ++
drivers/ata/libahci.c | 13 -
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 1145637..cf881e0 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -368,6 +368,12 @@ irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance);
irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
void ahci_print_info(struct ata_host *host, const char *scc_s);
int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
+void ahci_sw_activity(struct ata_link *link);
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat);
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+ struct ata_taskfile *tf, int is_cmd, u16 flags,
+ unsigned long timeout_msec);
static inline void __iomem *__ahci_port_base(struct ata_host *host,
unsigned int port_no)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index aaac4fb..de7e074 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -68,7 +68,6 @@ static ssize_t ahci_transmit_led_message(struct ata_port *ap,
u32 state,
static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
static int ahci_port_start(struct ata_port *ap);
@@ -553,7 +552,7 @@ static int ahci_scr_read(struct ata_link *link, unsigned
int sc_reg, u32 *val)
return -EINVAL;
}
-static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
+int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
void __iomem *port_mmio = ahci_port_base(link-ap);
int offset = ahci_scr_offset(link-ap, sc_reg);
@@ -564,6 +563,7 @@ static int ahci_scr_write(struct ata_link *link, unsigned
int sc_reg, u32 val)
}
return -EINVAL;
}
+EXPORT_SYMBOL_GPL(ahci_scr_write);
void ahci_start_engine(struct ata_port *ap)
{
@@ -869,7 +869,7 @@ int ahci_reset_controller(struct ata_host *host)
}
EXPORT_SYMBOL_GPL(ahci_reset_controller);
-static void ahci_sw_activity(struct ata_link *link)
+void ahci_sw_activity(struct ata_link *link)
{
struct ata_port *ap = link-ap;
struct ahci_port_priv *pp = ap-private_data;
@@ -882,6 +882,7 @@ static void ahci_sw_activity(struct ata_link *link)
if (!timer_pending(emp-timer))
mod_timer(emp-timer, jiffies + msecs_to_jiffies(10));
}
+EXPORT_SYMBOL_GPL(ahci_sw_activity);
static void ahci_sw_activity_blink(unsigned long arg)
{
@@ -1239,7 +1240,7 @@ int ahci_kick_engine(struct ata_port *ap)
}
EXPORT_SYMBOL_GPL(ahci_kick_engine);
-static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
+int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
struct ata_taskfile *tf, int is_cmd, u16 flags,
unsigned long timeout_msec)
{
@@ -1268,6 +1269,7 @@ static int ahci_exec_polled_cmd(struct ata_port *ap, int
pmp,
return 0;
}
+EXPORT_SYMBOL_GPL(ahci_exec_polled_cmd);
int ahci_do_softreset(struct ata_link *link, unsigned int *class,
int pmp, unsigned long deadline,
@@ -1552,7 +1554,7 @@ static void ahci_fbs_dec_intr(struct ata_port *ap)
dev_err(ap-host-dev, failed to clear device error\n);
}
-static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
+void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
{
struct ahci_host_priv *hpriv = ap-host-private_data;
struct ahci_port_priv *pp = ap-private_data;
@@ -1662,6 +1664,7 @@ static void ahci_error_intr(struct ata_port *ap, u32
irq_stat)
} else
ata_port_abort(ap);
}
+EXPORT_SYMBOL_GPL(ahci_error_intr);
static void ahci_handle_port_interrupt(struct ata_port *ap,
void __iomem *port_mmio, u32 status)
--
1.5.5
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[PATCH v2 0/5] ata: Add APM X-Gene SATA controller support
ata: Add APM X-Gene SATA controller support v2: * Clean up file sata_xgene.c with Lindent and etc * Clean up file sata_xgene_serdes.c with Lindent and etc * Add description to each patch v1: * inital version Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- Loc Ho (5): ata: Export AHCI library functions required by APM X-Gene SATA driver arm64: Add APM X-Gene DTS entry for SATA controllers ata: Add APM X-Gene SATA driver ata: Add APM X-Gene SATA serdes functions Documentation: Add documentation for APM X-Gene SATA DTS binding .../devicetree/bindings/ata/apm-xgene.txt | 84 + arch/arm64/boot/dts/apm-storm.dtsi | 73 + drivers/ata/Kconfig|7 + drivers/ata/Makefile |2 + drivers/ata/ahci.h |6 + drivers/ata/libahci.c | 13 +- drivers/ata/sata_xgene.c | 1394 ++ drivers/ata/sata_xgene.h | 112 ++ drivers/ata/sata_xgene_serdes.c| 2004 9 files changed, 3690 insertions(+), 5 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt create mode 100644 drivers/ata/sata_xgene.c create mode 100644 drivers/ata/sata_xgene.h create mode 100644 drivers/ata/sata_xgene_serdes.c -- To unsubscribe from this list: send the line unsubscribe linux-scsi in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 5/5] Documentation: Add documentation for APM X-Gene SATA DTS binding
Documentation: Add documentation for APM X-Gene SATA DTS binding
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
.../devicetree/bindings/ata/apm-xgene.txt | 84
1 files changed, 84 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/apm-xgene.txt
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt
b/Documentation/devicetree/bindings/ata/apm-xgene.txt
new file mode 100644
index 000..cd52864
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -0,0 +1,84 @@
+* APM X-Gene 6.0 Gb/s SATA nodes
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+Each SATA controller (pair of ports) have its own node.
+
+Required properties:
+- compatible : Shall be apm,xgene-ahci
+- reg : First memory resource shall be the AHCI memory
resource
+ Second memory resource shall be the Serdes memory
resource
+ Third memory resource shall be the optional Serdes
+ memory resource if mux'ed with another IP
+- interrupt-parent : Interrupt controller
+- interrupts : Interrupt mapping for SATA IRQ
+- #clock-cells : Shall be value of 1
+- clocks : Reference to the clock entry
+- clock-names : Shall be eth01clk, eth23clk, or eth45clk.
+
+Optional properties:
+- status : Shall be ok if enabled or na if disabled. Default
+ is ok.
+- serdes-diff-clk : Shall be 0 for external, 1 internal differential,
+ or 2 internal single ended clock. Default is 0.
+- gen-sel : Shall be 1 (force Gen1), 2 (Force Gen2, or 3 Gen3).
+ Default is 3.
+- EQA1 : Serdes EQ parameter for A1 chip. Default is 9.
+- EQ : Serdes EQ parameter for non-A1 chip. Default is 2.
+- GENAVG : Enable averaging Serdes calculation. Default is 0 for
+ A1 chip and 1 for non-A1 chip.
+- LBA1 : Serdes loopback buffer for A1 chip. Default is 1;
+- LB : Serdes loopback buffer for non-A1 chip. Default is 0;
+- LCA1 : Serdes loopback enable control for A1 chip. Default
+ is 1;
+- LC : Serdes loopback enable control for non-A1 chip.
+ Default is 0;
+- CDRA1: Serdes SPD select CDR for A1 chip. Default is
5.
+- CDR : Serdes SPD select CDR for non-A1 chip. Default is 5.
+- PQA1 : Serdes PQ for A1 chip. Default is 8.
+- PQ : Serdes PQ for non-A1 chip. Default is 0xA.
+- coherent : Enable coherent (1 = enable, 0 = disable).
+ Default is 1.
+
+Example:
+ sata0: sata@1a00 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a00 0x0 0x10
+ 0x0 0x1f21 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x86 0x4;
+ #clock-cells = 1;
+ clocks = eth01clk 0;
+ clock-names = eth01clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata1: sata@1a40 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a40 0x0 0x10
+ 0x0 0x1f22 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x87 0x4;
+ #clock-cells = 1;
+ clocks = eth23clk 0;
+ clock-names = eth23clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata2: sata@1a80 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a80 0x0 0x10
+ 0x0 0x1f23 0x0 0x1
+ 0x0 0x1f2d 0x0 0x1 ;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x88 0x4;
+ #clock-cells = 1;
+ clocks = sata45clk 0;
+ clock-names = sata45clk;
+ status = ok;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
--
1.5.5
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[PATCH v2 3/5] ata: Add APM X-Gene SATA driver
ata: Add APM X-Gene SATA driver Signed-off-by: Loc Ho l...@apm.com Signed-off-by: Tuan Phan tp...@apm.com Signed-off-by: Suman Tripathi stripa...@apm.com --- drivers/ata/Kconfig |7 + drivers/ata/Makefile |2 + drivers/ata/sata_xgene.c | 1394 ++ drivers/ata/sata_xgene.h | 112 4 files changed, 1515 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/sata_xgene.c create mode 100644 drivers/ata/sata_xgene.h diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 4e73772..41b9da3 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -106,6 +106,13 @@ config AHCI_IMX If unsure, say N. +config SATA_XGENE + tristate APM X-Gene 6.0Gbps SATA support + depends on SATA_AHCI_PLATFORM + default y if ARM64 + help + This option enables support for APM X-Gene SoC SATA controller. + config SATA_FSL tristate Freescale 3.0Gbps SATA support depends on FSL_SOC diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 46518c6..022f9d1 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -11,6 +11,8 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o obj-$(CONFIG_SATA_HIGHBANK)+= sata_highbank.o libahci.o obj-$(CONFIG_AHCI_IMX) += ahci_imx.o +sata-xgene-objs := sata_xgene.o sata_xgene_serdes.o +obj-$(CONFIG_SATA_XGENE) += sata-xgene.o # SFF w/ custom DMA obj-$(CONFIG_PDC_ADMA) += pdc_adma.o diff --git a/drivers/ata/sata_xgene.c b/drivers/ata/sata_xgene.c new file mode 100644 index 000..1f0f883 --- /dev/null +++ b/drivers/ata/sata_xgene.c @@ -0,0 +1,1394 @@ +/* + * AppliedMicro X-Gene SoC SATA Driver + * + * Copyright (c) 2013, Applied Micro Circuits Corporation + * Author: Loc Ho l...@apm.com + * Tuan Phan tp...@apm.com + * Suman Tripathi stripa...@apm.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + */ +#include linux/module.h +#include linux/platform_device.h +#include linux/of_address.h +#include linux/of_irq.h +#include linux/acpi.h +#include linux/efi.h +#include sata_xgene.h + +#undef XGENE_DBG_CSR /* Enable CSR read/write dumping */ +#ifdef XGENE_DBG_CSR +#define XGENE_CSRDBG(fmt, args...) \ + printk(KERN_INFO XGENESATA: fmt \n, ## args); +#else +#define XGENE_CSRDBG(fmt, args...) +#endif + +/* Max # of disk per a controller */ +#define MAX_AHCI_CHN_PERCTR2 + +#define SATA_DIAG_OFFSET 0xD000 +#define SATA_GLB_OFFSET0xD850 +#define SATA_SHIM_OFFSET 0xE000 +#define SATA_MASTER_OFFSET 0xF000 +#define SATA_PORT0_OFFSET 0x0100 +#define SATA_PORT1_OFFSET 0x0180 + +/* SATA host controller CSR */ +#define SLVRDERRATTRIBUTES_ADDR0x +#define SLVWRERRATTRIBUTES_ADDR0x0004 +#define MSTRDERRATTRIBUTES_ADDR0x0008 +#define MSTWRERRATTRIBUTES_ADDR0x000c +#define BUSCTLREG_ADDR 0x0014 +#define MSTAWAUX_COHERENT_BYPASS_SET(dst, src) \ + (((dst) ~0x0002) | (((u32)(src)1) 0x0002)) +#define MSTARAUX_COHERENT_BYPASS_SET(dst, src) \ + (((dst) ~0x0001) | (((u32)(src)) 0x0001)) +#define IOFMSTRWAUX_ADDR 0x0018 +#define INTSTATUSMASK_ADDR 0x002c +#define ERRINTSTATUS_ADDR 0x0030 +#define ERRINTSTATUSMASK_ADDR 0x0034 + +/* SATA host AHCI CSR */ +#define PORTCFG_ADDR 0x00a4 +#define PORTADDR_SET(dst, src) \ + (((dst) ~0x003f) | (((u32)(src)) 0x003f)) +#define PORTPHY1CFG_ADDR 0x00a8 +#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \ + (((dst) ~0x0010) | (((u32)(src) 0x14) 0x0010)) +#define PORTPHY2CFG_ADDR 0x00ac +#define PORTPHY3CFG_ADDR 0x00b0 +#define PORTPHY4CFG_ADDR 0x00b4 +#define PORTPHY5CFG_ADDR 0x00b8 +#define SCTL0_ADDR 0x012C +#define PORTPHY5CFG_RTCHG_SET(dst, src) \ + (((dst) ~0xfff0) | (((u32)(src) 0x14) 0xfff0)) +#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \ + (((dst)
[PATCH v2 2/5] arm64: Add APM X-Gene DTS entry for SATA controllers
arm64: Add APM X-Gene SATA clock and controller DTS entries.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
arch/arm64/boot/dts/apm-storm.dtsi | 73
1 files changed, 73 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi
b/arch/arm64/boot/dts/apm-storm.dtsi
index 359d7b6..09fc967 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -176,6 +176,36 @@
reg-names = csr-reg;
clock-output-names = eth8clk;
};
+
+ eth01clk: eth01clk@1f21c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = eth01clk;
+ reg = 0x0 0x1f21c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = eth01clk;
+ };
+
+ eth23clk: eth23clk@1f22c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = eth23clk;
+ reg = 0x0 0x1f22c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = eth23clk;
+ };
+
+ sata45clk: sata45clk@1f23c000 {
+ compatible = apm,xgene-device-clock;
+ #clock-cells = 1;
+ clocks = socplldiv2 0;
+ clock-names = sata45clk;
+ reg = 0x0 0x1f23c000 0x0 0x1000;
+ reg-names = csr-reg;
+ clock-output-names = sata45clk;
+ };
};
serial0: serial@1c02 {
@@ -193,5 +223,48 @@
reg = 0x0 0x1714 0x0 0x100;
mask = 0x1;
};
+
+ sata0: sata@1a00 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a00 0x0 0x10
+ 0x0 0x1f21 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x86 0x4;
+ #clock-cells = 1;
+ clocks = eth01clk 0;
+ clock-names = eth01clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata1: sata@1a40 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a40 0x0 0x10
+ 0x0 0x1f22 0x0 0x1;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x87 0x4;
+ #clock-cells = 1;
+ clocks = eth23clk 0;
+ clock-names = eth23clk;
+ status = na;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
+
+ sata2: sata@1a80 {
+ compatible = apm,xgene-ahci;
+ reg = 0x0 0x1a80 0x0 0x10
+ 0x0 0x1f23 0x0 0x1
+ 0x0 0x1f2d 0x0 0x1 ;
+ interrupt-parent = gic;
+ interrupts = 0x0 0x88 0x4;
+ #clock-cells = 1;
+ clocks = sata45clk 0;
+ clock-names = sata45clk;
+ status = ok;
+ serdes-diff-clk = 0;
+ gen-sel = 3;
+ };
};
};
--
1.5.5
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