Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-19 Thread Sreekanth Reddy 
On Fri, Jun 19, 2015 at 2:44 PM, Johannes Thumshirn jthumsh...@suse.de wrote:
 On Thu, Jun 18, 2015 at 03:27:26PM +0530, Sreekanth Reddy wrote:
 Hi,

 Any other review comments on this patch. please let us known if any
 changes are required.

 Thanks,
 Sreekanth


 Have you sent a follow up on this I may have missed?

 On Fri, Jun 12, 2015 at 4:46 PM, Sreekanth Reddy
 sreekanth.re...@avagotech.com wrote:
  Thanks Johannes, we will take care of this point in our current
  on-development mpt2sas/mpt3sas merging activity.
  diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
  b/drivers/scsi/mpt3sas/mpt3sas_base.c

 [...]

  index 14a781b..c13a365 100644
  --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
  +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
  @@ -83,7 +83,7 @@ static int msix_disable = -1;
   module_param(msix_disable, int, 0);
   MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
  (default=0));
 
  -static int max_msix_vectors = 8;
  +static int max_msix_vectors = -1;
   module_param(max_msix_vectors, int, 0);
   MODULE_PARM_DESC(max_msix_vectors,
 max msix vectors - (default=8));
  ^^^
 
  When changing the default value, please also update the description 
  reflecting
  this change.

Johannes, I didn't notice this previously, I will post next version of
this patch by updating the module parameter description

Thanks,
Sreekanth
 

 Thanks

 --
 Johannes Thumshirn   Storage
 jthumsh...@suse.de +49 911 74053 689
 SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
 GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
 HRB 21284 (AG Nürnberg)



-- 

Regards,
Sreekanth
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Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-19 Thread Johannes Thumshirn 
On Thu, Jun 18, 2015 at 03:27:26PM +0530, Sreekanth Reddy wrote:
 Hi,
 
 Any other review comments on this patch. please let us known if any
 changes are required.
 
 Thanks,
 Sreekanth
 

Have you sent a follow up on this I may have missed?

 On Fri, Jun 12, 2015 at 4:46 PM, Sreekanth Reddy
 sreekanth.re...@avagotech.com wrote:
  Thanks Johannes, we will take care of this point in our current
  on-development mpt2sas/mpt3sas merging activity.
  diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
  b/drivers/scsi/mpt3sas/mpt3sas_base.c

[...]

  index 14a781b..c13a365 100644
  --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
  +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
  @@ -83,7 +83,7 @@ static int msix_disable = -1;
   module_param(msix_disable, int, 0);
   MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
  (default=0));
 
  -static int max_msix_vectors = 8;
  +static int max_msix_vectors = -1;
   module_param(max_msix_vectors, int, 0);
   MODULE_PARM_DESC(max_msix_vectors,
 max msix vectors - (default=8));
 ^^^
 
  When changing the default value, please also update the description 
  reflecting
  this change.
 

Thanks

-- 
Johannes Thumshirn   Storage
jthumsh...@suse.de +49 911 74053 689
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
HRB 21284 (AG Nürnberg)
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Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-19 Thread Johannes Thumshirn 
On Fri, Jun 19, 2015 at 02:51:00PM +0530, Sreekanth Reddy wrote:
 On Fri, Jun 19, 2015 at 2:44 PM, Johannes Thumshirn jthumsh...@suse.de 
 wrote:
  On Thu, Jun 18, 2015 at 03:27:26PM +0530, Sreekanth Reddy wrote:
  Hi,
 
  Any other review comments on this patch. please let us known if any
  changes are required.
 
  Thanks,
  Sreekanth
 
 
  Have you sent a follow up on this I may have missed?
 
  On Fri, Jun 12, 2015 at 4:46 PM, Sreekanth Reddy
  sreekanth.re...@avagotech.com wrote:
   Thanks Johannes, we will take care of this point in our current
   on-development mpt2sas/mpt3sas merging activity.
   diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
   b/drivers/scsi/mpt3sas/mpt3sas_base.c
 
  [...]
 
   index 14a781b..c13a365 100644
   --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
   +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
   @@ -83,7 +83,7 @@ static int msix_disable = -1;
module_param(msix_disable, int, 0);
MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
   (default=0));
  
   -static int max_msix_vectors = 8;
   +static int max_msix_vectors = -1;
module_param(max_msix_vectors, int, 0);
MODULE_PARM_DESC(max_msix_vectors,
  max msix vectors - (default=8));
   ^^^
  
   When changing the default value, please also update the description 
   reflecting
   this change.
 
 Johannes, I didn't notice this previously, I will post next version of
 this patch by updating the module parameter description

No problem :-)

 
 Thanks,
 Sreekanth
  
 
  Thanks
 
  --
  Johannes Thumshirn   Storage
  jthumsh...@suse.de +49 911 74053 689
  SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
  GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
  HRB 21284 (AG Nürnberg)
 
 
 
 -- 
 
 Regards,
 Sreekanth

-- 
Johannes Thumshirn   Storage
jthumsh...@suse.de +49 911 74053 689
SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg
GF: F. Imendörffer, J. Smithard, J. Guild, D. Upmanyu, G. Norton
HRB 21284 (AG Nürnberg)
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-18 Thread Sreekanth Reddy 
Hi,

Any other review comments on this patch. please let us known if any
changes are required.

Thanks,
Sreekanth

On Fri, Jun 12, 2015 at 4:46 PM, Sreekanth Reddy
sreekanth.re...@avagotech.com wrote:
 Thanks Johannes, we will take care of this point in our current
 on-development mpt2sas/mpt3sas merging activity.


 Thanks,
 Sreekanth

 On Fri, Jun 12, 2015 at 4:39 PM, Johannes Thumshirn jthumsh...@suse.de 
 wrote:
 On Fri, Jun 12, 2015 at 03:12:13PM +0530, Sreekanth Reddy wrote:
 In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs 
 to up-to 96.

 Following are changes that are done in this patch
 1. Support this feature only for SAS3 C0 cards and also only when reply 
 post free queue count is greater than 8.
 2. Instead of using single ReplyPostHostIndex system interface, here 12 
 ReplyPostHostIndex system interfaces are used. reply post free queues 
 numbered from 0 to 7 use the first ReplyPostHostIndex system interface to 
 update its corresponding ReplyPostHostIndex values, reply post free queues 
 numbered from 8 to 15 will use the second ReplyPostHostIndex system 
 interface and so on. These 12 ReplyPostHostIndex system interfaces address 
 are saved in the array replyPostRegisterIndex[].
 3. Update the ReplyPostHostIndex value of corresponding reply post free 
 queue in the (its msix_index/8)th entry of replyPostRegisterIndex[] array 
 after processing the reply post descriptor.

 Signed-off-by: Sreekanth Reddy sreekanth.re...@avagotech.com
 ---
  drivers/scsi/mpt3sas/mpt3sas_base.c | 70 
 +
  drivers/scsi/mpt3sas/mpt3sas_base.h |  7 +++-
  2 files changed, 69 insertions(+), 8 deletions(-)

 diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
 b/drivers/scsi/mpt3sas/mpt3sas_base.c
 index 14a781b..c13a365 100644
 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
 +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
 @@ -83,7 +83,7 @@ static int msix_disable = -1;
  module_param(msix_disable, int, 0);
  MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
 (default=0));

 -static int max_msix_vectors = 8;
 +static int max_msix_vectors = -1;
  module_param(max_msix_vectors, int, 0);
  MODULE_PARM_DESC(max_msix_vectors,
max msix vectors - (default=8));

 When changing the default value, please also update the description 
 reflecting
 this change.

 @@ -1009,8 +1009,15 @@ _base_interrupt(int irq, void *bus_id)
   }

   wmb();
 - writel(reply_q-reply_post_host_index | (msix_index 
 - MPI2_RPHI_MSIX_INDEX_SHIFT), ioc-chip-ReplyPostHostIndex);
 + if (ioc-msix96_vector) {
 + writel(reply_q-reply_post_host_index | ((msix_index   7) 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-replyPostRegisterIndex[msix_index/8]);
 + } else {
 + writel(reply_q-reply_post_host_index | (msix_index 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-chip-ReplyPostHostIndex);
 + }
   atomic_dec(reply_q-busy);
   return IRQ_HANDLED;
  }
 @@ -1560,8 +1567,6 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)

   pci_read_config_word(ioc-pdev, base + 2, message_control);
   ioc-msix_vector_count = (message_control  0x3FF) + 1;
 - if (ioc-msix_vector_count  8)
 - ioc-msix_vector_count = 8;
   dinitprintk(ioc, pr_info(MPT3SAS_FMT
   msix is supported, vector_count(%d)\n,
   ioc-name, ioc-msix_vector_count));
 @@ -1880,6 +1885,31 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER 
 *ioc)
   if (r)
   goto out_fail;

 + /* Use the Combined reply queue feature only for SAS3 C0 HBAs and
 +  * also only when reply queue count is greater than 8
 +  */
 + if (ioc-msix96_vector  ioc-reply_queue_count  8) {
 + /* If this is an 96 vector supported device,
 + set up ReplyPostIndex addresses */
 + ioc-replyPostRegisterIndex = kcalloc(12,
 + sizeof(resource_size_t *), GFP_KERNEL);
 + if (!ioc-replyPostRegisterIndex) {
 + dfailprintk(ioc, printk(MPT3SAS_FMT
 + allocation for reply Post Register Index 
 failed!!!\n,
 +
 ioc-name));
 + r = -ENOMEM;
 + goto out_fail;
 + }
 +
 + for (i = 0; i  12; i++) {
 + ioc-replyPostRegisterIndex[i] = (resource_size_t *)
 + ((u8 *)ioc-chip-Doorbell +
 + MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
 + (i * 0x10));
 + }
 + } else
 + ioc-msix96_vector = 0;
 +
   list_for_each_entry(reply_q, ioc-reply_queue_list, list)
   pr_info(MPT3SAS_FMT %s: IRQ %d\n,
   reply_q-name,  ((ioc-msix_enable) ? PCI-MSI-X enabled 
 :
 @@ -1901,6 +1931,8 @@

[PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-12 Thread Sreekanth Reddy 
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to 
up-to 96.

Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post 
free queue count is greater than 8.
2. Instead of using single ReplyPostHostIndex system interface, here 12 
ReplyPostHostIndex system interfaces are used. reply post free queues numbered 
from 0 to 7 use the first ReplyPostHostIndex system interface to update its 
corresponding ReplyPostHostIndex values, reply post free queues numbered from 8 
to 15 will use the second ReplyPostHostIndex system interface and so on. These 
12 ReplyPostHostIndex system interfaces address are saved in the array 
replyPostRegisterIndex[].
3. Update the ReplyPostHostIndex value of corresponding reply post free queue 
in the (its msix_index/8)th entry of replyPostRegisterIndex[] array after 
processing the reply post descriptor.

Signed-off-by: Sreekanth Reddy sreekanth.re...@avagotech.com
---
 drivers/scsi/mpt3sas/mpt3sas_base.c | 70 +
 drivers/scsi/mpt3sas/mpt3sas_base.h |  7 +++-
 2 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 14a781b..c13a365 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -83,7 +83,7 @@ static int msix_disable = -1;
 module_param(msix_disable, int, 0);
 MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts (default=0));
 
-static int max_msix_vectors = 8;
+static int max_msix_vectors = -1;
 module_param(max_msix_vectors, int, 0);
 MODULE_PARM_DESC(max_msix_vectors,
 max msix vectors - (default=8));
@@ -1009,8 +1009,15 @@ _base_interrupt(int irq, void *bus_id)
}
 
wmb();
-   writel(reply_q-reply_post_host_index | (msix_index 
-   MPI2_RPHI_MSIX_INDEX_SHIFT), ioc-chip-ReplyPostHostIndex);
+   if (ioc-msix96_vector) {
+   writel(reply_q-reply_post_host_index | ((msix_index   7) 
+   MPI2_RPHI_MSIX_INDEX_SHIFT),
+   ioc-replyPostRegisterIndex[msix_index/8]);
+   } else {
+   writel(reply_q-reply_post_host_index | (msix_index 
+   MPI2_RPHI_MSIX_INDEX_SHIFT),
+   ioc-chip-ReplyPostHostIndex);
+   }
atomic_dec(reply_q-busy);
return IRQ_HANDLED;
 }
@@ -1560,8 +1567,6 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
 
pci_read_config_word(ioc-pdev, base + 2, message_control);
ioc-msix_vector_count = (message_control  0x3FF) + 1;
-   if (ioc-msix_vector_count  8)
-   ioc-msix_vector_count = 8;
dinitprintk(ioc, pr_info(MPT3SAS_FMT
msix is supported, vector_count(%d)\n,
ioc-name, ioc-msix_vector_count));
@@ -1880,6 +1885,31 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
if (r)
goto out_fail;
 
+   /* Use the Combined reply queue feature only for SAS3 C0 HBAs and
+* also only when reply queue count is greater than 8
+*/
+   if (ioc-msix96_vector  ioc-reply_queue_count  8) {
+   /* If this is an 96 vector supported device,
+   set up ReplyPostIndex addresses */
+   ioc-replyPostRegisterIndex = kcalloc(12,
+   sizeof(resource_size_t *), GFP_KERNEL);
+   if (!ioc-replyPostRegisterIndex) {
+   dfailprintk(ioc, printk(MPT3SAS_FMT
+   allocation for reply Post Register Index failed!!!\n,
+  ioc-name));
+   r = -ENOMEM;
+   goto out_fail;
+   }
+
+   for (i = 0; i  12; i++) {
+   ioc-replyPostRegisterIndex[i] = (resource_size_t *)
+   ((u8 *)ioc-chip-Doorbell +
+   MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
+   (i * 0x10));
+   }
+   } else
+   ioc-msix96_vector = 0;
+
list_for_each_entry(reply_q, ioc-reply_queue_list, list)
pr_info(MPT3SAS_FMT %s: IRQ %d\n,
reply_q-name,  ((ioc-msix_enable) ? PCI-MSI-X enabled :
@@ -1901,6 +1931,8 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
pci_release_selected_regions(ioc-pdev, ioc-bars);
pci_disable_pcie_error_reporting(pdev);
pci_disable_device(pdev);
+   if (ioc-msix96_vector)
+   kfree(ioc-replyPostRegisterIndex);
return r;
 }
 
@@ -4522,8 +4554,16 @@ _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, 
int sleep_flag)
 
/* initialize reply post host index */
list_for_each_entry(reply_q, ioc-reply_queue_list, list) {
-   writel(reply_q-msix_index

Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-12 Thread Johannes Thumshirn 
On Fri, Jun 12, 2015 at 03:12:13PM +0530, Sreekanth Reddy wrote:
 In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs 
 to up-to 96.
 
 Following are changes that are done in this patch
 1. Support this feature only for SAS3 C0 cards and also only when reply post 
 free queue count is greater than 8.
 2. Instead of using single ReplyPostHostIndex system interface, here 12 
 ReplyPostHostIndex system interfaces are used. reply post free queues 
 numbered from 0 to 7 use the first ReplyPostHostIndex system interface to 
 update its corresponding ReplyPostHostIndex values, reply post free queues 
 numbered from 8 to 15 will use the second ReplyPostHostIndex system interface 
 and so on. These 12 ReplyPostHostIndex system interfaces address are saved in 
 the array replyPostRegisterIndex[].
 3. Update the ReplyPostHostIndex value of corresponding reply post free queue 
 in the (its msix_index/8)th entry of replyPostRegisterIndex[] array after 
 processing the reply post descriptor.
 
 Signed-off-by: Sreekanth Reddy sreekanth.re...@avagotech.com
 ---
  drivers/scsi/mpt3sas/mpt3sas_base.c | 70 
 +
  drivers/scsi/mpt3sas/mpt3sas_base.h |  7 +++-
  2 files changed, 69 insertions(+), 8 deletions(-)
 
 diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
 b/drivers/scsi/mpt3sas/mpt3sas_base.c
 index 14a781b..c13a365 100644
 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
 +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
 @@ -83,7 +83,7 @@ static int msix_disable = -1;
  module_param(msix_disable, int, 0);
  MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
 (default=0));
  
 -static int max_msix_vectors = 8;
 +static int max_msix_vectors = -1;
  module_param(max_msix_vectors, int, 0);
  MODULE_PARM_DESC(max_msix_vectors,
max msix vectors - (default=8));

When changing the default value, please also update the description reflecting
this change.

 @@ -1009,8 +1009,15 @@ _base_interrupt(int irq, void *bus_id)
   }
  
   wmb();
 - writel(reply_q-reply_post_host_index | (msix_index 
 - MPI2_RPHI_MSIX_INDEX_SHIFT), ioc-chip-ReplyPostHostIndex);
 + if (ioc-msix96_vector) {
 + writel(reply_q-reply_post_host_index | ((msix_index   7) 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-replyPostRegisterIndex[msix_index/8]);
 + } else {
 + writel(reply_q-reply_post_host_index | (msix_index 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-chip-ReplyPostHostIndex);
 + }
   atomic_dec(reply_q-busy);
   return IRQ_HANDLED;
  }
 @@ -1560,8 +1567,6 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
  
   pci_read_config_word(ioc-pdev, base + 2, message_control);
   ioc-msix_vector_count = (message_control  0x3FF) + 1;
 - if (ioc-msix_vector_count  8)
 - ioc-msix_vector_count = 8;
   dinitprintk(ioc, pr_info(MPT3SAS_FMT
   msix is supported, vector_count(%d)\n,
   ioc-name, ioc-msix_vector_count));
 @@ -1880,6 +1885,31 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
   if (r)
   goto out_fail;
  
 + /* Use the Combined reply queue feature only for SAS3 C0 HBAs and
 +  * also only when reply queue count is greater than 8
 +  */
 + if (ioc-msix96_vector  ioc-reply_queue_count  8) {
 + /* If this is an 96 vector supported device,
 + set up ReplyPostIndex addresses */
 + ioc-replyPostRegisterIndex = kcalloc(12,
 + sizeof(resource_size_t *), GFP_KERNEL);
 + if (!ioc-replyPostRegisterIndex) {
 + dfailprintk(ioc, printk(MPT3SAS_FMT
 + allocation for reply Post Register Index failed!!!\n,
 +ioc-name));
 + r = -ENOMEM;
 + goto out_fail;
 + }
 +
 + for (i = 0; i  12; i++) {
 + ioc-replyPostRegisterIndex[i] = (resource_size_t *)
 + ((u8 *)ioc-chip-Doorbell +
 + MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
 + (i * 0x10));
 + }
 + } else
 + ioc-msix96_vector = 0;
 +
   list_for_each_entry(reply_q, ioc-reply_queue_list, list)
   pr_info(MPT3SAS_FMT %s: IRQ %d\n,
   reply_q-name,  ((ioc-msix_enable) ? PCI-MSI-X enabled :
 @@ -1901,6 +1931,8 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
   pci_release_selected_regions(ioc-pdev, ioc-bars);
   pci_disable_pcie_error_reporting(pdev);
   pci_disable_device(pdev);
 + if (ioc-msix96_vector)
 + kfree(ioc-replyPostRegisterIndex);
   return r;
  }
  
 @@ -4522,8 +4554,16 @@ _base_make_ioc_operational(struct MPT3SAS_ADAPTER 
 *ioc, int sleep_flag)
  
   /* initialize

Re: [PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-06-12 Thread Sreekanth Reddy 
Thanks Johannes, we will take care of this point in our current
on-development mpt2sas/mpt3sas merging activity.


Thanks,
Sreekanth

On Fri, Jun 12, 2015 at 4:39 PM, Johannes Thumshirn jthumsh...@suse.de wrote:
 On Fri, Jun 12, 2015 at 03:12:13PM +0530, Sreekanth Reddy wrote:
 In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs 
 to up-to 96.

 Following are changes that are done in this patch
 1. Support this feature only for SAS3 C0 cards and also only when reply post 
 free queue count is greater than 8.
 2. Instead of using single ReplyPostHostIndex system interface, here 12 
 ReplyPostHostIndex system interfaces are used. reply post free queues 
 numbered from 0 to 7 use the first ReplyPostHostIndex system interface to 
 update its corresponding ReplyPostHostIndex values, reply post free queues 
 numbered from 8 to 15 will use the second ReplyPostHostIndex system 
 interface and so on. These 12 ReplyPostHostIndex system interfaces address 
 are saved in the array replyPostRegisterIndex[].
 3. Update the ReplyPostHostIndex value of corresponding reply post free 
 queue in the (its msix_index/8)th entry of replyPostRegisterIndex[] array 
 after processing the reply post descriptor.

 Signed-off-by: Sreekanth Reddy sreekanth.re...@avagotech.com
 ---
  drivers/scsi/mpt3sas/mpt3sas_base.c | 70 
 +
  drivers/scsi/mpt3sas/mpt3sas_base.h |  7 +++-
  2 files changed, 69 insertions(+), 8 deletions(-)

 diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
 b/drivers/scsi/mpt3sas/mpt3sas_base.c
 index 14a781b..c13a365 100644
 --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
 +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
 @@ -83,7 +83,7 @@ static int msix_disable = -1;
  module_param(msix_disable, int, 0);
  MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts 
 (default=0));

 -static int max_msix_vectors = 8;
 +static int max_msix_vectors = -1;
  module_param(max_msix_vectors, int, 0);
  MODULE_PARM_DESC(max_msix_vectors,
max msix vectors - (default=8));

 When changing the default value, please also update the description reflecting
 this change.

 @@ -1009,8 +1009,15 @@ _base_interrupt(int irq, void *bus_id)
   }

   wmb();
 - writel(reply_q-reply_post_host_index | (msix_index 
 - MPI2_RPHI_MSIX_INDEX_SHIFT), ioc-chip-ReplyPostHostIndex);
 + if (ioc-msix96_vector) {
 + writel(reply_q-reply_post_host_index | ((msix_index   7) 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-replyPostRegisterIndex[msix_index/8]);
 + } else {
 + writel(reply_q-reply_post_host_index | (msix_index 
 + MPI2_RPHI_MSIX_INDEX_SHIFT),
 + ioc-chip-ReplyPostHostIndex);
 + }
   atomic_dec(reply_q-busy);
   return IRQ_HANDLED;
  }
 @@ -1560,8 +1567,6 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)

   pci_read_config_word(ioc-pdev, base + 2, message_control);
   ioc-msix_vector_count = (message_control  0x3FF) + 1;
 - if (ioc-msix_vector_count  8)
 - ioc-msix_vector_count = 8;
   dinitprintk(ioc, pr_info(MPT3SAS_FMT
   msix is supported, vector_count(%d)\n,
   ioc-name, ioc-msix_vector_count));
 @@ -1880,6 +1885,31 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER 
 *ioc)
   if (r)
   goto out_fail;

 + /* Use the Combined reply queue feature only for SAS3 C0 HBAs and
 +  * also only when reply queue count is greater than 8
 +  */
 + if (ioc-msix96_vector  ioc-reply_queue_count  8) {
 + /* If this is an 96 vector supported device,
 + set up ReplyPostIndex addresses */
 + ioc-replyPostRegisterIndex = kcalloc(12,
 + sizeof(resource_size_t *), GFP_KERNEL);
 + if (!ioc-replyPostRegisterIndex) {
 + dfailprintk(ioc, printk(MPT3SAS_FMT
 + allocation for reply Post Register Index failed!!!\n,
 +ioc-name));
 + r = -ENOMEM;
 + goto out_fail;
 + }
 +
 + for (i = 0; i  12; i++) {
 + ioc-replyPostRegisterIndex[i] = (resource_size_t *)
 + ((u8 *)ioc-chip-Doorbell +
 + MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
 + (i * 0x10));
 + }
 + } else
 + ioc-msix96_vector = 0;
 +
   list_for_each_entry(reply_q, ioc-reply_queue_list, list)
   pr_info(MPT3SAS_FMT %s: IRQ %d\n,
   reply_q-name,  ((ioc-msix_enable) ? PCI-MSI-X enabled :
 @@ -1901,6 +1931,8 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
   pci_release_selected_regions(ioc-pdev, ioc-bars);
   pci_disable_pcie_error_reporting(pdev);
   pci_disable_device(pdev);
 + if

[PATCH 01/20] [SCSI] mpt3sas: Added Combined Reply Queue feature to extend up-to 96 MSIX vector support

2015-03-30 Thread Sreekanth Reddy 
In this patch, increased the number of MSIX vector support for SAS3 C0 HBAs to 
up-to 96.

Following are changes that are done in this patch
1. Support this feature only for SAS3 C0 cards and also only when reply post 
free queue count is greater than 8.
2. Instead of using single ReplyPostHostIndex system interface, here 12 
ReplyPostHostIndex system interfaces are used. reply post free queues numbered 
from 0 to 7 use the first ReplyPostHostIndex system interface to update its 
corresponding ReplyPostHostIndex values, reply post free queues numbered from 8 
to 15 will use the second ReplyPostHostIndex system interface and so on. These 
12 ReplyPostHostIndex system interfaces address are saved in the array 
replyPostRegisterIndex[].
3. Update the ReplyPostHostIndex value of corresponding reply post free queue 
in the (its msix_index/8)th entry of replyPostRegisterIndex[] array after 
processing the reply post descriptor.

Signed-off-by: Sreekanth Reddy sreekanth.re...@avagotech.com
---
 drivers/scsi/mpt3sas/mpt3sas_base.c | 70 +
 drivers/scsi/mpt3sas/mpt3sas_base.h |  7 +++-
 2 files changed, 69 insertions(+), 8 deletions(-)

diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c 
b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 14a781b..c13a365 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -83,7 +83,7 @@ static int msix_disable = -1;
 module_param(msix_disable, int, 0);
 MODULE_PARM_DESC(msix_disable,  disable msix routed interrupts (default=0));
 
-static int max_msix_vectors = 8;
+static int max_msix_vectors = -1;
 module_param(max_msix_vectors, int, 0);
 MODULE_PARM_DESC(max_msix_vectors,
 max msix vectors - (default=8));
@@ -1009,8 +1009,15 @@ _base_interrupt(int irq, void *bus_id)
}
 
wmb();
-   writel(reply_q-reply_post_host_index | (msix_index 
-   MPI2_RPHI_MSIX_INDEX_SHIFT), ioc-chip-ReplyPostHostIndex);
+   if (ioc-msix96_vector) {
+   writel(reply_q-reply_post_host_index | ((msix_index   7) 
+   MPI2_RPHI_MSIX_INDEX_SHIFT),
+   ioc-replyPostRegisterIndex[msix_index/8]);
+   } else {
+   writel(reply_q-reply_post_host_index | (msix_index 
+   MPI2_RPHI_MSIX_INDEX_SHIFT),
+   ioc-chip-ReplyPostHostIndex);
+   }
atomic_dec(reply_q-busy);
return IRQ_HANDLED;
 }
@@ -1560,8 +1567,6 @@ _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
 
pci_read_config_word(ioc-pdev, base + 2, message_control);
ioc-msix_vector_count = (message_control  0x3FF) + 1;
-   if (ioc-msix_vector_count  8)
-   ioc-msix_vector_count = 8;
dinitprintk(ioc, pr_info(MPT3SAS_FMT
msix is supported, vector_count(%d)\n,
ioc-name, ioc-msix_vector_count));
@@ -1880,6 +1885,31 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
if (r)
goto out_fail;
 
+   /* Use the Combined reply queue feature only for SAS3 C0 HBAs and
+* also only when reply queue count is greater than 8
+*/
+   if (ioc-msix96_vector  ioc-reply_queue_count  8) {
+   /* If this is an 96 vector supported device,
+   set up ReplyPostIndex addresses */
+   ioc-replyPostRegisterIndex = kcalloc(12,
+   sizeof(resource_size_t *), GFP_KERNEL);
+   if (!ioc-replyPostRegisterIndex) {
+   dfailprintk(ioc, printk(MPT3SAS_FMT
+   allocation for reply Post Register Index failed!!!\n,
+  ioc-name));
+   r = -ENOMEM;
+   goto out_fail;
+   }
+
+   for (i = 0; i  12; i++) {
+   ioc-replyPostRegisterIndex[i] = (resource_size_t *)
+   ((u8 *)ioc-chip-Doorbell +
+   MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
+   (i * 0x10));
+   }
+   } else
+   ioc-msix96_vector = 0;
+
list_for_each_entry(reply_q, ioc-reply_queue_list, list)
pr_info(MPT3SAS_FMT %s: IRQ %d\n,
reply_q-name,  ((ioc-msix_enable) ? PCI-MSI-X enabled :
@@ -1901,6 +1931,8 @@ mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
pci_release_selected_regions(ioc-pdev, ioc-bars);
pci_disable_pcie_error_reporting(pdev);
pci_disable_device(pdev);
+   if (ioc-msix96_vector)
+   kfree(ioc-replyPostRegisterIndex);
return r;
 }
 
@@ -4522,8 +4554,16 @@ _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, 
int sleep_flag)
 
/* initialize reply post host index */
list_for_each_entry(reply_q, ioc-reply_queue_list, list) {
-   writel(reply_q-msix_index