Re: [PATCH 4/6] scsi: ufs: add missing macros for register bits from UFSHCI spec

[Subhash Jadavani]

On 2017-03-28 06:49, kusumi.tomoh...@gmail.com wrote:

From: Tomohiro Kusumi 

Add macros for register bits that can be found in JESD223C (v2.1).

Not all registers are defined in ufshci.h (i.e. some are unused
whether macros are defined or undefined), but all the bits for
those registers that are already defined should appear here.

Signed-off-by: Tomohiro Kusumi 
---
 drivers/scsi/ufs/ufshci.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h
index d14e9b9..88acfd3 100644
--- a/drivers/scsi/ufs/ufshci.h
+++ b/drivers/scsi/ufs/ufshci.h
@@ -48,6 +48,7 @@ enum {
REG_UFS_VERSION = 0x08,
REG_CONTROLLER_DEV_ID   = 0x10,
REG_CONTROLLER_PROD_ID  = 0x14,
+   REG_AUTO_HIBERNATE_IDLE_TIMER   = 0x18,
REG_INTERRUPT_STATUS= 0x20,
REG_INTERRUPT_ENABLE= 0x24,
REG_CONTROLLER_STATUS   = 0x30,
@@ -171,6 +172,7 @@ enum {
 /* HCE - Host Controller Enable 34h */
 #define CONTROLLER_ENABLE  UFS_BIT(0)
 #define CONTROLLER_DISABLE 0x0
+#define CRYPTO_GENERAL_ENABLE  UFS_BIT(1)

 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 #define UIC_PHY_ADAPTER_LAYER_ERRORUFS_BIT(31)


Looks good to me.
Reviewed-by: Subhash Jadavani 

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[PATCH 4/6] scsi: ufs: add missing macros for register bits from UFSHCI spec

[kusumi . tomohiro]

From: Tomohiro Kusumi 

Add macros for register bits that can be found in JESD223C (v2.1).

Not all registers are defined in ufshci.h (i.e. some are unused
whether macros are defined or undefined), but all the bits for
those registers that are already defined should appear here.

Signed-off-by: Tomohiro Kusumi 
---
 drivers/scsi/ufs/ufshci.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h
index d14e9b9..88acfd3 100644
--- a/drivers/scsi/ufs/ufshci.h
+++ b/drivers/scsi/ufs/ufshci.h
@@ -48,6 +48,7 @@ enum {
REG_UFS_VERSION = 0x08,
REG_CONTROLLER_DEV_ID   = 0x10,
REG_CONTROLLER_PROD_ID  = 0x14,
+   REG_AUTO_HIBERNATE_IDLE_TIMER   = 0x18,
REG_INTERRUPT_STATUS= 0x20,
REG_INTERRUPT_ENABLE= 0x24,
REG_CONTROLLER_STATUS   = 0x30,
@@ -171,6 +172,7 @@ enum {
 /* HCE - Host Controller Enable 34h */
 #define CONTROLLER_ENABLE  UFS_BIT(0)
 #define CONTROLLER_DISABLE 0x0
+#define CRYPTO_GENERAL_ENABLE  UFS_BIT(1)
 
 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
 #define UIC_PHY_ADAPTER_LAYER_ERRORUFS_BIT(31)
-- 
2.9.3