RE: [PATCH v3 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

[Noam Camus]

>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
>Sent: Monday, August 21, 2017 20:04 PM

>> +
>> +/* Handle an out of bounds mtm hs counter value */ static void __init 
>> +handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val) {
>> +pr_err("** The value must be in range [%d,%d] (inclusive)\n",
>> +MT_HS_CNT_MIN, MT_HS_CNT_MAX);
>> +
>> +mtm_hs_ctr = val;


>This error handling doesn't make sense to me - if the value is not in range, 
>why bother setting it at all. I'll fix it up locally.
Just look what we provide handle_mtm_hs_ctr_out_of_bounds_error() as parameter 
and it will be sensible to you :)

Noam 

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[PATCH v3 04/11] ARC: Add CPU topology

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.

This way with topology the scheduler is much efficient in
creating domains and later using them.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig|   27 
 arch/arc/include/asm/Kbuild |1 -
 arch/arc/include/asm/topology.h |   34 +++
 arch/arc/kernel/Makefile|1 +
 arch/arc/kernel/setup.c |4 +-
 arch/arc/kernel/smp.c   |5 ++
 arch/arc/kernel/topology.c  |  125 +++
 7 files changed, 194 insertions(+), 3 deletions(-)
 create mode 100644 arch/arc/include/asm/topology.h
 create mode 100644 arch/arc/kernel/topology.c

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index f464f97..08a9003 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -202,6 +202,33 @@ config ARC_SMP_HALT_ON_RESET
  at designated entry point. For other case, all jump to common
  entry point and spin wait for Master's signal.
 
+config NPS_CPU_TOPOLOGY
+   bool "Support cpu topology definition"
+   depends on EZNPS_MTM_EXT
+   default y
+   help
+ Support NPS cpu topology definition.
+ NPS400 got 16 clusters of cores.
+ NPS400 cluster got 16 cores.
+ NPS core got 16 symetrical threads.
+ Totally there are such 4096 threads (NR_CPUS=4096)
+
+config SCHED_MC
+   bool "Multi-core scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+   bool "SMT scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
 endif  #SMP
 
 config ARC_MCIP
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index 7bee4e4..d8cb607 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -43,7 +43,6 @@ generic-y += stat.h
 generic-y += statfs.h
 generic-y += termbits.h
 generic-y += termios.h
-generic-y += topology.h
 generic-y += trace_clock.h
 generic-y += types.h
 generic-y += ucontext.h
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
new file mode 100644
index 000..a9be3f8
--- /dev/null
+++ b/arch/arc/include/asm/topology.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_ARC_TOPOLOGY_H
+#define _ASM_ARC_TOPOLOGY_H
+
+#ifdef CONFIG_NPS_CPU_TOPOLOGY
+
+#include 
+
+struct cputopo_nps {
+   int thread_id;
+   int core_id;
+   cpumask_t thread_sibling;
+   cpumask_t core_sibling;
+};
+
+extern struct cputopo_nps cpu_topology[NR_CPUS];
+
+#define topology_core_id(cpu)  (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu) (_topology[cpu].core_sibling)
+#define topology_sibling_cpumask(cpu)  (_topology[cpu].thread_sibling)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
+#include 
+
+#endif /* _ASM_ARC_TOPOLOGY_H */
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8942c5c..46af80a 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARC_EMUL_UNALIGNED)  += unaligned.o
 obj-$(CONFIG_KGDB) += kgdb.o
 obj-$(CONFIG_ARC_METAWARE_HLINK)   += arc_hostlink.o
 obj-$(CONFIG_PERF_EVENTS)  += perf_event.o
+obj-$(CONFIG_NPS_CPU_TOPOLOGY) += topology.o
 
 obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
 CFLAGS_fpu.o   += -mdpfp
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index de29ea9..379ebda 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -571,14 +571,14 @@ static void c_stop(struct seq_file *m, void *v)
.show   = show_cpuinfo
 };
 
-static DEFINE_PER_CPU(struct cpu, cpu_topology);
+static DEFINE_PER_CPU(struct cpu, cpu_topo_info);
 
 static int __init topology_init(void)
 {
int cpu;
 
for_each_present_cpu(cpu)
-   register_cpu(_cpu(cpu_topology, cpu), cpu);
+   register_cpu(_cpu(cpu_topo_info, cpu), cpu);
 
return 0;
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..91668c5 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -67,6 +67,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
int i;
 
+   init_cpu_topology();
+   store_cpu_topology(smp_processor_id());
+
  

[PATCH v3 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

This commit add new configuration that enables us to distinguish
between building the kernel for platforms that have a different set
of auxiliary registers for each cpu and platforms that have a shared
set of auxiliary registers across every thread in each core.
On platforms that implement a different set of auxiliary registers
disabling this configuration insures that we initialize registers on
every cpu and not just for the first thread of the core.
Example for non shared registers is working with EZsim (non silicon)

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++
 arch/arc/plat-eznps/entry.S |2 +-
 2 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index b36afb1..e151e20 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -43,3 +43,14 @@ config EZNPS_MEM_ERROR_ALIGN
  simulator platform for NPS, is handled as a Level 2 interrupt
  (just a stock ARC700) which is recoverable. This option makes
  simulator behave like hardware.
+
+config EZNPS_SHARED_AUX_REGS
+   bool "ARC-EZchip Shared Auxiliary Registers Per Core"
+   depends on ARC_PLAT_EZNPS
+   default y
+   help
+ On the real chip of the NPS, auxiliary registers are shared between
+ all the cpus of the core, whereas on simulator platform for NPS,
+ each cpu has a different set of auxiliary registers. Configuration
+ should be unset if auxiliary registers are not shared between the cpus
+ of the core, so there will be a need to initialize them per cpu.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..091c92c 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -27,7 +27,7 @@
.align 1024 ; HW requierment for restart first PC
 
 ENTRY(res_service)
-#ifdef CONFIG_EZNPS_MTM_EXT
+#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
; There is no work for HW thread id != 0
lr  r3, [CTOP_AUX_THREAD_ID]
cmp r3, 0
-- 
1.7.1


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[PATCH v3 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HW scheduler.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 Documentation/admin-guide/kernel-parameters.txt |9 
 arch/arc/plat-eznps/mtm.c   |   46 ++-
 2 files changed, 53 insertions(+), 2 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 15f79c2..5b551f7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2693,6 +2693,15 @@
If the dependencies are under your control, you can
turn on cpu0_hotplug.
 
+   nps_mtm_hs_ctr= [KNL,ARC]
+   This parameter sets the maximum duration, in
+   cycles, each HW thread of the CTOP can run
+   without interruptions, before HW switches it.
+   The actual maximum duration is 16 times this
+   parameter's value.
+   Format: integer between 1 and 255
+   Default: 255
+
nptcg=  [IA-64] Override max number of concurrent global TLB
purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index dcbf8f6..9c78ad6 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -21,10 +21,13 @@
 #include 
 #include 
 
-#define MT_CTRL_HS_CNT 0xFF
+#define MT_HS_CNT_MIN  0x01
+#define MT_HS_CNT_MAX  0xFF
 #define MT_CTRL_ST_CNT 0xF
 #define NPS_NUM_HW_THREADS 0x10
 
+static int mtm_hs_ctr = MT_HS_CNT_MAX;
+
 #ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN
 int do_memory_error(unsigned long address, struct pt_regs *regs)
 {
@@ -127,7 +130,7 @@ void mtm_enable_core(unsigned int cpu)
/* Enable HW schedule, stall counter, mtm */
mt_ctrl.value = 0;
mt_ctrl.hsen = 1;
-   mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
+   mt_ctrl.hs_cnt = mtm_hs_ctr;
mt_ctrl.mten = 1;
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
@@ -138,3 +141,42 @@ void mtm_enable_core(unsigned int cpu)
 */
cpu_relax();
 }
+
+/* Handle an out of bounds mtm hs counter value */
+static void __init handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val)
+{
+   pr_err("** The value must be in range [%d,%d] (inclusive)\n",
+   MT_HS_CNT_MIN, MT_HS_CNT_MAX);
+
+   mtm_hs_ctr = val;
+}
+
+/* Verify and set the value of the mtm hs counter */
+static int __init set_mtm_hs_ctr(char *ctr_str)
+{
+   int ret;
+   long hs_ctr;
+
+   ret = kstrtol(ctr_str, 0, _ctr);
+   if (ret) {
+   pr_err("** Out of range mtm_hs_ctr, using default value %d\n",
+   MT_HS_CNT_MAX);
+   mtm_hs_ctr = MT_HS_CNT_MAX;
+   return -EINVAL;
+   }
+
+   if (hs_ctr > MT_HS_CNT_MAX) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MAX);
+   return -EDOM;
+   }
+
+   if (hs_ctr < MT_HS_CNT_MIN) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MIN);
+   return -EDOM;
+   }
+
+   mtm_hs_ctr = hs_ctr;
+
+   return 0;
+}
+early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
-- 
1.7.1


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[PATCH v3 01/11] ARC: set level of log per CPU during boot to be info level

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Now it can be hidden by passing higher loglevel sevirity at cmdline
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/setup.c |6 +++---
 arch/arc/mm/cache.c |2 +-
 arch/arc/mm/tlb.c   |2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..de29ea9 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
 
-   printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
arc_mmu_init();
arc_cache_init();
 
-   printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-   printk(arc_platform_smp_cpuinfo());
+   pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_info("%s", arc_platform_smp_cpuinfo());
 
arc_chk_core_config();
 }
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..bdb5227 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
unsigned int __maybe_unused cpu = smp_processor_id();
char str[256];
 
-   printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+   pr_info("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..2b6da60 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
char str[256];
struct cpuinfo_arc_mmu *mmu = _arc700[smp_processor_id()].mmu;
 
-   printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+   pr_info("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1


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[PATCH v3 11/11] ARC: [plat-eznps] avoid toggling of DPC register

[Noam Camus]

From: Elad Kanfi <elad...@mellanox.com>

HW bug description: in case of HW thread context switch
the dpc configuration of the exiting thread is dragged
one cycle into the next thread.
In order to avoid the consequences of this bug, the DPC register
is set to an initial value, and not changed afterwards.

Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |   12 
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index 7729d3d..0c7d110 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -39,6 +39,7 @@
 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
 #define CTOP_AUX_MT_CTRL   (CTOP_AUX_BASE + 0x020)
 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
+#define CTOP_AUX_DPC   (CTOP_AUX_BASE + 0x02C)
 #define CTOP_AUX_LPC   (CTOP_AUX_BASE + 0x030)
 #define CTOP_AUX_EFLAGS(CTOP_AUX_BASE + 0x080)
 #define CTOP_AUX_IACK  (CTOP_AUX_BASE + 0x088)
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index 9c78ad6..909bbd4 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -110,6 +110,18 @@ void mtm_enable_core(unsigned int cpu)
int i;
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
struct nps_host_reg_mtm_cfg mtm_cfg;
+   struct nps_host_reg_aux_dpc dpc;
+
+   /*
+* Initializing dpc register in each CPU.
+* Overwriting the init value of the DPC
+* register so that CMEM and FMT virtual address
+* spaces are accessible, and Data Plane HW
+* facilities are enabled.
+*/
+   dpc.ien = 1;
+   dpc.men = 1;
+   write_aux_reg(CTOP_AUX_DPC, dpc.value);
 
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
return;
-- 
1.7.1


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[PATCH v3 10/11] ARC: [plat-eznps] handle dedicated AUX registers

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Preserve eflags and gpa1 auxiliaries during exception
Registers used by compare exchange instructions.
GPA1 is used for compare value, and EFLAGS got bit reflects
atomic operation response.

EFLAGS is zeroed for each new user task so it won't get its
parent value.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/entry-compact.h |   24 
 arch/arc/include/asm/ptrace.h|5 +
 arch/arc/kernel/process.c|4 
 3 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 14c310f..9e4458a 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -192,6 +192,12 @@
PUSHAX  lp_start
PUSHAX  erbta
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   PUSHAX  CTOP_AUX_GPA1
+   PUSHAX  CTOP_AUX_EFLAGS
+#endif
+`
lr  r9, [ecr]
st  r9, [sp, PT_event]/* EV_Trap expects r9 to have ECR */
 .endm
@@ -208,6 +214,12 @@
  * by hardware and that is not good.
  *-*/
 .macro EXCEPTION_EPILOGUE
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   POPAX   CTOP_AUX_EFLAGS
+   POPAX   CTOP_AUX_GPA1
+#endif
+
POPAX   erbta
POPAX   lp_start
POPAX   lp_end
@@ -265,6 +277,12 @@
PUSHAX  lp_end
PUSHAX  lp_start
PUSHAX  bta_l\LVL\()
+
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   PUSHAX  CTOP_AUX_GPA1
+   PUSHAX  CTOP_AUX_EFLAGS
+#endif
 .endm
 
 /*--
@@ -277,6 +295,12 @@
  * by hardware and that is not good.
  *-*/
 .macro INTERRUPT_EPILOGUE  LVL
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   POPAX   CTOP_AUX_EFLAGS
+   POPAX   CTOP_AUX_GPA1
+#endif
+
POPAX   bta_l\LVL\()
POPAX   lp_start
POPAX   lp_end
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 5297faa..5a8cb22 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -19,6 +19,11 @@
 #ifdef CONFIG_ISA_ARCOMPACT
 struct pt_regs {
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   unsigned long eflags;   /* Extended FLAGS */
+   unsigned long gpa1; /* General Purpose Aux */
+#endif
+
/* Real registers */
unsigned long bta;  /* bta_l1, bta_l2, erbta */
 
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 5c631a1..5ac3b54 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -234,6 +234,10 @@ void start_thread(struct pt_regs * regs, unsigned long pc, 
unsigned long usp)
 */
regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS;
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+   regs->eflags = 0;
+#endif
+
/* bogus seed values for debugging */
regs->lp_start = 0x10;
regs->lp_end = 0x80;
-- 
1.7.1


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[PATCH v3 06/11] ARC: [NUMA] added CONFIG_NUMA for plat-eznps

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed to be lower than node1.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig|9 +
 arch/arc/include/asm/topology.h |6 ++
 arch/arc/kernel/setup.c |3 +++
 arch/arc/mm/init.c  |6 ++
 4 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 982bd18..18c37de 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -378,6 +378,15 @@ config ARC_HUGEPAGE_16M
 
 endchoice
 
+config NUMA
+   bool "NUMA Memory Allocation and Scheduler Support"
+   depends on SMP && DISCONTIGMEM
+   default y if ARC_PLAT_EZNPS
+   ---help---
+ NUMA memory allocation is required for NPS400 processors.
+ The reason is that node1 in NPS400 is assigned to lower
+ addresses than node0, which is not typical scenario.
+
 config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
default "0" if !DISCONTIGMEM
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
index a9be3f8..dfbc2ab 100644
--- a/arch/arc/include/asm/topology.h
+++ b/arch/arc/include/asm/topology.h
@@ -1,6 +1,12 @@
 #ifndef _ASM_ARC_TOPOLOGY_H
 #define _ASM_ARC_TOPOLOGY_H
 
+#ifdef CONFIG_NUMA
+#define cpu_to_node(cpu)   ((void)(cpu), 0)
+#define parent_node(node)  (node)
+#define cpumask_of_node(node)  ((void)node, cpu_online_mask)
+#endif
+
 #ifdef CONFIG_NPS_CPU_TOPOLOGY
 
 #include 
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 379ebda..3d1509b 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -577,6 +577,9 @@ static int __init topology_init(void)
 {
int cpu;
 
+   for_each_online_node(cpu)
+   register_one_node(cpu);
+
for_each_present_cpu(cpu)
register_cpu(_cpu(cpu_topo_info, cpu), cpu);
 
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 8c9415e..f9f80d9 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -113,6 +113,10 @@ void __init setup_arch_memory(void)
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
 
+   node_set_online(0);
+   node_set_state(0, N_MEMORY);
+   node_set_state(0, N_NORMAL_MEMORY);
+
/* first page of system - kernel .vector starts here */
min_low_pfn = ARCH_PFN_OFFSET;
 
@@ -182,6 +186,8 @@ void __init setup_arch_memory(void)
 * populated with normal memory zone while node 1 only has highmem
 */
node_set_online(1);
+   node_set_state(1, N_MEMORY);
+   node_set_state(1, N_HIGH_MEMORY);
 
min_high_pfn = PFN_DOWN(high_mem_start);
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
-- 
1.7.1


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[PATCH v3 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.

We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while using atomic operations e.g. cmpxchg.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/arcregs.h   |7 +++
 arch/arc/include/asm/processor.h |3 +++
 arch/arc/include/asm/switch_to.h |   11 +++
 arch/arc/plat-eznps/Makefile |2 +-
 arch/arc/plat-eznps/ctop.c   |   33 +
 5 files changed, 55 insertions(+), 1 deletions(-)
 create mode 100644 arch/arc/plat-eznps/ctop.c

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index ba8e802..9437d42 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -123,6 +123,13 @@
 #define PAGES_TO_MB(n_pages)   (PAGES_TO_KB(n_pages) >> 10)
 
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+struct eznps_dp {
+   unsigned int eflags;
+   unsigned int gpa1;
+};
+#endif
+
 /*
  ***
  * Build Configuration Registers, with encoded hardware config
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index fd7bdfa..130bb55 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -38,6 +38,9 @@ struct thread_struct {
 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
struct arc_fpu fpu;
 #endif
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   struct eznps_dp dp;
+#endif
 };
 
 #define INIT_THREAD  {  \
diff --git a/arch/arc/include/asm/switch_to.h b/arch/arc/include/asm/switch_to.h
index 1b171ab..4c53080 100644
--- a/arch/arc/include/asm/switch_to.h
+++ b/arch/arc/include/asm/switch_to.h
@@ -26,13 +26,24 @@
 
 #endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
+#define ARC_DP_PREV(p, n)  dp_save_restore(p, n)
+#define ARC_DP_NEXT(t)
+#else
+#define ARC_DP_PREV(p, n)
+#define ARC_DP_NEXT(n)
+#endif /* !CONFIG_ARC_PLAT_EZNPS */
+
 struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
 
 #define switch_to(prev, next, last)\
 do {   \
+   ARC_DP_PREV(prev, next);\
ARC_FPU_PREV(prev, next);   \
last = __switch_to(prev, next);\
ARC_FPU_NEXT(next); \
+   ARC_DP_NEXT(next);  \
mb();   \
 } while (0)
 
diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile
index 21091b1..8d43717 100644
--- a/arch/arc/plat-eznps/Makefile
+++ b/arch/arc/plat-eznps/Makefile
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y := entry.o platform.o
+obj-y := entry.o platform.o ctop.o
 obj-$(CONFIG_SMP) += smp.o
 obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c
new file mode 100644
index 000..8b13a08
--- /dev/null
+++ b/arch/arc/plat-eznps/ctop.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+
+void dp_save_restore(struct task_struct *prev, struct task_struct *next)
+{
+   struct eznps_dp *prev_task_dp = >thread.dp;
+   struct eznps_dp *next_task_dp = >thread.dp;
+
+   /* Here we save all Data Plane related auxiliary registers */
+   prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
+   write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
+
+   prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
+   write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
+}
+
-- 
1.7.1


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[PATCH v3 00/11] plat-eznps upstream cont. set 2

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Change Log:
V2 -> V3
1) turn ARC prink's into pr_info as suggested by Vineet
2) For new command line argument (hs counter) shorten error massage to a single 
line,
   again as Vineet commented.

V1 -> V2
1) I added "Handle memory error as an exception" patch from previous set
   It now turn do_memory_error() into weak sybol.
   It is then overriden by NPS400 platform, to simply call die().
2) This set is now based on arc-next branch

Summary:
With this patch set I continue the effort of upstreaming the eznps platform for 
arch/arc.

It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.

This set got more generic ARC changes than previous set.
Additional ifdef seem like unavoidable, however it may seem Ugly.
Let's see if we need to do it more elegant.

Elad Kanfi (1):
  ARC: [plat-eznps] avoid toggling of DPC register

Liav Rehana (2):
  ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
  ARC: [plat-eznps] handle dedicated AUX registers

Noam Camus (8):
  ARC: set level of log per CPU during boot to be info level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: Allow irq threading
  ARC: Add CPU topology
  ARC: Support more than one PGDIR for KVADDR
  ARC: [NUMA] added CONFIG_NUMA for plat-eznps
  ARC: [plat-eznps] new command line argument for HW scheduler at MTM
  ARC: [plat-eznps] Save/Restore extra auxiliary registers

 Documentation/admin-guide/kernel-parameters.txt |9 ++
 arch/arc/Kconfig|   48 +
 arch/arc/include/asm/Kbuild |1 -
 arch/arc/include/asm/arcregs.h  |7 ++
 arch/arc/include/asm/cacheflush.h   |3 +-
 arch/arc/include/asm/entry-compact.h|   24 +
 arch/arc/include/asm/highmem.h  |8 +-
 arch/arc/include/asm/pgtable.h  |9 ++
 arch/arc/include/asm/processor.h|8 +-
 arch/arc/include/asm/ptrace.h   |5 +
 arch/arc/include/asm/switch_to.h|   11 ++
 arch/arc/include/asm/topology.h |   40 +++
 arch/arc/kernel/Makefile|1 +
 arch/arc/kernel/process.c   |4 +
 arch/arc/kernel/setup.c |   13 ++-
 arch/arc/kernel/smp.c   |5 +
 arch/arc/kernel/topology.c  |  125 +++
 arch/arc/mm/cache.c |   14 ++-
 arch/arc/mm/fault.c |8 ++
 arch/arc/mm/highmem.c   |   16 ++-
 arch/arc/mm/init.c  |6 +
 arch/arc/mm/tlb.c   |4 +-
 arch/arc/mm/tlbex.S |   31 ++
 arch/arc/plat-eznps/Kconfig |   11 ++
 arch/arc/plat-eznps/Makefile|2 +-
 arch/arc/plat-eznps/ctop.c  |   33 ++
 arch/arc/plat-eznps/entry.S |2 +-
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |   58 ++-
 29 files changed, 481 insertions(+), 26 deletions(-)
 create mode 100644 arch/arc/include/asm/topology.h
 create mode 100644 arch/arc/kernel/topology.c
 create mode 100644 arch/arc/plat-eznps/ctop.c


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[PATCH v3 02/11] ARC: send ipi to all cpus sharing task mm in case of page fault

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
 arch/arc/include/asm/cacheflush.h |3 ++-
 arch/arc/mm/cache.c   |   12 ++--
 arch/arc/mm/tlb.c |2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h 
b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+  phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index bdb5227..bfad0fa 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long 
vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+  phys_addr_t paddr, unsigned long vaddr)
 {
-   __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+   struct ic_inv_args ic_inv = {
+   .paddr  = paddr,
+   .vaddr  = vaddr,
+   .sz = PAGE_SIZE
+   };
+
+   on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+__ic_line_inv_vaddr_helper, _inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index 2b6da60..e298da9 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned 
long vaddr_unaligned,
 
/* invalidate any existing icache lines (U-mapping) */
if (vma->vm_flags & VM_EXEC)
-   __inv_icache_page(paddr, vaddr);
+   __inv_icache_page(vma, paddr, vaddr);
}
}
 }
-- 
1.7.1


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[PATCH v3 05/11] ARC: Support more than one PGDIR for KVADDR

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096

For the extreme case like in eznps platform We use
all gutter between kernel and user.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig |   11 +++
 arch/arc/include/asm/highmem.h   |8 +---
 arch/arc/include/asm/pgtable.h   |9 +
 arch/arc/include/asm/processor.h |5 +++--
 arch/arc/mm/fault.c  |8 
 arch/arc/mm/highmem.c|   16 +++-
 arch/arc/mm/tlbex.S  |   31 +++
 7 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 08a9003..982bd18 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -477,6 +477,17 @@ config ARC_HAS_PAE40
  Enable access to physical memory beyond 4G, only supported on
  ARC cores with 40 bit Physical Addressing support
 
+config HIGHMEM_PGDS_SHIFT
+   int "log num of PGDs for HIGHMEM"
+   range 0 5
+   default "0" if !ARC_PLAT_EZNPS || !HIGHMEM
+   default "5" if ARC_PLAT_EZNPS
+   help
+ This way we can map more pages for HIGHMEM.
+ Single PGD (2M) is supporting 256 PTEs (8K PAGE_SIZE)
+ For FIXMAP where at least 2 PTEs are needed per CPU
+ large NR_CPUS e.g. 4096 will consume 32 PGDs
+
 config ARCH_PHYS_ADDR_T_64BIT
def_bool ARC_HAS_PAE40
 
diff --git a/arch/arc/include/asm/highmem.h b/arch/arc/include/asm/highmem.h
index b1585c9..c5cb473 100644
--- a/arch/arc/include/asm/highmem.h
+++ b/arch/arc/include/asm/highmem.h
@@ -17,13 +17,13 @@
 
 /* start after vmalloc area */
 #define FIXMAP_BASE(PAGE_OFFSET - FIXMAP_SIZE - PKMAP_SIZE)
-#define FIXMAP_SIZEPGDIR_SIZE  /* only 1 PGD worth */
-#define KM_TYPE_NR ((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS)
+#define FIXMAP_SIZE(PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
+#define KM_TYPE_NR (((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS) > 2 ?: 2)
 #define FIXMAP_ADDR(nr)(FIXMAP_BASE + ((nr) << PAGE_SHIFT))
 
 /* start after fixmap area */
 #define PKMAP_BASE (FIXMAP_BASE + FIXMAP_SIZE)
-#define PKMAP_SIZE PGDIR_SIZE
+#define PKMAP_SIZE (PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
 #define LAST_PKMAP (PKMAP_SIZE >> PAGE_SHIFT)
 #define LAST_PKMAP_MASK(LAST_PKMAP - 1)
 #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
@@ -32,6 +32,7 @@
 #define kmap_prot  PAGE_KERNEL
 
 
+#ifndef __ASSEMBLY__
 #include 
 
 extern void *kmap(struct page *page);
@@ -54,6 +55,7 @@ static inline void kunmap(struct page *page)
return;
kunmap_high(page);
 }
+#endif /* __ASSEMBLY__  */
 
 
 #endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 08fe338..d08e207 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -224,6 +224,8 @@
 #definePTRS_PER_PTE_BITUL(BITS_FOR_PTE)
 #definePTRS_PER_PGD_BITUL(BITS_FOR_PGD)
 
+#define PTRS_HMEM_PTE  _BITUL(BITS_FOR_PTE + CONFIG_HIGHMEM_PGDS_SHIFT)
+
 /*
  * Number of entries a user land program use.
  * TASK_SIZE is the maximum vaddr that can be used by a userland program.
@@ -285,7 +287,14 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 
 /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
 #define pte_pfn(pte)   (pte_val(pte) >> PAGE_SHIFT)
+#if CONFIG_HIGHMEM_PGDS_SHIFT
+#define __pte_index(addr)  (((addr) >= VMALLOC_END) ? \
+   (((addr) >> PAGE_SHIFT) & (PTRS_HMEM_PTE - 1)) \
+   :  \
+   (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#else
 #define __pte_index(addr)  (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#endif
 
 /*
  * pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 6e1242d..fd7bdfa 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -121,8 +121,9 @@ extern void start_thread(struct pt_regs * regs, unsigned 
long pc,
 
 #define VMALLOC_START  (PAGE_OFFSET - (CONFIG_ARC_KVADDR_SIZE << 20))
 
-/* 1 PGDIR_SIZE each for fixmap/pkmap, 2 PGDIR_SIZE gutter (see asm/highmem.h) 
*/
-#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - PGDIR_SIZE * 4)
+/* 1 << CONFIG_HIGHMEM_PGDS_SHIFT PGDIR_SIZE each for fixmap/pkmap */
+#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - \
+ PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT) * 2)
 
 #define VMALLOC_END(VMAL

[PATCH v2 06/12] ARC: Support more than one PGDIR for KVADDR

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096

For the extreme case like in eznps platform We use
all gutter between kernel and user.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig |   11 +++
 arch/arc/include/asm/highmem.h   |8 +---
 arch/arc/include/asm/pgtable.h   |9 +
 arch/arc/include/asm/processor.h |5 +++--
 arch/arc/mm/fault.c  |8 
 arch/arc/mm/highmem.c|   16 +++-
 arch/arc/mm/tlbex.S  |   31 +++
 7 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 08a9003..982bd18 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -477,6 +477,17 @@ config ARC_HAS_PAE40
  Enable access to physical memory beyond 4G, only supported on
  ARC cores with 40 bit Physical Addressing support
 
+config HIGHMEM_PGDS_SHIFT
+   int "log num of PGDs for HIGHMEM"
+   range 0 5
+   default "0" if !ARC_PLAT_EZNPS || !HIGHMEM
+   default "5" if ARC_PLAT_EZNPS
+   help
+ This way we can map more pages for HIGHMEM.
+ Single PGD (2M) is supporting 256 PTEs (8K PAGE_SIZE)
+ For FIXMAP where at least 2 PTEs are needed per CPU
+ large NR_CPUS e.g. 4096 will consume 32 PGDs
+
 config ARCH_PHYS_ADDR_T_64BIT
def_bool ARC_HAS_PAE40
 
diff --git a/arch/arc/include/asm/highmem.h b/arch/arc/include/asm/highmem.h
index b1585c9..c5cb473 100644
--- a/arch/arc/include/asm/highmem.h
+++ b/arch/arc/include/asm/highmem.h
@@ -17,13 +17,13 @@
 
 /* start after vmalloc area */
 #define FIXMAP_BASE(PAGE_OFFSET - FIXMAP_SIZE - PKMAP_SIZE)
-#define FIXMAP_SIZEPGDIR_SIZE  /* only 1 PGD worth */
-#define KM_TYPE_NR ((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS)
+#define FIXMAP_SIZE(PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
+#define KM_TYPE_NR (((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS) > 2 ?: 2)
 #define FIXMAP_ADDR(nr)(FIXMAP_BASE + ((nr) << PAGE_SHIFT))
 
 /* start after fixmap area */
 #define PKMAP_BASE (FIXMAP_BASE + FIXMAP_SIZE)
-#define PKMAP_SIZE PGDIR_SIZE
+#define PKMAP_SIZE (PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
 #define LAST_PKMAP (PKMAP_SIZE >> PAGE_SHIFT)
 #define LAST_PKMAP_MASK(LAST_PKMAP - 1)
 #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
@@ -32,6 +32,7 @@
 #define kmap_prot  PAGE_KERNEL
 
 
+#ifndef __ASSEMBLY__
 #include 
 
 extern void *kmap(struct page *page);
@@ -54,6 +55,7 @@ static inline void kunmap(struct page *page)
return;
kunmap_high(page);
 }
+#endif /* __ASSEMBLY__  */
 
 
 #endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 08fe338..d08e207 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -224,6 +224,8 @@
 #definePTRS_PER_PTE_BITUL(BITS_FOR_PTE)
 #definePTRS_PER_PGD_BITUL(BITS_FOR_PGD)
 
+#define PTRS_HMEM_PTE  _BITUL(BITS_FOR_PTE + CONFIG_HIGHMEM_PGDS_SHIFT)
+
 /*
  * Number of entries a user land program use.
  * TASK_SIZE is the maximum vaddr that can be used by a userland program.
@@ -285,7 +287,14 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 
 /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
 #define pte_pfn(pte)   (pte_val(pte) >> PAGE_SHIFT)
+#if CONFIG_HIGHMEM_PGDS_SHIFT
+#define __pte_index(addr)  (((addr) >= VMALLOC_END) ? \
+   (((addr) >> PAGE_SHIFT) & (PTRS_HMEM_PTE - 1)) \
+   :  \
+   (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#else
 #define __pte_index(addr)  (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#endif
 
 /*
  * pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 6e1242d..fd7bdfa 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -121,8 +121,9 @@ extern void start_thread(struct pt_regs * regs, unsigned 
long pc,
 
 #define VMALLOC_START  (PAGE_OFFSET - (CONFIG_ARC_KVADDR_SIZE << 20))
 
-/* 1 PGDIR_SIZE each for fixmap/pkmap, 2 PGDIR_SIZE gutter (see asm/highmem.h) 
*/
-#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - PGDIR_SIZE * 4)
+/* 1 << CONFIG_HIGHMEM_PGDS_SHIFT PGDIR_SIZE each for fixmap/pkmap */
+#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - \
+ PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT) * 2)
 
 #define VMALLOC_END(VMAL

[PATCH v2 05/12] ARC: Add CPU topology

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.

This way with topology the scheduler is much efficient in
creating domains and later using them.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig|   27 
 arch/arc/include/asm/Kbuild |1 -
 arch/arc/include/asm/topology.h |   34 +++
 arch/arc/kernel/Makefile|1 +
 arch/arc/kernel/setup.c |4 +-
 arch/arc/kernel/smp.c   |5 ++
 arch/arc/kernel/topology.c  |  125 +++
 7 files changed, 194 insertions(+), 3 deletions(-)
 create mode 100644 arch/arc/include/asm/topology.h
 create mode 100644 arch/arc/kernel/topology.c

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index f464f97..08a9003 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -202,6 +202,33 @@ config ARC_SMP_HALT_ON_RESET
  at designated entry point. For other case, all jump to common
  entry point and spin wait for Master's signal.
 
+config NPS_CPU_TOPOLOGY
+   bool "Support cpu topology definition"
+   depends on EZNPS_MTM_EXT
+   default y
+   help
+ Support NPS cpu topology definition.
+ NPS400 got 16 clusters of cores.
+ NPS400 cluster got 16 cores.
+ NPS core got 16 symetrical threads.
+ Totally there are such 4096 threads (NR_CPUS=4096)
+
+config SCHED_MC
+   bool "Multi-core scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+   bool "SMT scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
 endif  #SMP
 
 config ARC_MCIP
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index 7bee4e4..d8cb607 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -43,7 +43,6 @@ generic-y += stat.h
 generic-y += statfs.h
 generic-y += termbits.h
 generic-y += termios.h
-generic-y += topology.h
 generic-y += trace_clock.h
 generic-y += types.h
 generic-y += ucontext.h
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
new file mode 100644
index 000..a9be3f8
--- /dev/null
+++ b/arch/arc/include/asm/topology.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_ARC_TOPOLOGY_H
+#define _ASM_ARC_TOPOLOGY_H
+
+#ifdef CONFIG_NPS_CPU_TOPOLOGY
+
+#include 
+
+struct cputopo_nps {
+   int thread_id;
+   int core_id;
+   cpumask_t thread_sibling;
+   cpumask_t core_sibling;
+};
+
+extern struct cputopo_nps cpu_topology[NR_CPUS];
+
+#define topology_core_id(cpu)  (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu) (_topology[cpu].core_sibling)
+#define topology_sibling_cpumask(cpu)  (_topology[cpu].thread_sibling)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
+#include 
+
+#endif /* _ASM_ARC_TOPOLOGY_H */
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8942c5c..46af80a 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARC_EMUL_UNALIGNED)  += unaligned.o
 obj-$(CONFIG_KGDB) += kgdb.o
 obj-$(CONFIG_ARC_METAWARE_HLINK)   += arc_hostlink.o
 obj-$(CONFIG_PERF_EVENTS)  += perf_event.o
+obj-$(CONFIG_NPS_CPU_TOPOLOGY) += topology.o
 
 obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
 CFLAGS_fpu.o   += -mdpfp
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 8494b31..5256205 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -571,14 +571,14 @@ static void c_stop(struct seq_file *m, void *v)
.show   = show_cpuinfo
 };
 
-static DEFINE_PER_CPU(struct cpu, cpu_topology);
+static DEFINE_PER_CPU(struct cpu, cpu_topo_info);
 
 static int __init topology_init(void)
 {
int cpu;
 
for_each_present_cpu(cpu)
-   register_cpu(_cpu(cpu_topology, cpu), cpu);
+   register_cpu(_cpu(cpu_topo_info, cpu), cpu);
 
return 0;
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index d1aa917..167a620 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -67,6 +67,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
int i;
 
+   init_cpu_topology();
+   store_cpu_topology(smp_processor_id());
+
  

[PATCH v2 12/12] ARC: [plat-eznps] avoid toggling of DPC register

[Noam Camus]

From: Elad Kanfi <elad...@mellanox.com>

HW bug description: in case of HW thread context switch
the dpc configuration of the exiting thread is dragged
one cycle into the next thread.
In order to avoid the consequences of this bug, the DPC register
is set to an initial value, and not changed afterwards.

Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |   12 
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index 7729d3d..0c7d110 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -39,6 +39,7 @@
 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
 #define CTOP_AUX_MT_CTRL   (CTOP_AUX_BASE + 0x020)
 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
+#define CTOP_AUX_DPC   (CTOP_AUX_BASE + 0x02C)
 #define CTOP_AUX_LPC   (CTOP_AUX_BASE + 0x030)
 #define CTOP_AUX_EFLAGS(CTOP_AUX_BASE + 0x080)
 #define CTOP_AUX_IACK  (CTOP_AUX_BASE + 0x088)
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index dd1ea1f..777231d 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -112,6 +112,18 @@ void mtm_enable_core(unsigned int cpu)
int i;
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
struct nps_host_reg_mtm_cfg mtm_cfg;
+   struct nps_host_reg_aux_dpc dpc;
+
+   /*
+* Initializing dpc register in each CPU.
+* Overwriting the init value of the DPC
+* register so that CMEM and FMT virtual address
+* spaces are accessible, and Data Plane HW
+* facilities are enabled.
+*/
+   dpc.ien = 1;
+   dpc.men = 1;
+   write_aux_reg(CTOP_AUX_DPC, dpc.value);
 
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
return;
-- 
1.7.1


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[PATCH v2 08/12] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 Documentation/admin-guide/kernel-parameters.txt |9 
 arch/arc/plat-eznps/mtm.c   |   49 ++-
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 15f79c2..5b551f7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2693,6 +2693,15 @@
If the dependencies are under your control, you can
turn on cpu0_hotplug.
 
+   nps_mtm_hs_ctr= [KNL,ARC]
+   This parameter sets the maximum duration, in
+   cycles, each HW thread of the CTOP can run
+   without interruptions, before HW switches it.
+   The actual maximum duration is 16 times this
+   parameter's value.
+   Format: integer between 1 and 255
+   Default: 255
+
nptcg=  [IA-64] Override max number of concurrent global TLB
purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index 59a0162..dd1ea1f 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -21,10 +21,13 @@
 #include 
 #include 
 
-#define MT_CTRL_HS_CNT 0xFF
+#define MT_HS_CNT_MIN  0x01
+#define MT_HS_CNT_MAX  0xFF
 #define MT_CTRL_ST_CNT 0xF
 #define NPS_NUM_HW_THREADS 0x10
 
+static int mtm_hs_ctr = MT_HS_CNT_MAX;
+
 #ifdef CONFIG_EZNPS_MEM_ERROR
 int do_memory_error(unsigned long address, struct pt_regs *regs)
 {
@@ -129,7 +132,7 @@ void mtm_enable_core(unsigned int cpu)
/* Enable HW schedule, stall counter, mtm */
mt_ctrl.value = 0;
mt_ctrl.hsen = 1;
-   mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
+   mt_ctrl.hs_cnt = mtm_hs_ctr;
mt_ctrl.mten = 1;
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
@@ -140,3 +143,45 @@ void mtm_enable_core(unsigned int cpu)
 */
cpu_relax();
 }
+
+/* Handle an out of bounds mtm hs counter value */
+static void __init handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val)
+{
+   pr_err("** The value of mtm_hs_ctr is out of bounds!\n"
+  "** It must be in the range [%d,%d] (inclusive)\n"
+  "Setting mtm_hs_ctr to %d\n", MT_HS_CNT_MIN, MT_HS_CNT_MAX, val);
+
+   mtm_hs_ctr = val;
+}
+
+/* Verify and set the value of the mtm hs counter */
+static int __init set_mtm_hs_ctr(char *ctr_str)
+{
+   int ret;
+   long hs_ctr;
+
+   ret = kstrtol(ctr_str, 0, _ctr);
+   if (ret) {
+   pr_err("** Error parsing the value of mtm_hs_ctr\n"
+  "** Make sure you entered a valid integer value\n"
+  "Setting mtm_hs_ctr to default value: %d\n",
+  MT_HS_CNT_MAX);
+   mtm_hs_ctr = MT_HS_CNT_MAX;
+   return -EINVAL;
+   }
+
+   if (hs_ctr > MT_HS_CNT_MAX) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MAX);
+   return -EDOM;
+   }
+
+   if (hs_ctr < MT_HS_CNT_MIN) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MIN);
+   return -EDOM;
+   }
+
+   mtm_hs_ctr = hs_ctr;
+
+   return 0;
+}
+early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
-- 
1.7.1


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[PATCH v2 07/12] ARC: [NUMA] added CONFIG_NUMA for plat-eznps

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed to be lower than node1.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig|9 +
 arch/arc/include/asm/topology.h |6 ++
 arch/arc/kernel/setup.c |3 +++
 arch/arc/mm/init.c  |6 ++
 4 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 982bd18..18c37de 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -378,6 +378,15 @@ config ARC_HUGEPAGE_16M
 
 endchoice
 
+config NUMA
+   bool "NUMA Memory Allocation and Scheduler Support"
+   depends on SMP && DISCONTIGMEM
+   default y if ARC_PLAT_EZNPS
+   ---help---
+ NUMA memory allocation is required for NPS400 processors.
+ The reason is that node1 in NPS400 is assigned to lower
+ addresses than node0, which is not typical scenario.
+
 config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
default "0" if !DISCONTIGMEM
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
index a9be3f8..dfbc2ab 100644
--- a/arch/arc/include/asm/topology.h
+++ b/arch/arc/include/asm/topology.h
@@ -1,6 +1,12 @@
 #ifndef _ASM_ARC_TOPOLOGY_H
 #define _ASM_ARC_TOPOLOGY_H
 
+#ifdef CONFIG_NUMA
+#define cpu_to_node(cpu)   ((void)(cpu), 0)
+#define parent_node(node)  (node)
+#define cpumask_of_node(node)  ((void)node, cpu_online_mask)
+#endif
+
 #ifdef CONFIG_NPS_CPU_TOPOLOGY
 
 #include 
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 5256205..5f04635 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -577,6 +577,9 @@ static int __init topology_init(void)
 {
int cpu;
 
+   for_each_online_node(cpu)
+   register_one_node(cpu);
+
for_each_present_cpu(cpu)
register_cpu(_cpu(cpu_topo_info, cpu), cpu);
 
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 8c9415e..f9f80d9 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -113,6 +113,10 @@ void __init setup_arch_memory(void)
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)_end;
 
+   node_set_online(0);
+   node_set_state(0, N_MEMORY);
+   node_set_state(0, N_NORMAL_MEMORY);
+
/* first page of system - kernel .vector starts here */
min_low_pfn = ARCH_PFN_OFFSET;
 
@@ -182,6 +186,8 @@ void __init setup_arch_memory(void)
 * populated with normal memory zone while node 1 only has highmem
 */
node_set_online(1);
+   node_set_state(1, N_MEMORY);
+   node_set_state(1, N_HIGH_MEMORY);
 
min_high_pfn = PFN_DOWN(high_mem_start);
max_high_pfn = PFN_DOWN(high_mem_start + high_mem_sz);
-- 
1.7.1


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[PATCH v2 01/12] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

On ARC700, user mode memory error is treated as L2 interrupt, but NPS
hardware treats it as Machine Check exception.

Address this by defining an NPS specific bus error handler.

Signed-off-by: Noam Camus <noa...@mellanox.com>
Signed-off-by: Elad Kanfi <elad...@mellanox.com>
---
 arch/arc/kernel/traps.c |2 +-
 arch/arc/plat-eznps/Kconfig |   12 
 arch/arc/plat-eznps/mtm.c   |   11 +++
 3 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index ff83e78..62675b9 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -80,7 +80,7 @@ int name(unsigned long address, struct pt_regs *regs) \
 DO_ERROR_INFO(SIGILL, "Priv Op/Disabled Extn", do_privilege_fault, ILL_PRVOPC)
 DO_ERROR_INFO(SIGILL, "Invalid Extn Insn", do_extension_fault, ILL_ILLOPC)
 DO_ERROR_INFO(SIGILL, "Illegal Insn (or Seq)", insterror_is_error, ILL_ILLOPC)
-DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", do_memory_error, BUS_ADRERR)
+DO_ERROR_INFO(SIGBUS, "Invalid Mem Access", __weak do_memory_error, BUS_ADRERR)
 DO_ERROR_INFO(SIGTRAP, "Breakpoint Set", trap_is_brkpt, TRAP_BRKPT)
 DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
 
diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..fa25136 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,15 @@ config EZNPS_MTM_EXT
  any of them seem like CPU from Linux point of view.
  All threads within same core share the execution unit of the
  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+   bool "ARC-EZchip Memory error as an exception"
+   depends on EZNPS_MTM_EXT
+   default n
+   help
+ On the real chip of the NPS, user memory errors are handled
+ as a machine check exception, whereas on simulator platform
+ for NPS, is handled as an interrupt level 2 (like legacy arc
+ real chip architecture).This configuration will cause the kernel
+ to handle memory error similar to a machine check exception.
+ It means NOT sending a SIGBUS, but panic the system.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index e0cb36b..59a0162 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -25,6 +25,17 @@
 #define MT_CTRL_ST_CNT 0xF
 #define NPS_NUM_HW_THREADS 0x10
 
+#ifdef CONFIG_EZNPS_MEM_ERROR
+int do_memory_error(unsigned long address, struct pt_regs *regs)
+{
+   char *str = "Invalid Mem Access";
+
+   die(str, regs, address);
+
+   return 1;
+}
+#endif
+
 static void mtm_init_nat(int cpu)
 {
struct nps_host_reg_mtm_cfg mtm_cfg;
-- 
1.7.1


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[PATCH v2 10/12] ARC: [plat-eznps] Save/Restore extra auxiliary registers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.

We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while using atomic operations e.g. cmpxchg.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/arcregs.h   |7 +++
 arch/arc/include/asm/processor.h |3 +++
 arch/arc/include/asm/switch_to.h |   11 +++
 arch/arc/plat-eznps/Makefile |2 +-
 arch/arc/plat-eznps/ctop.c   |   33 +
 5 files changed, 55 insertions(+), 1 deletions(-)
 create mode 100644 arch/arc/plat-eznps/ctop.c

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index ba8e802..9437d42 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -123,6 +123,13 @@
 #define PAGES_TO_MB(n_pages)   (PAGES_TO_KB(n_pages) >> 10)
 
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+struct eznps_dp {
+   unsigned int eflags;
+   unsigned int gpa1;
+};
+#endif
+
 /*
  ***
  * Build Configuration Registers, with encoded hardware config
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index fd7bdfa..130bb55 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -38,6 +38,9 @@ struct thread_struct {
 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
struct arc_fpu fpu;
 #endif
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   struct eznps_dp dp;
+#endif
 };
 
 #define INIT_THREAD  {  \
diff --git a/arch/arc/include/asm/switch_to.h b/arch/arc/include/asm/switch_to.h
index 1b171ab..4c53080 100644
--- a/arch/arc/include/asm/switch_to.h
+++ b/arch/arc/include/asm/switch_to.h
@@ -26,13 +26,24 @@
 
 #endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
+#define ARC_DP_PREV(p, n)  dp_save_restore(p, n)
+#define ARC_DP_NEXT(t)
+#else
+#define ARC_DP_PREV(p, n)
+#define ARC_DP_NEXT(n)
+#endif /* !CONFIG_ARC_PLAT_EZNPS */
+
 struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
 
 #define switch_to(prev, next, last)\
 do {   \
+   ARC_DP_PREV(prev, next);\
ARC_FPU_PREV(prev, next);   \
last = __switch_to(prev, next);\
ARC_FPU_NEXT(next); \
+   ARC_DP_NEXT(next);  \
mb();   \
 } while (0)
 
diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile
index 21091b1..8d43717 100644
--- a/arch/arc/plat-eznps/Makefile
+++ b/arch/arc/plat-eznps/Makefile
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y := entry.o platform.o
+obj-y := entry.o platform.o ctop.o
 obj-$(CONFIG_SMP) += smp.o
 obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c
new file mode 100644
index 000..8b13a08
--- /dev/null
+++ b/arch/arc/plat-eznps/ctop.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+
+void dp_save_restore(struct task_struct *prev, struct task_struct *next)
+{
+   struct eznps_dp *prev_task_dp = >thread.dp;
+   struct eznps_dp *next_task_dp = >thread.dp;
+
+   /* Here we save all Data Plane related auxiliary registers */
+   prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
+   write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
+
+   prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
+   write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
+}
+
-- 
1.7.1


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[PATCH v2 09/12] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

The following commit adds a config that will enable us to distinguish
between building the kernel for platforms that have a different set
of auxiliary registers for each cpu and platforms that have a shared
set of auxiliary registers across every thread in each core.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++
 arch/arc/plat-eznps/entry.S |2 +-
 2 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index fa25136..019de58 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -44,3 +44,14 @@ config EZNPS_MEM_ERROR
  real chip architecture).This configuration will cause the kernel
  to handle memory error similar to a machine check exception.
  It means NOT sending a SIGBUS, but panic the system.
+
+config EZNPS_SHARED_AUX_REGS
+   bool "ARC-EZchip Shared Auxiliary Registers Per Core"
+   depends on ARC_PLAT_EZNPS
+   default y
+   help
+ On the real chip of the NPS, auxiliary registers are shared between
+ all the cpus of the core, whereas on simulator platform for NPS,
+ each cpu has a different set of auxiliary registers. Configuration
+ should be unset if auxiliary registers are not shared between the cpus
+ of the core, so there will be a need to initialize them per cpu.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..091c92c 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -27,7 +27,7 @@
.align 1024 ; HW requierment for restart first PC
 
 ENTRY(res_service)
-#ifdef CONFIG_EZNPS_MTM_EXT
+#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
; There is no work for HW thread id != 0
lr  r3, [CTOP_AUX_THREAD_ID]
cmp r3, 0
-- 
1.7.1


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[PATCH v2 03/12] ARC: send ipi to all cpus sharing task mm in case of page fault

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.

Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
 arch/arc/include/asm/cacheflush.h |3 ++-
 arch/arc/mm/cache.c   |   12 ++--
 arch/arc/mm/tlb.c |2 +-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/arch/arc/include/asm/cacheflush.h 
b/arch/arc/include/asm/cacheflush.h
index fc662f4..716dba1 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -33,7 +33,8 @@
 
 void flush_icache_range(unsigned long kstart, unsigned long kend);
 void __sync_icache_dcache(phys_addr_t paddr, unsigned long vaddr, int len);
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr);
+void __inv_icache_page(struct vm_area_struct *vma,
+  phys_addr_t paddr, unsigned long vaddr);
 void __flush_dcache_page(phys_addr_t paddr, unsigned long vaddr);
 
 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7d3e79b..e1ea57f 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -934,9 +934,17 @@ void __sync_icache_dcache(phys_addr_t paddr, unsigned long 
vaddr, int len)
 }
 
 /* wrapper to compile time eliminate alignment checks in flush loop */
-void __inv_icache_page(phys_addr_t paddr, unsigned long vaddr)
+void __inv_icache_page(struct vm_area_struct *vma,
+  phys_addr_t paddr, unsigned long vaddr)
 {
-   __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
+   struct ic_inv_args ic_inv = {
+   .paddr  = paddr,
+   .vaddr  = vaddr,
+   .sz = PAGE_SIZE
+   };
+
+   on_each_cpu_mask(mm_cpumask(vma->vm_mm),
+__ic_line_inv_vaddr_helper, _inv, 1);
 }
 
 /*
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index c5e70d8..a095608 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -626,7 +626,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned 
long vaddr_unaligned,
 
/* invalidate any existing icache lines (U-mapping) */
if (vma->vm_flags & VM_EXEC)
-   __inv_icache_page(paddr, vaddr);
+   __inv_icache_page(vma, paddr, vaddr);
}
}
 }
-- 
1.7.1


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[PATCH v2 02/12] ARC: set level of log per CPU during boot to be debug level

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/setup.c |6 +++---
 arch/arc/kernel/smp.c   |4 ++--
 arch/arc/mm/cache.c |2 +-
 arch/arc/mm/tlb.c   |2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
 
-   printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
arc_mmu_init();
arc_cache_init();
 
-   printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-   printk(arc_platform_smp_cpuinfo());
+   pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_platform_smp_cpuinfo());
 
arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
secondary_idle_tsk = idle;
 
-   pr_info("Idle Task [%d] %p", cpu, idle);
-   pr_info("Trying to bring up CPU%u ...\n", cpu);
+   pr_debug("Idle Task [%d] %p", cpu, idle);
+   pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
if (plat_smp_ops.cpu_kick)
plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..7d3e79b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
unsigned int __maybe_unused cpu = smp_processor_id();
char str[256];
 
-   printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
char str[256];
struct cpuinfo_arc_mmu *mmu = _arc700[smp_processor_id()].mmu;
 
-   printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1


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[PATCH 01/11] ARC: set level of log per CPU during boot to be debug level

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/setup.c |6 +++---
 arch/arc/kernel/smp.c   |4 ++--
 arch/arc/mm/cache.c |2 +-
 arch/arc/mm/tlb.c   |2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
 
-   printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
arc_mmu_init();
arc_cache_init();
 
-   printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-   printk(arc_platform_smp_cpuinfo());
+   pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_platform_smp_cpuinfo());
 
arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
secondary_idle_tsk = idle;
 
-   pr_info("Idle Task [%d] %p", cpu, idle);
-   pr_info("Trying to bring up CPU%u ...\n", cpu);
+   pr_debug("Idle Task [%d] %p", cpu, idle);
+   pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
if (plat_smp_ops.cpu_kick)
plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 3329d0d..15bc3e3 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
unsigned int __maybe_unused cpu = smp_processor_id();
char str[256];
 
-   printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
char str[256];
struct cpuinfo_arc_mmu *mmu = _arc700[smp_processor_id()].mmu;
 
-   printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1


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[PATCH 11/11] ARC: [plat-eznps] avoid toggling of DPC register

[Noam Camus]

From: Elad Kanfi <elad...@mellanox.com>

HW bug description: in case of HW thread context switch
the dpc configuration of the exiting thread is dragged
one cycle into the next thread.
In order to avoid the consequences of this bug, the DPC register
is set to an initial value, and not changed afterwards.

Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |   12 
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index 7729d3d..0c7d110 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -39,6 +39,7 @@
 #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
 #define CTOP_AUX_MT_CTRL   (CTOP_AUX_BASE + 0x020)
 #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
+#define CTOP_AUX_DPC   (CTOP_AUX_BASE + 0x02C)
 #define CTOP_AUX_LPC   (CTOP_AUX_BASE + 0x030)
 #define CTOP_AUX_EFLAGS(CTOP_AUX_BASE + 0x080)
 #define CTOP_AUX_IACK  (CTOP_AUX_BASE + 0x088)
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index f77335a..3c7dec9 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -101,6 +101,18 @@ void mtm_enable_core(unsigned int cpu)
int i;
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
struct nps_host_reg_mtm_cfg mtm_cfg;
+   struct nps_host_reg_aux_dpc dpc;
+
+   /*
+* Initializing dpc register in each CPU.
+* Overwriting the init value of the DPC
+* register so that CMEM and FMT virtual address
+* spaces are accessible, and Data Plane HW
+* facilities are enabled.
+*/
+   dpc.ien = 1;
+   dpc.men = 1;
+   write_aux_reg(CTOP_AUX_DPC, dpc.value);
 
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
return;
-- 
1.7.1


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[PATCH 00/11] plat-eznps upstream cont. set 2

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

With this patch set I continue the effort of upstreaming the eznps platform for 
arch/arc.

It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.

This set got more generic ARC changes than previous set.
Additional ifdef seem like unavoidable, however it may seem Ugly.
Let's see if we need to do it more elegant.

Elad Kanfi (1):
  ARC: [plat-eznps] avoid toggling of DPC register

Liav Rehana (2):
  ARC: [plat-eznps] Update the init sequence of aux regs per cpu.
  ARC: [plat-eznps] handle dedicated AUX registers

Noam Camus (8):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: Allow irq threading
  ARC: Add CPU topology
  ARC: Support more than one PGDIR for KVADDR
  ARC: [NUMA] added CONFIG_NUMA for plat-eznps
  ARC: [plat-eznps] new command line argument for HW scheduler at MTM
  ARC: [plat-eznps] Save/Restore extra auxiliary registers

 Documentation/admin-guide/kernel-parameters.txt |9 ++
 arch/arc/Kconfig|   48 +
 arch/arc/include/asm/Kbuild |1 -
 arch/arc/include/asm/arcregs.h  |7 ++
 arch/arc/include/asm/cacheflush.h   |3 +-
 arch/arc/include/asm/entry-compact.h|   24 +
 arch/arc/include/asm/highmem.h  |8 +-
 arch/arc/include/asm/pgtable.h  |9 ++
 arch/arc/include/asm/processor.h|8 +-
 arch/arc/include/asm/ptrace.h   |5 +
 arch/arc/include/asm/switch_to.h|   11 ++
 arch/arc/include/asm/topology.h |   40 +++
 arch/arc/kernel/Makefile|1 +
 arch/arc/kernel/process.c   |4 +
 arch/arc/kernel/setup.c |   13 ++-
 arch/arc/kernel/smp.c   |9 ++-
 arch/arc/kernel/topology.c  |  125 +++
 arch/arc/mm/cache.c |   14 ++-
 arch/arc/mm/fault.c |8 ++
 arch/arc/mm/highmem.c   |   16 ++-
 arch/arc/mm/init.c  |6 +
 arch/arc/mm/tlb.c   |4 +-
 arch/arc/mm/tlbex.S |   31 ++
 arch/arc/plat-eznps/Kconfig |   11 ++
 arch/arc/plat-eznps/Makefile|2 +-
 arch/arc/plat-eznps/ctop.c  |   33 ++
 arch/arc/plat-eznps/entry.S |2 +-
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |   61 +++-
 29 files changed, 486 insertions(+), 28 deletions(-)
 create mode 100644 arch/arc/include/asm/topology.h
 create mode 100644 arch/arc/kernel/topology.c
 create mode 100644 arch/arc/plat-eznps/ctop.c


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[PATCH 05/11] ARC: Support more than one PGDIR for KVADDR

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096

For the extreme case like in eznps platform We use
all gutter between kernel and user.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig |   11 +++
 arch/arc/include/asm/highmem.h   |8 +---
 arch/arc/include/asm/pgtable.h   |9 +
 arch/arc/include/asm/processor.h |5 +++--
 arch/arc/mm/fault.c  |8 
 arch/arc/mm/highmem.c|   16 +++-
 arch/arc/mm/tlbex.S  |   31 +++
 7 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index b759be1..54ba8e6 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -478,6 +478,17 @@ config ARC_HAS_PAE40
  Enable access to physical memory beyond 4G, only supported on
  ARC cores with 40 bit Physical Addressing support
 
+config HIGHMEM_PGDS_SHIFT
+   int "log num of PGDs for HIGHMEM"
+   range 0 5
+   default "0" if !ARC_PLAT_EZNPS || !HIGHMEM
+   default "5" if ARC_PLAT_EZNPS
+   help
+ This way we can map more pages for HIGHMEM.
+ Single PGD (2M) is supporting 256 PTEs (8K PAGE_SIZE)
+ For FIXMAP where at least 2 PTEs are needed per CPU
+ large NR_CPUS e.g. 4096 will consume 32 PGDs
+
 config ARCH_PHYS_ADDR_T_64BIT
def_bool ARC_HAS_PAE40
 
diff --git a/arch/arc/include/asm/highmem.h b/arch/arc/include/asm/highmem.h
index b1585c9..c5cb473 100644
--- a/arch/arc/include/asm/highmem.h
+++ b/arch/arc/include/asm/highmem.h
@@ -17,13 +17,13 @@
 
 /* start after vmalloc area */
 #define FIXMAP_BASE(PAGE_OFFSET - FIXMAP_SIZE - PKMAP_SIZE)
-#define FIXMAP_SIZEPGDIR_SIZE  /* only 1 PGD worth */
-#define KM_TYPE_NR ((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS)
+#define FIXMAP_SIZE(PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
+#define KM_TYPE_NR (((FIXMAP_SIZE >> PAGE_SHIFT)/NR_CPUS) > 2 ?: 2)
 #define FIXMAP_ADDR(nr)(FIXMAP_BASE + ((nr) << PAGE_SHIFT))
 
 /* start after fixmap area */
 #define PKMAP_BASE (FIXMAP_BASE + FIXMAP_SIZE)
-#define PKMAP_SIZE PGDIR_SIZE
+#define PKMAP_SIZE (PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT))
 #define LAST_PKMAP (PKMAP_SIZE >> PAGE_SHIFT)
 #define LAST_PKMAP_MASK(LAST_PKMAP - 1)
 #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
@@ -32,6 +32,7 @@
 #define kmap_prot  PAGE_KERNEL
 
 
+#ifndef __ASSEMBLY__
 #include 
 
 extern void *kmap(struct page *page);
@@ -54,6 +55,7 @@ static inline void kunmap(struct page *page)
return;
kunmap_high(page);
 }
+#endif /* __ASSEMBLY__  */
 
 
 #endif
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 08fe338..d08e207 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -224,6 +224,8 @@
 #definePTRS_PER_PTE_BITUL(BITS_FOR_PTE)
 #definePTRS_PER_PGD_BITUL(BITS_FOR_PGD)
 
+#define PTRS_HMEM_PTE  _BITUL(BITS_FOR_PTE + CONFIG_HIGHMEM_PGDS_SHIFT)
+
 /*
  * Number of entries a user land program use.
  * TASK_SIZE is the maximum vaddr that can be used by a userland program.
@@ -285,7 +287,14 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 
 /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
 #define pte_pfn(pte)   (pte_val(pte) >> PAGE_SHIFT)
+#if CONFIG_HIGHMEM_PGDS_SHIFT
+#define __pte_index(addr)  (((addr) >= VMALLOC_END) ? \
+   (((addr) >> PAGE_SHIFT) & (PTRS_HMEM_PTE - 1)) \
+   :  \
+   (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#else
 #define __pte_index(addr)  (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#endif
 
 /*
  * pte_offset gets a @ptr to PMD entry (PGD in our 2-tier paging system)
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 6e1242d..fd7bdfa 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -121,8 +121,9 @@ extern void start_thread(struct pt_regs * regs, unsigned 
long pc,
 
 #define VMALLOC_START  (PAGE_OFFSET - (CONFIG_ARC_KVADDR_SIZE << 20))
 
-/* 1 PGDIR_SIZE each for fixmap/pkmap, 2 PGDIR_SIZE gutter (see asm/highmem.h) 
*/
-#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - PGDIR_SIZE * 4)
+/* 1 << CONFIG_HIGHMEM_PGDS_SHIFT PGDIR_SIZE each for fixmap/pkmap */
+#define VMALLOC_SIZE   ((CONFIG_ARC_KVADDR_SIZE << 20) - \
+ PGDIR_SIZE * _BITUL(CONFIG_HIGHMEM_PGDS_SHIFT) * 2)
 
 #define VMALLOC_END(VMAL

[PATCH 04/11] ARC: Add CPU topology

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.

This way with topology the scheduler is much efficient in
creating domains and later using them.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig|   27 
 arch/arc/include/asm/Kbuild |1 -
 arch/arc/include/asm/topology.h |   34 +++
 arch/arc/kernel/Makefile|1 +
 arch/arc/kernel/setup.c |4 +-
 arch/arc/kernel/smp.c   |5 ++
 arch/arc/kernel/topology.c  |  125 +++
 7 files changed, 194 insertions(+), 3 deletions(-)
 create mode 100644 arch/arc/include/asm/topology.h
 create mode 100644 arch/arc/kernel/topology.c

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index dc1df6f..b759be1 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -203,6 +203,33 @@ config ARC_SMP_HALT_ON_RESET
  at designated entry point. For other case, all jump to common
  entry point and spin wait for Master's signal.
 
+config NPS_CPU_TOPOLOGY
+   bool "Support cpu topology definition"
+   depends on EZNPS_MTM_EXT
+   default y
+   help
+ Support NPS cpu topology definition.
+ NPS400 got 16 clusters of cores.
+ NPS400 cluster got 16 cores.
+ NPS core got 16 symetrical threads.
+ Totally there are such 4096 threads (NR_CPUS=4096)
+
+config SCHED_MC
+   bool "Multi-core scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Multi-core scheduler support improves the CPU scheduler's decision
+ making when dealing with multi-core CPU chips at a cost of slightly
+ increased overhead in some places. If unsure say N here.
+
+config SCHED_SMT
+   bool "SMT scheduler support"
+   depends on NPS_CPU_TOPOLOGY
+   help
+ Improves the CPU scheduler's decision making when dealing with
+ MultiThreading at a cost of slightly increased overhead in some
+ places. If unsure say N here.
+
 endif  #SMP
 
 config ARC_MCIP
diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild
index 7bee4e4..d8cb607 100644
--- a/arch/arc/include/asm/Kbuild
+++ b/arch/arc/include/asm/Kbuild
@@ -43,7 +43,6 @@ generic-y += stat.h
 generic-y += statfs.h
 generic-y += termbits.h
 generic-y += termios.h
-generic-y += topology.h
 generic-y += trace_clock.h
 generic-y += types.h
 generic-y += ucontext.h
diff --git a/arch/arc/include/asm/topology.h b/arch/arc/include/asm/topology.h
new file mode 100644
index 000..a9be3f8
--- /dev/null
+++ b/arch/arc/include/asm/topology.h
@@ -0,0 +1,34 @@
+#ifndef _ASM_ARC_TOPOLOGY_H
+#define _ASM_ARC_TOPOLOGY_H
+
+#ifdef CONFIG_NPS_CPU_TOPOLOGY
+
+#include 
+
+struct cputopo_nps {
+   int thread_id;
+   int core_id;
+   cpumask_t thread_sibling;
+   cpumask_t core_sibling;
+};
+
+extern struct cputopo_nps cpu_topology[NR_CPUS];
+
+#define topology_core_id(cpu)  (cpu_topology[cpu].core_id)
+#define topology_core_cpumask(cpu) (_topology[cpu].core_sibling)
+#define topology_sibling_cpumask(cpu)  (_topology[cpu].thread_sibling)
+
+void init_cpu_topology(void);
+void store_cpu_topology(unsigned int cpuid);
+const struct cpumask *cpu_coregroup_mask(int cpu);
+
+#else
+
+static inline void init_cpu_topology(void) { }
+static inline void store_cpu_topology(unsigned int cpuid) { }
+
+#endif
+
+#include 
+
+#endif /* _ASM_ARC_TOPOLOGY_H */
diff --git a/arch/arc/kernel/Makefile b/arch/arc/kernel/Makefile
index 8942c5c..46af80a 100644
--- a/arch/arc/kernel/Makefile
+++ b/arch/arc/kernel/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARC_EMUL_UNALIGNED)  += unaligned.o
 obj-$(CONFIG_KGDB) += kgdb.o
 obj-$(CONFIG_ARC_METAWARE_HLINK)   += arc_hostlink.o
 obj-$(CONFIG_PERF_EVENTS)  += perf_event.o
+obj-$(CONFIG_NPS_CPU_TOPOLOGY) += topology.o
 
 obj-$(CONFIG_ARC_FPU_SAVE_RESTORE) += fpu.o
 CFLAGS_fpu.o   += -mdpfp
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 8494b31..5256205 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -571,14 +571,14 @@ static void c_stop(struct seq_file *m, void *v)
.show   = show_cpuinfo
 };
 
-static DEFINE_PER_CPU(struct cpu, cpu_topology);
+static DEFINE_PER_CPU(struct cpu, cpu_topo_info);
 
 static int __init topology_init(void)
 {
int cpu;
 
for_each_present_cpu(cpu)
-   register_cpu(_cpu(cpu_topology, cpu), cpu);
+   register_cpu(_cpu(cpu_topo_info, cpu), cpu);
 
return 0;
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index d1aa917..167a620 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -67,6 +67,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
int i;
 
+   init_cpu_topology();
+   store_cpu_topology(smp_processor_id());
+
  

[PATCH 09/11] ARC: [plat-eznps] Save/Restore extra auxiliary registers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.

We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while using atomic operations e.g. cmpxchg.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/arcregs.h   |7 +++
 arch/arc/include/asm/processor.h |3 +++
 arch/arc/include/asm/switch_to.h |   11 +++
 arch/arc/plat-eznps/Makefile |2 +-
 arch/arc/plat-eznps/ctop.c   |   33 +
 5 files changed, 55 insertions(+), 1 deletions(-)
 create mode 100644 arch/arc/plat-eznps/ctop.c

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index ba8e802..9437d42 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -123,6 +123,13 @@
 #define PAGES_TO_MB(n_pages)   (PAGES_TO_KB(n_pages) >> 10)
 
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+struct eznps_dp {
+   unsigned int eflags;
+   unsigned int gpa1;
+};
+#endif
+
 /*
  ***
  * Build Configuration Registers, with encoded hardware config
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index fd7bdfa..130bb55 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -38,6 +38,9 @@ struct thread_struct {
 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
struct arc_fpu fpu;
 #endif
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   struct eznps_dp dp;
+#endif
 };
 
 #define INIT_THREAD  {  \
diff --git a/arch/arc/include/asm/switch_to.h b/arch/arc/include/asm/switch_to.h
index 1b171ab..4c53080 100644
--- a/arch/arc/include/asm/switch_to.h
+++ b/arch/arc/include/asm/switch_to.h
@@ -26,13 +26,24 @@
 
 #endif /* !CONFIG_ARC_FPU_SAVE_RESTORE */
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+extern void dp_save_restore(struct task_struct *p, struct task_struct *n);
+#define ARC_DP_PREV(p, n)  dp_save_restore(p, n)
+#define ARC_DP_NEXT(t)
+#else
+#define ARC_DP_PREV(p, n)
+#define ARC_DP_NEXT(n)
+#endif /* !CONFIG_ARC_PLAT_EZNPS */
+
 struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n);
 
 #define switch_to(prev, next, last)\
 do {   \
+   ARC_DP_PREV(prev, next);\
ARC_FPU_PREV(prev, next);   \
last = __switch_to(prev, next);\
ARC_FPU_NEXT(next); \
+   ARC_DP_NEXT(next);  \
mb();   \
 } while (0)
 
diff --git a/arch/arc/plat-eznps/Makefile b/arch/arc/plat-eznps/Makefile
index 21091b1..8d43717 100644
--- a/arch/arc/plat-eznps/Makefile
+++ b/arch/arc/plat-eznps/Makefile
@@ -2,6 +2,6 @@
 # Makefile for the linux kernel.
 #
 
-obj-y := entry.o platform.o
+obj-y := entry.o platform.o ctop.o
 obj-$(CONFIG_SMP) += smp.o
 obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
diff --git a/arch/arc/plat-eznps/ctop.c b/arch/arc/plat-eznps/ctop.c
new file mode 100644
index 000..8b13a08
--- /dev/null
+++ b/arch/arc/plat-eznps/ctop.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+
+void dp_save_restore(struct task_struct *prev, struct task_struct *next)
+{
+   struct eznps_dp *prev_task_dp = >thread.dp;
+   struct eznps_dp *next_task_dp = >thread.dp;
+
+   /* Here we save all Data Plane related auxiliary registers */
+   prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS);
+   write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags);
+
+   prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1);
+   write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1);
+}
+
-- 
1.7.1


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[PATCH 10/11] ARC: [plat-eznps] handle dedicated AUX registers

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Preserve eflags and gpa1 auxiliaries during exception
Registers used by compare exchange instructions.
GPA1 is used for compare value, and EFLAGS got bit reflects
atomic operation response.

EFLAGS is zeroed for each new user task so it won't get its
parent value.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/entry-compact.h |   24 
 arch/arc/include/asm/ptrace.h|5 +
 arch/arc/kernel/process.c|4 
 3 files changed, 33 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/entry-compact.h 
b/arch/arc/include/asm/entry-compact.h
index 14c310f..9e4458a 100644
--- a/arch/arc/include/asm/entry-compact.h
+++ b/arch/arc/include/asm/entry-compact.h
@@ -192,6 +192,12 @@
PUSHAX  lp_start
PUSHAX  erbta
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   PUSHAX  CTOP_AUX_GPA1
+   PUSHAX  CTOP_AUX_EFLAGS
+#endif
+`
lr  r9, [ecr]
st  r9, [sp, PT_event]/* EV_Trap expects r9 to have ECR */
 .endm
@@ -208,6 +214,12 @@
  * by hardware and that is not good.
  *-*/
 .macro EXCEPTION_EPILOGUE
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   POPAX   CTOP_AUX_EFLAGS
+   POPAX   CTOP_AUX_GPA1
+#endif
+
POPAX   erbta
POPAX   lp_start
POPAX   lp_end
@@ -265,6 +277,12 @@
PUSHAX  lp_end
PUSHAX  lp_start
PUSHAX  bta_l\LVL\()
+
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   PUSHAX  CTOP_AUX_GPA1
+   PUSHAX  CTOP_AUX_EFLAGS
+#endif
 .endm
 
 /*--
@@ -277,6 +295,12 @@
  * by hardware and that is not good.
  *-*/
 .macro INTERRUPT_EPILOGUE  LVL
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   .word CTOP_INST_SCHD_RW
+   POPAX   CTOP_AUX_EFLAGS
+   POPAX   CTOP_AUX_GPA1
+#endif
+
POPAX   bta_l\LVL\()
POPAX   lp_start
POPAX   lp_end
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 5297faa..5a8cb22 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -19,6 +19,11 @@
 #ifdef CONFIG_ISA_ARCOMPACT
 struct pt_regs {
 
+#ifdef CONFIG_ARC_PLAT_EZNPS
+   unsigned long eflags;   /* Extended FLAGS */
+   unsigned long gpa1; /* General Purpose Aux */
+#endif
+
/* Real registers */
unsigned long bta;  /* bta_l1, bta_l2, erbta */
 
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 5c631a1..5ac3b54 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -234,6 +234,10 @@ void start_thread(struct pt_regs * regs, unsigned long pc, 
unsigned long usp)
 */
regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS;
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+   regs->eflags = 0;
+#endif
+
/* bogus seed values for debugging */
regs->lp_start = 0x10;
regs->lp_end = 0x80;
-- 
1.7.1


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[PATCH 07/11] ARC: [plat-eznps] new command line argument for HW scheduler at MTM

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 Documentation/admin-guide/kernel-parameters.txt |9 
 arch/arc/plat-eznps/mtm.c   |   49 ++-
 2 files changed, 56 insertions(+), 2 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 15f79c2..5b551f7 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2693,6 +2693,15 @@
If the dependencies are under your control, you can
turn on cpu0_hotplug.
 
+   nps_mtm_hs_ctr= [KNL,ARC]
+   This parameter sets the maximum duration, in
+   cycles, each HW thread of the CTOP can run
+   without interruptions, before HW switches it.
+   The actual maximum duration is 16 times this
+   parameter's value.
+   Format: integer between 1 and 255
+   Default: 255
+
nptcg=  [IA-64] Override max number of concurrent global TLB
purges which is reported from either PAL_VM_SUMMARY or
SAL PALO.
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index e0cb36b..f77335a 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -21,10 +21,13 @@
 #include 
 #include 
 
-#define MT_CTRL_HS_CNT 0xFF
+#define MT_HS_CNT_MIN  0x01
+#define MT_HS_CNT_MAX  0xFF
 #define MT_CTRL_ST_CNT 0xF
 #define NPS_NUM_HW_THREADS 0x10
 
+static int mtm_hs_ctr = MT_HS_CNT_MAX;
+
 static void mtm_init_nat(int cpu)
 {
struct nps_host_reg_mtm_cfg mtm_cfg;
@@ -118,7 +121,7 @@ void mtm_enable_core(unsigned int cpu)
/* Enable HW schedule, stall counter, mtm */
mt_ctrl.value = 0;
mt_ctrl.hsen = 1;
-   mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
+   mt_ctrl.hs_cnt = mtm_hs_ctr;
mt_ctrl.mten = 1;
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
@@ -129,3 +132,45 @@ void mtm_enable_core(unsigned int cpu)
 */
cpu_relax();
 }
+
+/* Handle an out of bounds mtm hs counter value */
+static void __init handle_mtm_hs_ctr_out_of_bounds_error(uint8_t val)
+{
+   pr_err("** The value of mtm_hs_ctr is out of bounds!\n"
+  "** It must be in the range [%d,%d] (inclusive)\n"
+  "Setting mtm_hs_ctr to %d\n", MT_HS_CNT_MIN, MT_HS_CNT_MAX, val);
+
+   mtm_hs_ctr = val;
+}
+
+/* Verify and set the value of the mtm hs counter */
+static int __init set_mtm_hs_ctr(char *ctr_str)
+{
+   int ret;
+   long hs_ctr;
+
+   ret = kstrtol(ctr_str, 0, _ctr);
+   if (ret) {
+   pr_err("** Error parsing the value of mtm_hs_ctr\n"
+  "** Make sure you entered a valid integer value\n"
+  "Setting mtm_hs_ctr to default value: %d\n",
+  MT_HS_CNT_MAX);
+   mtm_hs_ctr = MT_HS_CNT_MAX;
+   return -EINVAL;
+   }
+
+   if (hs_ctr > MT_HS_CNT_MAX) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MAX);
+   return -EDOM;
+   }
+
+   if (hs_ctr < MT_HS_CNT_MIN) {
+   handle_mtm_hs_ctr_out_of_bounds_error(MT_HS_CNT_MIN);
+   return -EDOM;
+   }
+
+   mtm_hs_ctr = hs_ctr;
+
+   return 0;
+}
+early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
-- 
1.7.1


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[PATCH 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu.

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

The following commit adds a config that will enable us to distinguish
between building the kernel for platforms that have a different set
of auxiliary registers for each cpu and platforms that have a shared
set of auxiliary registers across every thread in each core.
On platforms that implement a different set of auxiliary registers
there is a need to initialize them on every cpu and not just the for the
first thread of the core.

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++
 arch/arc/plat-eznps/entry.S |2 +-
 2 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index daf749e..812bc29 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -44,3 +44,14 @@ config EZNPS_MEM_ERROR
  for NPS, it handled as an interrupt level 2 (like legacy arc
  real chip architecture).This configuration will cause the kernel
  to handle memory error as a machine check exception.
+
+config EZNPS_SHARED_AUX_REGS
+   bool "ARC-EZchip Shared Auxiliary Registers Per Core"
+   depends on ARC_PLAT_EZNPS
+   default y
+   help
+ On the real chip of the NPS, auxiliary registers are shared between
+ all the cpus of the core, whereas on simulator platform for NPS,
+ each cpu has a different set of auxiliary registers. Configuration
+ should be unset if auxiliary registers are not shared between the cpus
+ of the core, so there will be a need to initialize them per cpu.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 21665ae..4a29c80 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -27,7 +27,7 @@
.align 1024 ; HW requierment for restart first PC
 
 ENTRY(res_service)
-#ifdef CONFIG_EZNPS_MTM_EXT
+#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS)
; There is no work for HW thread id != 0
lr  r3, [CTOP_AUX_THREAD_ID]
cmp r3, 0
-- 
1.7.1


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RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Noam Camus 
> Sent: Wednesday, June 7, 2017 9:08 AM
>To: 'Vineet Gupta' <vineet.gup...@synopsys.com>; 
>linux-snps-arc@lists.infradead.org
>Cc: linux-ker...@vger.kernel.org; Elad Kanfi <elad...@mellanox.com>
>Subject: RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an 
>exception

>>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
>>Sent: Wednesday, June 7, 2017 1:11 AM
>...
>>> +
>>> +config EZNPS_MEM_ERROR
>>> +   bool "ARC-EZchip Memory error as an exception"
>>> +   depends on ARC_PLAT_EZNPS
>>> +   default n

>>So you set default to "n" - thus by default it works for the simulator not 
>>silicon ?
>Correct, this way I "align" Sim environment to react as close as possible to 
>how it work with silicon.

Sorry, but It is not correct.
Default is for silicon where it is naturally emits machine check and unlike 
simulator do not need OS to redirect the ISR L2 to machine check handler.
Above motivation of "align" is true, but default is silicon and not sim, as I 
wrote in my original configuration help.
Please re-update this CONFIG help section.

Thanks
-Noam
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RE: [PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
> Sent: Friday, June 2, 2017 21:36 PM
...

>>   arch/arc/include/asm/spinlock.h |6 ++
>>   1 files changed, 6 insertions(+), 0 deletions(-)
>> 
>> diff --git a/arch/arc/include/asm/spinlock.h 
>> b/arch/arc/include/asm/spinlock.h index 233d5ff..0a54ce7 100644
>> --- a/arch/arc/include/asm/spinlock.h
>> +++ b/arch/arc/include/asm/spinlock.h
>> @@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t 
>> *lock)
>>   
>>  __asm__ __volatile__(
>>  "1: ex  %0, [%1]\n"
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +"   .word %3\n"
>> +#endif
>>  "   breq  %0, %2, 1b\n"
>>  : "+" (val)
>>  : "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +, "i"(CTOP_INST_SCHD_RW)
>> +#endif
>>  : "memory");
>>   
>>  /*
>> 

>This is ugly - I will fix it up here to create an NPS version of 
>arch_spin_lock !
TNX

-Noam
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RE: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
> Sent: Friday, June 2, 2017 22:04 PM

>> diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig 
>> index feaa471..c5f946c 100644
>> --- a/arch/arc/plat-eznps/Kconfig
>> +++ b/arch/arc/plat-eznps/Kconfig
>> @@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
>>any of them seem like CPU from Linux point of view.
>>All threads within same core share the execution unit of the
>>core and HW scheduler round robin between them.
>> +
>> +config EZNPS_MEM_ERROR
>> +   bool "ARC-EZchip Memory error as an exception"
>> +   depends on ARC_PLAT_EZNPS
>> +   default n
>> +   help
>> + On the real chip of the NPS, user memory errors are handled
>> + as a machine check exception, whereas on simulator platform
>> + for NPS, it handled as an interrupt level 2 (like legacy arc
>> + real chip architecture).This configuration will cause the kernel
>> + to handle memory error as a machine check exception.

>Do you really need a Kconfig option here. AFAIKR you guys had some magic in 
>platform code to determine whether running on sim or hw - can that be not used 
>?
We do not have this anymore, needed to create dedicated one here.

...

>> diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S 
>> index 328261c..03e2892 100644
>> --- a/arch/arc/plat-eznps/entry.S
>> +++ b/arch/arc/plat-eznps/entry.S
>> @@ -68,3 +68,17 @@ ENTRY(res_service)
>>   
>>  j   stext
>>   END(res_service)
>> +
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +ENTRY(mem_service)
>> +; SW workaround to cover up on a difference between
>> +; NPS real chip and simulator behaviors.
>> +; NPS real chip will activate a machine check exception
>> +; in case of memory error, while the simulator will
>> +; trigger a level 2 interrupt. Therefor this code section
>> +; should be reached only in simulation mode.
>> +; DEAD END: display Regs and HALT
>> +
>> +j EV_MachineCheck
>> +END(mem_service)
>> +#endif


>Just squash the weak symbol patch in here - not worth a separate patch !
Ok , no problem.

-Noam

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[PATCH v2 06/11] ARC: [plat-eznps] Fix TLB Errata

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/mm/tlbex.S |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..0e1e47a 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+   /* verify if entry for this vaddr+ASID already exists */
+   srTLBProbe, [ARC_REG_TLBCOMMAND]
+   lrr0, [ARC_REG_TLBINDEX]
+   bbit0 r0, 31, 88f
+#endif
+
/* Get free TLB slot: Set = computed from vaddr, way = random */
sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,8 @@ ex_saved_reg1:
 #else
sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+
+88:
 .endm
 
 
-- 
1.7.1


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[PATCH v2 09/11] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can execute instructions.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/process.c   |7 +++
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 2a018de..d3c39e4 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -82,10 +82,17 @@
 void arch_cpu_idle(void)
 {
/* sleep, but enable all interrupts before committing */
+#if !defined(CONFIG_EZNPS_MTM_EXT)
__asm__ __volatile__(
"sleep %0   \n"
:
:"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const 
*/
+#else
+   __asm__ __volatile__(
+   ".word %0   \n"
+   :
+   :"i"(CTOP_INST_HWSCHD_WFT_IE12));
+#endif
 }
 
 asmlinkage void ret_from_fork(void);
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index ee2e32d..7729d3d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,6 +46,7 @@
 #define CTOP_AUX_UDMC  (CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
+#define CTOP_INST_HWSCHD_WFT_IE12  0x3E6F7344
 #define CTOP_INST_HWSCHD_OFF_R40x3C6F00BF
 #define CTOP_INST_HWSCHD_RESTORE_R40x3E6F7103
 #define CTOP_INST_SCHD_RW  0x3E6F7004
-- 
1.7.1


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[PATCH v2 08/11] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.

We noticed about 10% improvement of execution time with hackbench test.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/include/asm/spinlock.h |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 233d5ff..0a54ce7 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
__asm__ __volatile__(
"1: ex  %0, [%1]\n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+   "   .word %3\n"
+#endif
"   breq  %0, %2, 1b\n"
: "+" (val)
: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+   , "i"(CTOP_INST_SCHD_RW)
+#endif
: "memory");
 
/*
-- 
1.7.1


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[PATCH v2 01/11] ARC: set level of log per CPU during boot to be debug level

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
   e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
   scale machines such NPS400

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/setup.c |6 +++---
 arch/arc/kernel/smp.c   |4 ++--
 arch/arc/mm/cache.c |2 +-
 arch/arc/mm/tlb.c   |2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index fc8211f..8494b31 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -385,13 +385,13 @@ void setup_processor(void)
read_arc_build_cfg_regs();
arc_init_IRQ();
 
-   printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 
arc_mmu_init();
arc_cache_init();
 
-   printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
-   printk(arc_platform_smp_cpuinfo());
+   pr_debug("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
+   pr_debug("%s", arc_platform_smp_cpuinfo());
 
arc_chk_core_config();
 }
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index f462671..d1aa917 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -177,8 +177,8 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
 
secondary_idle_tsk = idle;
 
-   pr_info("Idle Task [%d] %p", cpu, idle);
-   pr_info("Trying to bring up CPU%u ...\n", cpu);
+   pr_debug("Idle Task [%d] %p", cpu, idle);
+   pr_debug("Trying to bring up CPU%u ...\n", cpu);
 
if (plat_smp_ops.cpu_kick)
plat_smp_ops.cpu_kick(cpu,
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..7d3e79b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -1188,7 +1188,7 @@ void __ref arc_cache_init(void)
unsigned int __maybe_unused cpu = smp_processor_id();
char str[256];
 
-   printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_cache_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Only master CPU needs to execute rest of function:
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index d0126fd..c5e70d8 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -814,7 +814,7 @@ void arc_mmu_init(void)
char str[256];
struct cpuinfo_arc_mmu *mmu = _arc700[smp_processor_id()].mmu;
 
-   printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
+   pr_debug("%s", arc_mmu_mumbojumbo(0, str, sizeof(str)));
 
/*
 * Can't be done in processor.h due to header include depenedencies
-- 
1.7.1


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[PATCH v2 03/11] ARC: typo fix in mm/fault.c

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
 arch/arc/mm/fault.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -207,7 +207,7 @@ void do_page_fault(unsigned long address, struct pt_regs 
*regs)
/* Are we prepared to handle this kernel fault?
 *
 * (The kernel has valid exception-points in the source
-*  when it acesses user-memory. When it fails in one
+*  when it accesses user-memory. When it fails in one
 *  of those points, we find it in a table and do a jump
 *  to some fixup code that loads an appropriate error
 *  code)
-- 
1.7.1


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[PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This commit adds the configuration CONFIG_EZNPS_MEM_ERROR.
If set, it will cause the kernel to handle user memory error
as a machine check exception.
It is required in order to align the NPS simulator memory
error handling to the one of the NPS400 real chip behavior.
We override weak symbole of mem_service to achieve that.

Signed-off-by: Elad Kanfi <elad...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |   11 +++
 arch/arc/plat-eznps/entry.S |   14 ++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index feaa471..c5f946c 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -32,3 +32,14 @@ config EZNPS_MTM_EXT
  any of them seem like CPU from Linux point of view.
  All threads within same core share the execution unit of the
  core and HW scheduler round robin between them.
+
+config EZNPS_MEM_ERROR
+   bool "ARC-EZchip Memory error as an exception"
+   depends on ARC_PLAT_EZNPS
+   default n
+   help
+ On the real chip of the NPS, user memory errors are handled
+ as a machine check exception, whereas on simulator platform
+ for NPS, it handled as an interrupt level 2 (like legacy arc
+ real chip architecture).This configuration will cause the kernel
+ to handle memory error as a machine check exception.
diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S
index 328261c..03e2892 100644
--- a/arch/arc/plat-eznps/entry.S
+++ b/arch/arc/plat-eznps/entry.S
@@ -68,3 +68,17 @@ ENTRY(res_service)
 
j   stext
 END(res_service)
+
+#if defined(CONFIG_EZNPS_MEM_ERROR)
+ENTRY(mem_service)
+   ; SW workaround to cover up on a difference between
+   ; NPS real chip and simulator behaviors.
+   ; NPS real chip will activate a machine check exception
+   ; in case of memory error, while the simulator will
+   ; trigger a level 2 interrupt. Therefor this code section
+   ; should be reached only in simulation mode.
+   ; DEAD END: display Regs and HALT
+
+   j EV_MachineCheck
+END(mem_service)
+#endif
-- 
1.7.1


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[PATCH v2 04/11] ARC: typos fix in kernel/entry-compact.S

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
 arch/arc/kernel/entry-compact.S |   22 +++---
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include 
-#include  /* {EXTRY,EXIT} */
+#include  /* {ENTRY,EXIT} */
 #include 
 #include 
 
@@ -80,8 +80,8 @@
.align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ;  Exceptions **
 VECTOR   EV_MachineCheck ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD ; 0x110, Data TLB miss (0x22)
 VECTOR   EV_TLBProtV ; 0x118, Protection Violation  (0x23)
 ; or Misaligned Access
 VECTOR   EV_PrivilegeV   ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap ; 0x128, Trap exception(0x25)
-VECTOR   EV_Extension; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; -
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; -
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
;-- (5) Type of Protection Violation? --
;
; ProtV Hardware Exception is triggered for Access Faults of 2 types
-   ;   -Access Violaton: 00_23_(00|01|02|03)_00
+   ;   -Access Violation   : 00_23_(00|01|02|03)_00
;x  r  w  r+w
;   -Unaligned Access   : 00_23_04_00
;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-   # Interrpts are actually disabled from this point on, but will get
+   # Interrupts are actually disabled from this point on, but will get
# reenabled after we return from interrupt/exception.
# But irq tracer needs to be told now...
TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
lr  r10, [status32]
 
; Restore REG File. In case multiple Events outstanding,
-   ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+   ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
; Note that we use realtime STATUS32 (not pt_regs->status32) to
; decide that.
 
-- 
1.7.1


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[PATCH v2 05/11] ARC: [plat-eznps] typo fix at Kconfig

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Signed-off-by: Noam Camus <noa...@mellanox.com>
Reviewed-by: Alexey Brodkin <abrod...@synopsys.com>
---
 arch/arc/plat-eznps/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
help
  Support for EZchip development platforms,
  based on ARC700 cores.
- We handle few flavours:
-   - Hardware Emulator AKA HE which is FPGA based chasis
+ We handle few flavors:
+   - Hardware Emulator AKA HE which is FPGA based chassis
- Simulator based on MetaWare nSIM
- NPS400 chip based on ASIC
 
-- 
1.7.1


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RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] 
>Sent: Thursday, May 25, 2017 14:31 PM
...
>> > Why don't you just make simulator behaving exactly as your real chip?
>> I can't change simulator core behavior. nSIM is a Synopsys proprietary code.

>Well probably it worth discussing with nSIM team if they may have any 
>suggestions on how to align nSIM behavior with your real HW?
We already talked with them, nothing we can do at this point.
What about turning mem_service into weak symbol and have my own platform copy 
(just like we do with res_service)?

-Noam 
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RE: [PATCH 10/10] ARC: [plat-eznps] Handle memory error as an exception

[Noam Camus]

> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] 
> Sent: Thursday, May 25, 2017 14:15 PM

>> 
>> diff --git a/arch/arc/kernel/entry-compact.S 
>> b/arch/arc/kernel/entry-compact.S index f285dbb..d152d36 100644
>> --- a/arch/arc/kernel/entry-compact.S
>> +++ b/arch/arc/kernel/entry-compact.S
>> @@ -203,6 +203,17 @@ END(handle_interrupt_level2)
>>  ; -
>>  ENTRY(mem_service)
>>  
>> +#if defined(CONFIG_EZNPS_MEM_ERROR)
>> +; SW workaround to cover up on a difference between
>> +; NPS real chip and simulator behaviors.
>> +; NPS real chip will activate a machine check exception
>> +; in case of memory error, while the simulator will
>> +; trigger a level 2 interrupt. Therefor this code section
>> +; should be reached only in simulation mode.
>> +; DEAD END: display Regs and HALT

>I'm not really buying that.

>Why don't you just make simulator behaving exactly as your real chip?
I can't change simulator core behavior. nSIM is a Synopsys proprietary code.

>Adding those stubs for some corner-cases here and there complicate code, 
>affect maintainability etc.
I agree, any suggestions to still have this but with reduced cost?

-Noam
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RE: [PATCH 07/10] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Noam Camus]

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] 
>Sent: Thursday, May 25, 2017 14:10 PM
...
>> diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c 
>> index ffd..e0cb36b 100644
>> --- a/arch/arc/plat-eznps/mtm.c
>> +++ b/arch/arc/plat-eznps/mtm.c
>> @@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
>>  mt_ctrl.value = 0;
>>  mt_ctrl.hsen = 1;
>>  mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
>> -mt_ctrl.sten = 1;
>> -mt_ctrl.st_cnt = MT_CTRL_ST_CNT;

>Even though I don't know your architecture this change doesn't make enough 
>sense to me in absence of better explanation of what is really done here.

>I.e. how removal of those 2 lines above improve your situation.
By removing 2 lines I am resorting to HW reset value where sten=0 i.e. feature 
is disabled.
I will rewrite the explanation

-Noam
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RE: [PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

[Noam Camus]

>From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] 
>Sent: Thursday, May 25, 2017 14:01 PM

...
>>  /* Get free TLB slot: Set = computed from vaddr, way = random */
>>  sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
>>  
>> @@ -287,6 +294,9 @@ ex_saved_reg1:
>>  #else
>>  sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
>>  #endif
>> +#ifdef CONFIG_EZNPS_MTM_EXT
>> +88:
>> +#endif

>Not sure if label itself required wrapping in ifdefs. It just makes code 
>bulkier and harder to read.
I will remove the wrapping.

-Noam
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[PATCH 03/10] ARC: typo fix in mm/fault.c

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/mm/fault.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 162c975..a0b7bd6 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -207,7 +207,7 @@ void do_page_fault(unsigned long address, struct pt_regs 
*regs)
/* Are we prepared to handle this kernel fault?
 *
 * (The kernel has valid exception-points in the source
-*  when it acesses user-memory. When it fails in one
+*  when it accesses user-memory. When it fails in one
 *  of those points, we find it in a table and do a jump
 *  to some fixup code that loads an appropriate error
 *  code)
-- 
1.7.1


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[PATCH 07/10] ARC: [plat-eznps] disabled stall counter due to a HW bug

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This counter represents threshold for consecutive stall that which
trigger HW threads scheduling.
Low values of this counter cause downgrade in performance
and in the worst case even a livelock.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/mtm.c |2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index ffd..e0cb36b 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -119,8 +119,6 @@ void mtm_enable_core(unsigned int cpu)
mt_ctrl.value = 0;
mt_ctrl.hsen = 1;
mt_ctrl.hs_cnt = MT_CTRL_HS_CNT;
-   mt_ctrl.sten = 1;
-   mt_ctrl.st_cnt = MT_CTRL_ST_CNT;
mt_ctrl.mten = 1;
write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value);
 
-- 
1.7.1


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[PATCH 06/10] ARC: [plat-eznps] Fix TLB Errata

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Due to a HW bug in NPS400 we get from time to time false TLB miss.
Workaround this by validating each miss.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/mm/tlbex.S |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index b30e4e3..1d48723 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -274,6 +274,13 @@ ex_saved_reg1:
 .macro COMMIT_ENTRY_TO_MMU
 #if (CONFIG_ARC_MMU_VER < 4)
 
+#ifdef CONFIG_EZNPS_MTM_EXT
+   /* verify if entry for this vaddr+ASID already exists */
+   srTLBProbe, [ARC_REG_TLBCOMMAND]
+   lrr0, [ARC_REG_TLBINDEX]
+   bbit0 r0, 31, 88f
+#endif
+
/* Get free TLB slot: Set = computed from vaddr, way = random */
sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
 
@@ -287,6 +294,9 @@ ex_saved_reg1:
 #else
sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
 #endif
+#ifdef CONFIG_EZNPS_MTM_EXT
+88:
+#endif
 .endm
 
 
-- 
1.7.1


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[PATCH 09/10] ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle task

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

When HW threads are active we want CPU to enter idle state only
for the calling HW thread and not to put on sleep all HW threads
sharing this core. For this need the NPS400 got dedicated instruction
so only calling thread is entring sleep and all other are still awake
and can execute instructions.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/process.c   |7 +++
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index 2a018de..d3c39e4 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -82,10 +82,17 @@
 void arch_cpu_idle(void)
 {
/* sleep, but enable all interrupts before committing */
+#if !defined(CONFIG_EZNPS_MTM_EXT)
__asm__ __volatile__(
"sleep %0   \n"
:
:"I"(ISA_SLEEP_ARG)); /* can't be "r" has to be embedded const 
*/
+#else
+   __asm__ __volatile__(
+   ".word %0   \n"
+   :
+   :"i"(CTOP_INST_HWSCHD_WFT_IE12));
+#endif
 }
 
 asmlinkage void ret_from_fork(void);
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index ee2e32d..7729d3d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,6 +46,7 @@
 #define CTOP_AUX_UDMC  (CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
+#define CTOP_INST_HWSCHD_WFT_IE12  0x3E6F7344
 #define CTOP_INST_HWSCHD_OFF_R40x3C6F00BF
 #define CTOP_INST_HWSCHD_RESTORE_R40x3E6F7103
 #define CTOP_INST_SCHD_RW  0x3E6F7004
-- 
1.7.1


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[PATCH 04/10] ARC: typos fix in kernel/entry-compact.S

[Noam Camus]

From: Liav Rehana <li...@mellanox.com>

Signed-off-by: Liav Rehana <li...@mellanox.com>
Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/kernel/entry-compact.S |   22 +++---
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arc/kernel/entry-compact.S b/arch/arc/kernel/entry-compact.S
index 9211707..f285dbb 100644
--- a/arch/arc/kernel/entry-compact.S
+++ b/arch/arc/kernel/entry-compact.S
@@ -25,12 +25,12 @@
  *
  * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
- *  -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
+ *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
  *   need ptregs anymore
  *
  * Vineetg: Oct 2009
  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
- *   out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
+ *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
  *   active (AE bit enabled).  This causes a double fault for a subseq valid
  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
  *   Instr Error could also cause similar scenario, so same there as well.
@@ -59,7 +59,7 @@
  */
 
 #include 
-#include  /* {EXTRY,EXIT} */
+#include  /* {ENTRY,EXIT} */
 #include 
 #include 
 
@@ -80,8 +80,8 @@
.align 4
 
 /* Each entry in the vector table must occupy 2 words. Since it is a jump
- * across sections (.vector to .text) we are gauranteed that 'j somewhere'
- * will use the 'j limm' form of the intrsuction as long as somewhere is in
+ * across sections (.vector to .text) we are guaranteed that 'j somewhere'
+ * will use the 'j limm' form of the instruction as long as somewhere is in
  * a section other than .vector.
  */
 
@@ -105,13 +105,13 @@ VECTOR   handle_interrupt_level1 ; Other devices
 
 ;  Exceptions **
 VECTOR   EV_MachineCheck ; 0x100, Fatal Machine check   (0x20)
-VECTOR   EV_TLBMissI ; 0x108, Intruction TLB miss   (0x21)
+VECTOR   EV_TLBMissI ; 0x108, Instruction TLB miss  (0x21)
 VECTOR   EV_TLBMissD ; 0x110, Data TLB miss (0x22)
 VECTOR   EV_TLBProtV ; 0x118, Protection Violation  (0x23)
 ; or Misaligned Access
 VECTOR   EV_PrivilegeV   ; 0x120, Privilege Violation   (0x24)
 VECTOR   EV_Trap ; 0x128, Trap exception(0x25)
-VECTOR   EV_Extension; 0x130, Extn Intruction Excp  (0x26)
+VECTOR   EV_Extension; 0x130, Extn Instruction Excp (0x26)
 
 .rept   24
 VECTOR   reserved; Reserved Exceptions
@@ -199,7 +199,7 @@ END(handle_interrupt_level2)
 
 ; -
 ; User Mode Memory Bus Error Interrupt Handler
-; (Kernel mode memory errors handled via seperate exception vectors)
+; (Kernel mode memory errors handled via separate exception vectors)
 ; -
 ENTRY(mem_service)
 
@@ -273,7 +273,7 @@ ENTRY(EV_TLBProtV)
;-- (5) Type of Protection Violation? --
;
; ProtV Hardware Exception is triggered for Access Faults of 2 types
-   ;   -Access Violaton: 00_23_(00|01|02|03)_00
+   ;   -Access Violation   : 00_23_(00|01|02|03)_00
;x  r  w  r+w
;   -Unaligned Access   : 00_23_04_00
;
@@ -327,7 +327,7 @@ END(call_do_page_fault)
 
 .Lrestore_regs:
 
-   # Interrpts are actually disabled from this point on, but will get
+   # Interrupts are actually disabled from this point on, but will get
# reenabled after we return from interrupt/exception.
# But irq tracer needs to be told now...
TRACE_ASM_IRQ_ENABLE
@@ -335,7 +335,7 @@ END(call_do_page_fault)
lr  r10, [status32]
 
; Restore REG File. In case multiple Events outstanding,
-   ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
+   ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
; Note that we use realtime STATUS32 (not pt_regs->status32) to
; decide that.
 
-- 
1.7.1


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[PATCH 05/10] ARC: [plat-eznps] typo fix at Kconfig

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig
index 1595a38..feaa471 100644
--- a/arch/arc/plat-eznps/Kconfig
+++ b/arch/arc/plat-eznps/Kconfig
@@ -12,8 +12,8 @@ menuconfig ARC_PLAT_EZNPS
help
  Support for EZchip development platforms,
  based on ARC700 cores.
- We handle few flavours:
-   - Hardware Emulator AKA HE which is FPGA based chasis
+ We handle few flavors:
+   - Hardware Emulator AKA HE which is FPGA based chassis
- Simulator based on MetaWare nSIM
- NPS400 chip based on ASIC
 
-- 
1.7.1


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[PATCH 08/10] ARC: [plat-eznps] spinlock aware for MTM

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This way when we execute "ex" during trying to hold lock we can switch to
other HW thread and utilize the core intead of just spinning on a lock.

We noticed about 10% improvement of execution time with hackbench test.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/include/asm/spinlock.h |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index 233d5ff..0a54ce7 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -252,9 +252,15 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
__asm__ __volatile__(
"1: ex  %0, [%1]\n"
+#ifdef CONFIG_EZNPS_MTM_EXT
+   "   .word %3\n"
+#endif
"   breq  %0, %2, 1b\n"
: "+" (val)
: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
+#ifdef CONFIG_EZNPS_MTM_EXT
+   , "i"(CTOP_INST_SCHD_RW)
+#endif
: "memory");
 
/*
-- 
1.7.1


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[PATCH 00/10] ARC plat-eznps upstream cont.

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

With this patch set I continue the effort of upstreaming the
eznps platform for arch/arc.

it combine of patches for typos and other for HW erratas and some
for performance.
All selected as ones that may be obvious for merge with arc next.

This was based on for-curr branch as the mos updated one I found
at this point of time. 

Liav Rehana (2):
  ARC: typo fix in mm/fault.c
  ARC: typos fix in kernel/entry-compact.S

Noam Camus (8):
  ARC: set level of log per CPU during boot to be debug level
  ARC: send ipi to all cpus sharing task mm in case of page fault
  ARC: [plat-eznps] typo fix at Kconfig
  ARC: [plat-eznps] Fix TLB Errata
  ARC: [plat-eznps] disabled stall counter due to a HW bug
  ARC: [plat-eznps] spinlock aware for MTM
  ARC: [plat-eznps] use schd.wft instruction instead of sleep at idle
task
  ARC: [plat-eznps] Handle memory error as an exception

 arch/arc/include/asm/cacheflush.h   |3 +-
 arch/arc/include/asm/spinlock.h |6 +
 arch/arc/kernel/entry-compact.S |   33 --
 arch/arc/kernel/process.c   |7 ++
 arch/arc/kernel/setup.c |6 ++--
 arch/arc/kernel/smp.c   |4 +-
 arch/arc/mm/cache.c |   14 ++--
 arch/arc/mm/fault.c |2 +-
 arch/arc/mm/tlb.c   |4 +-
 arch/arc/mm/tlbex.S |   10 +
 arch/arc/plat-eznps/Kconfig |   15 -
 arch/arc/plat-eznps/include/plat/ctop.h |1 +
 arch/arc/plat-eznps/mtm.c   |2 -
 13 files changed, 80 insertions(+), 27 deletions(-)


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[PATCH] ARC: Fix build for missing ATOMIC_INIT definition

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Make ATOMIC_INIT available for all ARC platforms (including plat-eznps)

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/include/asm/atomic.h |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index b65930a..54b54da 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -17,10 +17,11 @@
 #include 
 #include 
 
+#define ATOMIC_INIT(i) { (i) }
+
 #ifndef CONFIG_ARC_PLAT_EZNPS
 
 #define atomic_read(v)  READ_ONCE((v)->counter)
-#define ATOMIC_INIT(i) { (i) }
 
 #ifdef CONFIG_ARC_HAS_LLSC
 
-- 
1.7.1


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[PATCH v8 3/3] clocksource: Add clockevent support to NPS400 driver

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.

The design idea is that for each core there is dedicated register
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.

Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent

Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource

Signed-off-by: Noam Camus <noa...@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezc...@linaro.org>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 --
 .../bindings/timer/ezchip,nps400-timer0.txt|   17 ++
 .../bindings/timer/ezchip,nps400-timer1.txt|   15 ++
 drivers/clocksource/timer-nps.c|  170 
 4 files changed, 202 insertions(+), 15 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
deleted file mode 100644
index c8c03d7..000
--- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-NPS Network Processor
-
-Required properties:
-
-- compatible : should be "ezchip,nps400-timer"
-
-Clocks required for compatible = "ezchip,nps400-timer":
-- clocks : Must contain a single entry describing the clock input
-
-Example:
-
-timer {
-   compatible = "ezchip,nps400-timer";
-   clocks = <>;
-};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
new file mode 100644
index 000..e3cfce8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
@@ -0,0 +1,17 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer0"
+
+Clocks required for compatible = "ezchip,nps400-timer0":
+- interrupts : The interrupt of the first timer
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer0";
+   interrupts = <3>;
+   clocks = <>;
+};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
new file mode 100644
index 000..c0ab419
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer1"
+
+Clocks required for compatible = "ezchip,nps400-timer1":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer1";
+   clocks = <>;
+};
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 0c8e21f..b4c8a02 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -111,3 +111,173 @@ static int __init nps_setup_clocksource(struct 
device_node *node)
 
 CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
   nps_setup_clocksource);
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
+  nps_setup_clocksource);
+
+#ifdef CONFIG_EZNPS_MTM_EXT
+#include 
+
+/* Timer related Aux registers */
+#define NPS_REG_TIMER0_TSI 0xF850
+#define NPS_REG_TIMER0_LIMIT   0x23
+#define NPS_REG_TIMER0_CTRL0x22
+#define NPS_REG_TIMER0_CNT 0x21
+
+/*
+ * Interrupt Enabled (IE) - re-arm the timer
+ * Not Halted (NH) - is cleared when working with JTAG (for debug)
+ */
+#define TIMER0_CTRL_IE BIT(0)
+#define TIMER0_CTRL_NH BIT(1)
+
+static unsigned long nps_timer0_freq;
+static unsigned long nps_timer0_irq;
+
+static void nps_clkevent_rm_th

[RESEND PATCH v7 2/3] clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

nps_setup_clocksource() should take node as only argument as defined by
typedef int (*of_init_fn_1_ret)(struct device_node *)

Therefore need to replace:
int __init nps_setup_clocksource(struct device_node *node, struct clk *clk)
with
int __init nps_setup_clocksource(struct device_node *node)

This patch also serve as preparation for next patch which add support
for clockevents to nps400.
Specifically we add new function nps_get_timer_clk() to serve clocksource
and later clockevent registration.

Signed-off-by: Noam Camus <noa...@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezc...@linaro.org>
---
 drivers/clocksource/timer-nps.c |   65 +++---
 1 files changed, 39 insertions(+), 26 deletions(-)

diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 70c149a..0c8e21f 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -46,7 +46,35 @@
 /* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
 static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
 
-static unsigned long nps_timer_rate;
+static int __init nps_get_timer_clk(struct device_node *node,
+unsigned long *timer_freq,
+struct clk **clk)
+{
+   int ret;
+
+   *clk = of_clk_get(node, 0);
+   if (IS_ERR(*clk)) {
+   pr_err("timer missing clk");
+   return PTR_ERR(*clk);
+   }
+
+   ret = clk_prepare_enable(*clk);
+   if (ret) {
+   pr_err("Couldn't enable parent clk\n");
+   clk_put(*clk);
+   return ret;
+   }
+
+   *timer_freq = clk_get_rate(*clk);
+   if (!(*timer_freq)) {
+   pr_err("Couldn't get clk rate\n");
+   clk_disable_unprepare(*clk);
+   clk_put(*clk);
+   return -EINVAL;
+   }
+
+   return 0;
+}
 
 static cycle_t nps_clksrc_read(struct clocksource *clksrc)
 {
@@ -55,26 +83,24 @@ static cycle_t nps_clksrc_read(struct clocksource *clksrc)
return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
 }
 
-static int __init nps_setup_clocksource(struct device_node *node,
-   struct clk *clk)
+static int __init nps_setup_clocksource(struct device_node *node)
 {
int ret, cluster;
+   struct clk *clk;
+   unsigned long nps_timer1_freq;
+
 
for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
nps_msu_reg_low_addr[cluster] =
nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
-NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
 
-   ret = clk_prepare_enable(clk);
-   if (ret) {
-   pr_err("Couldn't enable parent clock\n");
+   ret = nps_get_timer_clk(node, _timer1_freq, );
+   if (ret)
return ret;
-   }
 
-   nps_timer_rate = clk_get_rate(clk);
-
-   ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
-   nps_timer_rate, 301, 32, nps_clksrc_read);
+   ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
+   nps_timer1_freq, 300, 32, nps_clksrc_read);
if (ret) {
pr_err("Couldn't register clock source.\n");
clk_disable_unprepare(clk);
@@ -83,18 +109,5 @@ static int __init nps_setup_clocksource(struct device_node 
*node,
return ret;
 }
 
-static int __init nps_timer_init(struct device_node *node)
-{
-   struct clk *clk;
-
-   clk = of_clk_get(node, 0);
-   if (IS_ERR(clk)) {
-   pr_err("Can't get timer clock.\n");
-   return PTR_ERR(clk);
-   }
-
-   return nps_setup_clocksource(node, clk);
-}
-
 CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
-  nps_timer_init);
+  nps_setup_clocksource);
-- 
1.7.1


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[RESEND PATCH v7 1/3] soc: Support for NPS HW scheduling

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.

Signed-off-by: Noam Camus <noa...@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezc...@linaro.org>
---
 arch/arc/plat-eznps/include/plat/ctop.h |2 -
 include/soc/nps/mtm.h   |   59 +++
 2 files changed, 59 insertions(+), 2 deletions(-)
 create mode 100644 include/soc/nps/mtm.h

diff --git a/arch/arc/plat-eznps/include/plat/ctop.h 
b/arch/arc/plat-eznps/include/plat/ctop.h
index 9d6718c..ee2e32d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,9 +46,7 @@
 #define CTOP_AUX_UDMC  (CTOP_AUX_BASE + 0x300)
 
 /* EZchip core instructions */
-#define CTOP_INST_HWSCHD_OFF_R30x3B6F00BF
 #define CTOP_INST_HWSCHD_OFF_R40x3C6F00BF
-#define CTOP_INST_HWSCHD_RESTORE_R30x3E6F70C3
 #define CTOP_INST_HWSCHD_RESTORE_R40x3E6F7103
 #define CTOP_INST_SCHD_RW  0x3E6F7004
 #define CTOP_INST_SCHD_RD  0x3E6F7084
diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h
new file mode 100644
index 000..d2f5e7e
--- /dev/null
+++ b/include/soc/nps/mtm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_MTM_H
+#define SOC_NPS_MTM_H
+
+#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
+#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
+
+static inline void hw_schd_save(unsigned int *flags)
+{
+   __asm__ __volatile__(
+   "   .word %1\n"
+   "   st r3,[%0]\n"
+   :
+   : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
+   : "r3", "memory");
+}
+
+static inline void hw_schd_restore(unsigned int flags)
+{
+   __asm__ __volatile__(
+   "   mov r3, %0\n"
+   "   .word %1\n"
+   :
+   : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
+   : "r3");
+}
+
+#endif /* SOC_NPS_MTM_H */
-- 
1.7.1


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RE: [PATCH v2] ARC: [plat-eznps] set default baud for early console

[Noam Camus]

> From: Alexey Brodkin [mailto:alexey.brod...@synopsys.com] 
> Sent: Tuesday, November 8, 2016 4:08 PM

>Could you please provide a changelog (v1 -> v2) so reviewers may have a hint 
>about changes you made if any.
... Just fix some typos in log
This line somehow was removed from patch while sending (It is at patch head 
followed by line with ---)
Basically in V1 I wrote that default value is good while I meant is NOT good 
(fixed in V2).

Thanks,
Noam
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[PATCH] ARC: [plat-eznps] remove IPI clear from SMP operations

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Generic IRQ mechanism is already acknowledge the IPI IRQ.
Doing this once more time in IPI handler is not needed.

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/plat-eznps/smp.c |6 --
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/arch/arc/plat-eznps/smp.c b/arch/arc/plat-eznps/smp.c
index 5e901f8..56a4c85 100644
--- a/arch/arc/plat-eznps/smp.c
+++ b/arch/arc/plat-eznps/smp.c
@@ -140,16 +140,10 @@ static void eznps_init_per_cpu(int cpu)
mtm_enable_core(cpu);
 }
 
-static void eznps_ipi_clear(int irq)
-{
-   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
-}
-
 struct plat_smp_ops plat_smp_ops = {
.info   = smp_cpuinfo_buf,
.init_early_smp = eznps_init_cpumasks,
.cpu_kick   = eznps_smp_wakeup_cpu,
.ipi_send   = eznps_ipi_send,
.init_per_cpu   = eznps_init_per_cpu,
-   .ipi_clear  = eznps_ipi_clear,
 };
-- 
1.7.1


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RE: [PATCH 5/9] ARC: breakout aux handling into a seperate header

[Noam Camus]

>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
>Sent: Tuesday, November 1, 2016 12:48 AM

>ARC timers use aux registers for programming and this paves way for moving ARC 
>timer drivers into drivers/clocksource

Maybe in this patch or just another one could you move from timer.c to the new 
soc header all timer related Aux registers definitions?
This could be used by timer-nps driver.
 
i.e.:
/* Timer related Aux registers */
#define ARC_REG_TIMER0_LIMIT0x23/* timer 0 limit */
#define ARC_REG_TIMER0_CTRL 0x22/* timer 0 control */
#define ARC_REG_TIMER0_CNT  0x21/* timer 0 count */
#define ARC_REG_TIMER1_LIMIT0x102   /* timer 1 limit */
#define ARC_REG_TIMER1_CTRL 0x101   /* timer 1 control */
#define ARC_REG_TIMER1_CNT  0x100   /* timer 1 count */

#define TIMER_CTRL_IE   (1 << 0) /* Interrupt when Count reaches limit */
#define TIMER_CTRL_NH   (1 << 1) /* Count only when CPU NOT halted */

#define ARC_TIMER_MAX   0x


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[PATCH v2] ARC: Adjust cpuinfo for non-continuous cpu ids

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

num_possible_cpus() returns how many CPUs may be present on system.
However we want the highest possible CPU number.
This may be differ in a sparsed possible CPUs map.
Such map achived by OF for plat-eznps.

For example if we have:
possible cpus mask 0,3

Then:
num_possible_cpus() is equal 2
while
nr_cpu_ids is equal 4.

Only for value 4 c_start() will provide correct cpuinfo at procfs.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/kernel/setup.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index 64907de..bd2e3a4 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -512,7 +512,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
 * way to pass it w/o having to kmalloc/free a 2 byte string.
 * Encode cpu-id as 0xFF, which is decoded by show routine.
 */
-   return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
+   return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 }
 
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-- 
1.7.1


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RE: [PATCH] ARC: Adjust cpuinfo for non-continuous cpu ids

[Noam Camus]

> From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
> Sent: Tuesday, October 18, 2016 8:49 PM

>>
>> num_possible_cpus() returns how many CPUs may be present on system.
>> However we want the highest possible CPU number.
>
>Highest possible number "Detected" at boot ? Can you explain a bit more !

While trying to provide explanation I decided to "rethink" on this patch.
Its effect is not visible to you due to another "local" patch I use which 
justify this patch.
I need to reconsider both patches (maybe I will even remove both of them).

Thanks for the feedback.
Noam 
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[PATCH] ARC: Adjust cpuinfo for non-continuous cpu ids

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

num_possible_cpus() returns how many CPUs may be present on system.
However we want the highest possible CPU number.
This may be differ in a sparsed possible CPUs map.

Signed-off-by: Noam Camus <no...@ezchip.com>
Acked-by: Vineet Gupta <vgu...@synopsys.com>
---
 arch/arc/kernel/setup.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index f52a0d0..d13ce84 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -506,7 +506,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
 * way to pass it w/o having to kmalloc/free a 2 byte string.
 * Encode cpu-id as 0xFF, which is decoded by show routine.
 */
-   return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
+   return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 }
 
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-- 
1.7.1


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[PATCH] ARC: CONFIG_NODES_SHIFT fix default values

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Seem like values assigned as absolute number and not and
shift value, i.e. should be 0 for one node (2^0) and 1 for
couple of nodes (2^1)

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/Kconfig |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 6af0b43..f347715 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -383,8 +383,8 @@ endchoice
 
 config NODES_SHIFT
int "Maximum NUMA Nodes (as a power of 2)"
-   default "1" if !DISCONTIGMEM
-   default "2" if DISCONTIGMEM
+   default "0" if !DISCONTIGMEM
+   default "1" if DISCONTIGMEM
depends on NEED_MULTIPLE_NODES
---help---
  Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
-- 
1.7.1


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[PATCH] ARC: [plat-eznps] add missing atomic_fetch_xxx operations

[Noam Camus]

From: Noam Camus <noa...@mellanox.com>

Build brekeage since last changes to generic atomic operations.
Added couple of missing macros which are now mandatory

Signed-off-by: Noam Camus <noa...@mellanox.com>
---
 arch/arc/include/asm/atomic.h |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index 4e3c1b6..4f732bf 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -284,6 +284,7 @@ static inline int atomic_fetch_##op(int i, atomic_t *v) 
\
 ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
 #define atomic_sub(i, v) atomic_add(-(i), (v))
 #define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
+#define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v))
 
 #undef ATOMIC_OPS
 #define ATOMIC_OPS(op, c_op, asm_op)   \
@@ -292,6 +293,7 @@ ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
 
 ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
 #define atomic_andnot(mask, v) atomic_and(~(mask), (v))
+#define atomic_fetch_andnot(mask, v) atomic_fetch_and(~(mask), (v))
 ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
 ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
 
-- 
1.7.1


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RE: Click source driver

[Noam Camus]

>From: Vineet Gupta [mailto:vineet.gup...@synopsys.com] 
>Sent: Tuesday, June 28, 2016 11:32 AM

>> I noticed that arc-timer driver appears twice in DTS file so first one 
>> will invoke initialization of clockevent and second the clocksource. 
>> Please note that both update same global variable arc_timer_freq and 
>> you can end up with different value from clocksource used by clockevent for 
>> secondaries CPUs.
>>

>Can you please elaborate this a bit more - where/how exactly is timer freq 
>different for NPS ?
In NPS chip the timer0 is shared among all HW threads from the same core.
There is also dedicated design for choosing which threads will get the timer 
interrupt when it arrives.
This is different from ARC700.
In simulator we use regular ARC700 cores without simulating this HW behavior so 
generic ARC driver is good for us when working with simulator.
See below link for patch I use and going to upstream:
https://github.com/Mellanox/linux/commit/94f1b4d7b28634ce579101aa79e9853566883536


>> So my updated driver will like today will use arc-timer clickevent for 
>> simulator and for real chip it will be used for both clocksource and 
>> clockevent.
>>

>Again I'm not sure if I understand this - why do u need to make this 
>distinctions for sim vs. real chip !
I hope above clarifying things

>> How do you suggest to achieve that?
>>
>> Using arc-timer technique of double nodes at DTS or just single node 
>> to init both of them
>>

>the current arc timer driver expects to be called twice - i.e. 2 DT nodes for 
>"snps,arc-timer" - for first it processes clockevent, for second it does 
>clocksource. If u instantiate it only once, only clockevent will be called.

>I'm sorry but I don't understand the issue here !

>From above link to my patch you can see that I choose to have 2 separate 
>"compatiable" implementations one for timer0 and another for timer1. This way 
>I can separate the origin clock each one uses.
In your case (I believe so) the order of " snps,arc-timer" at DTS files is 
important and since for both you call arc_get_timer_clk() which in turn update 
same global variable called arc_timer_freq.
So if in your DTS file each node got different clocks=, then second 
node will override this value set by first node.

-Noam

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RE: [PATCH V2 63/63] clocksources: Switch back to the clksrc table

[Noam Camus]

>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] 
>Sent: Friday, June 17, 2016 12:27 AM

>All the clocksource drivers's init function are now converted to return an 
>error code. CLOCKSOURCE_OF_DECLARE is no longer used as well as the clksrc-of 
>table.

>Let's convert back the names:
> - CLOCKSOURCE_OF_DECLARE_RET => CLOCKSOURCE_OF_DECLARE
> - clksrc-of-ret  => clksrc-of

> Signed-off-by: Daniel Lezcano <daniel.lezc...@linaro.org>
> ---
> arch/arc/kernel/time.c|  6 +++---
> arch/arm/kernel/smp_twd.c |  6 +++---
> arch/microblaze/kernel/timer.c|  2 +-
> arch/mips/ralink/cevt-rt3352.c|  2 +-
> arch/nios2/kernel/time.c  |  2 +-
> drivers/clocksource/arm_arch_timer.c  |  6 +++---
> drivers/clocksource/arm_global_timer.c|  2 +-
> drivers/clocksource/armv7m_systick.c  |  2 +-
> drivers/clocksource/asm9260_timer.c   |  2 +-
> drivers/clocksource/bcm2835_timer.c   |  2 +-
> drivers/clocksource/bcm_kona_timer.c  |  4 ++--
> drivers/clocksource/cadence_ttc_timer.c   |  2 +-
> drivers/clocksource/clksrc-dbx500-prcmu.c |  2 +-
> drivers/clocksource/clksrc-probe.c| 14 --
> drivers/clocksource/clksrc_st_lpc.c   |  2 +-
> drivers/clocksource/clps711x-timer.c  |  2 +-
> drivers/clocksource/dw_apb_timer_of.c |  8 
> drivers/clocksource/exynos_mct.c  |  4 ++--
> drivers/clocksource/fsl_ftm_timer.c   |  2 +-
> drivers/clocksource/h8300_timer16.c   |  2 +-
> drivers/clocksource/h8300_timer8.c|  2 +-
> drivers/clocksource/h8300_tpu.c   |  2 +-
> drivers/clocksource/meson6_timer.c|  2 +-
> drivers/clocksource/mips-gic-timer.c  |  2 +-
> drivers/clocksource/moxart_timer.c|  2 +-
> drivers/clocksource/mps2-timer.c  |  2 +-
> drivers/clocksource/mtk_timer.c   |  2 +-
> drivers/clocksource/mxs_timer.c   |  2 +-
> drivers/clocksource/nomadik-mtu.c |  2 +-
> drivers/clocksource/pxa_timer.c   |  2 +-
> drivers/clocksource/qcom-timer.c  |  4 ++--
> drivers/clocksource/rockchip_timer.c  |  8 
> drivers/clocksource/samsung_pwm_timer.c   |  8 
> drivers/clocksource/sun4i_timer.c |  2 +-
> drivers/clocksource/tango_xtal.c  |  2 +-
> drivers/clocksource/tegra20_timer.c   |  4 ++--
> drivers/clocksource/time-armada-370-xp.c  |  6 +++---
> drivers/clocksource/time-efm32.c  |  4 ++--
> drivers/clocksource/time-lpc32xx.c|  2 +-
> drivers/clocksource/time-orion.c  |  2 +-
> drivers/clocksource/time-pistachio.c  |  2 +-
> drivers/clocksource/timer-atlas7.c|  2 +-
> drivers/clocksource/timer-atmel-pit.c |  2 +-
> drivers/clocksource/timer-atmel-st.c  |  2 +-
> drivers/clocksource/timer-digicolor.c |  2 +-
> drivers/clocksource/timer-imx-gpt.c   | 24 
> drivers/clocksource/timer-integrator-ap.c |  2 +-
> drivers/clocksource/timer-keystone.c  |  2 +-
> drivers/clocksource/timer-nps.c   |  4 ++--
> drivers/clocksource/timer-oxnas-rps.c |  4 ++--
> drivers/clocksource/timer-prima2.c|  2 +-
> drivers/clocksource/timer-sp804.c |  4 ++--
> drivers/clocksource/timer-stm32.c |  2 +-
> drivers/clocksource/timer-sun5i.c |  4 ++--
> drivers/clocksource/timer-ti-32k.c|  2 +-
> drivers/clocksource/timer-u300.c  |  2 +-
> drivers/clocksource/versatile.c   |  4 ++--
> drivers/clocksource/vf_pit_timer.c|  2 +-
> drivers/clocksource/vt8500_timer.c|  2 +-
> drivers/clocksource/zevio-timer.c |  2 +-
> include/asm-generic/vmlinux.lds.h |  2 --
> include/linux/clocksource.h   |  5 +
> 62 files changed, 98 insertions(+), 117 deletions(-)

[..]

> diff --git a/drivers/clocksource/timer-nps.c 
> b/drivers/clocksource/timer-nps.c index b5c7b2b..70c149a 100644
> --- a/drivers/clocksource/timer-nps.c
> +++ b/drivers/clocksource/timer-nps.c
> @@ -96,5 +96,5 @@ static int __init nps_timer_init(struct device_node *node)
>   return nps_setup_clocksource(node, clk);  }
 
> -CLOCKSOURCE_OF_DECLARE_RET(ezchip_nps400_clksrc, "ezchip,nps400-timer",
> -nps_timer_init);
> +CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
> +nps_timer_init);
> diff --git a/drivers/clocksource/timer-oxnas-rps.c 
> b/drivers/clocksource/timer-oxnas-rps.c
> index 0d99f40..bd887e2 100644
> --- a/drivers/clocksource/timer-oxnas-rps.c
> +++ b/drivers/clocksource/timer-oxnas-rps.c
> @@ -293,5 +293,5 @@ err_alloc:
>   return ret;
> }
 

Acked-by: Noam Camus <noa...@mellanox.com>

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Re: [PATCH v8 3/3] irqchip: add nps Internal and external irqchips

[Noam Camus]

Hi Marc,

Could you review this patch, this is last one of this set which needs ack.
This patch set is out there long time and I will appreciate any feedback.

Regards,
Noam

From: linux-snps-arc <linux-snps-arc-boun...@lists.infradead.org> on behalf of 
Noam Camus <noa...@mellanox.com>
Sent: Sunday, April 3, 2016 9:14 PM
To: daniel.lezc...@linaro.org; marc.zyng...@arm.com; ja...@lakedaemon.net
Cc: Thomas Gleixner; linux-snps-arc@lists.infradead.org; Noam Camus; 
linux-ker...@vger.kernel.org
Subject: [PATCH v8 3/3] irqchip: add nps Internal and external irqchips

From: Noam Camus <no...@ezchip.com>

Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
---
v8:
Change macro name from IPI_IRQ to NPS_IPI_IRQ.
This was needed due to build warning when building for parsic.

v7:
Rebased on latest HEAD (4.6-rc1)

v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...

This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.

This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.

v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 ++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  165 
 4 files changed, 189 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3e12479..1ab632a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -244,3 +244,9 @@ config IRQ_MXS
 config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+

[PATCH v7 2/3] clocksource: Add NPS400 timers driver

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
Cc: Rob Herring <robh...@kernel.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: John Stultz <john.stu...@linaro.org>
Cc: Vineet Gupta <vgu...@synopsys.com>
---
v7:
Rebased on latest HEAD (4.6-rc1)

v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...

This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.

This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.

v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 +++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   98 
 4 files changed, 124 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c346be6..3932d09 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -181,6 +181,16 @@ config CLKSRC_TI_32K
  This option enables support for Texas Instruments 32.768 Hz 
clocksource
  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+   bool "NPS400 clocksource driver" if COMPILE_TEST
+   depends on !PHYS_ADDR_T_64BIT
+   select CLKSRC_MMIO
+   select CLKSRC_OF if OF
+   help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
 config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index dc2b899..0b0a4b5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 
 obj-$(CONFIG_ARM_

[PATCH v7 3/3] irqchip: add nps Internal and external irqchips

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
---
v7:
Rebased on latest HEAD (4.6-rc1)

v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...

This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.

This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.

v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 ++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  165 
 4 files changed, 189 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 3e12479..1ab632a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -244,3 +244,9 @@ config IRQ_MXS
 config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b03cfcb..9d54d53 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -65,3 +65,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
 obj-$(CONFIG_PIC32_EVIC)   += irq-pic32-evic.o
 obj-$(CONFIG_MVEBU_ODMI)   += irq-mvebu-odmi.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..97e4294
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 20

[PATCH v7 1/3] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
Cc: Vineet Gupta <vgu...@synopsys.com>
---
v7:
Rebased on latest HEAD (4.6-rc1)

v6:
Files headers changed to start with:
Copyright (c) 2016, Mellanox Technologies
...

This is due to the acquisition of EZchip made by Mellanox.
One can still find "EZchip" used in tree, and this is ok.

This patch set is a requierement before I can insert new platform to ARC,
one that supports the NPS400 SoC.

v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus
---
 include/soc/nps/common.h |  166 ++
 1 files changed, 166 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..e959176
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic

[PATCH v6 1/3] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 include/soc/nps/common.h |  166 ++
 1 files changed, 166 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..e959176
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blk

RE: Interesting csd deadlock on ARC

[Noam Camus]

>From: Peter Zijlstra [mailto:pet...@infradead.org] 
>Sent: Tuesday, February 23, 2016 12:40 PM

>The only requirement for irq_work is that it runs after the NMI completes and 
>runs from regular IRQ context. >There are no strict interrupt priority 
>requirements, only that it happens.

We here already use self IPI and irq_work on ARC (with no NMI concerns).
Please see patch at:
https://github.com/EZchip/linux/commit/e42556738e610295f917c79dae166373cd11de88

Noam

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Re: [PATCH v5 3/3] irqchip: add nps Internal and external irqchips

[Noam Camus]

Hi Jason,

The patch set got change log, see cover letter that summarize all changes with 
respect to whole set.
https://lkml.org/lkml/2016/2/11/609

Let me know if it works for you.

Noam


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RE: [PATCH v5 0/3] Adding NPS400 drivers

[Noam Camus]

Waiting for your feedback on my v5 patch set :)

-Original Message-
From: Noam Camus 
Sent: Thursday, February 11, 2016 8:41 PM
To: linux-ker...@vger.kernel.org
Cc: linux-snps-arc@lists.infradead.org; daniel.lezc...@linaro.org; 
marc.zyng...@arm.com; Chris Metcalf; Tal Zilcer; Gilad Ben Yossef; Noam Camus
Subject: [PATCH v5 0/3] Adding NPS400 drivers

From: Noam Camus <no...@ezchip.com>

Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h 
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC uses 
irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   82 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  149 +++
 include/soc/nps/common.h   |  150 
 9 files changed, 431 insertions(+), 0 deletions(-)  create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c  create mode 100644 
drivers/irqchip/irq-eznps.c  create mode 100644 include/soc/nps/common.h


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[PATCH v5 0/3] Adding NPS400 drivers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Change Log--
v5:
Clocksource, irqchip - Fix gracefull return.
replace call to panic() with pr_err() and 
proper return value.

v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver at init

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   82 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  149 +++
 include/soc/nps/common.h   |  150 
 9 files changed, 431 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c
 create mode 100644 include/soc/nps/common.h


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[PATCH v5 1/3] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 include/soc/nps/common.h |  150 ++
 1 files changed, 150 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* S

RE: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

[Noam Camus]

>From: Daniel Lezcano [mailto:daniel.lezc...@linaro.org] 
>Sent: Wednesday, February 10, 2016 12:55 AM

>> pr_err() in case of error just like most drivers around. By "hang" do 
>> you mean calling panic()?

>No. I meant the errors are caught but no action is taken, the execution 
>continues normally as nothing wrong happened. This is why I asked if you 
>expect the host to hang at boot time with the last error as a hint.

>I was expecting to see a call to clk_disable_unprepare if 
>clocksource_register_hz fails, and returning 'ret' if clk_prepare_enable fails.
Ok, I will fix that, and handle gracefull return. Thanks


>Using the mmio generic code will save:

>+static struct clocksource nps_counter = {
>+  .name   = "EZnps-tick",
>+  .rating = 301,
>+  .read   = nps_clksrc_read,
>+  .mask   = CLOCKSOURCE_MASK(32),
>+  .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
>+};

>Up to you.
I will do that, thanks again

Noam

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[PATCH v4 3/3] irqchip: add nps Internal and external irqchips

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  145 
 4 files changed, 169 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..acc55a3
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_NR_CPU_IRQS 8  /* number of interrupt lines of NPS400 CPU */
+#define NPS_TIMER0_IRQ  3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb &= ~(1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb |= (1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+   /* Don't ack GIC before all device access attempts are done */
+   mb();
+
+   nps_ack_gic();
+}
+
+static void nps

[PATCH v4 2/3] clocksource: Add NPS400 timers driver

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
Cc: Rob Herring <robh...@kernel.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: John Stultz <john.stu...@linaro.org>
Acked-by: Vineet Gupta <vgu...@synopsys.com>
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 
 drivers/clocksource/Kconfig|   10 +++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   80 
 4 files changed, 106 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..fa7be50 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,16 @@ config CLKSRC_TI_32K
  This option enables support for Texas Instruments 32.768 Hz 
clocksource
  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+   bool "NPS400 clocksource driver" if COMPILE_TEST
+   depends on !PHYS_ADDR_T_64BIT
+   select CLKSRC_MMIO
+   select CLKSRC_OF if OF
+   help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+ This counter is accessed via couple of 32 bit memory mapped registers.
+
 config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..5a15970
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_MSU_TICK_LOW   0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+   int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+   return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static void __init nps_setup_clocksource(struct device_node *node,
+struct clk *clk)
+{
+   int ret, cluster;
+
+   for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+   nps_msu_reg_low_addr[cluster] =
+   nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
+
+   ret = clk_prepare_enable(clk);
+   if (ret) {
+   

[PATCH v4 1/3] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 include/soc/nps/common.h |  150 ++
 1 files changed, 150 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* S

[PATCH v4 0/3] Adding NPS400 drivers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Change Log--
v4:
clocksource -- Apply all Daniel comments (Thanks)
Handle gracefull return and also using 
clocksoure mmio driver

v3:
irqchip - Fix ARM build failure by adding missing include of linux/irq.h
clocksource -- Avoid 64bit arch's to build driver by adding new dependency 
!PHYS_ADDR_T_64BIT
This is since we use explicit io access of 32 
bit. So for test coverage we allow
not only build for ARC, but restrict it to 32 
bit arch's.
irqchip - Apply all Thomas comments (Thank you)

v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|   10 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   80 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  145 +++
 include/soc/nps/common.h   |  150 
 9 files changed, 425 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c
 create mode 100644 include/soc/nps/common.h


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Re: [PATCH v3 2/3] clocksource: Add NPS400 timers driver

[Noam Camus]

>From: Daniel Lezcano 
>Sent: Tuesday, February 9, 2016 3:38 PM

>Actually I was referring to clk_prepare_enable, clocksource_register_hz.
>Agree clk_get_rate is always valid.
Thanks for making this clear.
Any way as you can see I do call pr_err() in case of error just like most 
drivers around.
By "hang" do you mean calling panic()?
What if there is another clocksource in DT (even with worse rating)?
I still prefer using it then having non workable machine.

>>
>>> You can simplify the driver even more by using
>>> clocksource_mmio_init.
>> Since my base address depends on cluster number, which CPU is part
>> of,  this interface is not much of a use. On top of that it assumes
>> that I am little endian by using readl family accessories.

>Why can't you use ?

>clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
>nps_timer_rate, 32, nps_clksrc_read);

I believe that the simplification is meant for drivers that can actually use 
the clocksource_mmio..() accessories. Could you explain what is the advantage 
here, for my case, to use clocksource_mmio driver?

Thanks for your patience
-Noam


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[PATCH v3 1/3] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 include/soc/nps/common.h |  150 ++
 1 files changed, 150 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..35ebb00
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#ifdef CONFIG_SMP
+#define IPI_IRQ5
+#endif
+
+#define NPS_HOST_REG_BASE  0xF600
+
+#define NPS_MSU_BLKID  0x018
+
+#define CTOP_INST_RSPI_GIC_0_R12   0x3C56117E
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+
+/* In order to increase compilation test coverage */
+#ifdef CONFIG_ARC
+static inline void nps_ack_gic(void)
+{
+   __asm__ __volatile__ (
+   "   .word %0\n"
+   :
+   : "i"(CTOP_INST_RSPI_GIC_0_R12)
+   : "memory");
+}
+#else
+static inline void nps_ack_gic(void) { }
+#define write_aux_reg(r, v)
+#define read_aux_reg(r) 0
+#endif
+
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+#ifdef __arc__
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+#endif
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* S

[PATCH v2 3/3] irqchip: add nps Internal and external irqchips

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  151 
 4 files changed, 175 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..ac29f32
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#undef NR_CPU_IRQS
+#define NR_CPU_IRQS8  /* number of interrupt lines of NPS400 CPU */
+#define TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb &= ~(1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb |= (1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+   /* Don't ack before all device access attempts are done */
+   mb();
+
+#ifdef __arc__
+   _

[PATCH v2 0/3] Adding NPS400 drivers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Change Log--
v2:
Add header file include/soc/nps/common.h.
Now to build we do not depend on ARC subtree.

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (3):
  soc: Support for EZchip SoC
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|7 +
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   84 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  151 
 include/soc/nps/common.h   |  140 ++
 9 files changed, 422 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c
 create mode 100644 include/soc/nps/common.h


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[PATCH 2/2] irqchip: add nps Internal and external irqchips

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Jason Cooper <ja...@lakedaemon.net>
Cc: Marc Zyngier <marc.zyng...@arm.com>
---
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  151 
 4 files changed, 175 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 drivers/irqchip/irq-eznps.c

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
new file mode 100644
index 000..888b2b9
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
@@ -0,0 +1,17 @@
+EZchip NPS Interrupt Controller
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-ic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value shall be 1.
+
+
+Example:
+
+intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+};
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4d7294e..bc5e775 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -193,3 +193,9 @@ config IRQ_MXS
def_bool y if MACH_ASM9260 || ARCH_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+
+config EZNPS_GIC
+   bool "NPS400 Global Interrupt Manager (GIM)"
+   select IRQ_DOMAIN
+   help
+ Support the EZchip NPS400 global interrupt controller
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 177f78f..1390142 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)+= 
irq-renesas-h8s.o
 obj-$(CONFIG_ARCH_SA1100)  += irq-sa11x0.o
 obj-$(CONFIG_INGENIC_IRQ)  += irq-ingenic.o
 obj-$(CONFIG_IMX_GPCV2)+= irq-imx-gpcv2.o
+obj-$(CONFIG_EZNPS_GIC)+= irq-eznps.o
diff --git a/drivers/irqchip/irq-eznps.c b/drivers/irqchip/irq-eznps.c
new file mode 100644
index 000..8401780
--- /dev/null
+++ b/drivers/irqchip/irq-eznps.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#undef NR_CPU_IRQS
+#define NR_CPU_IRQS8  /* number of interrupt lines of NPS400 CPU */
+#define TIMER0_IRQ 3
+
+/*
+ * NPS400 core includes an Interrupt Controller (IC) support.
+ * All cores can deactivate level irqs at first level control
+ * at cores mesh layer called MTM.
+ * For devices out side chip e.g. uart, network there is another
+ * level called Global Interrupt Manager (GIM).
+ * This second level can control level and edge interrupt.
+ *
+ * NOTE: AUX_IENABLE and CTOP_AUX_IACK are auxiliary registers
+ * with private HW copy per CPU.
+ */
+
+static void nps400_irq_mask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb &= ~(1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_unmask(struct irq_data *irqd)
+{
+   unsigned int ienb;
+   unsigned int irq = irqd_to_hwirq(irqd);
+
+   ienb = read_aux_reg(AUX_IENABLE);
+   ienb |= (1 << irq);
+   write_aux_reg(AUX_IENABLE, ienb);
+}
+
+static void nps400_irq_eoi_global(struct irq_data *irqd)
+{
+   unsigned int __maybe_unused irq = irqd_to_hwirq(irqd);
+
+   write_aux_reg(CTOP_AUX_IACK, 1 << irq);
+
+   /* Don't ack before all device access attempts are done */
+   mb();
+
+#ifdef __arc__
+   _

[PATCH 1/2] clocksource: Add NPS400 timers driver

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.

Signed-off-by: Noam Camus <no...@ezchip.com>
Cc: Daniel Lezcano <daniel.lezc...@linaro.org>
Cc: Rob Herring <robh...@kernel.org>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: John Stultz <john.stu...@linaro.org>
---
 .../bindings/timer/ezchip,nps400-timer.txt |   15 
 drivers/clocksource/Kconfig|7 ++
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   84 
 4 files changed, 107 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c

diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt 
b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
new file mode 100644
index 000..c8c03d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer"
+
+Clocks required for compatible = "ezchip,nps400-timer":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <>;
+};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2eb5f0e..859e83d 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -132,6 +132,13 @@ config CLKSRC_TI_32K
  This option enables support for Texas Instruments 32.768 Hz 
clocksource
  available on many OMAP-like platforms.
 
+config CLKSRC_NPS
+   bool "NPS400 clocksource driver" if COMPILE_TEST
+   select CLKSRC_OF if OF
+   help
+ NPS400 clocksource support.
+ Got 64 bit counter with update rate up to 1000MHz.
+
 config CLKSRC_STM32
bool "Clocksource for STM32 SoCs" if !ARCH_STM32
depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 56bd16e..056cffd 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
 obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
 obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
 obj-$(CONFIG_CLKSRC_TI_32K)+= timer-ti-32k.o
+obj-$(CONFIG_CLKSRC_NPS)   += timer-nps.o
 
 obj-$(CONFIG_ARM_ARCH_TIMER)   += arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
new file mode 100644
index 000..bf9a490
--- /dev/null
+++ b/drivers/clocksource/timer-nps.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define NPS_MSU_TICK_LOW   0xC8
+#define NPS_CLUSTER_OFFSET 8
+#define NPS_CLUSTER_NUM16
+
+/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
+static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
+
+static unsigned long nps_timer_rate;
+
+static cycle_t nps_clksrc_read(struct clocksource *clksrc)
+{
+   int cluster = raw_smp_processor_id() >> NPS_CLUSTER_OFFSET;
+
+   return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
+}
+
+static struct clocksource nps_counter = {
+   .name   = "EZnps-tick",
+   .rating = 301,
+   .read   = nps_clksrc_read,
+   .mask   = CLOCKSOURCE_MASK(32),
+   .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __init nps_setup_clocksource(struct device_node *node,
+struct clk *clk)
+{
+   struct clocksource *clksrc = _counter;
+   int ret, cluster;
+
+   for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
+   nps_msu_reg_low_addr[cluster] =
+   nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
+NPS

[PATCH 0/2] Adding NPS400 drivers

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

General summay:
Both drivers are now apart of previous basic patch set of new platform for ARC.
The rest is now can be seen at ARC srctree:
https://git.kernel.org/cgit/linux/kernel/git/vgupta/arc.git/

Now ARC is supporting DT for clockevents and the interrupt controller ARC
uses irq domain handling.

Compare to last version now clocksource driver do not include clockevent 
registration
since NPS400 can use ARC generic driver.

Compare to last version now irqchip driver sets domain as default since it is 
the root domain.
Also mapping of IPI is done in this driver.

Last thing is that drivers can be build cleanly for i386 (still runs only for 
ARC)
Note: in order to build we need to merge drivers into srctree which includes 
new header:
soc/nps/common.h
This header is part of patch set applied to ARC srctree.

Regards,
Noam Camus

Noam Camus (2):
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips

 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 +++
 .../bindings/timer/ezchip,nps400-timer.txt |   15 ++
 drivers/clocksource/Kconfig|7 +
 drivers/clocksource/Makefile   |1 +
 drivers/clocksource/timer-nps.c|   84 +++
 drivers/irqchip/Kconfig|6 +
 drivers/irqchip/Makefile   |1 +
 drivers/irqchip/irq-eznps.c|  151 
 8 files changed, 282 insertions(+), 0 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/ezchip,nps400-ic.txt
 create mode 100644 
Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
 create mode 100644 drivers/clocksource/timer-nps.c
 create mode 100644 drivers/irqchip/irq-eznps.c


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Re: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips

[Noam Camus]

Hi Marc,

Please respond to Vineet last email.
I wish to close the IPI handling within my patch set.

Regards,
Noam

From: Vineet Gupta <vineet.gup...@synopsys.com>
Sent: Monday, January 25, 2016 3:08:34 PM
To: Marc Zyngier; Noam Camus; linux-snps-arc@lists.infradead.org
Cc: linux-ker...@vger.kernel.org; Chris Metcalf; daniel.lezc...@linaro.org; 
Thomas Gleixner; Jason Cooper
Subject: Re: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips

Hi Marc,

On Friday 18 December 2015 10:01 PM, Marc Zyngier wrote:
> On 18/12/15 14:29, Noam Camus wrote:
>>> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
>>> Sent: Friday, December 18, 2015 1:21 PM
>>
>>>> I need this for my per CPU irqs such timer and IPI which do not come
>>>> from some external device but from CPUs. For these IRQs I am calling
>>>> to irq_create_mapping() from my platform at arch/arc and at that point
>>>> I got no irqdomain and using irq_find_host() is not good since I got
>>>> no device_node (at most I can have DT root).
>>
>>> That's a problem. You should never do that for your timer (doing a 
>>> request_irq will do the right thing, and that's what your timer driver 
>>> already does).
>>
>> Please be more specific, from all that I wrote what is the problem?
>
> Calling irq_create_mapping out of the blue like you do it here:
>
> +static void eznps_init_per_cpu(int cpu)
> +{
> + /* Create mapping for all per cpu IRQs */
> + if (cpu == 0) {
> + irq_create_mapping(NULL, TIMER0_IRQ);
> + irq_create_mapping(NULL, IPI_IRQ);
> + }
>
> is simply not acceptable.

I understand but... see below

>>> As for initializing your IPIs, they are usually outside of the IRQ
>>> space, so you should handle them separately (and get your irqchip
>>> to initialize them).
>> I am handling all my IRQs within same irqchip, which is the only one
>> I have. So I am not sure what you expect here. Please be more
>> elaborate.
>
> Do not create a mapping for IPIs. Full stop. Handle them independently
> from your normal IRQs.

why not ? IPI is a hardware construct afterall.

Anyhow I looked in arch/arm and do_IPI/handle_IPI are the handlers. do_IPI is
called from asm, irq-gic.c calls handle_IPI. I can't seem to find an explicit
request_irq / request_percpu_irq for IPI irq ?

...

>> Note that I am working with ARC (seem alike) here and we do not
>> define CONFIG_HANDLE_DOMAIN_IRQ and do not implement
>> set_handle_irq().
>>
>> So for ARC this reverse mapping is something we can leave without
>> (maybe because we are kind of a legacy domain).
>
> Yeah, I just located the crap: arch_do_IRQ() happily takes a hwirq (the
> vector number), and uses that as a Linux IRQ. This looks a lot like ARM
> pre-DT, about 10 years ago.
>
> Well, time to meet the 21st century. If you intend to use DT, please fix
> your arch port. Otherwise, just hardcode everything in your platform and
> don't pretend to support device tree.

Following works for me, hopefully it is closer to 21st century code :-)

--->
>From 619eb5179d865140a723dd524d0e42fbf234b53b Mon Sep 17 00:00:00 2001
From: Vineet Gupta <vgu...@synopsys.com>
Date: Fri, 1 Jan 2016 15:12:54 +0530
Subject: [PATCH] ARC: [intc-*] Do a domain lookup in primary handler for hwirq
 -> linux virq

The primary interrupt handler arch_do_IRQ() was passing hwirq as linux
virq to core code. This was fragile and worked so far as we only had 
legacy/linear
domains.

This came out of a rant by Marc Zyngier.
http://lists.infradead.org/pipermail/linux-snps-arc/2015-December/000298.html

Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Thomas Gleixner <t...@linutronix.de>
Cc: Noam Camus <no...@ezchip.com>
Signed-off-by: Vineet Gupta <vgu...@synopsys.com>
---
 arch/arc/Kconfig   |  1 +
 arch/arc/kernel/intc-arcv2.c   |  9 ++---
 arch/arc/kernel/intc-compact.c | 10 ++
 arch/arc/kernel/irq.c  |  9 ++---
 4 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 6312f607932f..576f1c40ba75 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -31,6 +31,7 @@ config ARC
select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
select HAVE_OPROFILE
select HAVE_PERF_EVENTS
+   select HANDLE_DOMAIN_IRQ
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA
select NO_BOOTMEM
diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c
index 0394f9f61b46..cede73b50d31 100644
--- a/arch/arc/kernel/intc-arcv2.c
+++ b/arch/arc/kernel/intc-arcv2.c
@@ -130,21 +130,24 @@ static const struct irq_domain_ops arcv2_irq_ops = {
 

Re: [PATCH v5 10/20] ARC: IRQ: do not use hwirq directly at arch_do_IRQ()

[Noam Camus]

>From: Vineet Gupta 
>Sent: Wednesday, December 30, 2015 12:10 PM

>> --- a/arch/arc/Kconfig
>> +++ b/arch/arc/Kconfig
>> @@ -32,6 +32,7 @@ config ARC
>>   select HAVE_OPROFILE
>>   select HAVE_PERF_EVENTS
>>   select IRQ_DOMAIN
>> + select HANDLE_DOMAIN_IRQ if ARC_PLAT_EZNPS

>On same lines as prev comment - just do this unconditionally for ARC port -
assuming this works with legacy domain as well.

Yes it should work for legacy domain.
On the other hand I can select it at the driver Kconfig itself and remove this 
line altogether.


>>
>> +#ifdef CONFIG_HANDLE_DOMAIN_IRQ
>> +extern void set_handle_irq(void (*handle_irq)(unsigned int hwirq,
>> +   struct pt_regs *));
>> +#endif

>Not needed !

I need to have it since we do not know at arch/arc/kernel/irq.c what is the 
domain allocated by the timer driver


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[PATCH v5 20/20] ARC: Add eznps platform to Kconfig and Makefile

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This commit should be left last since only now eznps platform
is in state which one can actually use.
Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/Kconfig  |1 +
 arch/arc/Makefile |5 +
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 079946e..9d828a3 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -92,6 +92,7 @@ source "arch/arc/plat-sim/Kconfig"
 source "arch/arc/plat-tb10x/Kconfig"
 source "arch/arc/plat-axs10x/Kconfig"
 #New platform adds here
+source "arch/arc/plat-eznps/Kconfig"
 
 endmenu
 
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index aeb1902..6212fea 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -99,6 +99,11 @@ core-y   += arch/arc/boot/dts/
 core-$(CONFIG_ARC_PLAT_SIM)+= arch/arc/plat-sim/
 core-$(CONFIG_ARC_PLAT_TB10X)  += arch/arc/plat-tb10x/
 core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/
+core-$(CONFIG_ARC_PLAT_EZNPS)  += arch/arc/plat-eznps/
+
+ifdef CONFIG_ARC_PLAT_EZNPS
+KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include
+endif
 
 drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/
 
-- 
1.7.1


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Re: [PATCH v5 04/20] clocksource: Add NPS400 timers driver

[Noam Camus]

>From: kbuild test robot <l...@intel.com>
>Sent: Sunday, December 27, 2015 4:55 PM

>[if your patch is applied to the wrong git tree, please drop us a note to help 
>improving the system]
>Hi Noam,

>[auto build test ERROR on arc/for-next]
>[also build test ERROR on v4.4-rc6 next-20151223]

>url:
>https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-plat-eznps-to-ARC/20151227-220433
>base:   https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
>config: i386-allmodconfig (attached as .config)
>reproduce:
>   # save the attached .config to linux build tree
>  make ARCH=i386

This is meant for ARC only (not i386), I will add to the Kconfig file a 
dependency on my platform. 

-Noam
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[PATCH v5 00/20] Adding plat-eznps to ARC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

v5:
1) irqchip -- work with handle_domain_irq(), and remove use of 
irq_set_default_host()
2) clocksource -- initialize clockevents as well by parsing interrupts node of 
DT
3) Do not use IPI with irq generic infrastructure

v4:
1) irqchip -- use irq_domain_add_linear()
2) clocksource -- use of_clk_get()
3) New header at include/soc use by platform and drivers
4) update DTS file for above fixed drivers

v3:
1)  irqchip: use MACROS instead of structures to decribe
registers.
2)  clocksource: use 32bit counter and avoid 2 halfs read
of 64bit dance.

v2:
1)  Remove out of tree platform include path
2)  Move atomic/bitop/cmpxchg for platform to end.
Remove macro duplication.
Fix some bad implementation.
3)  define cpu_relax_lowlatency() for platform.
4)  rename init_irq_cpu() to init_per_cpu()
reorder call to init_per_cpu() for secondary
use it instead of init_cpu_smp().
5)  set res_service to call stext
6)  fix build failure for CTOP_AUX_BASE at assembly code
7)  Use ilog2 for mtm_init_nat()
8)  Add CLKSRC_NPS option to Kconfig
change nps_clksrc_read() to be more readable.

General summay:
This set introduce new platform to ARC architecture.
Platform name called "eznps" for working with EZchip NPS400
Network Proccessor.
NPS400 is targeted to service "fast path" network applications.

NPS400 got mesh of 256 extended ARC cores (AKA CTOP), each core
got 16 HW threads. This is basically SMT core where at any point of
time only one HW thread is active.
Each core have HW scheduler that round robin between eligible HW
threads. Totaly, kernel sees 4096 CPUs which I belive is a high record.
There is no cache coherency between cores so generic user applications
and kernel do not use D$.

Cores got special memory mappings for huge pages (8MB).
Mapping is static and should provide application enough memory without
any "TLB miss". This mapping is on top of TLB mapping.

This is a basic set that will later be followed with additional
set of patches with all advanced features.

Many thanks to all people helping to make this happen.

Regards,
Noam Camus

Noam Camus (19):
  Documentation: Add EZchip vendor to binding list
  soc: Support for EZchip SoC
  ARC: [plat-eznps] define IPI_IRQ
  clocksource: Add NPS400 timers driver
  irqchip: add nps Internal and external irqchips
  ARC: Set vmalloc size from configuration
  ARC: rwlock: disable interrupts in !LLSC variant
  ARC: Mark secondary cpu online only after all HW setup is done
  ARC: IRQ: use device tree to get timer device configuration
  ARC: IRQ: do not use hwirq directly at arch_do_IRQ()
  ARC: IPI: do not use generic IRQ domain
  ARC: [plat-eznps] Add eznps board defconfig and dts
  ARC: [plat-eznps] Add eznps platform
  ARC: [plat-eznps] Use dedicated user stack top
  ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg
  ARC: [plat-eznps] Use dedicated SMP barriers
  ARC: [plat-eznps] Use dedicated identity auxiliary register.
  ARC: [plat-eznps] Use dedicated COMMAND_LINE_SIZE
  ARC: Add eznps platform to Kconfig and Makefile

Tal Zilcer (1):
  ARC: [plat-eznps] Use dedicated cpu_relax()

 Documentation/devicetree/bindings/arc/eznps.txt|7 +
 .../interrupt-controller/ezchip,nps400-ic.txt  |   17 ++
 .../bindings/timer/ezchip,nps400-timer.txt |   17 ++
 .../devicetree/bindings/vendor-prefixes.txt|1 +
 MAINTAINERS|6 +
 arch/arc/Kconfig   |   10 +
 arch/arc/Makefile  |5 +
 arch/arc/boot/dts/eznps.dts|   94 +
 arch/arc/configs/nps_defconfig |   85 +
 arch/arc/include/asm/Kbuild|1 -
 arch/arc/include/asm/atomic.h  |   79 -
 arch/arc/include/asm/barrier.h |8 +
 arch/arc/include/asm/bitops.h  |   54 ++
 arch/arc/include/asm/cmpxchg.h |   87 +++--
 arch/arc/include/asm/entry-compact.h   |8 +
 arch/arc/include/asm/hardirq.h |   22 +++
 arch/arc/include/asm/irq.h |9 +
 arch/arc/include/asm/pgtable.h |2 +-
 arch/arc/include/asm/processor.h   |   36 +++-
 arch/arc/include/asm/setup.h   |4 +
 arch/arc/include/asm/smp.h |6 +
 arch/arc/include/asm/spinlock.h|   14 ++
 arch/arc/kernel/ctx_sw.c   |   13 ++
 arch/arc/kernel/irq.c  |   25 +++
 arch/arc/kernel/setup.c|1 -
 arch/arc/kernel/smp.c  |   39 -
 arch/arc/kernel/time.c |8 +
 arch/arc/mm/tlb.c  

[PATCH v5 12/20] ARC: [plat-eznps] Add eznps board defconfig and dts

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

Adding default configuration file and DTS file

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/boot/dts/eznps.dts|   94 
 arch/arc/configs/nps_defconfig |   85 
 2 files changed, 179 insertions(+), 0 deletions(-)
 create mode 100644 arch/arc/boot/dts/eznps.dts
 create mode 100644 arch/arc/configs/nps_defconfig

diff --git a/arch/arc/boot/dts/eznps.dts b/arch/arc/boot/dts/eznps.dts
new file mode 100644
index 000..2434948
--- /dev/null
+++ b/arch/arc/boot/dts/eznps.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+   compatible = "ezchip,arc-nps";
+   clock-frequency = <8333>;   /* 83.33 MHZ */
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+   present-cpus = "0-1,16-17";
+   possible-cpus = "0-4095";
+
+   aliases {
+   ethernet0 = 
+   pll = 
+   };
+
+   chosen {
+   bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 
console=ttyS0,115200n8";
+   };
+
+   memory {
+   device_type = "memory";
+   reg = <0x8000 0x2000>;  /* 512M */
+   };
+
+   clocks {
+   sysclk: sysclk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <8333>;
+   };
+   };
+
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   /* child and parent address space 1:1 mapped */
+   ranges;
+
+   intc: interrupt-controller {
+   compatible = "ezchip,nps400-ic";
+   interrupt-controller;
+   #interrupt-cells = <1>;
+   };
+
+   timer {
+   compatible = "ezchip,nps400-timer";
+   clocks = <>;
+   clock-names="sysclk";
+   interrupts = <3>;
+   };
+
+   uart@f7209000 {
+   compatible = "snps,dw-apb-uart";
+   device_type = "serial";
+   reg = <0xf7209000 0x100>;
+   interrupts = <6>;
+   clocks = <>;
+   clock-names="baudclk";
+   baud = <115200>;
+   reg-shift = <2>;
+   reg-io-width = <4>;
+   native-endian;
+   };
+
+   gmac0: ethernet@f747 {
+   compatible = "ezchip,nps-mgt-enet";
+   reg = <0xf747 0x1940>;
+   interrupts = <7>;
+   /* Filled in by U-Boot */
+   mac-address = [ 00 C0 00 F0 04 03 ];
+   };
+   };
+};
diff --git a/arch/arc/configs/nps_defconfig b/arch/arc/configs/nps_defconfig
new file mode 100644
index 000..13a67ac
--- /dev/null
+++ b/arch/arc/configs/nps_defconfig
@@ -0,0 +1,85 @@
+CONFIG_CROSS_COMPILE="arceb-linux-"
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARC_PLAT_EZNPS=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4096
+CONFIG_ARC_CACHE_LINE_SHIFT=5
+# CONFIG_ARC_CACHE_PAGES is not set
+# CONFIG_ARC_HAS_LLSC is not set
+CONFIG_ARC_VMALLOC_SIZE=192
+CONFIG_ARC_E

RE: [PATCH v4 05/19] irqchip: add nps Internal and external irqchips

[Noam Camus]

From: Marc Zyngier [mailto:marc.zyng...@arm.com] 
Sent: Wednesday, December 16, 2015 11:31 AM

>> +static int __init nps400_of_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> +if (parent)
>> +panic("DeviceTree incore ic not a root irq controller\n");
>> +
>> +nps400_root_domain = irq_domain_add_linear(node, NR_CPU_IRQS,
>> +   _irq_ops, NULL);
>> +
>> +if (!nps400_root_domain)
>> +panic("nps400 root irq domain not avail\n");
>> +
>> +/* with this we don't need to export nps400_root_domain */
>> +irq_set_default_host(nps400_root_domain);

>Why do you need this? Devices should have their interrupt-parent pointing to 
>this node, and irq_find_host should sort it >out. I must be missing some 
>information (only being CC'd on this single patch).
Sorry, I will CC you by my next version, in the meantime please refer to:
https://lkml.org/lkml/2015/12/15/864

I need this for my per CPU irqs such timer and IPI which do not come from some 
external device but from CPUs.
For these IRQs I am calling to irq_create_mapping() from my platform at 
arch/arc and at that point I got no irqdomain and using irq_find_host() is not 
good since I got no device_node (at most I can have DT root).
Is there device_node for DT root? 
Please advise what to do?

>> +
>> +return 0;
>> +}
>> +IRQCHIP_DECLARE(ezchip_nps400_ic, "ezchip,nps400-ic", 
>> +nps400_of_init);
>> 

>Another thing I'm not seeing here is where is the interrupt actually taken. 
>This code only contains the EOI part, but not the ACK side, as well as the 
>reverse lookup hwirq -> irq). Where is that code?

ACK is an optional handler and is not needed by my platform.
I will add comment that since my IRQs are EOI based I do not need an ACK.

I do not understand reverse lookup remark, where is it missing?
Could you point me to an example for such reverse lookup? 

Regards,
Noam

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[PATCH v4 02/19] soc: Support for EZchip SoC

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.

Signed-off-by: Noam Camus <no...@ezchip.com>
---
 include/soc/nps/common.h |  123 ++
 1 files changed, 123 insertions(+), 0 deletions(-)
 create mode 100644 include/soc/nps/common.h

diff --git a/include/soc/nps/common.h b/include/soc/nps/common.h
new file mode 100644
index 000..3bc30a8
--- /dev/null
+++ b/include/soc/nps/common.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright(c) 2015 EZchip Technologies.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ */
+
+#ifndef SOC_NPS_COMMON_H
+#define SOC_NPS_COMMON_H
+
+#define NPS_HOST_REG_BASE  0xF600
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 0x5B60
+#define CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 0x00010422
+
+#ifndef __ASSEMBLY__
+/* CPU global ID */
+struct global_id {
+   union {
+   struct {
+#ifdef CONFIG_EZNPS_MTM_EXT
+   u32 __reserved:20, cluster:4, core:4, thread:4;
+#else
+   u32 __reserved:24, cluster:4, core:4;
+#endif
+   };
+   u32 value;
+   };
+};
+
+/*
+ * Convert logical to physical CPU IDs
+ *
+ * The conversion swap bits 1 and 2 of cluster id (out of 4 bits)
+ * Now quad of logical clusters id's are adjacent physically,
+ * and not like the id's physically came with each cluster.
+ * Below table is 4x4 mesh of core clusters as it layout on chip.
+ * Cluster ids are in format: logical (physical)
+ *
+ *-   --
+ * 3 |  5 (3)   7 (7)  | | 13 (11)   15 (15)|
+ *
+ * 2 |  4 (2)   6 (6)  | | 12 (10)   14 (14)|
+ *-   --
+ * 1 |  1 (1)   3 (5)  | |  9  (9)   11 (13)|
+ *
+ * 0 |  0 (0)   2 (4)  | |  8  (8)   10 (12)|
+ *-   --
+ *   0   123
+ */
+static inline int nps_cluster_logic_to_phys(int cluster)
+{
+__asm__ __volatile__(
+   "   mov r3,%0\n"
+   "   .short %1\n"
+   "   .word %2\n"
+   "   mov %0,r3\n"
+   : "+r"(cluster)
+   : "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST),
+ "i"(CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM)
+   : "r3");
+
+   return cluster;
+}
+
+#define NPS_CPU_TO_CLUSTER_NUM(cpu) \
+   ({ struct global_id gid; gid.value = cpu; \
+   nps_cluster_logic_to_phys(gid.cluster); })
+
+struct nps_host_reg_address {
+   union {
+   struct {
+   u32 base:8, cl_x:4, cl_y:4,
+   blkid:6, reg:8, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+struct nps_host_reg_address_non_cl {
+   union {
+   struct {
+   u32 base:7, blkid:11, reg:12, __reserved:2;
+   };
+   u32 value;
+   };
+};
+
+static inline void *nps_host_reg_non_cl(u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address_non_cl reg_address;
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.blkid = blkid;
+   reg_address.reg = reg;
+
+   return (void *)reg_address.value;
+}
+
+static inline void *nps_host_reg(u32 cpu, u32 blkid, u32 reg)
+{
+   struct nps_host_reg_address reg_address;
+   u32 cl = NPS_CPU_TO_CLUSTER_NUM(cpu);
+
+   reg_address.value = NPS_HOST_REG_BASE;
+   reg_address.cl_x  = (cl >> 2) & 0x3;
+   reg_address.cl_y  = cl & 0x3;
+   reg_address.blkid = blkid;
+   reg_address.reg   = reg;
+
+   return (void *)reg_address.value;
+}
+#endif /* __ASSEMBLY__ */
+
+#endif /* SOC_NPS_COMMON_H */
-- 
1.7.1


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[PATCH v4 14/19] ARC: [plat-eznps] Use dedicated atomic/bitops/cmpxchg

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus <no...@ezchip.com>
---
 arch/arc/include/asm/atomic.h  |   79 +++-
 arch/arc/include/asm/bitops.h  |   54 +
 arch/arc/include/asm/cmpxchg.h |   87 +---
 3 files changed, 202 insertions(+), 18 deletions(-)

diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h
index 7730d30..a626996 100644
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -17,6 +17,7 @@
 #include 
 #include 
 
+#ifndef CONFIG_ARC_PLAT_EZNPS
 #define atomic_read(v)  READ_ONCE((v)->counter)
 
 #ifdef CONFIG_ARC_HAS_LLSC
@@ -180,12 +181,84 @@ ATOMIC_OP(andnot, &= ~, bic)
 ATOMIC_OP(or, |=, or)
 ATOMIC_OP(xor, ^=, xor)
 
-#undef ATOMIC_OPS
-#undef ATOMIC_OP_RETURN
-#undef ATOMIC_OP
 #undef SCOND_FAIL_RETRY_VAR_DEF
 #undef SCOND_FAIL_RETRY_ASM
 #undef SCOND_FAIL_RETRY_VARS
+#else /* CONFIG_ARC_PLAT_EZNPS */
+static inline int atomic_read(const atomic_t *v)
+{
+   int temp;
+
+   __asm__ __volatile__(
+   "   ld.di %0, [%1]"
+   : "=r"(temp)
+   : "r"(>counter)
+   : "memory");
+   return temp;
+}
+
+static inline void atomic_set(atomic_t *v, int i)
+{
+   __asm__ __volatile__(
+   "   st.di %0,[%1]"
+   :
+   : "r"(i), "r"(>counter)
+   : "memory");
+}
+
+#define ATOMIC_OP(op, c_op, asm_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   __asm__ __volatile__(   \
+   "   mov r2, %0\n"   \
+   "   mov r3, %1\n"   \
+   "   .word %2\n" \
+   :   \
+   : "r"(i), "r"(>counter), "i"(asm_op) \
+   : "r2", "r3", "memory");\
+}  \
+
+#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{  \
+   unsigned int temp = i;  \
+   \
+   /* Explicit full memory barrier needed before/after */  \
+   smp_mb();   \
+   \
+   __asm__ __volatile__(   \
+   "   mov r2, %0\n"   \
+   "   mov r3, %1\n"   \
+   "   .word %2\n" \
+   "   mov %0, r2" \
+   : "+r"(temp)\
+   : "r"(>counter), "i"(asm_op) \
+   : "r2", "r3", "memory");\
+   \
+   smp_mb();   \
+   \
+   temp c_op i;\
+   \
+   return temp;\
+}
+
+#define ATOMIC_OPS(op, c_op, asm_op)   \
+   ATOMIC_OP(op, c_op, asm_op) \
+   ATOMIC_OP_RETURN(op, c_op, asm_op)
+
+ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3)
+#define atomic_sub(i, v) atomic_add(-(i), (v))
+#define atomic_sub_return(i, v) atomic_add_return(-(i), (v))
+
+ATOMIC_OP(and, &=, CTOP_INST_AAND_DI_R2_R2_R3)
+#define atomic_andnot(mask, v) atomic_and(~(mask), (v))
+ATOMIC_OP(or, |=, CTOP_INST_AOR_DI_R2_R2_R3)
+ATOMIC_OP(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3)
+#endif /* CONFIG_ARC_PLAT_EZNPS */
+
+#undef ATOMIC_OPS
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
 
 /**
  * __atomic_add_un

[PATCH v4 07/19] ARC: rwlock: disable interrupts in !LLSC variant

[Noam Camus]

From: Noam Camus <no...@ezchip.com>

If we hold rwlock and interrupt occures we may
end up spinning on it for ever during softirq.
Note that this lock is an internal lock
and since the lock is free to be used from any context,
the lock needs to be IRQ-safe.

Below you may see an example for interrupt we get while
nl_table_lock is holding its rw->lock_mutex and we spinned
on it for ever.

The concept for the fix was taken from SPARC.

[2015-05-12 19:16:12] Stack Trace:
[2015-05-12 19:16:12]   arc_unwind_core+0xb8/0x11c
[2015-05-12 19:16:12]   dump_stack+0x68/0xac
[2015-05-12 19:16:12]   _raw_read_lock+0xa8/0xac
[2015-05-12 19:16:12]   netlink_broadcast_filtered+0x56/0x35c
[2015-05-12 19:16:12]   nlmsg_notify+0x42/0xa4
[2015-05-12 19:16:13]   neigh_update+0x1fe/0x44c
[2015-05-12 19:16:13]   neigh_event_ns+0x40/0xa4
[2015-05-12 19:16:13]   arp_process+0x46e/0x5a8
[2015-05-12 19:16:13]   __netif_receive_skb_core+0x358/0x500
[2015-05-12 19:16:13]   process_backlog+0x92/0x154
[2015-05-12 19:16:13]   net_rx_action+0xb8/0x188
[2015-05-12 19:16:13]   __do_softirq+0xda/0x1d8
[2015-05-12 19:16:14]   irq_exit+0x8a/0x8c
[2015-05-12 19:16:14]   arch_do_IRQ+0x6c/0xa8
[2015-05-12 19:16:14]   handle_interrupt_level1+0xe4/0xf0

Signed-off-by: Noam Camus <no...@ezchip.com>
Acked-by: Peter Zijlstra <pet...@infradead.org>
---
 arch/arc/include/asm/spinlock.h |   14 ++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arc/include/asm/spinlock.h b/arch/arc/include/asm/spinlock.h
index db8c59d..800e7c4 100644
--- a/arch/arc/include/asm/spinlock.h
+++ b/arch/arc/include/asm/spinlock.h
@@ -610,7 +610,9 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
 static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
int ret = 0;
+   unsigned long flags;
 
+   local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
 
/*
@@ -623,6 +625,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
}
 
arch_spin_unlock(&(rw->lock_mutex));
+   local_irq_restore(flags);
 
smp_mb();
return ret;
@@ -632,7 +635,9 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
 static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
int ret = 0;
+   unsigned long flags;
 
+   local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
 
/*
@@ -646,6 +651,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
ret = 1;
}
arch_spin_unlock(&(rw->lock_mutex));
+   local_irq_restore(flags);
 
return ret;
 }
@@ -664,16 +670,24 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
+   unsigned long flags;
+
+   local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter++;
arch_spin_unlock(&(rw->lock_mutex));
+   local_irq_restore(flags);
 }
 
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
+   unsigned long flags;
+
+   local_irq_save(flags);
arch_spin_lock(&(rw->lock_mutex));
rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
arch_spin_unlock(&(rw->lock_mutex));
+   local_irq_restore(flags);
 }
 
 #endif
-- 
1.7.1


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