Re: [linux-sunxi] Re: A20 I2S Input/output error whan trying to play
On 9 April 2014 21:18, Dennis Kerrisk dennisk8...@gmail.com wrote: Thanks I will check out what I did on the A10 board. I did notice some differences in sunxi-i2sdma.c There are some if CONFIG_ARCH_SUN4I || CONFIG_ARCH_SUN5I that don't include the CONFIG_ARCH_SUN7I. And if I include CONFIG_ARCH_SUN7I I get errors So I will follow that back. Hi Dennis, have a look at sound/soc/sunxi/hdmiaudio/sunxi-hdmipcm.c and compare it with sunxi-i2sdma.c. They are almost the same but do have some small differences(i.e. sunxi_pcm_enqueue is called in trigger). HDMI audio works on both A10 and A20 and the code seems to be a direct copy of the I2S code. CK I am trying to play to an external I2S DAC, but that should not matter, because there is no feedback from the DAC. I will probably just disconnect it and hook up my scope, Dennis On Wednesday, April 9, 2014 12:51:56 PM UTC-6, CodeKipper wrote: On 9 April 2014 20:28, Dennis Kerrisk denni...@gmail.com wrote: I am also getting dma trigger messages in the log: [15379.941504] [IIS] dma trigger start [15379.948491] [IIS] 0x01c22400+0x24 = 0x0, line= 235 [15389.952592] [IIS] dma trigger stop On Wednesday, April 9, 2014 12:05:39 PM UTC-6, Dennis Kerrisk wrote: I now have the I2S showing up in ALSA, but when I try to play to it I get: oot@OlimexWork:~# aplay -D hw:1,0 /usr/src/y.wav Playing WAVE '/usr/src/y.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo aplay: pcm_write:1710: write error: Input/output error Here are the outputs from aplay -l and -L root@OlimexWork:~# aplay -L null Discard all samples (playback) or generate zero samples (capture) sysdefault:CARD=sunxicodec sunxi-CODEC, sunxi PCM Default Audio Device sysdefault:CARD=sunxisndi2s sunxi-sndi2s, Default Audio Device Hi Dennis, It is probably worth retracing your steps on the A10 board. What are you connecting to? and how are you configuring it? I think you're entering uncharted territory so it would be nice to get the overall picture. You will need to add some debugging to the triggering functions to ensure they are being called and would also be wise to get a snap shot of the register values before playback/capture occurs. I've no linux experience with i2s but I would be under the impression that you would be interfacing to a codec driver (loads of which live under sound/soc/codecs) and that will have to be a glue layer between that and the i2s driver. If anybody else has soon i2s experience of the A10 or linux then please share, CK root@OlimexWork:~# aplay -l List of PLAYBACK Hardware Devices card 0: sunxicodec [sunxi-CODEC], device 0: M1 PCM [sunxi PCM] Subdevices: 1/1 Subdevice #0: subdevice #0 card 1: sunxisndi2s [sunxi-sndi2s], device 0: SUNXI-I2S sndi2s-0 [] Subdevices: 1/1 Subdevice #0: subdevice #0 What could I be missing or not have set up correctly? Dennis -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: A20 I2S Input/output error whan trying to play
Hi, There was some talk about i2s at cubieforums http://www.cubieforums.com/index.php?topic=1081.msg12862#msg12862. Can't remember my login credentials, but if I recall correctly the patch made changes to dma and formats. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 1/5] pinctrl: sunxi: add PL and PM pin definitions
Hi, On Thu, Apr 10, 2014 at 02:25:43PM +0200, Boris BREZILLON wrote: Define PL and PM pin macros that will be used in A31 and A23 pin definitions. Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks! -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH v2 2/5] pinctrl: sunxi: support multiple pin controller
On Thu, Apr 10, 2014 at 02:25:44PM +0200, Boris BREZILLON wrote: Add support for multiple pin controller instances. First remove the static definition of the sunxi gpio chip struct and fill the dynamically struct instead. Then define a new pin_base field in the sunxi_pinctrl_desc which will be used to specify the gpiochip base pin. Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks! -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] [PATCH v2 5/5] ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch
The A31 SoC has PL and PM banks, we thus need to increase the default ARCH_NR_GPIO when building for the sunxi architecture. Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 503da0a..fe915ea 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1628,9 +1628,9 @@ config ARCH_NR_GPIO int default 1024 if ARCH_SHMOBILE || ARCH_TEGRA default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX + default 416 if ARCH_SUNXI default 392 if ARCH_U8500 default 352 if ARCH_VT8500 - default 288 if ARCH_SUNXI default 264 if MACH_H4700 default 0 help -- 1.8.3.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH v2 3/5] pinctrl: sunxi: define A31 R_PIO pin functions
The A31 SoC provides both PL and PM pio bank through the R_PIO block.
These pins all support gpio function and can bbe assigned to system
peripherals (like TWI, P2WI, JTAG, ...)
Add new compatible string to the DT bindings doc.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/pinctrl-sunxi-pins.h | 74 ++
drivers/pinctrl/pinctrl-sunxi.c| 1 +
3 files changed, 76 insertions(+)
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index f5da7e3..d8d0656 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -11,6 +11,7 @@ Required properties:
allwinner,sun5i-a10s-pinctrl
allwinner,sun5i-a13-pinctrl
allwinner,sun6i-a31-pinctrl
+ allwinner,sun6i-a31-r-pinctrl
allwinner,sun7i-a20-pinctrl
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h
b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 3d60669..51100ca 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2820,6 +2820,74 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x2, nand1)),/* CE3 */
};
+static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, s_twi), /* SCK */
+ SUNXI_FUNCTION(0x3, s_p2wi)), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, s_twi), /* SDA */
+ SUNXI_FUNCTION(0x3, s_p2wi)), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL2,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, s_uart)), /* TX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL3,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, s_uart)), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL4,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, s_ir)), /* RX */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL5,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, s_jtag)), /* MS */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL6,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, s_jtag)), /* CK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL7,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, s_jtag)), /* DO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL8,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, s_jtag)), /* DI */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM0,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM1,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM2,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, 1wire)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM3,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM4,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM5,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM6,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out)),
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PM7,
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x3, rtc)), /* CLKO */
+};
+
static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
SUNXI_FUNCTION(0x0, gpio_in),
@@ -3855,6 +3923,12 @@ static const struct sunxi_pinctrl_desc
sun6i_a31_pinctrl_data = {
[linux-sunxi] [PATCH v2 2/5] pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.
First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 30 ++
drivers/pinctrl/pinctrl-sunxi.h | 1 +
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index f9fabe9..64bcc68 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -538,19 +538,6 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip, unsigned offset)
return irq_find_mapping(pctl-domain, desc-irqnum);
}
-static struct gpio_chip sunxi_pinctrl_gpio_chip = {
- .owner = THIS_MODULE,
- .request= sunxi_pinctrl_gpio_request,
- .free = sunxi_pinctrl_gpio_free,
- .direction_input= sunxi_pinctrl_gpio_direction_input,
- .direction_output = sunxi_pinctrl_gpio_direction_output,
- .get= sunxi_pinctrl_gpio_get,
- .set= sunxi_pinctrl_gpio_set,
- .of_xlate = sunxi_pinctrl_gpio_of_xlate,
- .to_irq = sunxi_pinctrl_gpio_to_irq,
- .of_gpio_n_cells= 3,
- .can_sleep = false,
-};
static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
unsigned int type)
@@ -858,11 +845,22 @@ static int sunxi_pinctrl_probe(struct platform_device
*pdev)
}
last_pin = pctl-desc-pins[pctl-desc-npins - 1].pin.number;
- pctl-chip = sunxi_pinctrl_gpio_chip;
- pctl-chip-ngpio = round_up(last_pin, PINS_PER_BANK);
+ pctl-chip-owner = THIS_MODULE;
+ pctl-chip-request = sunxi_pinctrl_gpio_request,
+ pctl-chip-free = sunxi_pinctrl_gpio_free,
+ pctl-chip-direction_input = sunxi_pinctrl_gpio_direction_input,
+ pctl-chip-direction_output = sunxi_pinctrl_gpio_direction_output,
+ pctl-chip-get = sunxi_pinctrl_gpio_get,
+ pctl-chip-set = sunxi_pinctrl_gpio_set,
+ pctl-chip-of_xlate = sunxi_pinctrl_gpio_of_xlate,
+ pctl-chip-to_irq = sunxi_pinctrl_gpio_to_irq,
+ pctl-chip-of_gpio_n_cells = 3,
+ pctl-chip-can_sleep = false,
+ pctl-chip-ngpio = round_up(last_pin, PINS_PER_BANK) -
+ pctl-desc-pin_base;
pctl-chip-label = dev_name(pdev-dev);
pctl-chip-dev = pdev-dev;
- pctl-chip-base = 0;
+ pctl-chip-base = pctl-desc-pin_base;
ret = gpiochip_add(pctl-chip);
if (ret)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index ed3c4d7..35d15b2 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -450,6 +450,7 @@ struct sunxi_pinctrl_desc {
int npins;
struct pinctrl_gpio_range *ranges;
int nranges;
+ unsignedpin_base;
};
struct sunxi_pinctrl_function {
--
1.8.3.2
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[linux-sunxi] [PATCH v2 0/5] ARM: sunxi: add multi pin controller support
Hello, This series rework the sunxi pinctrl driver to support the PL and PM pins available on the A31 SoC, which are controlled using the R_PIO block. This series add support for multi pin controller which was previously impossible for several reasons: 1) the pinctrl instance was registering a static instance of the gpio chip, which means, in case you were probing 2 devices, the gpio chip was added twice to the gpiochip list 2) the base pin of the gpio chip was always set to 0, and thus the 2 gpiochip pin numbers were overlapping I still haven't reworked the interrupt part (to handle the per bank interrupt instead of the one interrupt for the whole gpio chip approach), but this will be part of another series. Best Regards, Boris Changes since v1: - rework the pinctrl driver to support multiple pin controller instances - removed reset and clock gate patches from the series - removed A31 DT modifications from the series (we need to get the PRCM reset and clk drivers before being able to declare the r_pio node, and we're still discussing how this should be implemented) Boris BREZILLON (5): pinctrl: sunxi: add PL and PM pin definitions pinctrl: sunxi: support multiple pin controller pinctrl: sunxi: define A31 R_PIO pin functions pinctrl: sunxi: add reset control support ARM: sunxi: update the default ARCH_NR_GPIO for sunxi arch .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 + arch/arm/Kconfig | 2 +- drivers/pinctrl/pinctrl-sunxi-pins.h | 74 ++ drivers/pinctrl/pinctrl-sunxi.c| 40 +++- drivers/pinctrl/pinctrl-sunxi.h| 69 5 files changed, 169 insertions(+), 17 deletions(-) -- 1.8.3.2 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 4/5] pinctrl: sunxi: add reset control support
On Thu, Apr 10, 2014 at 02:25:46PM +0200, Boris BREZILLON wrote:
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted for the pin controller to be usable.
Try to retrieve a reset line and deassert if one was found.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index ee62027..b752495 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -26,6 +26,7 @@
#include linux/pinctrl/pinconf-generic.h
#include linux/pinctrl/pinmux.h
#include linux/platform_device.h
+#include linux/reset.h
#include linux/slab.h
#include core.h
@@ -792,6 +793,7 @@ static int sunxi_pinctrl_probe(struct platform_device
*pdev)
const struct of_device_id *device;
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
+ struct reset_control *rstc;
int i, ret, last_pin;
struct clk *clk;
@@ -885,6 +887,13 @@ static int sunxi_pinctrl_probe(struct platform_device
*pdev)
clk_prepare_enable(clk);
+ rstc = devm_reset_control_get(pdev-dev, NULL);
You should use devm_reset_control_get_optional here.
+ if (!IS_ERR(rstc)) {
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ goto gpiochip_error;
+ }
+
It would be good to put back the device in reset if probe fails later
on.
Thanks
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
signature.asc
Description: Digital signature
[linux-sunxi] [PATCH v3 2/7] pinctrl: sunxi: disable clk when failing to probe pin controller
Disable the clk when failing to probe the pin controller device.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 2d9ca1c..73d11e2 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -891,7 +891,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
pctl-irq = irq_of_parse_and_map(node, 0);
if (!pctl-irq) {
ret = -EINVAL;
- goto gpiochip_error;
+ goto clk_error;
}
pctl-domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -899,7 +899,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
if (!pctl-domain) {
dev_err(pdev-dev, Couldn't register IRQ domain\n);
ret = -ENOMEM;
- goto gpiochip_error;
+ goto clk_error;
}
for (i = 0; i SUNXI_IRQ_NUMBER; i++) {
@@ -917,6 +917,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
return 0;
+clk_error:
+ clk_disable_unprepare(clk);
gpiochip_error:
if (gpiochip_remove(pctl-chip))
dev_err(pdev-dev, failed to remove gpio chip\n);
--
1.8.3.2
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[linux-sunxi] [PATCH v3 6/7] pinctrl: sunxi: add reset control support
The A31 SoC define a reset line for the R_PIO block which needs to be
deasserted.
Try to retrieve a reset control and deassert if one was found.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 17b5f80..07af35a 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -26,6 +26,7 @@
#include linux/pinctrl/pinconf-generic.h
#include linux/pinctrl/pinmux.h
#include linux/platform_device.h
+#include linux/reset.h
#include linux/slab.h
#include core.h
@@ -792,6 +793,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
const struct of_device_id *device;
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
+ struct reset_control *rstc;
int i, ret, last_pin;
struct clk *clk;
@@ -887,10 +889,17 @@ static int sunxi_pinctrl_probe(struct platform_device
*pdev)
if (ret)
goto gpiochip_error;
+ rstc = devm_reset_control_get_optional(pdev-dev, NULL);
+ if (!IS_ERR(rstc)) {
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ goto clk_error;
+ }
+
pctl-irq = irq_of_parse_and_map(node, 0);
if (!pctl-irq) {
ret = -EINVAL;
- goto clk_error;
+ goto rstc_error;
}
pctl-domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
@@ -898,7 +907,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
if (!pctl-domain) {
dev_err(pdev-dev, Couldn't register IRQ domain\n);
ret = -ENOMEM;
- goto clk_error;
+ goto rstc_error;
}
for (i = 0; i SUNXI_IRQ_NUMBER; i++) {
@@ -916,6 +925,9 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
return 0;
+rstc_error:
+ if (!IS_ERR(rstc))
+ reset_control_assert(rstc);
clk_error:
clk_disable_unprepare(clk);
gpiochip_error:
--
1.8.3.2
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[linux-sunxi] [PATCH v3 4/7] pinctrl: sunxi: support multiple pin controller
Add support for multiple pin controller instances.
First remove the static definition of the sunxi gpio chip struct and fill
the dynamically struct instead.
Then define a new pin_base field in the sunxi_pinctrl_desc which will be
used to specify the gpiochip base pin.
Signed-off-by: Boris BREZILLON boris.brezil...@free-electrons.com
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/pinctrl/pinctrl-sunxi.c | 30 ++
drivers/pinctrl/pinctrl-sunxi.h | 1 +
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 73d11e2..6db1c9e 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -538,19 +538,6 @@ static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip
*chip, unsigned offset)
return irq_find_mapping(pctl-domain, desc-irqnum);
}
-static struct gpio_chip sunxi_pinctrl_gpio_chip = {
- .owner = THIS_MODULE,
- .request= sunxi_pinctrl_gpio_request,
- .free = sunxi_pinctrl_gpio_free,
- .direction_input= sunxi_pinctrl_gpio_direction_input,
- .direction_output = sunxi_pinctrl_gpio_direction_output,
- .get= sunxi_pinctrl_gpio_get,
- .set= sunxi_pinctrl_gpio_set,
- .of_xlate = sunxi_pinctrl_gpio_of_xlate,
- .to_irq = sunxi_pinctrl_gpio_to_irq,
- .of_gpio_n_cells= 3,
- .can_sleep = false,
-};
static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
unsigned int type)
@@ -858,11 +845,22 @@ static int sunxi_pinctrl_probe(struct platform_device
*pdev)
}
last_pin = pctl-desc-pins[pctl-desc-npins - 1].pin.number;
- pctl-chip = sunxi_pinctrl_gpio_chip;
- pctl-chip-ngpio = round_up(last_pin, PINS_PER_BANK);
+ pctl-chip-owner = THIS_MODULE;
+ pctl-chip-request = sunxi_pinctrl_gpio_request,
+ pctl-chip-free = sunxi_pinctrl_gpio_free,
+ pctl-chip-direction_input = sunxi_pinctrl_gpio_direction_input,
+ pctl-chip-direction_output = sunxi_pinctrl_gpio_direction_output,
+ pctl-chip-get = sunxi_pinctrl_gpio_get,
+ pctl-chip-set = sunxi_pinctrl_gpio_set,
+ pctl-chip-of_xlate = sunxi_pinctrl_gpio_of_xlate,
+ pctl-chip-to_irq = sunxi_pinctrl_gpio_to_irq,
+ pctl-chip-of_gpio_n_cells = 3,
+ pctl-chip-can_sleep = false,
+ pctl-chip-ngpio = round_up(last_pin, PINS_PER_BANK) -
+ pctl-desc-pin_base;
pctl-chip-label = dev_name(pdev-dev);
pctl-chip-dev = pdev-dev;
- pctl-chip-base = 0;
+ pctl-chip-base = pctl-desc-pin_base;
ret = gpiochip_add(pctl-chip);
if (ret)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index ed3c4d7..35d15b2 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -450,6 +450,7 @@ struct sunxi_pinctrl_desc {
int npins;
struct pinctrl_gpio_range *ranges;
int nranges;
+ unsignedpin_base;
};
struct sunxi_pinctrl_function {
--
1.8.3.2
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Re: [linux-sunxi] Livesuite image building tools
Last time I tried the sunxi-bsp tools they weren't working and I didn't see much interest in fixing them (myself included). The lichee tools are going to have no support unless you buy a Dev kit from wits but wits is actually very helpful if you do. I had the Lichee tools for a31 and they worked very well. I haven't tried them for other chips. Either way though you are probably on your own though so I would just experiment. On Apr 6, 2014 1:17 PM, beat...@beattie-home.net wrote: I'm trying to get build root to build an image that I can flash into my Cubieboard2 and boot. I think this means an image that Livesuit (which I have working) can read. It looks like sunxi-bsp is the preferred solution for building Livesuit images around here. I think I have buildroot building all of the u-boot files I need, and from looking at sunxi-bsp it looks like what I need mostly at this point is linux-sunxi/allwinner-tools from github (which is mostly proprietary binaries). I have also noted that there seems to be a newer toolset (from allwinner?) under the name Lichee? Is the linux-sunxi/allwinner-tools the way to go, or is there another way to build a Livesuit image from scratch? Also what do people think of the lichee toolset. Brian * https://github.com/linux-sunxi/allwinner-tools* -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
