Re: [linux-sunxi] Allwinner R8 module
On Sun, May 10, 2015 at 10:23 PM, Luc Verhaegen l...@skynet.be wrote: On Sun, May 10, 2015 at 09:49:43PM -0400, jonsm...@gmail.com wrote: Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. *sigh* I am amazed that people still fall for what i can now only call the kickstarter trap. * only 9usd * 1y delivery time * full mainline support * linux-sunxi is not mentioned even once I don't care about their board, I want to know the price/specs of the R8 module from Allwinner. I want to put it on my own board. None of that fits together, and i am amazed that people actually fall for that still. Luc Verhaegen. -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Allwinner R8 module
Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Allwinner R8 module
On Sun, May 10, 2015 at 09:49:43PM -0400, jonsm...@gmail.com wrote: Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. *sigh* I am amazed that people still fall for what i can now only call the kickstarter trap. * only 9usd * 1y delivery time * full mainline support * linux-sunxi is not mentioned even once None of that fits together, and i am amazed that people actually fall for that still. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] how to get latest sunxi ?
https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.4 https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.4 https://github.com/linux-sunxi/linux-sunxi/tree/stage/sunxi-3.4 https://github.com/linux-sunxi/linux-sunxi/tree/stage/sunxi-3.4 Or mainline. I’ve been using 3.19 for awhile now. Clement On May 11, 2015, at 1:48 AM, Antoine RODRIGUEZ antoi...@connetport.com wrote: Hi, how can I get the lastest sunxi for A20 ? I see here a lot of improvements but the git is stuck on 2014 ... Maybe I don't look on the good branch... Someone can advise me where to get the latest updates for sunxi ? Best regards, -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Allwinner R8 module
I think you should be happy that your work is in use by thousands. And there is mention of sunxi in QA “I want to know more about the Allwinner R8 processor!”. Clement On May 11, 2015, at 10:23 AM, Luc Verhaegen l...@skynet.be wrote: On Sun, May 10, 2015 at 09:49:43PM -0400, jonsm...@gmail.com wrote: Does anyone have any info on the new Allwinner R8 module being used in the Chip $9 PC Kickstarter? It is A13+flash+RAM on module. I'd like to get a pin out and projected price. That module has to be really low cost if they are able to make a $9 computer out of it. *sigh* I am amazed that people still fall for what i can now only call the kickstarter trap. * only 9usd * 1y delivery time * full mainline support * linux-sunxi is not mentioned even once None of that fits together, and i am amazed that people actually fall for that still. Luc Verhaegen. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
Hi,
On Sun, May 10, 2015 at 12:16:21PM +0530, Vishnu Patekar wrote:
added the common sun8i.dtsi and allwinner,sun8i compatible for common
sun8i features, I've referred the h3 dtsi by Jens Kuske.
accordingly modified the sun8i-a23.dtsi and a23 dts.
I don't have a23 device, however, dts got compiled.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
Once again, that patch does several unrelated things at once.
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
arch/arm/boot/dts/sun8i-a23.dtsi | 432 +--
arch/arm/boot/dts/sun8i.dtsi | 481
++
4 files changed, 486 insertions(+), 439 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
index dd31c53..b3f19e7 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -16,10 +16,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
It removes some check patch warning (and it's not even mentionned in
the commit log).
* Or, alternatively,
*
@@ -55,5 +51,5 @@
/ {
model = Ippo Q8H Dual Core Tablet (v1.2);
- compatible = ippo,q8h-v1.2, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v1.2, allwinner,sun8i, allwinner,sun8i-a23;
It adds a new compatible to boards.
};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index f5658d1..5db4010 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -57,7 +53,7 @@
/ {
model = Ippo Q8H Dual Core Tablet (v5);
- compatible = ippo,q8h-v5, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v5, allwinner,sun8i, allwinner,sun8i-a23;
aliases {
serial0 = r_uart;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi
b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6d6eda3..c17be9e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -47,41 +43,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include skeleton.dtsi
-
-#include dt-bindings/interrupt-controller/arm-gic.h
-
-#include dt-bindings/pinctrl/sun4i-a10.h
+#include sun8i.dtsi
/ {
- interrupt-parent = gic;
-
- chosen {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- framebuffer@0 {
- compatible = allwinner,simple-framebuffer,
- simple-framebuffer;
- allwinner,pipeline = de_be0-lcd0;
- clocks = pll6 0;
- status = disabled;
- };
- };
-
- timer {
- compatible = arm,armv7-timer;
- interrupts = GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
- GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
- GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
- GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW);
- clock-frequency = 2400;
- arm,cpu-registers-not-fw-configured;
- };
-
cpus {
- enable-method = allwinner,sun8i-a23;
+ enable-method = allwinner,sun8i;
It updates a CPU enable method.
#address-cells = 1;
#size-cells = 0;
@@ -103,32 +69,6 @@
};
clocks {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = 0;
-
[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
Hi,
On Sun, May 10, 2015 at 12:16:22PM +0530, Vishnu Patekar wrote:
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217
+++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include sun8i.dtsi
+
+/ {
+ cpus {
+ enable-method = allwinner,sun8i;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 0;
+ };
+
+ cpu@1 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 1;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 3;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ clock-output-names = pll5;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun8i-a23-axi-clk;
+ reg = 0x01c20050 0x4;
+ clocks = cpu;
+ clock-output-names = axi;
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun8i-a23-ahb1-gates-clk;
+ reg = 0x01c20060 0x8;
+ clocks = ahb1;
+ clock-output-names = ahb1_mipidsi, ahb1_dma,
+ ahb1_mmc0, ahb1_mmc1, ahb1_mmc2,
+ ahb1_nand, ahb1_sdram,
+ ahb1_hstimer, ahb1_spi0,
+ ahb1_spi1, ahb1_otg, ahb1_ehci,
+ ahb1_ohci, ahb1_ve, ahb1_lcd,
+ ahb1_csi, ahb1_be, ahb1_fe,
+
[linux-sunxi] [PATCH 0/6] Introduce Allwinner A33 support
Hello everyone, This patch series introduces basic kernel support for Allwinner's A33 SoC, A33 is very similar to A23. mainly adds common sun8i dtsi, a33 pinctrl. It also adds interrupts, timers, watchdog, RTC, and UARTs, which are mostly compatible to those in earlier SoCs like A23 and A31, and can simply be reused. These patches are based on https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Patch 1 adds machine support for the A33. Patch 2 adds the pin sets for the A33 main PIO. Patch 3 adds support to reuse A23 clocks. A33 specific clocks not yet implemented. Patch 4 adds common sun8i.dtsi, modified sun8i-a23.dtsi and a23 based dts, I've referred the h3 dtsi by Jens Kuske. removed the checkpatch warning related to Linux Foundation address in dtsi,dts. Patch 5 adds the DTSI for the A33, based on common sun8i.dtsi. Patch 6 adds a DT for the ET_Q8_A33 tablet, which these patches were developed and tested with. Vishnu Patekar (6): ARM: sunxi: Add Machine support for A33 pinctrl: sunxi: add allwinner A33 PIO controller support clk: sunxi: Add A33 clock for compilation ARM: dts: sunxi: add common sun8i dtsi ARM: dts: sunxi: Add Allwinner A33 DTSI ARM: dts: sun8i: Add ET-Q8 A33 support Documentation/devicetree/bindings/arm/sunxi.txt| 1 + .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 + arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +- arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts| 6 +- arch/arm/boot/dts/sun8i-a23.dtsi | 432 + arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 + arch/arm/boot/dts/sun8i-a33.dtsi | 217 + arch/arm/boot/dts/sun8i.dtsi | 481 +++ arch/arm/mach-sunxi/Kconfig| 2 +- arch/arm/mach-sunxi/platsmp.c | 2 +- arch/arm/mach-sunxi/sunxi.c| 4 +- drivers/clk/sunxi/clk-sunxi.c | 1 + drivers/pinctrl/sunxi/Kconfig | 5 + drivers/pinctrl/sunxi/Makefile | 1 + drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 + 16 files changed, 1340 insertions(+), 444 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi create mode 100644 arch/arm/boot/dts/sun8i.dtsi create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c -- 1.9.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
Hi,
On Sun, May 10, 2015 at 4:50 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Is this patch really necessary at all? The A33 is a pin compatible drop in
for the A23, I would expect things to work just fine using the A23 pinmux
code
for the A33. and also the a23 pinctrl compatibles.
A33 has UART0 available on PB[01], which is quite nice.
Also EINT seems to be missing a group.
So pin compatible is mostly true. :)
ChenYu
Regards,
Hans
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513
+
4 files changed, 521 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index fdd8046..9462ab7 100644
---
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -16,6 +16,8 @@ Required properties:
allwinner,sun7i-a20-pinctrl
allwinner,sun8i-a23-pinctrl
allwinner,sun8i-a23-r-pinctrl
+ allwinner,sun8i-a33-pinctrl
+
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 2eb893e..dd83aab 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
+
+config PINCTRL_SUN8I_A33
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile
b/drivers/pinctrl/sunxi/Makefile
index b796d57..227a121 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) +=
pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
new file mode 100644
index 000..00265f0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -0,0 +1,513 @@
+/*
+ * Allwinner a33 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-sunxi.h
+
+static const struct sunxi_desc_pin sun8i_a33_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* TX */
+ SUNXI_FUNCTION(0x3, uart0), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RX */
+ SUNXI_FUNCTION(0x3, uart0), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
+
[linux-sunxi] Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
On Sun, May 10, 2015 at 12:16:19PM +0530, Vishnu Patekar wrote: A33 PIO has 7 ports which starts from PB and has two interrupt ports. Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com Acked-by: Maxime Ripard maxime.rip...@free-electrons.com Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
On Sun, May 10, 2015 at 12:16:23PM +0530, Vishnu Patekar wrote:
ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
It has 512MB RAM, 4GB Nand, 7 Display, RDA5900P wifi, GSL1680 touch, etc.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108
++
2 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 82f4b9b..d44b1d6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a33-et-q8.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts
b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
new file mode 100644
index 000..260d5a3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun8i-a33.dtsi
+#include sunxi-common-regulators.dtsi
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/input/input.h
+#include dt-bindings/pinctrl/sun4i-a10.h
+
+/ {
+ model = ET Q8 A33 ;
There's one trailing space here.
+ compatible = et-q8-q33, allwinner,sun8i, allwinner,sun8i-a33;
All compatibles must be under the vendor,IP format.
What is the maker of your board? That should also be in the DT name,
under the format sun8i-a33-vendor-board.dts
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ bootargs = earlyprintk console=ttyS0,115200;
+ };
Please use stdout-path here, just like we're doing on the other
boards.
+};
+
+lradc {
+ vref-supply = reg_vcc3v0;
+ status = okay;
+
+ button@200 {
+ label = Volume Up;
+ linux,code = KEY_VOLUMEUP;
+ channel = 0;
+ voltage = 20;
+ };
+
+ button@400 {
+ label = Volume Down;
+ linux,code = KEY_VOLUMEDOWN;
+ channel = 0;
+ voltage = 40;
+ };
+};
+
+i2c0 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+};
+
+i2c1 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+};
+
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins_a;
+ /* pull-ups and devices require PMIC regulator */
+ status = failed;
+};
Is this still true, or is it just a copy/paste mistake?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel
[linux-sunxi] Re: [PATCH 1/6] ARM: sunxi: Add Machine support for A33
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
Allwinnner A33 quad core cortex-a7 based SOC.
It is similar to A23.
Renamed cpu method to allwinner,sun8i for common sun8i smp.
smp code is generic for A23, A33 and hopefully H3.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/platsmp.c | 2 +-
arch/arm/mach-sunxi/sunxi.c | 4 ++--
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index 42941fd..e32f082 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -9,4 +9,5 @@ using one of the following compatible strings:
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
+ allwinner,sun8i-a33
allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 81502b9..38bedd8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -35,7 +35,7 @@ config MACH_SUN7I
select SUN5I_HSTIMER
config MACH_SUN8I
- bool Allwinner A23 (sun8i) SoCs support
+ bool Allwinner (sun8i) SoCs support
default ARCH_SUNXI
select ARM_GIC
select MFD_SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..c56b501 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
.smp_prepare_cpus = sun8i_smp_prepare_cpus,
.smp_boot_secondary = sun8i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun8i_a23_smp, allwinner,sun8i-a23, sun8i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun8i_smp, allwinner,sun8i, sun8i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1bc811a..8937d0d 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, Allwinner sun7i (A20) Family)
MACHINE_END
static const char * const sun8i_board_dt_compat[] = {
- allwinner,sun8i-a23,
+ allwinner,sun8i,
NULL,
};
This is wrong it should be:
static const char * const sun8i_board_dt_compat[] = {
allwinner,sun8i-a23,
allwinner,sun8i-a33,
NULL,
};
To match what you've said it will be in
Documentation/devicetree/bindings/arm/sunxi.txt
(which is correct).
Otherwise this patch looks good, thanks for your work on this.
Regards,
Hans
-DT_MACHINE_START(SUN8I_DT, Allwinner sun8i (A23) Family)
+DT_MACHINE_START(SUN8I_DT, Allwinner sun8i Family)
.dt_compat = sun8i_board_dt_compat,
.init_late = sunxi_dt_cpufreq_init,
MACHINE_END
--
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[linux-sunxi] Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Is this patch really necessary at all? The A33 is a pin compatible drop in
for the A23, I would expect things to work just fine using the A23 pinmux code
for the A33. and also the a23 pinctrl compatibles.
Regards,
Hans
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +
4 files changed, 521 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index fdd8046..9462ab7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -16,6 +16,8 @@ Required properties:
allwinner,sun7i-a20-pinctrl
allwinner,sun8i-a23-pinctrl
allwinner,sun8i-a23-r-pinctrl
+ allwinner,sun8i-a33-pinctrl
+
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 2eb893e..dd83aab 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
+
+config PINCTRL_SUN8I_A33
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index b796d57..227a121 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
new file mode 100644
index 000..00265f0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -0,0 +1,513 @@
+/*
+ * Allwinner a33 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-sunxi.h
+
+static const struct sunxi_desc_pin sun8i_a33_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* TX */
+ SUNXI_FUNCTION(0x3, uart0), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RX */
+ SUNXI_FUNCTION(0x3, uart0), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, i2s0),/* SYNC */
+ SUNXI_FUNCTION(0x3, aif2),/* SYNC */
+
[linux-sunxi] Re: [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
It has 512MB RAM, 4GB Nand, 7 Display, RDA5900P wifi, GSL1680 touch, etc.
Where does the ET prefix come from ? The ippo boards have an ippo prefix as
that is written on the pcb ...
Regards,
Hans
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 ++
2 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 82f4b9b..d44b1d6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a33-et-q8.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts
b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
new file mode 100644
index 000..260d5a3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun8i-a33.dtsi
+#include sunxi-common-regulators.dtsi
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/input/input.h
+#include dt-bindings/pinctrl/sun4i-a10.h
+
+/ {
+ model = ET Q8 A33 ;
+ compatible = et-q8-q33, allwinner,sun8i, allwinner,sun8i-a33;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ bootargs = earlyprintk console=ttyS0,115200;
+ };
+};
+
+lradc {
+ vref-supply = reg_vcc3v0;
+ status = okay;
+
+ button@200 {
+ label = Volume Up;
+ linux,code = KEY_VOLUMEUP;
+ channel = 0;
+ voltage = 20;
+ };
+
+ button@400 {
+ label = Volume Down;
+ linux,code = KEY_VOLUMEDOWN;
+ channel = 0;
+ voltage = 40;
+ };
+};
+
+i2c0 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+};
+
+i2c1 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+};
+
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins_a;
+ /* pull-ups and devices require PMIC regulator */
+ status = failed;
+};
+
+uart0 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+};
--
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[linux-sunxi] Re: [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
Hi,
On 10-05-15 11:00, Chen-Yu Tsai wrote:
Hi,
On Sun, May 10, 2015 at 4:50 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
Is this patch really necessary at all? The A33 is a pin compatible drop in
for the A23, I would expect things to work just fine using the A23 pinmux
code
for the A33. and also the a23 pinctrl compatibles.
A33 has UART0 available on PB[01], which is quite nice.
Also EINT seems to be missing a group.
So pin compatible is mostly true. :)
Ok, lets go with this patch then:
Acked-by: Hans de Goede hdego...@redhat.com
Regards,
Hans
ChenYu
Regards,
Hans
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513
+
4 files changed, 521 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index fdd8046..9462ab7 100644
---
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -16,6 +16,8 @@ Required properties:
allwinner,sun7i-a20-pinctrl
allwinner,sun8i-a23-pinctrl
allwinner,sun8i-a23-r-pinctrl
+ allwinner,sun8i-a33-pinctrl
+
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 2eb893e..dd83aab 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
+
+config PINCTRL_SUN8I_A33
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile
b/drivers/pinctrl/sunxi/Makefile
index b796d57..227a121 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) +=
pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
new file mode 100644
index 000..00265f0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -0,0 +1,513 @@
+/*
+ * Allwinner a33 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-sunxi.h
+
+static const struct sunxi_desc_pin sun8i_a33_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* TX */
+ SUNXI_FUNCTION(0x3, uart0), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RX */
+ SUNXI_FUNCTION(0x3, uart0), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4,
[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
Hi,
On Sun, May 10, 2015 at 2:23 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
This seems to only contain stuff which can be shared with the a23 dts,
why is this not all in the common sun8i.dtsi ?
Allwinner H3 is also sun8i, I've referred the referred the H3 dtsi
patch sent by Jens Kuske.
I've added common parts bet a23 and h3 in sun8i.dtsi.
same note added in common sun8i PATCH 4, which I'm going to resend
after your comment.
Regards,
Hans
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217
+++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include sun8i.dtsi
+
+/ {
+ cpus {
+ enable-method = allwinner,sun8i;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 0;
+ };
+
+ cpu@1 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 1;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 3;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ clock-output-names = pll5;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun8i-a23-axi-clk;
+ reg = 0x01c20050 0x4;
+ clocks = cpu;
+ clock-output-names = axi;
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun8i-a23-ahb1-gates-clk;
+ reg =
[linux-sunxi] Re: [PATCH 1/3] phy-sun4i-usb: Add a sunxi specific function for setting squelch-detect
Hi,
On 08-05-15 18:06, Felipe Balbi wrote:
Hi,
On Sun, Mar 29, 2015 at 12:50:46PM +0200, Hans de Goede wrote:
The sunxi otg phy has a bug where it wrongly detects a high speed squelch
when reset on the root port gets de-asserted with a lo-speed device.
The workaround for this is to disable squelch detect before de-asserting
reset, and re-enabling it after the reset de-assert is done. Add a sunxi
specific phy function to allow the sunxi-musb glue to do this.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/phy/phy-sun4i-usb.c | 9 +
include/linux/phy/phy-sun4i-usb.h | 26 ++
2 files changed, 35 insertions(+)
create mode 100644 include/linux/phy/phy-sun4i-usb.h
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 221e8ab..01eb08d 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -33,6 +33,7 @@
#include linux/of_address.h
#include linux/of_gpio.h
#include linux/phy/phy.h
+#include linux/phy/phy-sun4i-usb.h
#include linux/platform_device.h
#include linux/regulator/consumer.h
#include linux/reset.h
@@ -75,6 +76,7 @@
#define PHY_OTG_FUNC_EN 0x28
#define PHY_VBUS_DET_EN 0x29
#define PHY_DISCON_TH_SEL 0x2a
+#define PHY_SQUELCH_DETECT 0x3c
#define MAX_PHYS 3
@@ -322,6 +324,13 @@ static int sun4i_usb_phy_power_off(struct phy *_phy)
return 0;
}
+void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
+{
+ struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
+
+ sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
+}
+
static struct phy_ops sun4i_usb_phy_ops = {
.init = sun4i_usb_phy_init,
.exit = sun4i_usb_phy_exit,
diff --git a/include/linux/phy/phy-sun4i-usb.h
b/include/linux/phy/phy-sun4i-usb.h
new file mode 100644
index 000..50aed92
--- /dev/null
+++ b/include/linux/phy/phy-sun4i-usb.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2015 Hans de Goede hdego...@redhat.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef PHY_SUN4I_USB_H_
+#define PHY_SUN4I_USB_H_
+
+#include phy.h
+
+/**
+ * sun4i_usb_phy_set_squelch_detect() - Enable/disable squelch detect
+ * @phy: reference to a sun4i usb phy
+ * @enabled: wether to enable or disable squelch detect
+ */
+void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled);
breaks build if MUSB=y and SUN41_PHY=m
Ah, good one. So I assume that it is ok to fix this by doing:
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -66,6 +66,7 @@ config USB_MUSB_SUNXI
tristate Allwinner (sunxi)
depends on ARCH_SUNXI
depends on NOP_USB_XCEIV
+ depends on PHY_SUN4I_USB
select EXTCON
select GENERIC_PHY
select SUNXI_SRAM
?
Also I've not heard anything back from you wrt my other musb
sunxi preparation patches and the actual musb-sunxi patch¸ are
those all ready for merging?
Regards,
Hans
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[linux-sunxi] Re: [PATCH 1/6] ARM: sunxi: Add Machine support for A33
Hi,
On Sun, May 10, 2015 at 12:16:18PM +0530, Vishnu Patekar wrote:
Allwinnner A33 quad core cortex-a7 based SOC.
There's one n to many in Allwinner, and having a verb in that sentence
would help
It is similar to A23.
Renamed cpu method to allwinner,sun8i for common sun8i smp.
smp code is generic for A23, A33 and hopefully H3.
Please do only one thing in a patch.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/platsmp.c | 2 +-
arch/arm/mach-sunxi/sunxi.c | 4 ++--
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index 42941fd..e32f082 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -9,4 +9,5 @@ using one of the following compatible strings:
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
+ allwinner,sun8i-a33
Here you're introducing a new compatible for a machine that is
sun8i-a33 [1]
allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 81502b9..38bedd8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -35,7 +35,7 @@ config MACH_SUN7I
select SUN5I_HSTIMER
config MACH_SUN8I
- bool Allwinner A23 (sun8i) SoCs support
+ bool Allwinner (sun8i) SoCs support
default ARCH_SUNXI
select ARM_GIC
select MFD_SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..c56b501 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
.smp_prepare_cpus = sun8i_smp_prepare_cpus,
.smp_boot_secondary = sun8i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun8i_a23_smp, allwinner,sun8i-a23, sun8i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun8i_smp, allwinner,sun8i, sun8i_smp_ops);
Like I was saying, this is an unrelated thing, it should be in a
separate patch.
And this is wrong.
A compatible should be made for the first IP that uses it. The first
user of that particular method has been the A23, it should be what's
in the compatible.
If the A33 is by chance using the exact same code, then we have two
choices, either reuse that compatible, or introduce a new one if it
slightly differs. And since the A33 has more cores than the A23, it
does differ.
So please add a new compatible.
That also breaks the SMP code in the A23 which is a no-go, since the
compatible would have changed but not the DT.
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1bc811a..8937d0d 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, Allwinner sun7i (A20) Family)
MACHINE_END
static const char * const sun8i_board_dt_compat[] = {
- allwinner,sun8i-a23,
+ allwinner,sun8i,
[1] ... And here, you don't introduce that new machine compatible, but
remove one a use another one instead
Apart from the documentation mismatch, you really shouldn't do that.
The machine compatible should be a identifier for the board and the
SoC, so that we can identify both easily, and possibly enable
quirks. The only question you should ask yourself whenever you add a
new compatible is is this exactly the same IP ?
In such a case, is the A23 *exactly* the same as the H3 and the A33?
The answer is obviously no, otherwise we would not have this patchset
in the first place.
So you just need to introduce a new compatible for the A33, just like
you did in the Documentation, and add that new compatible in the machine.
NULL,
};
-DT_MACHINE_START(SUN8I_DT, Allwinner sun8i (A23) Family)
+DT_MACHINE_START(SUN8I_DT, Allwinner sun8i Family)
.dt_compat = sun8i_board_dt_compat,
.init_late = sunxi_dt_cpufreq_init,
MACHINE_END
--
1.9.1
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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[linux-sunxi] Re: [PATCH 2/6] clk: sunxi: Add H3 clocks support
Hi,
On 09/05/15 13:27, Maxime Ripard wrote:
On Wed, May 06, 2015 at 11:31:29AM +0200, Jens Kuske wrote:
The H3 clock control unit is similar to the those of other sun8i family
members like the A23.
The AHB1 gates got split up into AHB1 and AHB2, with AHB2 clock source
being muxable between AHB1 and PLL6/2, but still sharing gate registers.
The documentation isn't totally clear about which devices belong to
AHB2 now, especially USB EHIC/OHIC, so it is mostly based on Allwinner
kernel source code.
Signed-off-by: Jens Kuske jensku...@gmail.com
---
Documentation/devicetree/bindings/clock/sunxi.txt | 7
drivers/clk/sunxi/clk-sunxi.c | 46
++-
2 files changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 4fa11af..4eeb893 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -14,6 +14,8 @@ Required properties:
allwinner,sun4i-a10-pll5-clk - for the PLL5 clock
allwinner,sun4i-a10-pll6-clk - for the PLL6 clock
allwinner,sun6i-a31-pll6-clk - for the PLL6 clock on A31
+allwinner,sun8i-h3-pll6-clk - for the PLL6 clock on H3
+allwinner,sun8i-h3-pll8-clk - for the PLL8 clock on H3
allwinner,sun9i-a80-gt-clk - for the GT bus clock on A80
allwinner,sun4i-a10-cpu-clk - for the CPU multiplexer clock
allwinner,sun4i-a10-axi-clk - for the AXI clock
@@ -28,8 +30,11 @@ Required properties:
allwinner,sun7i-a20-ahb-gates-clk - for the AHB gates on A20
allwinner,sun6i-a31-ar100-clk - for the AR100 on A31
allwinner,sun6i-a31-ahb1-clk - for the AHB1 clock on A31
+allwinner,sun8i-h3-ahb2-clk - for the AHB2 clock on H3
allwinner,sun6i-a31-ahb1-gates-clk - for the AHB1 gates on A31
allwinner,sun8i-a23-ahb1-gates-clk - for the AHB1 gates on A23
+allwinner,sun8i-h3-ahb1-gates-clk - for the AHB1 gates on H3
+allwinner,sun8i-h3-ahb2-gates-clk - for the AHB2 gates on H3
allwinner,sun9i-a80-ahb0-gates-clk - for the AHB0 gates on A80
allwinner,sun9i-a80-ahb1-gates-clk - for the AHB1 gates on A80
allwinner,sun9i-a80-ahb2-gates-clk - for the AHB2 gates on A80
@@ -52,8 +57,10 @@ Required properties:
allwinner,sun6i-a31-apb1-gates-clk - for the APB1 gates on A31
allwinner,sun7i-a20-apb1-gates-clk - for the APB1 gates on A20
allwinner,sun8i-a23-apb1-gates-clk - for the APB1 gates on A23
+allwinner,sun8i-h3-apb1-gates-clk - for the APB1 gates on H3
allwinner,sun9i-a80-apb1-gates-clk - for the APB1 gates on A80
allwinner,sun6i-a31-apb2-gates-clk - for the APB2 gates on A31
+allwinner,sun8i-h3-apb2-gates-clk - for the APB2 gates on H3
allwinner,sun8i-a23-apb2-gates-clk - for the APB2 gates on A23
allwinner,sun5i-a13-mbus-clk - for the MBUS clock on A13
allwinner,sun4i-a10-mmc-clk - for the MMC clock
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e1e2bd..152a1f7 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -727,6 +727,12 @@ static const struct factors_data sun5i_a13_ahb_data
__initconst = {
.getter = sun5i_a13_get_ahb_factors,
};
+static const struct factors_data sun8i_h3_pll8_data __initconst = {
+.enable = 31,
+.table = sun6i_a31_pll6_config,
+.getter = sun6i_a31_get_pll6_factors,
+};
This looks like it's just another instance of the A31 pll6.
In such a case, we don't need to declare a new driver, just reuse the
same compatible.
If I reuse pll6 for pll8 I get errors because of the .name = pll6x2
field, already existing clock or something like that. (And pll8 doesn't
even have a x2 version)
static const struct factors_data sun4i_apb1_data __initconst = {
.mux = 24,
.muxmask = BIT(1) | BIT(0),
@@ -777,6 +783,10 @@ static const struct mux_data sun6i_a31_ahb1_mux_data
__initconst = {
.shift = 12,
};
+static const struct mux_data sun8i_h3_ahb2_mux_data __initconst = {
+.shift = 0,
+};
+
static void __init sunxi_mux_clk_setup(struct device_node *node,
struct mux_data *data)
{
@@ -892,7 +902,7 @@ static void __init sunxi_divider_clk_setup(struct
device_node *node,
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
*/
-#define SUNXI_GATES_MAX_SIZE64
+#define SUNXI_GATES_MAX_SIZE160
struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
@@ -926,6 +936,10 @@ static const struct gates_data
sun8i_a23_ahb1_gates_data __initconst = {
.mask = {0x25386742, 0x2505111},
};
+static const struct gates_data sun8i_h3_ahb1_gates_data __initconst = {
+.mask = {0x1fbc6760, 0x00701b39, 0x, 0x, 0x0081},
+};
+
Judging from the user manual, there's a few gates in
[linux-sunxi] [PATCH 2/6] pinctrl: sunxi: add allwinner A33 PIO controller support
A33 PIO has 7 ports which starts from PB and has two interrupt ports.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c | 513 +
4 files changed, 521 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
diff --git
a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index fdd8046..9462ab7 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -16,6 +16,8 @@ Required properties:
allwinner,sun7i-a20-pinctrl
allwinner,sun8i-a23-pinctrl
allwinner,sun8i-a23-r-pinctrl
+ allwinner,sun8i-a33-pinctrl
+
- reg: Should contain the register physical address and length for the
pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 2eb893e..dd83aab 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -38,6 +38,11 @@ config PINCTRL_SUN8I_A23
def_bool MACH_SUN8I
select PINCTRL_SUNXI_COMMON
+
+config PINCTRL_SUN8I_A33
+ def_bool MACH_SUN8I
+ select PINCTRL_SUNXI_COMMON
+
config PINCTRL_SUN8I_A23_R
def_bool MACH_SUN8I
depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index b796d57..227a121 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o
obj-$(CONFIG_PINCTRL_SUN7I_A20)+= pinctrl-sun7i-a20.o
obj-$(CONFIG_PINCTRL_SUN8I_A23)+= pinctrl-sun8i-a23.o
obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN8I_A33)+= pinctrl-sun8i-a33.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
new file mode 100644
index 000..00265f0
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -0,0 +1,513 @@
+/*
+ * Allwinner a33 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ * Copyright (C) 2014 Maxime Ripard maxime.rip...@free-electrons.com
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed as is without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/pinctrl/pinctrl.h
+
+#include pinctrl-sunxi.h
+
+static const struct sunxi_desc_pin sun8i_a33_pins[] = {
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* TX */
+ SUNXI_FUNCTION(0x3, uart0), /* TX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PB_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RX */
+ SUNXI_FUNCTION(0x3, uart0), /* RX */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PB_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* RTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 2)), /* PB_EINT2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, uart2), /* CTS */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 3)), /* PB_EINT3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, i2s0), /* SYNC */
+ SUNXI_FUNCTION(0x3, aif2), /* SYNC */
+ SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 4)), /* PB_EINT4 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+ SUNXI_FUNCTION(0x0, gpio_in),
+ SUNXI_FUNCTION(0x1, gpio_out),
+ SUNXI_FUNCTION(0x2, i2s0), /* BCLK */
+ SUNXI_FUNCTION(0x3, aif2), /* BCLK */
+
[linux-sunxi] [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
added the common sun8i.dtsi and allwinner,sun8i compatible for common
sun8i features, I've referred the h3 dtsi by Jens Kuske.
accordingly modified the sun8i-a23.dtsi and a23 dts.
I don't have a23 device, however, dts got compiled.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
arch/arm/boot/dts/sun8i-a23.dtsi | 432 +--
arch/arm/boot/dts/sun8i.dtsi | 481 ++
4 files changed, 486 insertions(+), 439 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
index dd31c53..b3f19e7 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -16,10 +16,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -55,5 +51,5 @@
/ {
model = Ippo Q8H Dual Core Tablet (v1.2);
- compatible = ippo,q8h-v1.2, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v1.2, allwinner,sun8i, allwinner,sun8i-a23;
};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index f5658d1..5db4010 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -57,7 +53,7 @@
/ {
model = Ippo Q8H Dual Core Tablet (v5);
- compatible = ippo,q8h-v5, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v5, allwinner,sun8i, allwinner,sun8i-a23;
aliases {
serial0 = r_uart;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6d6eda3..c17be9e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -47,41 +43,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include skeleton.dtsi
-
-#include dt-bindings/interrupt-controller/arm-gic.h
-
-#include dt-bindings/pinctrl/sun4i-a10.h
+#include sun8i.dtsi
/ {
- interrupt-parent = gic;
-
- chosen {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- framebuffer@0 {
- compatible = allwinner,simple-framebuffer,
-simple-framebuffer;
- allwinner,pipeline = de_be0-lcd0;
- clocks = pll6 0;
- status = disabled;
- };
- };
-
- timer {
- compatible = arm,armv7-timer;
- interrupts = GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW);
- clock-frequency = 2400;
- arm,cpu-registers-not-fw-configured;
- };
-
cpus {
- enable-method = allwinner,sun8i-a23;
+ enable-method = allwinner,sun8i;
#address-cells = 1;
#size-cells = 0;
@@ -103,32 +69,6 @@
};
clocks {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = 0;
- compatible = fixed-clock;
- clock-frequency = 2400;
- clock-output-names = osc24M;
- };
-
- osc32k: osc32k_clk {
- #clock-cells = 0;
- compatible = fixed-clock;
- clock-frequency = 32768;
-
[linux-sunxi] [PATCH 6/6] ARM: dts: sun8i: Add ET-Q8 A33 support
ET-Q8_A33 is A33 based cheap tablet in common Q8 format.
It has 512MB RAM, 4GB Nand, 7 Display, RDA5900P wifi, GSL1680 touch, etc.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/Makefile| 3 +-
arch/arm/boot/dts/sun8i-a33-et-q8.dts | 108 ++
2 files changed, 110 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/sun8i-a33-et-q8.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 82f4b9b..d44b1d6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -570,7 +570,8 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-wexler-tab7200.dtb
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a33-et-q8.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-a33-et-q8.dts
b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
new file mode 100644
index 000..260d5a3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33-et-q8.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar vishnupatekar0...@gmail.com
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include sun8i-a33.dtsi
+#include sunxi-common-regulators.dtsi
+
+#include dt-bindings/gpio/gpio.h
+#include dt-bindings/input/input.h
+#include dt-bindings/pinctrl/sun4i-a10.h
+
+/ {
+ model = ET Q8 A33 ;
+ compatible = et-q8-q33, allwinner,sun8i, allwinner,sun8i-a33;
+
+ aliases {
+ serial0 = uart0;
+ };
+
+ chosen {
+ bootargs = earlyprintk console=ttyS0,115200;
+ };
+};
+
+lradc {
+ vref-supply = reg_vcc3v0;
+ status = okay;
+
+ button@200 {
+ label = Volume Up;
+ linux,code = KEY_VOLUMEUP;
+ channel = 0;
+ voltage = 20;
+ };
+
+ button@400 {
+ label = Volume Down;
+ linux,code = KEY_VOLUMEDOWN;
+ channel = 0;
+ voltage = 40;
+ };
+};
+
+i2c0 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c0_pins_a;
+ status = okay;
+};
+
+i2c1 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c1_pins_a;
+ status = okay;
+};
+
+i2c2 {
+ pinctrl-names = default;
+ pinctrl-0 = i2c2_pins_a;
+ /* pull-ups and devices require PMIC regulator */
+ status = failed;
+};
+
+uart0 {
+ pinctrl-names = default;
+ pinctrl-0 = uart0_pins_a;
+ status = okay;
+};
--
1.9.1
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[linux-sunxi] [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include sun8i.dtsi
+
+/ {
+ cpus {
+ enable-method = allwinner,sun8i;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 0;
+ };
+
+ cpu@1 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 1;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 3;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ clock-output-names = pll5;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun8i-a23-axi-clk;
+ reg = 0x01c20050 0x4;
+ clocks = cpu;
+ clock-output-names = axi;
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun8i-a23-ahb1-gates-clk;
+ reg = 0x01c20060 0x8;
+ clocks = ahb1;
+ clock-output-names = ahb1_mipidsi, ahb1_dma,
+ ahb1_mmc0, ahb1_mmc1, ahb1_mmc2,
+ ahb1_nand, ahb1_sdram,
+ ahb1_hstimer, ahb1_spi0,
+ ahb1_spi1, ahb1_otg, ahb1_ehci,
+ ahb1_ohci, ahb1_ve, ahb1_lcd,
+ ahb1_csi, ahb1_be, ahb1_fe,
+ ahb1_gpu, ahb1_spinlock,
+
[linux-sunxi] [PATCH 1/6] ARM: sunxi: Add Machine support for A33
Allwinnner A33 quad core cortex-a7 based SOC.
It is similar to A23.
Renamed cpu method to allwinner,sun8i for common sun8i smp.
smp code is generic for A23, A33 and hopefully H3.
Signed-off-by: Vishnu Patekar vishnupatekar0...@gmail.com
---
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/Kconfig | 2 +-
arch/arm/mach-sunxi/platsmp.c | 2 +-
arch/arm/mach-sunxi/sunxi.c | 4 ++--
4 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt
b/Documentation/devicetree/bindings/arm/sunxi.txt
index 42941fd..e32f082 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -9,4 +9,5 @@ using one of the following compatible strings:
allwinner,sun6i-a31
allwinner,sun7i-a20
allwinner,sun8i-a23
+ allwinner,sun8i-a33
allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 81502b9..38bedd8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -35,7 +35,7 @@ config MACH_SUN7I
select SUN5I_HSTIMER
config MACH_SUN8I
- bool Allwinner A23 (sun8i) SoCs support
+ bool Allwinner (sun8i) SoCs support
default ARCH_SUNXI
select ARM_GIC
select MFD_SUN6I_PRCM
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index e8483ec..c56b501 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -189,4 +189,4 @@ struct smp_operations sun8i_smp_ops __initdata = {
.smp_prepare_cpus = sun8i_smp_prepare_cpus,
.smp_boot_secondary = sun8i_smp_boot_secondary,
};
-CPU_METHOD_OF_DECLARE(sun8i_a23_smp, allwinner,sun8i-a23, sun8i_smp_ops);
+CPU_METHOD_OF_DECLARE(sun8i_smp, allwinner,sun8i, sun8i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 1bc811a..8937d0d 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,11 +66,11 @@ DT_MACHINE_START(SUN7I_DT, Allwinner sun7i (A20) Family)
MACHINE_END
static const char * const sun8i_board_dt_compat[] = {
- allwinner,sun8i-a23,
+ allwinner,sun8i,
NULL,
};
-DT_MACHINE_START(SUN8I_DT, Allwinner sun8i (A23) Family)
+DT_MACHINE_START(SUN8I_DT, Allwinner sun8i Family)
.dt_compat = sun8i_board_dt_compat,
.init_late = sunxi_dt_cpufreq_init,
MACHINE_END
--
1.9.1
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[linux-sunxi] [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
A33 clock control unit is similar to A23.
A33 specific clocks are not yet implemented, added CLK_OF_DECLARE
to get it compiled for A33.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 7e1e2bd..6d25e4e 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1389,6 +1389,7 @@ static void __init sun6i_init_clocks(struct device_node
*node)
CLK_OF_DECLARE(sun6i_a31_clk_init, allwinner,sun6i-a31, sun6i_init_clocks);
CLK_OF_DECLARE(sun6i_a31s_clk_init, allwinner,sun6i-a31s, sun6i_init_clocks);
CLK_OF_DECLARE(sun8i_a23_clk_init, allwinner,sun8i-a23, sun6i_init_clocks);
+CLK_OF_DECLARE(sun8i_a33_clk_init, allwinner,sun8i-a33, sun6i_init_clocks);
static void __init sun9i_init_clocks(struct device_node *node)
{
--
1.9.1
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Re: [linux-sunxi] Re: UART SIR mode register
On Sat, 2015-05-09 at 05:52 -0700, stul...@gmail.com wrote: On Friday, May 8, 2015 at 12:31:52 PM UTC+3, stu...@gmail.com wrote: Dear All; I would like to enable SIR mode in UART modem control register for only one of my UART ports. I am planning to transceive IrDa by using that port. In A20 User manual, page 655, it states that 6th bit of UART_MCR register controls this mode. In Android SDK for A20, when I search for UART_MCR_SIRE, it finds only at sw_uart.h, but it seems this is not implemented in sw_uart.c In sunxi-kernel, there is no such define at all. Can you please guide me, how can I enable SIR mode for only one of my UARTs ? Seems community is silent these days... Excellent case on how to ask help! When nobody responds to a question that's asked on Friday afternoon (depends on the timezone though) and no response has been received within 28 hours, follow up with an insult. Here's a hint: the silence could be because we don't know an answer and/or your question was incomplete (ie. what kernel, what device). Päikest, Priit :) -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
This seems to only contain stuff which can be shared with the a23 dts,
why is this not all in the common sun8i.dtsi ?
Regards,
Hans
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217 +++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include sun8i.dtsi
+
+/ {
+ cpus {
+ enable-method = allwinner,sun8i;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 0;
+ };
+
+ cpu@1 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 1;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 3;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ clock-output-names = pll5;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun8i-a23-axi-clk;
+ reg = 0x01c20050 0x4;
+ clocks = cpu;
+ clock-output-names = axi;
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun8i-a23-ahb1-gates-clk;
+ reg = 0x01c20060 0x8;
+ clocks = ahb1;
+ clock-output-names = ahb1_mipidsi, ahb1_dma,
+ ahb1_mmc0, ahb1_mmc1, ahb1_mmc2,
+ ahb1_nand, ahb1_sdram,
+ ahb1_hstimer, ahb1_spi0,
+ ahb1_spi1, ahb1_otg, ahb1_ehci,
+
[linux-sunxi] Re: [PATCH 4/6] ARM: dts: sunxi: add common sun8i dtsi
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
added the common sun8i.dtsi and allwinner,sun8i compatible for common
sun8i features, I've referred the h3 dtsi by Jens Kuske.
accordingly modified the sun8i-a23.dtsi and a23 dts.
I don't have a23 device, however, dts got compiled.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
Please edit ~/.gitconfig and add:
[diff]
renames = copies
And then resend this patch to make it easier to review what is
actually changing.
Thanks,
Hans
---
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts | 6 +-
arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts | 6 +-
arch/arm/boot/dts/sun8i-a23.dtsi | 432 +--
arch/arm/boot/dts/sun8i.dtsi | 481 ++
4 files changed, 486 insertions(+), 439 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
index dd31c53..b3f19e7 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -16,10 +16,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -55,5 +51,5 @@
/ {
model = Ippo Q8H Dual Core Tablet (v1.2);
- compatible = ippo,q8h-v1.2, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v1.2, allwinner,sun8i, allwinner,sun8i-a23;
};
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
index f5658d1..5db4010 100644
--- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -57,7 +53,7 @@
/ {
model = Ippo Q8H Dual Core Tablet (v5);
- compatible = ippo,q8h-v5, allwinner,sun8i-a23;
+ compatible = ippo,q8h-v5, allwinner,sun8i, allwinner,sun8i-a23;
aliases {
serial0 = r_uart;
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 6d6eda3..c17be9e 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -18,10 +18,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
*
* Or, alternatively,
*
@@ -47,41 +43,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include skeleton.dtsi
-
-#include dt-bindings/interrupt-controller/arm-gic.h
-
-#include dt-bindings/pinctrl/sun4i-a10.h
+#include sun8i.dtsi
/ {
- interrupt-parent = gic;
-
- chosen {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- framebuffer@0 {
- compatible = allwinner,simple-framebuffer,
-simple-framebuffer;
- allwinner,pipeline = de_be0-lcd0;
- clocks = pll6 0;
- status = disabled;
- };
- };
-
- timer {
- compatible = arm,armv7-timer;
- interrupts = GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW),
-GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW);
- clock-frequency = 2400;
- arm,cpu-registers-not-fw-configured;
- };
-
cpus {
- enable-method = allwinner,sun8i-a23;
+ enable-method = allwinner,sun8i;
#address-cells = 1;
#size-cells = 0;
@@ -103,32 +69,6 @@
};
clocks {
- #address-cells = 1;
- #size-cells = 1;
- ranges;
-
- osc24M: osc24M_clk {
- #clock-cells = 0;
- compatible = fixed-clock;
- clock-frequency = 2400;
-
[linux-sunxi] Re: [PATCH 3/6] clk: sunxi: Add A33 clock for compilation
Hi, On Sun, May 10, 2015 at 12:16:20PM +0530, Vishnu Patekar wrote: A33 clock control unit is similar to A23. A33 specific clocks are not yet implemented, added CLK_OF_DECLARE to get it compiled for A33. That commit log doesn't make any sense. What you're doing isn't about whether or not that will be compiled, but whether you're registering the clocks and which clocks you protect. Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com Isn't it supposed to have a space in the middle of your name, just like you have in your mail address? Thanks, Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner A33 DTSI
Hi,
On 10-05-15 11:33, Vishnu Patekar wrote:
Hi,
On Sun, May 10, 2015 at 2:23 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 10-05-15 08:46, Vishnu Patekar wrote:
this is based on common sun8i.dtsi patch.
sun8i-a23.dtsi and sun8i-a33.dtsi are same, A33 specific features
e.g. clocks can be added in future.
Signed-off-by: VishnuPatekar vishnupatekar0...@gmail.com
This seems to only contain stuff which can be shared with the a23 dts,
why is this not all in the common sun8i.dtsi ?
Allwinner H3 is also sun8i, I've referred the referred the H3 dtsi
patch sent by Jens Kuske.
I've added common parts bet a23 and h3 in sun8i.dtsi.
Ah, I see, ok that works for me.
Regards,
Hans
same note added in common sun8i PATCH 4, which I'm going to resend
after your comment.
Regards,
Hans
---
arch/arm/boot/dts/sun8i-a33.dtsi | 217
+++
1 file changed, 217 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-a33.dtsi
diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi
b/arch/arm/boot/dts/sun8i-a33.dtsi
new file mode 100644
index 000..32489fc
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the Software), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include sun8i.dtsi
+
+/ {
+ cpus {
+ enable-method = allwinner,sun8i;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 0;
+ };
+
+ cpu@1 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 1;
+ };
+
+ cpu@2 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 2;
+ };
+
+ cpu@3 {
+ compatible = arm,cortex-a7;
+ device_type = cpu;
+ reg = 3;
+ };
+ };
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ clocks {
+ /* dummy clock until actually implemented */
+ pll5: pll5_clk {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 0;
+ clock-output-names = pll5;
+ };
+
+ axi: axi_clk@01c20050 {
+ #clock-cells = 0;
+ compatible = allwinner,sun8i-a23-axi-clk;
+ reg = 0x01c20050 0x4;
+ clocks = cpu;
+ clock-output-names = axi;
+ };
+
+ ahb1_gates: clk@01c20060 {
+ #clock-cells = 1;
+ compatible = allwinner,sun8i-a23-ahb1-gates-clk;
+ reg = 0x01c20060 0x8;
[linux-sunxi] how to get latest sunxi ?
Hi, how can I get the lastest sunxi for A20 ? I see here a lot of improvements but the git is stuck on 2014 ... Maybe I don't look on the good branch... Someone can advise me where to get the latest updates for sunxi ? Best regards, -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: UART SIR mode register
On Sun, 2015-05-10 at 19:01 +0300, Sertac Tüllük wrote: Thank you so much for your answer. You are also right about the question might be incomplete ( If so, pls let me know after re -reading my e-mail, and checking 8250-sunxi.c file in current kernel, and explaining by what is the relation between SIR mode of AXX UART and whichever AXX based DEVICE / KERNEL it is? ) [...] Now, could you please tell me, what is the rude thing about saying community is silent these days ? In your follow-up email, the word 'community' was quoted: http://en.wikipedia.org/wiki/Scare_quotes It might have been unintentional, but the quotes, also lack of detail in your request and the way those messages were timed is the reason I interpreted your follow-up as an insult. I am not blaming anybody, and not saying Hey, why don't you answer my question in 28 hours Still, I am soo thankful to everyone who contributed to this community, and if I can do to provide this functionality ( SIR mode in UART), I will try my best to write a patch file and a tutorial of controlling your IR devices by using your AXX hardware / sunxi -kernel. Regards. Päikest, Priit :) -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: UART SIR mode register
Thank you so much for your answer. You are also right about the question might be incomplete ( If so, pls let me know after re-reading my e-mail, and checking 8250-sunxi.c file in current kernel, and explaining by what is the relation between SIR mode of AXX UART and whichever AXX based DEVICE / KERNEL it is? ) However, I was expecting that at least someone who wrote / debug / test this driver : 1) Comment on the driver that nobody have defined UART_MCR register flags since the beginning. 2) Give an idea of how to implement this functionality in sunxi-kernel , just a comment. I love this community and I am very very thankful for this great work. I am trying to provide help as much as I can, - By asking some newbie questions since mid-2013 - By providing patch files for my hardware ( See: https://groups.google.com/forum/#!msg/linux-sunxi/OFdLuIlIotw/0hKTxXJBPnUJ or https://www.olimex.com/forum/index.php?topic=4245.0 ) - By providing some documentation : (See: http://dl.linux-sunxi.org/users/stulluk/ ) - By writing some pages to sunxi-wiki ( as an unexperienced newbie, see: http://linux-sunxi.org/Camera or http://linux-sunxi.org/FFmpeg ) - By communicating with other experienced contributors and sharing this information to help other people ( See: https://github.com/stulluk/FFmpeg-Cedrus ) Now, could you please tell me, what is the rude thing about saying community is silent these days ? I am not blaming anybody, and not saying Hey, why don't you answer my question in 28 hours Still, I am soo thankful to everyone who contributed to this community, and if I can do to provide this functionality ( SIR mode in UART), I will try my best to write a patch file and a tutorial of controlling your IR devices by using your AXX hardware / sunxi-kernel. Regards. 2015-05-10 11:28 GMT+03:00 Priit Laes pl...@plaes.org: On Sat, 2015-05-09 at 05:52 -0700, stul...@gmail.com wrote: On Friday, May 8, 2015 at 12:31:52 PM UTC+3, stu...@gmail.com wrote: Dear All; I would like to enable SIR mode in UART modem control register for only one of my UART ports. I am planning to transceive IrDa by using that port. In A20 User manual, page 655, it states that 6th bit of UART_MCR register controls this mode. In Android SDK for A20, when I search for UART_MCR_SIRE, it finds only at sw_uart.h, but it seems this is not implemented in sw_uart.c In sunxi-kernel, there is no such define at all. Can you please guide me, how can I enable SIR mode for only one of my UARTs ? Seems community is silent these days... Excellent case on how to ask help! When nobody responds to a question that's asked on Friday afternoon (depends on the timezone though) and no response has been received within 28 hours, follow up with an insult. Here's a hint: the silence could be because we don't know an answer and/or your question was incomplete (ie. what kernel, what device). Päikest, Priit :) -- You received this message because you are subscribed to a topic in the Google Groups linux-sunxi group. To unsubscribe from this topic, visit https://groups.google.com/d/topic/linux-sunxi/304ZGF85iUM/unsubscribe. To unsubscribe from this group and all its topics, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: UART SIR mode register
Thank you. I hope I could get some technical reply from the author of the driver some day. 2015-05-10 20:00 GMT+03:00 Priit Laes pl...@plaes.org: On Sun, 2015-05-10 at 19:01 +0300, Sertac Tüllük wrote: Thank you so much for your answer. You are also right about the question might be incomplete ( If so, pls let me know after re -reading my e-mail, and checking 8250-sunxi.c file in current kernel, and explaining by what is the relation between SIR mode of AXX UART and whichever AXX based DEVICE / KERNEL it is? ) [...] Now, could you please tell me, what is the rude thing about saying community is silent these days ? In your follow-up email, the word 'community' was quoted: http://en.wikipedia.org/wiki/Scare_quotes It might have been unintentional, but the quotes, also lack of detail in your request and the way those messages were timed is the reason I interpreted your follow-up as an insult. I am not blaming anybody, and not saying Hey, why don't you answer my question in 28 hours Still, I am soo thankful to everyone who contributed to this community, and if I can do to provide this functionality ( SIR mode in UART), I will try my best to write a patch file and a tutorial of controlling your IR devices by using your AXX hardware / sunxi -kernel. Regards. Päikest, Priit :) -- You received this message because you are subscribed to a topic in the Google Groups linux-sunxi group. To unsubscribe from this topic, visit https://groups.google.com/d/topic/linux-sunxi/304ZGF85iUM/unsubscribe. To unsubscribe from this group and all its topics, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
