[linux-sunxi] [PATCH v3 2/5] ARM: sun5i: Add R8 DTSI

2015-10-09 Thread Maxime Ripard 
The R8 is very close to the A13, but it still has a few differences,
notably a composite output, which the A13 lacks.

Add a DTSI based on the A13's to hold those differences.

Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
Reviewed-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i-r8.dtsi | 59 +
 1 file changed, 59 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi

diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
new file mode 100644
index ..0ef865601ac9
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2015 Free Electrons
+ * Copyright 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun5i-a13.dtsi"
+
+/ {
+   chosen {
+   framebuffer@1 {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "de_be0-lcd0-tve0";
+   clocks = < 1>, <_gates 34>, <_gates 36>,
+<_gates 44>;
+   status = "disabled";
+   };
+   };
+};
-- 
2.5.3

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[linux-sunxi] [PATCH v3 4/5] ARM: sun5i: dt: Add UART3 CTS and RTS pins

2015-10-09 Thread Maxime Ripard 
Add a separate pinctrl node for the UART3 CTS and RTS pins shared between
the A10s and A13.

Signed-off-by: Maxime Ripard 
Reviewed-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 433c83a321ca..7d355e52efe2 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -536,6 +536,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   uart3_pins_cts_rts_a: uart3-cts-rts@0 {
+   allwinner,pins = "PG11", "PG12";
+   allwinner,function = "uart3";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
 
timer@01c20c00 {
-- 
2.5.3

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[linux-sunxi] [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

2015-10-09 Thread Maxime Ripard 
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.

Signed-off-by: Maxime Ripard 
Reviewed-by: Hans de Goede 
---
 arch/arm/boot/dts/Makefile  |   3 +-
 arch/arm/boot/dts/sun5i-r8-chip.dts | 213 
 2 files changed, 215 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 342ab3116feb..bf165ed4e7fa 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
sun5i-a13-q8-tablet.dtb \
-   sun5i-a13-utoo-p66.dtb
+   sun5i-a13-utoo-p66.dtb \
+   sun5i-r8-chip.dtb
 dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
sun6i-a31-colombus.dtb \
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts 
b/arch/arm/boot/dts/sun5i-r8-chip.dts
new file mode 100644
index ..0d450a828372
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -0,0 +1,213 @@
+/*
+ * Copyright 2015 Free Electrons
+ * Copyright 2015 NextThing Co
+ *
+ * Maxime Ripard 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-r8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+
+/ {
+   model = "NextThing C.H.I.P.";
+   compatible = "nextthing,chip", "allwinner,sun5i-r8";
+
+   aliases {
+   i2c0 = 
+   i2c2 = 
+   serial0 = 
+   serial1 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+
+   axp209: pmic@34 {
+   reg = <0x34>;
+
+   /*
+* The interrupt is routed through the "External Fast
+* Interrupt Request" pin (ball G13 of the module)
+* directly to the main interrupt controller, without
+* any other controller interfering.
+*/
+   interrupts = <0>;
+   };
+};
+
+#include "axp209.dtsi"
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+
+   xio: gpio@38 {
+   compatible = "nxp,pcf8574a";
+   reg = <0x38>;
+
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   interrupt-parent = <>;
+   interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   non-removable;

[linux-sunxi] [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI

2015-10-09 Thread Maxime Ripard 
The uart3 pins are shared between the A10s and A13, move the pinctrl node
to the common DTSI to avoid duplication.

Signed-off-by: Maxime Ripard 
Reviewed-by: Hans de Goede 
---
 arch/arm/boot/dts/sun5i-a10s.dtsi | 7 ---
 arch/arm/boot/dts/sun5i.dtsi  | 7 +++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi 
b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 0fdabe8eb9e8..2ebd32f5bc6e 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -204,13 +204,6 @@
allwinner,pull = ;
};
 
-   uart3_pins_a: uart3@0 {
-   allwinner,pins = "PG9", "PG10";
-   allwinner,function = "uart3";
-   allwinner,drive = ;
-   allwinner,pull = ;
-   };
-
emac_pins_a: emac0@0 {
allwinner,pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 78b993abbaa3..433c83a321ca 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -529,6 +529,13 @@
allwinner,drive = ;
allwinner,pull = ;
};
+
+   uart3_pins_a: uart3@0 {
+   allwinner,pins = "PG9", "PG10";
+   allwinner,function = "uart3";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
};
 
timer@01c20c00 {
-- 
2.5.3

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[linux-sunxi] [PATCH v3 1/5] ARM: sunxi: Add R8 support

2015-10-09 Thread Maxime Ripard 
The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.

In order to have a consistent naming, instead of mentionning the allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.

Signed-off-by: Maxime Ripard 
Reviewed-by: Hans de Goede 
Acked-by: Stephen Boyd 
---
 Documentation/arm/sunxi/README  | 2 +-
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 3 ++-
 drivers/clk/sunxi/clk-sunxi.c   | 1 +
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index 5e38e1582f95..430d279a8df3 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -25,7 +25,7 @@ SunXi family
 + Datasheet
   
http://dl.linux-sunxi.org/A10s/A10s%20Datasheet%20-%20v1.20%20%282012-03-27%29.pdf
 
-  - Allwinner A13 (sun5i)
+  - Allwinner A13 / R8 (sun5i)
 + Datasheet
  
http://dl.linux-sunxi.org/A13/A13%20Datasheet%20-%20v1.12%20%282012-03-29%29.pdf
 + User Manual
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index 67da20539540..bb9b0faa919d 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -6,6 +6,7 @@ using one of the following compatible strings:
   allwinner,sun4i-a10
   allwinner,sun5i-a10s
   allwinner,sun5i-a13
+  allwinner,sun5i-r8
   allwinner,sun6i-a31
   allwinner,sun7i-a20
   allwinner,sun8i-a23
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 65bab2876343..8583a9ca86bd 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -26,10 +26,11 @@ static const char * const sunxi_board_dt_compat[] = {
"allwinner,sun4i-a10",
"allwinner,sun5i-a10s",
"allwinner,sun5i-a13",
+   "allwinner,sun5i-r8",
NULL,
 };
 
-DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
+DT_MACHINE_START(SUNXI_DT, "Allwinner sun4i/sun5i Families")
.dt_compat  = sunxi_board_dt_compat,
.init_late  = sunxi_dt_cpufreq_init,
 MACHINE_END
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 413070d07b3f..9c79af0c03b2 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1196,6 +1196,7 @@ static void __init sun5i_init_clocks(struct device_node 
*node)
 }
 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
 CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
+CLK_OF_DECLARE(sun5i_r8_clk_init, "allwinner,sun5i-r8", sun5i_init_clocks);
 CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
 
 static const char *sun6i_critical_clocks[] __initdata = {
-- 
2.5.3

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[linux-sunxi] External Interrupts on kernel 3.4.x

2015-10-09 Thread Sgufa 
Hello,
has anyone experience with EINT pins on A20?

My goal is to discriminate between raising and falling edge on the same pin. I 
need to measure the time between the two edges and print it to dmesg. If i 
export the edge detection to both i can only see the number of interrupts in 
/proc/interrupts. I need to separately detect the two edges, both rising and 
falling ones, in order to measure the time between them.

Any help would be much appreciated.

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Re: [linux-sunxi] DCDC2 (VDD-SYS) voltage for A23/A33?

2015-10-09 Thread Maxime Ripard 
On Wed, Oct 07, 2015 at 12:43:13AM +0800, wens Tsai wrote:
> >> On the side, I'm wondering if we can put the voltage ranges for
> >> important regulators directly in the axp dtsi. It's likely most
> >> boards follow the reference design, and will use the regulators
> >> accordingly.
> >>
> >> We could also do this for A31/A31s paired with AXP221/AXP221s.
> >> Since I already have a patch for axp221.dtsi, I can incorporate
> >> the changes.
> >
> > That doesn't really work unfortunately. We're seeing some combination
> > of the PMICs and the SoCs that have different boundaries, for example,
> > while the AXP209 is used on the A10 and A20 that have an upper
> > boundary of 1.4V for the CPU regulator, while it's also used with the
> > R8 that has a limit at 1.3V.
> 
> I understand. I'm just saying it's doable for the A31/AXP221 pair,
> and the AXP223/A23/A33 pairs. I think we won't be seeing new chips
> paired with them. The A80 and A83 both have their own companion
> PMICs, and the H3 doesn't seem to use one in designs we've seen.
> The A31 and A31s have the same tolerances, as do the A23 and A33.

Thing is, we can probably expect the same behaviour when the R* and H*
designs will be out.

I'd really just prefer to leave the glue between the PMIC and the SoC
in the board DTS, and not make any assumption about what PMIC is
associated with what SoC in the DTSI.

Maxime

-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[linux-sunxi] [PATCH v3 0/5] ARM: sunxi: Introduce CHIP support

2015-10-09 Thread Maxime Ripard 
Hi,

Here is a serie introducing the support for the Allwinner R8 and the
Nextthing's CHIP.

Support is almost complete for the CHIP itself, the only missing part
for now is the WiFi chip that needs to be powered through two combined
regulators (AXP209's LDO3 and LDO4). The audio codec is also missing
since it's not already enabled in the DT.

Both these features will be addressed eventually.

Let me know what you think,
Maxime

Changes from v2:
  - Fixed whitespace issue
  - Changed DTSI include to R8
  - Removed i2c1 to be consitent with the other boards

Changes from v1:
  - Collected tags
  - Removed unused include files
  - Removed ipsout, dram and vcc regulators
  - Added USB power supply

Maxime Ripard (5):
  ARM: sunxi: Add R8 support
  ARM: sun5i: Add R8 DTSI
  ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI
  ARM: sun5i: dt: Add UART3 CTS and RTS pins
  ARM: sun5i: Add C.H.I.P DTS

 Documentation/arm/sunxi/README  |   2 +-
 Documentation/devicetree/bindings/arm/sunxi.txt |   1 +
 arch/arm/boot/dts/Makefile  |   3 +-
 arch/arm/boot/dts/sun5i-a10s.dtsi   |   7 -
 arch/arm/boot/dts/sun5i-r8-chip.dts | 213 
 arch/arm/boot/dts/sun5i-r8.dtsi |  59 +++
 arch/arm/boot/dts/sun5i.dtsi|  14 ++
 arch/arm/mach-sunxi/sunxi.c |   3 +-
 drivers/clk/sunxi/clk-sunxi.c   |   1 +
 9 files changed, 293 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
 create mode 100644 arch/arm/boot/dts/sun5i-r8.dtsi

-- 
2.5.3

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Re: [linux-sunxi] [PATCH] ARM: dts: sun7i: Correct USB regulators on pcDuino v3 Nano

2015-10-09 Thread Chen-Yu Tsai 
Hi,

On Sat, Oct 10, 2015 at 9:47 AM, Adam Sampson  wrote:
> The LinkSprite pcDuino v3 Nano's two USB host ports are powered by a
> single RT9701GB regulator, which has its enable input tied to the A20's
> PD2 pin, pulled up to 3v3 via a 10k resistor.
>
> However, the script.bin that shipped with the device listed PH11 and PH3
> as Vbus control pins for the two USB ports. Neither of these are
> actually connected to anything.
>
> Siarhei Siamashka spotted this problem while reviewing the other
> LinkSprite boards. This patch fixes it by only defining a single
> regulator, controlled by PD2. Testing shows that the USB ports are now
> (correctly) only powered up once the USB PHY driver is loaded.
>
> Signed-off-by: Adam Sampson 

Since Siarhei spotted the issue, maybe add a Reported-by tag where credit
is due?

> ---
>  arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 13 ++---
>  1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts 
> b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> index 5361fce..f75e3bd 100644
> --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> @@ -158,7 +158,7 @@
> };
>
> usb1_vbus_pin_pcduino3_nano: usb1_vbus_pin@0 {
> -   allwinner,pins = "PH11";
> +   allwinner,pins = "PD2";
> allwinner,function = "gpio_out";
> allwinner,drive = ;
> allwinner,pull = ;
> @@ -166,18 +166,17 @@
>  };
>
>  _ahci_5v {
> +   pinctrl-names = "default";

This is already in sunxi-common-regulators.dtsi.
No need to add it again.

> pinctrl-0 = <_pwr_pin_pcduino3_nano>;
> gpio = < 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
> status = "okay";
>  };
>
> +/* A single regulator (U24) powers both USB host ports. */
>  _usb1_vbus {
> +   pinctrl-names = "default";

And this.

The rest looks good.

Thanks!
ChenYu

> pinctrl-0 = <_vbus_pin_pcduino3_nano>;
> -   gpio = < 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
> -   status = "okay";
> -};
> -
> -_usb2_vbus {
> +   gpio = < 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
> status = "okay";
>  };
>
> @@ -189,6 +188,6 @@
>
>   {
> usb1_vbus-supply = <_usb1_vbus>;
> -   usb2_vbus-supply = <_usb2_vbus>;
> +   usb2_vbus-supply = <_usb1_vbus>;
> status = "okay";
>  };
> --
> 2.1.4
>
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[linux-sunxi] Re: [PATCH v3 00/12] pwm: add support for atomic update

2015-10-09 Thread Boris Brezillon 
Hi Thierry,

On Mon, 21 Sep 2015 11:33:17 +0200
Boris Brezillon  wrote:

> Hello,
> 
> This series adds support for atomic PWM update, or IOW, the capability
> to update all the parameters of a PWM device (enabled/disabled, period,
> duty and polarity) in one go.

Anything preventing this series from being applied (AKA ping)?

> 
> Best Regards,
> 
> Boris
> 
> Changes since v2:
> - rebased on top of 4.3-rc2
> - reintroduced pwm-regulator patches
> 
> Changes since v1:
> - dropped applied patches
> - squashed Heiko's fixes into the rockchip driver changes
> - made a few cosmetic changes
> - added kerneldoc comments
> - added Heiko's patch to display more information in debugfs
> - dropped pwm-regulator patches (should be submitted separately)
> 
> Boris Brezillon (11):
>   pwm: introduce default period and polarity concepts
>   pwm: define a new pwm_state struct
>   pwm: move the enabled/disabled info to pwm_state struct
>   backlight: pwm_bl: remove useless call to pwm_set_period
>   pwm: declare a default PWM state
>   pwm: add the PWM initial state retrieval infra
>   pwm: add the core infrastructure to allow atomic update
>   pwm: rockchip: add initial state retrieval
>   pwm: rockchip: add support for atomic update
>   regulator: pwm: implement ->enable(), ->disable() and ->is_enabled
> methods
>   regulator: pwm: properly initialize the ->state field
> 
> Heiko Stübner (1):
>   pwm: add information about polarity, duty cycle and period to debugfs
> 
>  drivers/leds/leds-pwm.c  |   2 +-
>  drivers/pwm/core.c   | 169 
> +++
>  drivers/pwm/pwm-pxa.c|   2 +-
>  drivers/pwm/pwm-rockchip.c   | 119 +++-
>  drivers/pwm/pwm-sun4i.c  |   3 +-
>  drivers/regulator/pwm-regulator.c|  65 --
>  drivers/video/backlight/lm3630a_bl.c |   4 +-
>  drivers/video/backlight/pwm_bl.c |  10 ++-
>  drivers/video/fbdev/ssd1307fb.c  |   2 +-
>  include/linux/pwm.h  |  89 +++---
>  10 files changed, 392 insertions(+), 73 deletions(-)
> 



-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] [PATCH v2 1/3] ARM: dts: sun4i: Allow to use the PH6 pin for GPIO on pcDuino1/2

2015-10-09 Thread Siarhei Siamashka 
The pcDuino1 board does not use any power switches at all for its
two USB host ports and the VBUS pins are always connected to 5V.

The pcDuino2 board uses the RT9701GB power switch for its single
USB host port, but the USB_EN pin (PD2) is pulled up with a 10K
resistor. So that the USB power is still enabled by default,
resulting in the same behaviour as pcDuino1 if nobody touches
the PD2 pin. This minor difference is going to be handled in a
follow-up patch, introducing a separate dts file for pcDuino2.

The primary reason for this fix is that the current dts file
unnecessarily meddles with the PH3 and PH6 pins. But the PH6 pin
is available on the Arduino-compatible expansion header and may
have a better use for other purposes. This patch fixes the
problem and now the PH6 pin can be used with the GPIO sysfs
interface. Tested on a pcDuino2 board with a multimeter:

echo 230 > /sys/class/gpio/export
echo "out" > /sys/class/gpio/gpio230/direction
echo 0 > /sys/class/gpio/gpio230/value
echo 1 > /sys/class/gpio/gpio230/value

USB still works as expected too.

Signed-off-by: Siarhei Siamashka 
---
 arch/arm/boot/dts/sun4i-a10-pcduino.dts | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts 
b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index c882421..0b45d27 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -180,14 +180,6 @@
};
 };
 
-_usb1_vbus {
-   status = "okay";
-};
-
-_usb2_vbus {
-   status = "okay";
-};
-
 #include "axp209.dtsi"
 
 _dcdc2 {
@@ -222,7 +214,7 @@
 };
 
  {
-   usb1_vbus-supply = <_usb1_vbus>;
-   usb2_vbus-supply = <_usb2_vbus>;
+   usb1_vbus-supply = <_vcc5v0>; /* USB1 VBUS is always on */
+   usb2_vbus-supply = <_vcc5v0>; /* USB2 VBUS is always on */
status = "okay";
 };
-- 
2.4.9

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[linux-sunxi] [PATCH v2 2/3] ARM: sun4i: dt: Add new LinkSprite pcDuino2 board

2015-10-09 Thread Siarhei Siamashka 
The LinkSprite pcDuino2 board is almost identical to the older
LinkSprite pcDuino1 board according to the schematic pdf files.
So we just include the existing "sun4i-a10-pcduino.dts" file and
make the necessary adjustments.

Signed-off-by: Siarhei Siamashka 
---
 arch/arm/boot/dts/Makefile   |  3 +-
 arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 78 
 2 files changed, 80 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun4i-a10-pcduino2.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 342ab31..c10d5aa 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -587,7 +587,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
-   sun4i-a10-pcduino.dtb
+   sun4i-a10-pcduino.dtb \
+   sun4i-a10-pcduino2.dtb
 dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino2.dts 
b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts
new file mode 100644
index 000..de483a1
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino2.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2015 Siarhei Siamashka 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * The LinkSprite pcDuino2 board is almost identical to the older
+ * LinkSprite pcDuino1 board. The only software visible difference
+ * is that the pcDuino2 board got a USB VBUS voltage regulator, which
+ * is controlled by the PD2 pin (pulled-up by default). Also one of
+ * the USB host ports has been replaced with a USB WIFI chip.
+ */
+
+#include "sun4i-a10-pcduino.dts"
+
+/ {
+   model = "LinkSprite pcDuino2";
+   compatible = "linksprite,a10-pcduino2", "allwinner,sun4i-a10";
+};
+
+ {
+   usb2_vbus_pin_pcduino2: usb2_vbus_pin@0 {
+   allwinner,pins = "PD2";
+   allwinner,function = "gpio_out";
+   allwinner,drive = ;
+   allwinner,pull = ;
+   };
+};
+
+_usb2_vbus {
+   pinctrl-names = "default";
+   pinctrl-0 = <_vbus_pin_pcduino2>;
+   gpio = < 3 2 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+};
+
+ {
+   usb1_vbus-supply = <_vcc3v3>; /* USB WIFI is always on */
+   usb2_vbus-supply = <_usb2_vbus>;
+   status = "okay";
+};
-- 
2.4.9

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[linux-sunxi] [PATCH v2 0/3] ARM: dts: sun4i: Enable USB DRC and voltage-scaling on pcDuino1/2

2015-10-09 Thread Siarhei Siamashka 
Hello,

This is the v2 of the older patches from:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-October/374377.html

Changes since v1:
- The voltage scaling patch (AXP209 PMU regulators) has been already
  applied by Maxime, so it is not included in this patch set anymore.
- A new patch with a separate dts for pcDuino2 has been added,
  as had been requested during the previous review round.
- Instead of removing "usb1_vbus-supply" and "usb2_vbus-supply",
  they now refer to "reg_vcc5v0" (this had been discussed on IRC).

Siarhei Siamashka (3):
  ARM: dts: sun4i: Allow to use the PH6 pin for GPIO on pcDuino1/2
  ARM: sun4i: dt: Add new LinkSprite pcDuino2 board
  ARM: dts: sun4i: Enable USB DRC on pcDuino1/2

 arch/arm/boot/dts/Makefile   |  3 +-
 arch/arm/boot/dts/sun4i-a10-pcduino.dts  | 29 
 arch/arm/boot/dts/sun4i-a10-pcduino2.dts | 78 
 3 files changed, 100 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun4i-a10-pcduino2.dts

-- 
2.4.9

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Re: [linux-sunxi] DCDC2 (VDD-SYS) voltage for A23/A33?

2015-10-09 Thread wens Tsai 
On Fri, Oct 9, 2015 at 4:56 PM, Maxime Ripard
 wrote:
> On Wed, Oct 07, 2015 at 12:43:13AM +0800, wens Tsai wrote:
>> >> On the side, I'm wondering if we can put the voltage ranges for
>> >> important regulators directly in the axp dtsi. It's likely most
>> >> boards follow the reference design, and will use the regulators
>> >> accordingly.
>> >>
>> >> We could also do this for A31/A31s paired with AXP221/AXP221s.
>> >> Since I already have a patch for axp221.dtsi, I can incorporate
>> >> the changes.
>> >
>> > That doesn't really work unfortunately. We're seeing some combination
>> > of the PMICs and the SoCs that have different boundaries, for example,
>> > while the AXP209 is used on the A10 and A20 that have an upper
>> > boundary of 1.4V for the CPU regulator, while it's also used with the
>> > R8 that has a limit at 1.3V.
>>
>> I understand. I'm just saying it's doable for the A31/AXP221 pair,
>> and the AXP223/A23/A33 pairs. I think we won't be seeing new chips
>> paired with them. The A80 and A83 both have their own companion
>> PMICs, and the H3 doesn't seem to use one in designs we've seen.
>> The A31 and A31s have the same tolerances, as do the A23 and A33.
>
> Thing is, we can probably expect the same behaviour when the R* and H*
> designs will be out.
>
> I'd really just prefer to leave the glue between the PMIC and the SoC
> in the board DTS, and not make any assumption about what PMIC is
> associated with what SoC in the DTSI.

Got it. Hopefully I'll send out the conversion patches today.

ChenYu

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[linux-sunxi] Re: [PATCH v3 3/5] ARM: sun5i: dt: Move uart3 pinctrl node to common DTSI

2015-10-09 Thread Chen-Yu Tsai 
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
 wrote:
> The uart3 pins are shared between the A10s and A13, move the pinctrl node
> to the common DTSI to avoid duplication.
>
> Signed-off-by: Maxime Ripard 
> Reviewed-by: Hans de Goede 

Reviewed-by: Chen-Yu Tsai 

Thanks

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[linux-sunxi] Re: [PATCH v3 1/5] ARM: sunxi: Add R8 support

2015-10-09 Thread Chen-Yu Tsai 
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
 wrote:
> The R8 is a new Allwinner SoC based on the A13. While both are very
> similar, there's still a few differences. Introduce a new compatible to
> deal with them.
>
> In order to have a consistent naming, instead of mentionning the allwinner
   ^   ^
nit:   mentioning  Allwinner

Fix when you apply?

> A series as the machine name, switch to sun4i/sun5i like what is done for
> the other families.
>
> Signed-off-by: Maxime Ripard 
> Reviewed-by: Hans de Goede 
> Acked-by: Stephen Boyd 

Reviewed-by: Chen-Yu Tsai 

Thanks

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[linux-sunxi] Re: [PATCH v3 4/5] ARM: sun5i: dt: Add UART3 CTS and RTS pins

2015-10-09 Thread Chen-Yu Tsai 
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
 wrote:
> Add a separate pinctrl node for the UART3 CTS and RTS pins shared between
> the A10s and A13.
>
> Signed-off-by: Maxime Ripard 
> Reviewed-by: Hans de Goede 

Reviewed-by: Chen-Yu Tsai 

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[linux-sunxi] Re: [PATCH v3 5/5] ARM: sun5i: Add C.H.I.P DTS

2015-10-09 Thread Chen-Yu Tsai 
On Fri, Oct 9, 2015 at 4:42 PM, Maxime Ripard
 wrote:
> The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
> RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
> and two connectors to plug additional boards on top of it.
>
> Signed-off-by: Maxime Ripard 
> Reviewed-by: Hans de Goede 
> ---
>  arch/arm/boot/dts/Makefile  |   3 +-
>  arch/arm/boot/dts/sun5i-r8-chip.dts | 213 
> 
>  2 files changed, 215 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/sun5i-r8-chip.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 342ab3116feb..bf165ed4e7fa 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -600,7 +600,8 @@ dtb-$(CONFIG_MACH_SUN5I) += \
> sun5i-a13-olinuxino.dtb \
> sun5i-a13-olinuxino-micro.dtb \
> sun5i-a13-q8-tablet.dtb \
> -   sun5i-a13-utoo-p66.dtb
> +   sun5i-a13-utoo-p66.dtb \
> +   sun5i-r8-chip.dtb
>  dtb-$(CONFIG_MACH_SUN6I) += \
> sun6i-a31-app4-evb1.dtb \
> sun6i-a31-colombus.dtb \
> diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts 
> b/arch/arm/boot/dts/sun5i-r8-chip.dts
> new file mode 100644
> index ..0d450a828372
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts

snip

> +_dcdc2 {
> +   regulator-min-microvolt = <100>;
> +   regulator-max-microvolt = <140>;
> +   regulator-name = "cpuvdd";

Other boards seem to follow the power pin names on the SoC and call
this "vdd-cpu".

> +   regulator-always-on;
> +};
> +
> +_dcdc3 {
> +   regulator-min-microvolt = <100>;
> +   regulator-max-microvolt = <130>;
> +   regulator-name = "corevdd";

And this was named "vdd-int" or "vdd-int-dll" (for SoCs with separate
VDD_DLL pins).

> +   regulator-always-on;
> +};
> +
> +_ldo1 {
> +   regulator-name = "rtcvdd";

And this one was "vdd-rtc".

I know you followed the names set in the design doc. Just wondering if there
should be some convention on these.

> +};
> +
> +_ldo2 {
> +   regulator-min-microvolt = <270>;
> +   regulator-max-microvolt = <330>;
> +   regulator-name = "avcc";
> +   regulator-always-on;
> +};
> +
> +_ldo5 {
> +   regulator-min-microvolt = <180>;
> +   regulator-max-microvolt = <180>;
> +   regulator-name = "vcc-1v8";
> +};
> +
> +_usb0_vbus {
> +   pinctrl-0 = <_vbus_pin>;
> +   vin-supply = <_vcc5v0>;
> +   gpio = < 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */

  status = "okay"; ?

The rest looks good.

Regards
ChenYu

> +};
> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_b>;
> +   status = "okay";
> +};
> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_pins_a>,
> +   <_pins_cts_rts_a>;
> +   status = "okay";
> +};
> +
> +_otg {
> +   dr_mode = "otg";
> +   status = "okay";
> +};
> +
> +_power_supply {
> +   status = "okay";
> +};
> +
> + {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <_id_det_pin>;
> +   status = "okay";
> +
> +   usb0_id_det-gpio = < 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
> +   usb0_vbus_power-supply = <_power_supply>;
> +   usb0_vbus-supply = <_usb0_vbus>;
> +   usb1_vbus-supply = <_vcc5v0>;
> +};
> --
> 2.5.3
>

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