Re: [linux-sunxi] A20 higher External interrupr (EINT22-EINT31)

[ivoronov]

Dear Andrea, Maxime & Co,

In the past I have set up EINT7 for my Cubie2 per manual 
http://linux-sunxi.org/External_interrupts and it works well on 3.19 through 
4.2 kernels.

In looking at audio sunxi-codec working I switched to 4.4-rc1 over the last 
week and discovered the following:
1) my module with EINT7 stop working
2) also EINT20 example from http://linux-sunxi.org/External_interrupts does not 
work "as is".

Any suggestion on what is going wrong?

Thank you,

Best regards,
Ivan

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[linux-sunxi] [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock

[Josef Gajdusek]

This patch adds a driver for the THS clock which is present on the
Allwinner H3.

Signed-off-by: Josef Gajdusek 
---
 Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
 drivers/clk/sunxi/Makefile|  1 +
 drivers/clk/sunxi/clk-h3-ths.c| 98 +++
 3 files changed, 100 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk-h3-ths.c

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 23e7bce..6d63b35 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -73,6 +73,7 @@ Required properties:
"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
+   "allwinner,sun8i-h3-ths-clk" - for THS on H3
 
 Required properties for all clocks:
 - reg : shall be the control register address for the clock.
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index f520af6..1bf8e1c 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o
 obj-y += clk-a10-mod1.o
 obj-y += clk-a10-pll2.o
 obj-y += clk-a20-gmac.o
+obj-y += clk-h3-ths.o
 obj-y += clk-mod0.o
 obj-y += clk-simple-gates.o
 obj-y += clk-sun8i-bus-gates.o
diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c
new file mode 100644
index 000..663afc0
--- /dev/null
+++ b/drivers/clk/sunxi/clk-h3-ths.c
@@ -0,0 +1,98 @@
+/*
+ * Sunxi THS clock driver
+ *
+ * Copyright (C) 2015 Josef Gajdusek
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define SUN8I_H3_THS_CLK_ENABLE31
+#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0
+#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2
+
+static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock);
+
+static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = {
+   { .val = 0, .div = 1 },
+   { .val = 1, .div = 2 },
+   { .val = 2, .div = 4 },
+   { .val = 3, .div = 6 },
+   { } /* sentinel */
+};
+
+static void __init sun8i_h3_ths_clk_setup(struct device_node *node)
+{
+   struct clk *clk;
+   struct clk_gate *gate;
+   struct clk_divider *div;
+   const char *parent;
+   const char *clk_name = node->name;
+   void __iomem *reg;
+   int err;
+
+   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+
+   if (IS_ERR(reg))
+   return;
+
+   gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!gate)
+   goto err_unmap;
+
+   div = kzalloc(sizeof(*gate), GFP_KERNEL);
+   if (!div)
+   goto err_gate_free;
+
+   of_property_read_string(node, "clock-output-names", _name);
+   parent = of_clk_get_parent_name(node, 0);
+
+   gate->reg = reg;
+   gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE;
+   gate->lock = _h3_ths_clk_lock;
+
+   div->reg = reg;
+   div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT;
+   div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH;
+   div->table = sun8i_h3_ths_clk_table;
+   div->lock = _h3_ths_clk_lock;
+
+   clk = clk_register_composite(NULL, clk_name, , 1,
+NULL, NULL,
+>hw, _divider_ops,
+>hw, _gate_ops,
+CLK_SET_RATE_PARENT);
+
+   if (IS_ERR(clk))
+   goto err_div_free;
+
+   err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+   if (err)
+   goto err_unregister_clk;
+
+   return;
+
+err_unregister_clk:
+   clk_unregister(clk);
+err_gate_free:
+   kfree(gate);
+err_div_free:
+   kfree(div);
+err_unmap:
+   iounmap(reg);
+}
+
+CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk",
+  sun8i_h3_ths_clk_setup);
-- 
2.4.10

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[linux-sunxi] [PATCH v2 5/5] ARM: dts: sun8i: Add THS node to the H3 .dtsi

[Josef Gajdusek]

This patch adds nodes for the THS driver and the THS clock to the Allwinner
H3 .dtsi file.

Signed-off-by: Josef Gajdusek 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 33 +
 1 file changed, 33 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 58de718..48500d4 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -77,6 +77,14 @@
};
};
 
+   thermal-zones {
+   cpu_thermal: cpu_thermal {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 0>;
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -236,6 +244,14 @@
"ahb1_ephy", "ahb1_dbg";
};
 
+   ths_clk: clk@01c20074 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ths-clk";
+   reg = <0x01c20074 0x4>;
+   clocks = <>;
+   clock-output-names = "ths";
+   };
+
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
@@ -364,6 +380,10 @@
reg = <0x01c14000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+
+   ths_calibration: calib@234 {
+   reg = <0x234 0x4>;
+   };
};
 
usbphy: phy@01c19400 {
@@ -529,6 +549,19 @@
interrupts = ;
};
 
+   ths: ths@01c25000 {
+   #thermal-sensor-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x88>;
+   interrupts = ;
+   resets = <_rst 104>;
+   reset-names = "ahb";
+   clocks = <_gates 72>, <_clk>;
+   clock-names = "ahb", "ths";
+   nvmem-cells = <_calibration>;
+   nvmem-cell-names = "calibration";
+   };
+
uart0: serial@01c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
-- 
2.4.10

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[linux-sunxi] [PATCH v2 3/5] thermal: Add a driver for the Allwinner THS sensor

[Josef Gajdusek]

This patch adds support for the Sunxi thermal sensor on the Allwinner H3.
Should be easily extendable for the A33/A83T/... as they have similar but
not completely identical sensors.

Signed-off-by: Josef Gajdusek 
---
 drivers/thermal/Kconfig |   7 +
 drivers/thermal/Makefile|   1 +
 drivers/thermal/sun8i_ths.c | 365 
 3 files changed, 373 insertions(+)
 create mode 100644 drivers/thermal/sun8i_ths.c

diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index c463c89..2b41147 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -365,6 +365,13 @@ config INTEL_PCH_THERMAL
  Thermal reporting device will provide temperature reading,
  programmable trip points and other information.
 
+config SUN8I_THS
+   tristate "sun8i THS driver"
+   depends on MACH_SUN8I
+   depends on OF
+   help
+ Enable this to support thermal reporting on some newer Allwinner SoCs.
+
 menu "Texas Instruments thermal drivers"
 depends on ARCH_HAS_BANDGAP || COMPILE_TEST
 source "drivers/thermal/ti-soc-thermal/Kconfig"
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cfae6a6..227e1a1 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -48,3 +48,4 @@ obj-$(CONFIG_INTEL_PCH_THERMAL)   += intel_pch_thermal.o
 obj-$(CONFIG_ST_THERMAL)   += st/
 obj-$(CONFIG_TEGRA_SOCTHERM)   += tegra_soctherm.o
 obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
+obj-$(CONFIG_SUN8I_THS)+= sun8i_ths.o
diff --git a/drivers/thermal/sun8i_ths.c b/drivers/thermal/sun8i_ths.c
new file mode 100644
index 000..2c976ac
--- /dev/null
+++ b/drivers/thermal/sun8i_ths.c
@@ -0,0 +1,365 @@
+/*
+ * Sunxi THS driver
+ *
+ * Copyright (C) 2015 Josef Gajdusek
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define THS_H3_CTRL0   0x00
+#define THS_H3_CTRL1   0x04
+#define THS_H3_CDAT0x14
+#define THS_H3_CTRL2   0x40
+#define THS_H3_INT_CTRL0x44
+#define THS_H3_STAT0x48
+#define THS_H3_ALARM_CTRL  0x50
+#define THS_H3_SHUTDOWN_CTRL   0x60
+#define THS_H3_FILTER  0x70
+#define THS_H3_CDATA   0x74
+#define THS_H3_DATA0x80
+
+#define THS_H3_CTRL0_SENSOR_ACQ0_OFFS   0
+#define THS_H3_CTRL0_SENSOR_ACQ0(x) \
+   ((x) << THS_H3_CTRL0_SENSOR_ACQ0_OFFS)
+#define THS_H3_CTRL1_ADC_CALI_EN_OFFS   17
+#define THS_H3_CTRL1_ADC_CALI_EN \
+   BIT(THS_H3_CTRL1_ADC_CALI_EN_OFFS)
+#define THS_H3_CTRL1_OP_BIAS_OFFS   20
+#define THS_H3_CTRL1_OP_BIAS(x) \
+   ((x) << THS_H3_CTRL1_OP_BIAS_OFFS)
+#define THS_H3_CTRL2_SENSE_EN_OFFS  0
+#define THS_H3_CTRL2_SENSE_EN \
+   BIT(THS_H3_CTRL2_SENSE_EN_OFFS)
+#define THS_H3_CTRL2_SENSOR_ACQ1_OFFS   16
+#define THS_H3_CTRL2_SENSOR_ACQ1(x) \
+   ((x) << THS_H3_CTRL2_SENSOR_ACQ1_OFFS)
+
+#define THS_H3_INT_CTRL_ALARM_INT_EN_OFFS   0
+#define THS_H3_INT_CTRL_ALARM_INT_EN \
+   BIT(THS_H3_INT_CTRL_ALARM_INT_EN_OFFS)
+#define THS_H3_INT_CTRL_SHUT_INT_EN_OFFS   4
+#define THS_H3_INT_CTRL_SHUT_INT_EN \
+   BIT(THS_H3_INT_CTRL_SHUT_INT_EN_OFFS)
+#define THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS   8
+#define THS_H3_INT_CTRL_DATA_IRQ_EN \
+   BIT(THS_H3_INT_CTRL_DATA_IRQ_EN_OFFS)
+#define THS_H3_INT_CTRL_THERMAL_PER_OFFS   12
+#define THS_H3_INT_CTRL_THERMAL_PER(x) \
+   ((x) << THS_H3_INT_CTRL_THERMAL_PER_OFFS)
+
+#define THS_H3_STAT_ALARM_INT_STS_OFFS  0
+#define THS_H3_STAT_ALARM_INT_STS \
+   BIT(THS_H3_STAT_ALARM_INT_STS_OFFS)
+#define THS_H3_STAT_SHUT_INT_STS_OFFS   4
+#define THS_H3_STAT_SHUT_INT_STS \
+   BIT(THS_H3_STAT_SHUT_INT_STS_OFFS)
+#define THS_H3_STAT_DATA_IRQ_STS_OFFS   8
+#define THS_H3_STAT_DATA_IRQ_STS \
+   BIT(THS_H3_STAT_DATA_IRQ_STS_OFFS)
+#define THS_H3_STAT_ALARM_OFF_STS_OFFS  12
+#define THS_H3_STAT_ALARM_OFF_STS \
+   BIT(THS_H3_STAT_ALARM_OFF_STS_OFFS)
+
+#define THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS0
+#define THS_H3_ALARM_CTRL_ALARM0_T_HYST(x) \
+   ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HYST_OFFS)
+#define THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS 16
+#define THS_H3_ALARM_CTRL_ALARM0_T_HOT(x) \
+   ((x) << THS_H3_ALARM_CTRL_ALARM0_T_HOT_OFFS)
+
+#define 

[linux-sunxi] [PATCH v2 4/5] dt-bindings: document sun8i_ths

[Josef Gajdusek]

This patch adds the binding documentation for the sun8i_ths driver

Signed-off-by: Josef Gajdusek 
---
 .../devicetree/bindings/thermal/sun8i-ths.txt  | 31 ++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt

diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt 
b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
new file mode 100644
index 000..67056bf
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
@@ -0,0 +1,31 @@
+* sun8i THS
+
+Required properties:
+- compatible : "allwinner,sun8i-h3-ths"
+- reg : Address range of the thermal registers and location of the calibration
+value
+- resets : Must contain an entry for each entry in reset-names.
+   see ../reset/reset.txt for details
+- reset-names : Must include the name "ahb"
+- clocks : Must contain an entry for each entry in clock-names.
+- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
+  clock
+
+Optional properties:
+- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names
+- nvmem-cell-names : Must contain "calibration" for the cell containing the
+  temperature calibration cell, if available
+
+Example:
+ths: ths@01c25000 {
+   #thermal-sensor-cells = <0>;
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x88>, <0x01c14234 0x4>;
+   interrupts = ;
+   resets = <_rst 136>;
+   reset-names = "ahb";
+   clocks = <_gates 72>, <_clk>;
+   clock-names = "ahb", "ths";
+   nvmem-cells = <_calibration>;
+   nvmem-cell-names = "calibration";
+};
-- 
2.4.10

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[linux-sunxi] [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Josef Gajdusek]

Add a node describing the Security ID memory to the
Allwinner H3 .dtsi file.

Signed-off-by: Josef Gajdusek 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 0faa38a..58de718 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -359,6 +359,13 @@
#size-cells = <0>;
};
 
+   sid: eeprom@01c14000 {
+   compatible = "allwinner,sun4i-a10-sid";
+   reg = <0x01c14000 0x400>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   };
+
usbphy: phy@01c19400 {
compatible = "allwinner,sun8i-h3-usb-phy";
reg = <0x01c19400 0x2c>,
-- 
2.4.10

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[linux-sunxi] [PATCH v2 0/5] sunxi: THS support

[Josef Gajdusek]

Hello everyone,

this is v2 of my THS patchset

Changelog:

 * Some stylistic changes
 * devm_reset_control_get_optional -> devm_reset_control_get
 * Added the clk-h3-ths clock driver
   - Note: A23/A33/A83T do not have a separate clock, H3 seems to be the first
 (and only?) SoC with it
   - Because of this, I moved the clock init code to the H3-specific init
 function.
 * Use the nvmem cell abstraction instead of accessing the configuration memory 
directly
 * Use the IRQ line (and fixed incorrect interrupt number in the DTS)
 * Renamed to sun8i_ths

Ad the "magical constants": what I meant is that altough the datasheet explains
what they are, it does not explain how to pick their values. "ADC" and "Sensor"
"acquire time" are also not exactly the most helpful descriptions.
Anyway, I changed the values such as the final sampling rate is about 1Hz.

Josef Gajdusek (5):
  ARM: dts: sun8i: Add SID node
  clk: sunxi: Add driver for the H3 THS clock
  thermal: Add a driver for the Allwinner THS sensor
  dt-bindings: document sun8i_ths
  ARM: dts: sun8i: Add THS node to the H3 .dtsi

 Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
 .../devicetree/bindings/thermal/sun8i-ths.txt  |  31 ++
 arch/arm/boot/dts/sun8i-h3.dtsi|  40 +++
 drivers/clk/sunxi/Makefile |   1 +
 drivers/clk/sunxi/clk-h3-ths.c |  98 ++
 drivers/thermal/Kconfig|   7 +
 drivers/thermal/Makefile   |   1 +
 drivers/thermal/sun8i_ths.c| 365 +
 8 files changed, 544 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
 create mode 100644 drivers/clk/sunxi/clk-h3-ths.c
 create mode 100644 drivers/thermal/sun8i_ths.c

-- 
2.4.10

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[linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Maxime Ripard]

Hi,

On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:
> >> +   bus_gates: clk@01c20060 {
> >> +   #clock-cells = <1>;
> >> +   compatible = "allwinner,sun8i-h3-bus-gates-clk";
> >> +   reg = <0x01c20060 0x14>;
> >> +   clocks = <>, <>, <>, <>;
> >> +   clock-names = "ahb1", "ahb2", "apb1", "apb2";
> >> +   clock-indices = <5>, <6>, <8>,
> >> +   <9>, <10>, <13>,
> >> +   <14>, <17>, <18>,
> >> +   <19>, <20>,
> >> +   <21>, <23>,
> >> +   <24>, <25>,
> >> +   <26>, <27>,
> >> +   <28>, <29>,
> >> +   <30>, <31>, <32>,
> >> +   <35>, <36>, <37>,
> >> +   <40>, <41>, <43>,
> >> +   <44>, <52>, <53>,
> >> +   <54>, <64>,
> >> +   <65>, <69>, <72>,
> >> +   <76>, <77>, <78>,
> >> +   <96>, <97>, <98>,
> >> +   <112>, <113>,
> >> +   <114>, <115>, <116>,
> >> +   <128>, <135>;
> >> +   clock-output-names = "ahb1_ce", "ahb1_dma", 
> >> "ahb1_mmc0",
> >> +   "ahb1_mmc1", "ahb1_mmc2", 
> >> "ahb1_nand",
> >> +   "ahb1_sdram", "ahb2_gmac", 
> >> "ahb1_ts",
> >> +   "ahb1_hstimer", "ahb1_spi0",
> >> +   "ahb1_spi1", "ahb1_otg",
> >> +   "ahb1_otg_ehci0", "ahb1_ehic1",
> > 
> > ahb1_ehci1? Same for the following 3 lines.
> I'll fix them...
> > 
> >> +   "ahb1_ehic2", "ahb1_ehic3",
> >> +   "ahb1_otg_ohci0", "ahb2_ohic1",
> >> +   "ahb2_ohic2", "ahb2_ohic3", 
> >> "ahb1_ve",
> >> +   "ahb1_lcd0", "ahb1_lcd1", 
> >> "ahb1_deint",
> >> +   "ahb1_csi", "ahb1_tve", 
> >> "ahb1_hdmi",
> >> +   "ahb1_de", "ahb1_gpu", 
> >> "ahb1_msgbox",
> >> +   "ahb1_spinlock", "apb1_codec",
> >> +   "apb1_spdif", "apb1_pio", 
> >> "apb1_ths",
> >> +   "apb1_i2s0", "apb1_i2s1", 
> >> "apb1_i2s2",
> >> +   "apb2_i2c0", "apb2_i2c1", 
> >> "apb2_i2c2",
> >> +   "apb2_uart0", "apb2_uart1",
> >> +   "apb2_uart2", "apb2_uart3", 
> >> "apb2_scr",
> >> +   "ahb1_ephy", "ahb1_dbg";
> > 
> > If it weren't for the last 2 clocks, we could cleanly split out apb1 and 
> > apb2
> > gates. Having a separate AHB clock gate taking 2 addresses seems messy
> > as well. :(
> 
> Well, maybe we still should do that, if we split the resets too at least
> apb[12]  would line up again.
> 
> I don't know what to do with these bus things any more, all variants I
> sent had issues somewhere...

AFAIK, Arnd had some objections, but he never got back to us when we
explained how the hardware was laid out, so I don't know if they still
apply.

> >> +   };
> >> +
> >> +   mmc0_clk: clk@01c20088 {
> >> +   #clock-cells = <1>;
> >> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> >> +   reg = <0x01c20088 0x4>;
> >> +   clocks = <>, < 0>, < 0>;
> >> +   clock-output-names = "mmc0",
> >> +"mmc0_output",
> >> +"mmc0_sample";
> >> +   };
> >> +
> >> +   mmc1_clk: clk@01c2008c {
> >> +   #clock-cells = <1>;
> >> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> >> +   reg = <0x01c2008c 0x4>;
> >> +   clocks = <>, < 0>, < 0>;
> >> +   clock-output-names = "mmc1",
> >> +"mmc1_output",
> >> +"mmc1_sample";
> >> +   };
> >> +
> >> +   mmc2_clk: clk@01c20090 {
> >> +   #clock-cells = <1>;
> >> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> >> +   reg 

Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for the lamobo-r1 board

[Thomas Kaiser]

Hi,

Hans de Goede wrote:

> On 22-11-15 20:59, Maxime Ripard wrote: 
> >> + { 
> >> +cpu-supply = <_dcdc2>; 
> >> +operating-points = < 
> >> +/* kHz  uV */ 
> >> +96140 
> >> +912000140 
> >> +864000135 
> >> +72125 
> >> +528000115 
> >> +312000110 
> >> +144000105 
> >> +>; 
> > 
> > Why are you using a custom set of OPPs here, the default ones were 
> > unstable? 
>
> The fex file uses non standard OPPs
>

Which fex file? In case you're referring to an 'official' one please  
keep in mind how SinoVoip 'develops' stuff. By doing copy 
(remember the .dts for the Banana Pi M2?). Anyway, the fex files used 
by R1 users since a year contain comparable OPPs:

https://github.com/igorpecovnik/lib/blob/next/config/lamobo-r1.fex
https://github.com/Bananian/fex/blob/master/BPI-R1/script.fex

Stuff contained in official SinoVoip OS images can not be regarded 
safe or even tested since noone uses these OS images due to being 
broken more or less. And Lamobo R1 users that were relying on mainline 
kernel the last months already used a .dts sharing the default OPPs: 

https://github.com/igorpecovnik/lib/blob/next/patch/sun7i-a20-lamobo-r1.dts

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Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Hans de Goede]

HI,

On 23-11-15 09:57, Maxime Ripard wrote:

Hi,

On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:

+   bus_gates: clk@01c20060 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun8i-h3-bus-gates-clk";
+   reg = <0x01c20060 0x14>;
+   clocks = <>, <>, <>, <>;
+   clock-names = "ahb1", "ahb2", "apb1", "apb2";
+   clock-indices = <5>, <6>, <8>,
+   <9>, <10>, <13>,
+   <14>, <17>, <18>,
+   <19>, <20>,
+   <21>, <23>,
+   <24>, <25>,
+   <26>, <27>,
+   <28>, <29>,
+   <30>, <31>, <32>,
+   <35>, <36>, <37>,
+   <40>, <41>, <43>,
+   <44>, <52>, <53>,
+   <54>, <64>,
+   <65>, <69>, <72>,
+   <76>, <77>, <78>,
+   <96>, <97>, <98>,
+   <112>, <113>,
+   <114>, <115>, <116>,
+   <128>, <135>;
+   clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
+   "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
+   "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
+   "ahb1_hstimer", "ahb1_spi0",
+   "ahb1_spi1", "ahb1_otg",
+   "ahb1_otg_ehci0", "ahb1_ehic1",


ahb1_ehci1? Same for the following 3 lines.

I'll fix them...



+   "ahb1_ehic2", "ahb1_ehic3",
+   "ahb1_otg_ohci0", "ahb2_ohic1",
+   "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
+   "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
+   "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
+   "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
+   "ahb1_spinlock", "apb1_codec",
+   "apb1_spdif", "apb1_pio", "apb1_ths",
+   "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
+   "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
+   "apb2_uart0", "apb2_uart1",
+   "apb2_uart2", "apb2_uart3", "apb2_scr",
+   "ahb1_ephy", "ahb1_dbg";


If it weren't for the last 2 clocks, we could cleanly split out apb1 and apb2
gates. Having a separate AHB clock gate taking 2 addresses seems messy
as well. :(


Well, maybe we still should do that, if we split the resets too at least
apb[12]  would line up again.

I don't know what to do with these bus things any more, all variants I
sent had issues somewhere...


AFAIK, Arnd had some objections, but he never got back to us when we
explained how the hardware was laid out, so I don't know if they still
apply.


+   };
+
+   mmc0_clk: clk@01c20088 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20088 0x4>;
+   clocks = <>, < 0>, < 0>;
+   clock-output-names = "mmc0",
+"mmc0_output",
+"mmc0_sample";
+   };
+
+   mmc1_clk: clk@01c2008c {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c2008c 0x4>;
+   clocks = <>, < 0>, < 0>;
+   clock-output-names = "mmc1",
+"mmc1_output",
+"mmc1_sample";
+   };
+
+   mmc2_clk: clk@01c20090 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun4i-a10-mmc-clk";
+   reg = <0x01c20090 0x4>;
+   clocks = <>, < 0>, < 0>;
+   clock-output-names = "mmc2",
+"mmc2_output",
+"mmc2_sample";
+   };
+
+   mbus_clk: clk@01c2015c {
+   #clock-cells = <0>;
+   compatible = 

Re: [linux-sunxi] Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets

[Maxime Ripard]

Hi,

On Mon, Nov 23, 2015 at 03:41:52PM +0800, Chen-Yu Tsai wrote:
> On Thu, Nov 5, 2015 at 2:47 PM, Jean-Francois Moine  wrote:
> > On Wed, 4 Nov 2015 08:30:14 -0800
> > Maxime Ripard  wrote:
> >
> >> Hi Arnd,
> >>
> >> On Fri, Oct 30, 2015 at 09:27:03AM +0100, Arnd Bergmann wrote:
> >> > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote:
> >> > >
> >> > > +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev 
> >> > > *rcdev,
> >> > > +   const struct of_phandle_args 
> >> > > *reset_spec)
> >> > > +{
> >> > > +   unsigned int index = reset_spec->args[0];
> >> > > +
> >> > > +   if (index < 96)
> >> > > +   return index;
> >> > > +   else if (index < 128)
> >> > > +   return index + 32;
> >> > > +   else if (index < 160)
> >> > > +   return index + 64;
> >> > > +   else
> >> > > +   return -EINVAL;
> >> > > +}
> >> > > +
> >> > >
> >> >
> >> > This looks like you are doing something wrong and should either
> >> > put the actual number into DT,
> >>
> >> This is the actual number, except that there's some useless registers
> >> in between. Allwinner documents it like that:
> >>
> >> 0x0   Reset 0
> >> 0x4   Reset 1
> >> 0xc   Reset 2
> >>
> >> So we have to adjust the offset to account with the blank register in
> >> between (0x8).
> >>
> >> > or use a two-cell representation, with the first cell indicating the
> >> > block (0, 1 or 2), and the second cell the index.
> >>
> >> And the missing register is not a block either.
> >>
> >> That would also imply either changing the bindings of that driver (and
> >> all the current DTS that are using it), or introducing a whole new
> >> driver just to deal with some extraordinary offset calculation.
> >
> > In the H3, the holes are not used, but what would occur if these holes
> > would be used for some other purpose in future SoCs? Double mapping?
> 
> We'd have a different compatible string for it.
> 
> My suggestion for the resets is to just split them into 3 nodes: AHB
> (since AHB1 and AHB2 devices are mixed together in the bunch), APB1,
> and APB2 reset controls.
> 
> This follows what we have for existing SoCs, and gets rid of the unused
> hole. We can use the existing "allwinner,sun6i-a31-clock-reset" and
> "allwinner,sun6i-a31-ahb1-reset" compatibles.

That seems a bit weird to have a single clock and split resets, but as
long as they are not mixed, and you can compute easily the id from the
datasheet, ok.

Maxime

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Re: [linux-sunxi] Re: [PATCH] ARM: dts: sun7i: Add dts file for the lamobo-r1 board

[Hans de Goede]

Hi,

On 22-11-15 20:59, Maxime Ripard wrote:

Hi,

On Fri, Nov 20, 2015 at 08:11:53PM +0100, Hans de Goede wrote:

From: Jelle de Jong 

The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such
on the PCB, is meant as a A20 based router board. As such the board comes
with a built-in switch chip giving it 5 gigabit ethernet boards, and it
has a large empty area on the pcb with mounting holes which will fit a
2.5 inch harddisk. To complete its networking features it has a
Realtek RTL8192CU for WiFi 802.11 b/g/n.

Signed-off-by: Jelle de Jong 
Signed-off-by: Hans de Goede 
---
  arch/arm/boot/dts/Makefile|   1 +
  arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts | 297 ++
  2 files changed, 298 insertions(+)
  create mode 100644 arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 28b0403..7572c29 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -639,6 +639,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
+   sun7i-a20-lamobo-r1.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts 
b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
new file mode 100644
index 000..975b0b2
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -0,0 +1,297 @@
+/*
+ * Copyright 2015 Jelle de Jong 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include 
+#include 
+#include 
+
+/ {
+   model = "Lamobo R1";
+   compatible = "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_lamobo_r1>;
+
+   green {
+   label = "lamobo_r1:green:usr";
+   gpios = < 7 24 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   reg_gmac_3v3: gmac-3v3 {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_power_pin_lamobo_r1>;
+   regulator-name = "gmac-3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   enable-active-high;
+   gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+   };
+};
+
+_pwr_pin_a {
+   allwinner,pins = "PB3";
+};
+
+ {
+   target-supply = <_ahci_5v>;
+   status = "okay";
+};
+
+ {
+   cpu-supply = <_dcdc2>;
+  

[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Maxime Ripard]

Hi,

On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
> Add a node describing the Security ID memory to the
> Allwinner H3 .dtsi file.
> 
> Signed-off-by: Josef Gajdusek 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 0faa38a..58de718 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -359,6 +359,13 @@
>   #size-cells = <0>;
>   };
>  
> + sid: eeprom@01c14000 {
> + compatible = "allwinner,sun4i-a10-sid";
> + reg = <0x01c14000 0x400>;

The datasheet says it's 256 bytes wide, while the size here is of 1kB,
is it intentional?

Thanks,
Maxime

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[linux-sunxi] Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths

[Maxime Ripard]

Hi,

On Mon, Nov 23, 2015 at 09:02:51AM +0100, Josef Gajdusek wrote:
> This patch adds the binding documentation for the sun8i_ths driver
> 
> Signed-off-by: Josef Gajdusek 
> ---
>  .../devicetree/bindings/thermal/sun8i-ths.txt  | 31 
> ++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> 
> diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt 
> b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> new file mode 100644
> index 000..67056bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> @@ -0,0 +1,31 @@
> +* sun8i THS
> +
> +Required properties:
> +- compatible : "allwinner,sun8i-h3-ths"
> +- reg : Address range of the thermal registers and location of the 
> calibration
> +value
> +- resets : Must contain an entry for each entry in reset-names.
> +   see ../reset/reset.txt for details
> +- reset-names : Must include the name "ahb"

If you have a single reset line, you don't need reset-names.

Thanks!
Maxime

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Re: [linux-sunxi] [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock

[LABBE Corentin]

On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote:
> This patch adds a driver for the THS clock which is present on the
> Allwinner H3.
> 
> Signed-off-by: Josef Gajdusek 
> ---

Hello
Just a minor comment below.

> +static void __init sun8i_h3_ths_clk_setup(struct device_node *node)
> +{
> + struct clk *clk;
> + struct clk_gate *gate;
> + struct clk_divider *div;
> + const char *parent;
> + const char *clk_name = node->name;
> + void __iomem *reg;
> + int err;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +
> + if (IS_ERR(reg))
> + return;
> +
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto err_unmap;
> +
> + div = kzalloc(sizeof(*gate), GFP_KERNEL);
copy/paste error, you mean sizeof(*div) ?

> + if (!div)
> + goto err_gate_free;
> +
> + of_property_read_string(node, "clock-output-names", _name);

Regards

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[linux-sunxi] Re: [PATCH v2 4/5] dt-bindings: document sun8i_ths

[Chen-Yu Tsai]

On Mon, Nov 23, 2015 at 4:02 PM, Josef Gajdusek  wrote:
> This patch adds the binding documentation for the sun8i_ths driver
>
> Signed-off-by: Josef Gajdusek 
> ---
>  .../devicetree/bindings/thermal/sun8i-ths.txt  | 31 
> ++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-ths.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/sun8i-ths.txt 
> b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> new file mode 100644
> index 000..67056bf
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/sun8i-ths.txt
> @@ -0,0 +1,31 @@
> +* sun8i THS
> +
> +Required properties:
> +- compatible : "allwinner,sun8i-h3-ths"
> +- reg : Address range of the thermal registers and location of the 
> calibration
> +value

You are now using nvmem for the calibration data. You don't need the second
entry.

> +- resets : Must contain an entry for each entry in reset-names.
> +   see ../reset/reset.txt for details
> +- reset-names : Must include the name "ahb"
> +- clocks : Must contain an entry for each entry in clock-names.
> +- clock-names : Must contain "ahb" for the bus gate and "ths" for the THS
> +  clock
> +
> +Optional properties:
> +- nvmem-cells : Must contain an entry for each entry in nvmem-cell-names
> +- nvmem-cell-names : Must contain "calibration" for the cell containing the
> +  temperature calibration cell, if available
> +
> +Example:
> +ths: ths@01c25000 {
> +   #thermal-sensor-cells = <0>;
> +   compatible = "allwinner,sun8i-h3-ths";
> +   reg = <0x01c25000 0x88>, <0x01c14234 0x4>;

Same here.

ChenYu

> +   interrupts = ;
> +   resets = <_rst 136>;
> +   reset-names = "ahb";
> +   clocks = <_gates 72>, <_clk>;
> +   clock-names = "ahb", "ths";
> +   nvmem-cells = <_calibration>;
> +   nvmem-cell-names = "calibration";
> +};
> --
> 2.4.10
>

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Re: [linux-sunxi] [PATCH] spi: dts: sun4i: Add support for inter-word wait cycles using the SPI Wait Clock Register

[Marcus Weseloh]

2015-11-22 20:45 GMT+01:00 Maxime Ripard :
>> Julien, Rob: thanks for your comments! Ok, I will make the following changes:
>>
>> - remove "sun4i,spi-wdelay" from the sun4i binding and add the
>> property to the spi-bus.txt binding instead
>> - remove the comment about the additional 3 cycles from the documentation
>> - modfy the spi-sun4i driver to take care of the minimum 3 cycle period
>>
>> Does that sound right?
>>
>> And maybe I could also use a more descriptive name for the property,
>> maybe "spi-word-wait-cycles"?
>
> I don't think it should be in a clock-rate dependant unit. Using micro
> or nano-seconds would be more appropriate I guess.

Thanks Maxime, using a time based value instead of cycles sounds like
a much better approach.

However... I'm starting to think that the proposed inter-word wait
time DT property is just an ugly workaround. Let me explain my
use-case:

I'm developing a driver for a sensor that requires a minimum wait time
between words. The wait time depends on the mode the sensor is set to:
37.5us in slow mode, 12.5us in fast mode. I initially used spidev to
test the sensor from userspace. And for that use case, the
"spi-wdelay" property that I proposed works well. But now I am writing
the proper protocol driver and suddenly the explicit wait time setting
seems just wrong. Ideally, the protocol driver would just expose a DT
property that allows to choose between "slow" and "fast" mode.

I think that the correct approach would be to extend the SPI
controller API to allow protocol drivers to set an inter-word delay.
That would keep the magic numbers inside my protocol driver and out of
the devicetree. And an additional ioctl call could set that inter-word
delay from spidev, allowing userspace to set this value as well if
needed.

Mark: would you be open to such a change to the SPI controller API?

I could use the already available spi_transfer.delay_usecs for this,
but I would require that I wrap each word in a single transfer, which
adds significant processing overhead to the communication with the
sensor.

Cheers,

Marcus

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[linux-sunxi] Re: [PATCH] ARM: dts: sun8i-h3-orangepi-plus: Enable USB host controllers

[Troy Dack]

On Wednesday, 18 November 2015 03:12:11 UTC+11, Jens Kuske wrote:
>
> Enable the 2 USB host controllers used on the Orange Pi Plus 
> and add the necessary regulators. 
>
> Signed-off-by: Reinder de Haan  
> Signed-off-by: Hans de Goede  
> Signed-off-by: Jens Kuske  
> --- 
>
> Hi Hans, 
>
> with these regulators USB works on the Orange Pi Plus too. 
> I don't know if adding the regulators in the dts is okay, since most 
> regulators are defined in the sunxi-common-regulators.dtsi, but 
> we use different pins. 
>
> Jens 
>
>
>  arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 44 
>  
>  1 file changed, 44 insertions(+) 
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
> b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
> index e67df59..1cb6c66 100644 
> --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
> +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
> @@ -58,6 +58,35 @@ 
>  chosen { 
>  stdout-path = "serial0:115200n8"; 
>  }; 
> + 
> +reg_usb3_vbus: usb3-vbus { 
> +compatible = "regulator-fixed"; 
> +pinctrl-names = "default"; 
> +pinctrl-0 = <_vbus_pin_a>; 
> +regulator-name = "usb3-vbus"; 
> +regulator-min-microvolt = <500>; 
> +regulator-max-microvolt = <500>; 
> +regulator-boot-on; 
> +enable-active-high; 
> +gpio = < 6 11 GPIO_ACTIVE_HIGH>; 
> +}; 
> +}; 
> + 
> + { 
> +status = "okay"; 
> +}; 
> + 
> + { 
> +status = "okay"; 
> +}; 
> + 
> + { 
> +usb3_vbus_pin_a: usb3_vbus_pin@0 { 
> +allwinner,pins = "PG11"; 
> +allwinner,function = "gpio_out"; 
> +allwinner,drive = ; 
> +allwinner,pull = ; 
> +}; 
>  }; 
>   
>   { 
> @@ -70,8 +99,23 @@ 
>  status = "okay"; 
>  }; 
>   
> +_usb1_vbus { 
> +gpio = < 6 13 GPIO_ACTIVE_HIGH>; 
> +status = "okay"; 
> +}; 
> + 
>   { 
>  pinctrl-names = "default"; 
>  pinctrl-0 = <_pins_a>; 
>  status = "okay"; 
>  }; 
> + 
> +_vbus_pin_a { 
> +allwinner,pins = "PG13"; 
> +}; 
> + 
> + { 
> +usb1_vbus-supply = <_usb1_vbus>; 
> +usb3_vbus-supply = <_usb3_vbus>; 
> +status = "okay"; 
> +}; 
>

I've been trying to test these patches by using Hans' github sunxi-wip 
branches of the kernel and U-Boot.

U-Boot at commit 7e17fd2 "suxni: Add support for Orangepi Plus and Orangepi 
PC boards"
Kernel at commit cb45b8  "ARM: dts: sun8i-h3-orangepi-plus: Enable USB host 
controllers"

Both have been built using the default defconfig for an OrangePi Plus

U-Boot starts and successfully boots the kernel, but the kernel does not 
appear to boot fully and hangs at:

[0.861175] cpu cpu0: failed to get cpu0 clock: -2
[0.865973] cpufreq-dt: probe of cpufreq-dt failed with error -2
[0.872017] Registering SWP/SWPB emulation handler

Full boot log: http://pastebin.com/VGkEix9p

Building the kernel (or just using a dab) with the dts from commit 0a8c01 
"ARM: dts: sun8i: Add Orange Pi Plus support" results in the kernel booting 
fully to a login prompt.  Of course without enabled/working USB.

There is a fair chance I've done something wrong that is causing this.  Any 
advice on how to get a bootable kernel?

Thanks,
   Troy

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Maxime Ripard]

On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
>  wrote:
> > Hi,
> >
> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
> >> Add a node describing the Security ID memory to the
> >> Allwinner H3 .dtsi file.
> >>
> >> Signed-off-by: Josef Gajdusek 
> >> ---
> >>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
> >>  1 file changed, 7 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
> >> b/arch/arm/boot/dts/sun8i-h3.dtsi
> >> index 0faa38a..58de718 100644
> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> >> @@ -359,6 +359,13 @@
> >>   #size-cells = <0>;
> >>   };
> >>
> >> + sid: eeprom@01c14000 {
> >> + compatible = "allwinner,sun4i-a10-sid";
> >> + reg = <0x01c14000 0x400>;
> >
> > The datasheet says it's 256 bytes wide, while the size here is of 1kB,
> > is it intentional?
> 
> My H3 datasheet (v1.1) says its 1 kB wide.

Is it? in the Security ID section, it is said to be 2kb == 256B wide.

> It'd be nice if Allwinner actually listed the "usable" E-fuse
> offsets and widths, instead of having us dig through the SDK code.

Yep.

Thanks!
Maxime

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Maxime Ripard]

On Mon, Nov 23, 2015 at 07:24:40PM -0800, Sugar Wu wrote:
> I will give you the right widths as soon.

Great, thanks!
Maxime

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

On Tue, Nov 24, 2015 at 2:38 PM, Maxime Ripard
 wrote:
> On Tue, Nov 24, 2015 at 11:13:13AM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
>>  wrote:
>> > Hi,
>> >
>> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> >> Add a node describing the Security ID memory to the
>> >> Allwinner H3 .dtsi file.
>> >>
>> >> Signed-off-by: Josef Gajdusek 
>> >> ---
>> >>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>> >>  1 file changed, 7 insertions(+)
>> >>
>> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>> >> b/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> index 0faa38a..58de718 100644
>> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> >> @@ -359,6 +359,13 @@
>> >>   #size-cells = <0>;
>> >>   };
>> >>
>> >> + sid: eeprom@01c14000 {
>> >> + compatible = "allwinner,sun4i-a10-sid";
>> >> + reg = <0x01c14000 0x400>;
>> >
>> > The datasheet says it's 256 bytes wide, while the size here is of 1kB,
>> > is it intentional?
>>
>> My H3 datasheet (v1.1) says its 1 kB wide.
>
> Is it? in the Security ID section, it is said to be 2kb == 256B wide.

Right. I was looking at the memory map. Maybe it's sparsely mapped?
I guess we'll know soon.

ChenYu

>> It'd be nice if Allwinner actually listed the "usable" E-fuse
>> offsets and widths, instead of having us dig through the SDK code.
>
> Yep.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Sugar Wu]

On Monday, November 23, 2015 at 8:43:59 PM UTC+8, Maxime Ripard wrote:
>
> Hi, 
>
> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: 
> > Add a node describing the Security ID memory to the 
> > Allwinner H3 .dtsi file. 
> > 
> > Signed-off-by: Josef Gajdusek  
> > --- 
> >  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++ 
> >  1 file changed, 7 insertions(+) 
> > 
> > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
> b/arch/arm/boot/dts/sun8i-h3.dtsi 
> > index 0faa38a..58de718 100644 
> > --- a/arch/arm/boot/dts/sun8i-h3.dtsi 
> > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi 
> > @@ -359,6 +359,13 @@ 
> >  #size-cells = <0>; 
> >  }; 
> >   
> > +sid: eeprom@01c14000 { 
> > +compatible = "allwinner,sun4i-a10-sid"; 
> > +reg = <0x01c14000 0x400>; 
>
> The datasheet says it's 256 bytes wide, while the size here is of 1kB, 
> is it intentional? 

SID memory map is 0x01c14000 ~ 0x01c143FF, include 2048bits efuse space.
H3 efuse space is SID_SRAM, its range is  0x01c14200 ~ +0x100.

>  
>
Thanks, 
> Maxime 
>
> -- 
> Maxime Ripard, Free Electrons 
> Embedded Linux, Kernel and Android engineering 
> http://free-electrons.com 
>

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Chen-Yu Tsai]

Hi,

On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard
 wrote:
> Hi,
>
> On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote:
>> Add a node describing the Security ID memory to the
>> Allwinner H3 .dtsi file.
>>
>> Signed-off-by: Josef Gajdusek 
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>> b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 0faa38a..58de718 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -359,6 +359,13 @@
>>   #size-cells = <0>;
>>   };
>>
>> + sid: eeprom@01c14000 {
>> + compatible = "allwinner,sun4i-a10-sid";
>> + reg = <0x01c14000 0x400>;
>
> The datasheet says it's 256 bytes wide, while the size here is of 1kB,
> is it intentional?

My H3 datasheet (v1.1) says its 1 kB wide.

It'd be nice if Allwinner actually listed the "usable" E-fuse offsets
and widths, instead of having us dig through the SDK code.

Regards
ChenYu

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[linux-sunxi] Re: [PATCH v2 1/5] ARM: dts: sun8i: Add SID node

[Sugar Wu]

I will give you the right widths as soon.

在 2015年11月24日星期二 UTC+8上午11:13:41，Chen-Yu Tsai写道：
>
> Hi, 
>
> On Mon, Nov 23, 2015 at 8:43 PM, Maxime Ripard 
>  wrote: 
> > Hi, 
> > 
> > On Mon, Nov 23, 2015 at 09:02:48AM +0100, Josef Gajdusek wrote: 
> >> Add a node describing the Security ID memory to the 
> >> Allwinner H3 .dtsi file. 
> >> 
> >> Signed-off-by: Josef Gajdusek  
> >> --- 
> >>  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++ 
> >>  1 file changed, 7 insertions(+) 
> >> 
> >> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
> b/arch/arm/boot/dts/sun8i-h3.dtsi 
> >> index 0faa38a..58de718 100644 
> >> --- a/arch/arm/boot/dts/sun8i-h3.dtsi 
> >> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi 
> >> @@ -359,6 +359,13 @@ 
> >>   #size-cells = <0>; 
> >>   }; 
> >> 
> >> + sid: eeprom@01c14000 { 
> >> + compatible = "allwinner,sun4i-a10-sid"; 
> >> + reg = <0x01c14000 0x400>; 
> > 
> > The datasheet says it's 256 bytes wide, while the size here is of 1kB, 
> > is it intentional? 
>
> My H3 datasheet (v1.1) says its 1 kB wide. 
>
> It'd be nice if Allwinner actually listed the "usable" E-fuse offsets 
> and widths, instead of having us dig through the SDK code. 
>
> Regards 
> ChenYu 
>

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[linux-sunxi] [PATCH v4 4/6] regulator: axp20x: Support new AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai 
Reviewed-by: Mark Brown 
---
 drivers/regulator/axp20x-regulator.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/regulator/axp20x-regulator.c 
b/drivers/regulator/axp20x-regulator.c
index 35de22fdb7a0..55cce8125716 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -244,6 +244,7 @@ static int axp20x_set_dcdc_freq(struct platform_device 
*pdev, u32 dcdcfreq)
step = 75;
break;
case AXP221_ID:
+   case AXP223_ID:
min = 1800;
max = 4050;
def = 3000;
@@ -322,6 +323,7 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev 
*rdev, int id, u32 work
break;
 
case AXP221_ID:
+   case AXP223_ID:
if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
return -EINVAL;
 
@@ -360,6 +362,7 @@ static int axp20x_regulator_probe(struct platform_device 
*pdev)
nregulators = AXP20X_REG_ID_MAX;
break;
case AXP221_ID:
+   case AXP223_ID:
regulators = axp22x_regulators;
nregulators = AXP22X_REG_ID_MAX;
break;
-- 
2.6.2

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[linux-sunxi] [PATCH v4 0/6] mfd: axp20x: Add support for RSB based AXP223

[Chen-Yu Tsai]

Hi everyone,

This is v4 of the AXP223 PMIC series.

Changes since v3:

  - Removed settings for axp223 reg_rtc_ldo from board dts files that
are already in axp22x.dtsi. The name is kept.

  - Dropped simplefb label and defconfig patches, as they are merged.

Changes since v2:

  - s/It's/Its/ for the commit messages of patches 5 and 7

  - Add Rob's Acked-by for patch 1

Changes since v1:

  - Dropped NMI interrupt controller dts patch (Merged)

  - Change MFD_AXP20X to represent the axp20x core, and drop MFD_AXP20X_CORE
  
  - Keep the axp20x core bits named axp20x.c

  - Add patch 7 to add AXP223 to sun8i-q8-common.dtsi

  - Add patch 8 & 9 to update defconfigs

  - Make axp20x drivers tristate and buildable as modules

  - Drop "_sunxi" substring from identifiers in axp20x-rsb driver


This series adds support for the Reduced Serial Bus based AXP223 PMIC.
The AXP223 is functionally identical to the AXP221, which we already
support. Only some default values for the regulators are different.
The defaults fit their recommended application, paired with different
SoCs.

Patch 1 adds AXP223 to the list of supported chips in the DT binding.

Patch 2 splits the axp20x mfd driver into 2 parts, a core library, and
an I2C driver.

Patch 3 adds an RSB based driver for the AXP223.

Patch 4 adds support for the AXP223 regulators

Patch 5 enables the AXP223 PMIC and its regulators for the Sinlinx
SinA33.

Patch 6 enables the AXP223 PMIC and its regulators for A23/A33 based
Q8 devices.


Regards
ChenYu


Chen-Yu Tsai (6):
  mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings
  mfd: axp20x: Split the driver into core and i2c bits
  mfd: axp20x: Add support for RSB based AXP223 PMIC
  regulator: axp20x: Support new AXP223 PMIC
  ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator
nodes
  ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

 Documentation/devicetree/bindings/mfd/axp20x.txt |   7 +-
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts   |  79 +-
 arch/arm/boot/dts/sun8i-q8-common.dtsi   |  86 ++-
 drivers/mfd/Kconfig  |  25 -
 drivers/mfd/Makefile |   2 +
 drivers/mfd/axp20x-i2c.c | 127 +++
 drivers/mfd/axp20x-rsb.c |  93 +
 drivers/mfd/axp20x.c | 110 +++-
 drivers/regulator/axp20x-regulator.c |   3 +
 include/linux/mfd/axp20x.h   |  34 +-
 10 files changed, 458 insertions(+), 108 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c
 create mode 100644 drivers/mfd/axp20x-rsb.c

-- 
2.6.2

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[linux-sunxi] [PATCH v4 1/6] mfd: axp20x: Add AXP223 to list of supported PMICs in DT bindings

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/mfd/axp20x.txt | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt 
b/Documentation/devicetree/bindings/mfd/axp20x.txt
index a474359dd206..fd39fa54571b 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -5,11 +5,12 @@ axp152 (X-Powers)
 axp202 (X-Powers)
 axp209 (X-Powers)
 axp221 (X-Powers)
+axp223 (X-Powers)
 
 Required properties:
 - compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
- "x-powers,axp221"
-- reg: The I2C slave address for the AXP chip
+ "x-powers,axp221", "x-powers,axp223"
+- reg: The I2C slave address or RSB hardware address for the AXP chip
 - interrupt-parent: The parent interrupt controller
 - interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
 - interrupt-controller: The PMIC has its own internal IRQs
@@ -51,7 +52,7 @@ LDO3  : LDO   : ldo3in-supply
 LDO4   : LDO   : ldo24in-supply: shared supply
 LDO5   : LDO   : ldo5in-supply
 
-AXP221 regulators, type, and corresponding input supply names:
+AXP221/AXP223 regulators, type, and corresponding input supply names:
 
 RegulatorTypeSupply Name Notes
 ---- -
-- 
2.6.2

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[linux-sunxi] Re: Is FFmpeg for sunxi support 4K(3840×2160) encoding?

[Sugar Wu]

Sorry, A80 not support 4K.

在 2015年11月23日星期一 UTC+8上午10:29:49，Arnold kang写道：
>
> HI all ,
>I want to encoding 4K video on allwinner A80 SOC. I want to know the 
> LIB support it ? thanks
>

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[linux-sunxi] [PATCH v4 6/6] ARM: dts: sun8i: q8-common: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

A23/A33 Q8 tablets have an X-Powers AXP223 PMIC connected via RSB. Its
regulators provide power to various parts of the SoC and the board.

Also add lcd regulator supply for simplefb and update the existing
vmmc-supply for mmc0.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-q8-common.dtsi | 86 +-
 1 file changed, 84 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi 
b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 1a69231d2da5..01ab47b32d8d 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -56,7 +56,6 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = < 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-   /* backlight is powered by AXP223 DC1SW */
};
 
chosen {
@@ -67,7 +66,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_q8>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -92,6 +91,85 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc1sw {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-lcd";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-rtc";
 };
 
 _uart {
@@ -99,3 +177,7 @@
pinctrl-0 = <_uart_pins_a>;
status = "okay";
 };
+
+_lcd {
+   vcc-lcd-supply = <_dc1sw>;
+};
-- 
2.6.2

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[linux-sunxi] [PATCH v4 3/6] mfd: axp20x: Add support for RSB based AXP223 PMIC

[Chen-Yu Tsai]

The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
It is functionally identical to AXP221; only the regulator default
voltage/status and the external host interface are different.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/mfd/Kconfig| 11 ++
 drivers/mfd/Makefile   |  1 +
 drivers/mfd/axp20x-rsb.c   | 93 ++
 drivers/mfd/axp20x.c   |  2 +
 include/linux/mfd/axp20x.h |  1 +
 5 files changed, 108 insertions(+)
 create mode 100644 drivers/mfd/axp20x-rsb.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 804cd3dcce32..13c565103e96 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -107,6 +107,17 @@ config MFD_AXP20X_I2C
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
 
+config MFD_AXP20X_RSB
+   tristate "X-Powers AXP series PMICs with RSB"
+   select MFD_AXP20X
+   depends on SUNXI_RSB
+   help
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with RSB.
+ This driver include only the core APIs. You have to select individual
+ components like regulators or the PEK (Power Enable Key) under the
+ corresponding menus.
+
 config MFD_CROS_EC
tristate "ChromeOS Embedded Controller"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a6913007d667..caea6637d5e8 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)+= da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
 obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
+obj-$(CONFIG_MFD_AXP20X_RSB)   += axp20x-rsb.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-rsb.c b/drivers/mfd/axp20x-rsb.c
new file mode 100644
index ..3ea0d5db37d0
--- /dev/null
+++ b/drivers/mfd/axp20x-rsb.c
@@ -0,0 +1,93 @@
+/*
+ * axp20x-rsb.c - RSB driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the RSB variants.
+ *
+ * Author: Chen-Yu Tsai 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct of_device_id axp20x_rsb_of_match[] = {
+   { .compatible = "x-powers,axp223", .data = (void *) AXP223_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_rsb_of_match);
+
+static int axp20x_rsb_match_device(struct axp20x_dev *axp20x,
+struct device *dev)
+{
+   const struct of_device_id *of_id;
+
+   of_id = of_match_device(axp20x_rsb_of_match, dev);
+   if (!of_id) {
+   dev_err(dev, "Unable to match OF ID\n");
+   return -ENODEV;
+   }
+   axp20x->variant = (long) of_id->data;
+
+   return axp20x_match_device(axp20x, dev);
+}
+
+static int axp20x_rsb_probe(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x;
+   int ret;
+
+   axp20x = devm_kzalloc(>dev, sizeof(*axp20x), GFP_KERNEL);
+   if (!axp20x)
+   return -ENOMEM;
+
+   ret = axp20x_rsb_match_device(axp20x, >dev);
+   if (ret)
+   return ret;
+
+   axp20x->dev = >dev;
+   axp20x->irq = rdev->irq;
+   sunxi_rsb_device_set_drvdata(rdev, axp20x);
+
+   axp20x->regmap = devm_regmap_init_sunxi_rsb(rdev, axp20x->regmap_cfg);
+   if (IS_ERR(axp20x->regmap)) {
+   ret = PTR_ERR(axp20x->regmap);
+   dev_err(>dev, "regmap init failed: %d\n", ret);
+   return ret;
+   }
+
+   return axp20x_device_probe(axp20x);
+}
+
+static int axp20x_rsb_remove(struct sunxi_rsb_device *rdev)
+{
+   struct axp20x_dev *axp20x = sunxi_rsb_device_get_drvdata(rdev);
+
+   return axp20x_device_remove(axp20x);
+}
+
+static struct sunxi_rsb_driver axp20x_rsb_driver = {
+   .driver = {
+   .name   = "axp20x-rsb",
+   .of_match_table = of_match_ptr(axp20x_rsb_of_match),
+   },
+   .probe  = axp20x_rsb_probe,
+   .remove = axp20x_rsb_remove,
+};
+module_sunxi_rsb_driver(axp20x_rsb_driver);
+
+MODULE_DESCRIPTION("PMIC MFD sunXi RSB driver for AXP20X");
+MODULE_AUTHOR("Chen-Yu Tsai ");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 01f139856bf1..8057000da9d6 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -32,6 +32,7 @@ 

[linux-sunxi] [PATCH v4 5/6] ARM: dts: sun8i: sinlinx-sina33: Add AXP223 PMIC device and regulator nodes

[Chen-Yu Tsai]

This board has a X-Powers AXP223 PMIC connected via RSB. Its regulators
provide power to various parts of the SoC and the board.

Also update the regulator supply phandles.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 79 +-
 1 file changed, 76 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts 
b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
index 13ce68f06dd6..91a0fde47fdd 100644
--- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
@@ -68,7 +68,7 @@
 };
 
  {
-   vref-supply = <_vcc3v0>;
+   vref-supply = <_dcdc1>;
status = "okay";
 
button@200 {
@@ -96,7 +96,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_sina33>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
cd-inverted;
@@ -106,7 +106,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
@@ -132,6 +132,79 @@
 
 _rsb {
status = "okay";
+
+   axp22x: pmic@3e3 {
+   compatible = "x-powers,axp223";
+   reg = <0x3e3>;
+   interrupt-parent = <_intc>;
+   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   };
+};
+
+#include "axp22x.dtsi"
+
+_aldo1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-io";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <235>;
+   regulator-max-microvolt = <265>;
+   regulator-name = "vdd-dll";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <270>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pll-avcc";
+};
+
+_dc5ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpus";
+};
+
+_dcdc1 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-3v0";
+};
+
+_dcdc2 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-sys";
+};
+
+_dcdc3 {
+   regulator-always-on;
+   regulator-min-microvolt = <90>;
+   regulator-max-microvolt = <140>;
+   regulator-name = "vdd-cpu";
+};
+
+_dcdc5 {
+   regulator-always-on;
+   regulator-min-microvolt = <150>;
+   regulator-max-microvolt = <150>;
+   regulator-name = "vcc-dram";
+};
+
+_rtc_ldo {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-rtc";
 };
 
  {
-- 
2.6.2

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[linux-sunxi] [PATCH v4 2/6] mfd: axp20x: Split the driver into core and i2c bits

[Chen-Yu Tsai]

The axp20x driver assumes the device is i2c based. This is not the
case with later chips, which use a proprietary 2 wire serial bus
by Allwinner called "Reduced Serial Bus".

This patch follows the example of mfd/wm831x and splits it into
an interface independent core, and an i2c specific glue layer.
MFD_AXP20X and the new MFD_AXP20X_I2C are changed to tristate
symbols, allowing the driver to be built as modules.

Included but unused header files are removed as well.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/mfd/Kconfig|  14 +++--
 drivers/mfd/Makefile   |   1 +
 drivers/mfd/axp20x-i2c.c   | 127 +
 drivers/mfd/axp20x.c   | 108 +-
 include/linux/mfd/axp20x.h |  33 +++-
 5 files changed, 183 insertions(+), 100 deletions(-)
 create mode 100644 drivers/mfd/axp20x-i2c.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4d92df6ef9fe..804cd3dcce32 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -91,14 +91,18 @@ config MFD_BCM590XX
  Support for the BCM590xx PMUs from Broadcom
 
 config MFD_AXP20X
-   bool "X-Powers AXP20X"
+   tristate
select MFD_CORE
-   select REGMAP_I2C
select REGMAP_IRQ
-   depends on I2C=y
+
+config MFD_AXP20X_I2C
+   tristate "X-Powers AXP series PMICs with I2C"
+   select MFD_AXP20X
+   select REGMAP_I2C
+   depends on I2C
help
- If you say Y here you get support for the X-Powers AXP202, AXP209 and
- AXP288 power management IC (PMIC).
+ If you say Y here you get support for the X-Powers AXP series power
+ management ICs (PMICs) controlled with I2C.
  This driver include only the core APIs. You have to select individual
  components like regulators or the PEK (Power Enable Key) under the
  corresponding menus.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a8b76b81b467..a6913007d667 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -107,6 +107,7 @@ obj-$(CONFIG_PMIC_DA9052)   += da9052-core.o
 obj-$(CONFIG_MFD_DA9052_SPI)   += da9052-spi.o
 obj-$(CONFIG_MFD_DA9052_I2C)   += da9052-i2c.o
 obj-$(CONFIG_MFD_AXP20X)   += axp20x.o
+obj-$(CONFIG_MFD_AXP20X_I2C)   += axp20x-i2c.o
 
 obj-$(CONFIG_MFD_LP3943)   += lp3943.o
 obj-$(CONFIG_MFD_LP8788)   += lp8788.o lp8788-irq.o
diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c
new file mode 100644
index ..75b247af2514
--- /dev/null
+++ b/drivers/mfd/axp20x-i2c.c
@@ -0,0 +1,127 @@
+/*
+ * axp20x-i2c.c - I2C driver for the X-Powers' Power Management ICs
+ *
+ * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK 
DC-DC
+ * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature
+ * as well as configurable GPIOs.
+ *
+ * This driver supports the I2C variants.
+ *
+ * Author: Carlo Caione 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static const struct of_device_id axp20x_i2c_of_match[] = {
+   { .compatible = "x-powers,axp152", .data = (void *) AXP152_ID },
+   { .compatible = "x-powers,axp202", .data = (void *) AXP202_ID },
+   { .compatible = "x-powers,axp209", .data = (void *) AXP209_ID },
+   { .compatible = "x-powers,axp221", .data = (void *) AXP221_ID },
+   { },
+};
+MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match);
+
+/*
+ * This is useless for OF-enabled devices, but it is needed by I2C subsystem
+ */
+static const struct i2c_device_id axp20x_i2c_id[] = {
+   { },
+};
+MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id);
+
+static const struct acpi_device_id axp20x_i2c_acpi_match[] = {
+   {
+   .id = "INT33F4",
+   .driver_data = AXP288_ID,
+   },
+   { },
+};
+MODULE_DEVICE_TABLE(acpi, axp20x_i2c_acpi_match);
+
+static int axp20x_i2c_match_device(struct axp20x_dev *axp20x,
+  struct device *dev)
+{
+   const struct acpi_device_id *acpi_id;
+   const struct of_device_id *of_id;
+
+   if (dev->of_node) {
+   of_id = of_match_device(axp20x_i2c_of_match, dev);
+   if (!of_id) {
+   dev_err(dev, "Unable to match OF ID\n");
+   return -ENODEV;
+   }
+   axp20x->variant = (long) of_id->data;
+   } else {
+   acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev);
+   if (!acpi_id || !acpi_id->driver_data) {
+   dev_err(dev, "Unable to match ACPI ID and data\n");
+   return -ENODEV;
+   }
+   axp20x->variant = (long) acpi_id->driver_data;
+   }
+
+ 

Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jens Kuske]

On 23/11/15 11:50, Hans de Goede wrote:
> HI,
> 
> On 23-11-15 09:57, Maxime Ripard wrote:
>> Hi,
>>
>> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:
> +   bus_gates: clk@01c20060 {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun8i-h3-bus-gates-clk";
> +   reg = <0x01c20060 0x14>;
> +   clocks = <>, <>, <>, <>;
> +   clock-names = "ahb1", "ahb2", "apb1", "apb2";
> +   clock-indices = <5>, <6>, <8>,
> +   <9>, <10>, <13>,
> +   <14>, <17>, <18>,
> +   <19>, <20>,
> +   <21>, <23>,
> +   <24>, <25>,
> +   <26>, <27>,
> +   <28>, <29>,
> +   <30>, <31>, <32>,
> +   <35>, <36>, <37>,
> +   <40>, <41>, <43>,
> +   <44>, <52>, <53>,
> +   <54>, <64>,
> +   <65>, <69>, <72>,
> +   <76>, <77>, <78>,
> +   <96>, <97>, <98>,
> +   <112>, <113>,
> +   <114>, <115>, <116>,
> +   <128>, <135>;
> +   clock-output-names = "ahb1_ce", "ahb1_dma", 
> "ahb1_mmc0",
> +   "ahb1_mmc1", "ahb1_mmc2", 
> "ahb1_nand",
> +   "ahb1_sdram", "ahb2_gmac", 
> "ahb1_ts",
> +   "ahb1_hstimer", "ahb1_spi0",
> +   "ahb1_spi1", "ahb1_otg",
> +   "ahb1_otg_ehci0", "ahb1_ehic1",

 ahb1_ehci1? Same for the following 3 lines.
>>> I'll fix them...

> +   "ahb1_ehic2", "ahb1_ehic3",
> +   "ahb1_otg_ohci0", "ahb2_ohic1",
> +   "ahb2_ohic2", "ahb2_ohic3", 
> "ahb1_ve",
> +   "ahb1_lcd0", "ahb1_lcd1", 
> "ahb1_deint",
> +   "ahb1_csi", "ahb1_tve", 
> "ahb1_hdmi",
> +   "ahb1_de", "ahb1_gpu", 
> "ahb1_msgbox",
> +   "ahb1_spinlock", "apb1_codec",
> +   "apb1_spdif", "apb1_pio", 
> "apb1_ths",
> +   "apb1_i2s0", "apb1_i2s1", 
> "apb1_i2s2",
> +   "apb2_i2c0", "apb2_i2c1", 
> "apb2_i2c2",
> +   "apb2_uart0", "apb2_uart1",
> +   "apb2_uart2", "apb2_uart3", 
> "apb2_scr",
> +   "ahb1_ephy", "ahb1_dbg";

 If it weren't for the last 2 clocks, we could cleanly split out apb1 and 
 apb2
 gates. Having a separate AHB clock gate taking 2 addresses seems messy
 as well. :(
>>>
>>> Well, maybe we still should do that, if we split the resets too at least
>>> apb[12]  would line up again.
>>>
>>> I don't know what to do with these bus things any more, all variants I
>>> sent had issues somewhere...
>>
>> AFAIK, Arnd had some objections, but he never got back to us when we
>> explained how the hardware was laid out, so I don't know if they still
>> apply.
>>
> +   };
> +
> +   mmc0_clk: clk@01c20088 {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c20088 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc0",
> +"mmc0_output",
> +"mmc0_sample";
> +   };
> +
> +   mmc1_clk: clk@01c2008c {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c2008c 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc1",
> +"mmc1_output",
> +"mmc1_sample";
> +   };

[linux-sunxi] Allwinner A20: systemd / Time has been changed

[philippe . baret]

Hi,

Via microSD card, i am trying to install FreedomBox image (debian 
"stretch/sid") on a Cubietruck 128 SSD edition. Whilst FreedomBox image has 
been installed on Cubietruck SSD by some users without problem, i experienced 
some loop messages at a point of the process from systemd. The message shows 
like this : "systemd(1): Time has been changed." I have tried to empty the 
battery of the board using some wire as a solution and it does not change 
anything to that problem.

Any idea or solution ?

FreedomBox website
https://wiki.debian.org/FreedomBox

Exemples of systemd messages :
http://i.imgur.com/aPvqltr.png
http://i.imgur.com/bolU7xN.png

Messages just before loop messages start
http://i.imgur.com/uApun3f.png

+++
Philippe

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Re: [linux-sunxi] Re: [PATCH v4 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Chen-Yu Tsai]

On Mon, Nov 23, 2015 at 6:50 PM, Hans de Goede  wrote:
> HI,
>
>
> On 23-11-15 09:57, Maxime Ripard wrote:
>>
>> Hi,
>>
>> On Sun, Nov 01, 2015 at 02:33:23PM +0100, Jens Kuske wrote:
>
> +   bus_gates: clk@01c20060 {
> +   #clock-cells = <1>;
> +   compatible =
> "allwinner,sun8i-h3-bus-gates-clk";
> +   reg = <0x01c20060 0x14>;
> +   clocks = <>, <>, <>, <>;
> +   clock-names = "ahb1", "ahb2", "apb1", "apb2";
> +   clock-indices = <5>, <6>, <8>,
> +   <9>, <10>, <13>,
> +   <14>, <17>, <18>,
> +   <19>, <20>,
> +   <21>, <23>,
> +   <24>, <25>,
> +   <26>, <27>,
> +   <28>, <29>,
> +   <30>, <31>, <32>,
> +   <35>, <36>, <37>,
> +   <40>, <41>, <43>,
> +   <44>, <52>, <53>,
> +   <54>, <64>,
> +   <65>, <69>, <72>,
> +   <76>, <77>, <78>,
> +   <96>, <97>, <98>,
> +   <112>, <113>,
> +   <114>, <115>, <116>,
> +   <128>, <135>;
> +   clock-output-names = "ahb1_ce", "ahb1_dma",
> "ahb1_mmc0",
> +   "ahb1_mmc1", "ahb1_mmc2",
> "ahb1_nand",
> +   "ahb1_sdram", "ahb2_gmac",
> "ahb1_ts",
> +   "ahb1_hstimer", "ahb1_spi0",
> +   "ahb1_spi1", "ahb1_otg",
> +   "ahb1_otg_ehci0", "ahb1_ehic1",


 ahb1_ehci1? Same for the following 3 lines.
>>>
>>> I'll fix them...


> +   "ahb1_ehic2", "ahb1_ehic3",
> +   "ahb1_otg_ohci0", "ahb2_ohic1",
> +   "ahb2_ohic2", "ahb2_ohic3",
> "ahb1_ve",
> +   "ahb1_lcd0", "ahb1_lcd1",
> "ahb1_deint",
> +   "ahb1_csi", "ahb1_tve",
> "ahb1_hdmi",
> +   "ahb1_de", "ahb1_gpu",
> "ahb1_msgbox",
> +   "ahb1_spinlock", "apb1_codec",
> +   "apb1_spdif", "apb1_pio",
> "apb1_ths",
> +   "apb1_i2s0", "apb1_i2s1",
> "apb1_i2s2",
> +   "apb2_i2c0", "apb2_i2c1",
> "apb2_i2c2",
> +   "apb2_uart0", "apb2_uart1",
> +   "apb2_uart2", "apb2_uart3",
> "apb2_scr",
> +   "ahb1_ephy", "ahb1_dbg";


 If it weren't for the last 2 clocks, we could cleanly split out apb1 and
 apb2
 gates. Having a separate AHB clock gate taking 2 addresses seems messy
 as well. :(
>>>
>>>
>>> Well, maybe we still should do that, if we split the resets too at least
>>> apb[12]  would line up again.
>>>
>>> I don't know what to do with these bus things any more, all variants I
>>> sent had issues somewhere...
>>
>>
>> AFAIK, Arnd had some objections, but he never got back to us when we
>> explained how the hardware was laid out, so I don't know if they still
>> apply.
>>
> +   };
> +
> +   mmc0_clk: clk@01c20088 {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c20088 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc0",
> +"mmc0_output",
> +"mmc0_sample";
> +   };
> +
> +   mmc1_clk: clk@01c2008c {
> +   #clock-cells = <1>;
> +   compatible = "allwinner,sun4i-a10-mmc-clk";
> +   reg = <0x01c2008c 0x4>;
> +   clocks = <>, < 0>, < 0>;
> +   clock-output-names = "mmc1",
> +"mmc1_output",
> + 

[linux-sunxi] Re: [PATCH] ARM: dts: sun8i: Add Orange Pi PC support

[Maxime Ripard]

Hi,

On Wed, Nov 18, 2015 at 01:40:33PM +0800, Chen-Yu Tsai wrote:
> + {
> + /* USB VBUS is always on */
> + status = "okay";
> +};

You can tie it to reg_5v0 then :)

Thanks!
Maxime


-- 
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[linux-sunxi] Re: [PATCH v2 2/5] clk: sunxi: Add driver for the H3 THS clock

[Rob Herring]

On Mon, Nov 23, 2015 at 09:02:49AM +0100, Josef Gajdusek wrote:
> This patch adds a driver for the THS clock which is present on the
> Allwinner H3.
> 
> Signed-off-by: Josef Gajdusek 

Acked-by: Rob Herring 

> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
>  drivers/clk/sunxi/Makefile|  1 +
>  drivers/clk/sunxi/clk-h3-ths.c| 98 
> +++
>  3 files changed, 100 insertions(+)
>  create mode 100644 drivers/clk/sunxi/clk-h3-ths.c
> 
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt 
> b/Documentation/devicetree/bindings/clock/sunxi.txt
> index 23e7bce..6d63b35 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -73,6 +73,7 @@ Required properties:
>   "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
>   "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
>   "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
> + "allwinner,sun8i-h3-ths-clk" - for THS on H3
>  
>  Required properties for all clocks:
>  - reg : shall be the control register address for the clock.
> diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
> index f520af6..1bf8e1c 100644
> --- a/drivers/clk/sunxi/Makefile
> +++ b/drivers/clk/sunxi/Makefile
> @@ -8,6 +8,7 @@ obj-y += clk-a10-hosc.o
>  obj-y += clk-a10-mod1.o
>  obj-y += clk-a10-pll2.o
>  obj-y += clk-a20-gmac.o
> +obj-y += clk-h3-ths.o
>  obj-y += clk-mod0.o
>  obj-y += clk-simple-gates.o
>  obj-y += clk-sun8i-bus-gates.o
> diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c
> new file mode 100644
> index 000..663afc0
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-h3-ths.c
> @@ -0,0 +1,98 @@
> +/*
> + * Sunxi THS clock driver
> + *
> + * Copyright (C) 2015 Josef Gajdusek
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define SUN8I_H3_THS_CLK_ENABLE  31
> +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT   0
> +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH   2
> +
> +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock);
> +
> +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = {
> + { .val = 0, .div = 1 },
> + { .val = 1, .div = 2 },
> + { .val = 2, .div = 4 },
> + { .val = 3, .div = 6 },
> + { } /* sentinel */
> +};
> +
> +static void __init sun8i_h3_ths_clk_setup(struct device_node *node)
> +{
> + struct clk *clk;
> + struct clk_gate *gate;
> + struct clk_divider *div;
> + const char *parent;
> + const char *clk_name = node->name;
> + void __iomem *reg;
> + int err;
> +
> + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
> +
> + if (IS_ERR(reg))
> + return;
> +
> + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!gate)
> + goto err_unmap;
> +
> + div = kzalloc(sizeof(*gate), GFP_KERNEL);
> + if (!div)
> + goto err_gate_free;
> +
> + of_property_read_string(node, "clock-output-names", _name);
> + parent = of_clk_get_parent_name(node, 0);
> +
> + gate->reg = reg;
> + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE;
> + gate->lock = _h3_ths_clk_lock;
> +
> + div->reg = reg;
> + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT;
> + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH;
> + div->table = sun8i_h3_ths_clk_table;
> + div->lock = _h3_ths_clk_lock;
> +
> + clk = clk_register_composite(NULL, clk_name, , 1,
> +  NULL, NULL,
> +  >hw, _divider_ops,
> +  >hw, _gate_ops,
> +  CLK_SET_RATE_PARENT);
> +
> + if (IS_ERR(clk))
> + goto err_div_free;
> +
> + err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
> + if (err)
> + goto err_unregister_clk;
> +
> + return;
> +
> +err_unregister_clk:
> + clk_unregister(clk);
> +err_gate_free:
> + kfree(gate);
> +err_div_free:
> + kfree(div);
> +err_unmap:
> + iounmap(reg);
> +}
> +
> +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk",
> +sun8i_h3_ths_clk_setup);
> -- 
> 2.4.10
> 

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