[linux-sunxi] Re: [PATCH v4] ARM: dts: sun8i: Add dts file for Olimex A33-OLinuXino

[stefan . mavrodiev]

On Tuesday, July 26, 2016 5:33:52 PM EEST Maxime Ripard wrote:
> Hi Stefan,
> 
> On Mon, Jul 25, 2016 at 03:37:23PM +0300, Stefan Mavrodiev wrote:
> > A33-OLinuXino is A33 development board designed by Olimex LTD.
> > 
> > It has AXP233 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
> > headphone and mic jacks, connector for LiPo battery and optional
> > 4GB NAND Flash.
> > 
> > It has two 40-pin headers. One for LCD panel, and one for
> > additional modules. Also there is CSI/DSI connector.
> > 
> > Signed-off-by: Stefan Mavrodiev 
> 
> It looks mostly good, a few comments though.
> 
> > + {
> > +   led_pin_olinuxino: led_pins@0 {
> > +   allwinner,pins = "PB7";
> > +allwinner,function = "gpio_out";
> 
> This line is not properly indented.
> 
> > +   allwinner,drive = ;
> > +   allwinner,pull = ;
> > +};
> 
> And this one too.
> 
> > +_dc1sw {
> > +   regulator-name = "vcc-lcd";
> > +};
> 
> No constraints on this one?
> 
> > +_dcdc1 {
> > +   regulator-always-on;
> > +   regulator-min-microvolt = <330>;
> > +   regulator-max-microvolt = <330>;
> > +   regulator-name = "vcc-dsi";
> > +};
> 
> What is it used for? Is it really necessary to keep it on at all time?

I think so.
This is the supply for the MMC.
> 
> Thanks,
> Maxime

Best regards,
Stefan Mavrodiev


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[linux-sunxi] Re: [PATCH v4] ARM: dts: sun8i: Add dts file for Olimex A33-OLinuXino

[Maxime Ripard]

Hi Stefan,

On Mon, Jul 25, 2016 at 03:37:23PM +0300, Stefan Mavrodiev wrote:
> A33-OLinuXino is A33 development board designed by Olimex LTD.
> 
> It has AXP233 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
> headphone and mic jacks, connector for LiPo battery and optional
> 4GB NAND Flash.
> 
> It has two 40-pin headers. One for LCD panel, and one for
> additional modules. Also there is CSI/DSI connector.
> 
> Signed-off-by: Stefan Mavrodiev 

It looks mostly good, a few comments though.
> + {
> + led_pin_olinuxino: led_pins@0 {
> + allwinner,pins = "PB7";
> +allwinner,function = "gpio_out";

This line is not properly indented.

> + allwinner,drive = ;
> + allwinner,pull = ;
> +};

And this one too.

> +_dc1sw {
> + regulator-name = "vcc-lcd";
> +};

No constraints on this one?

> +_dcdc1 {
> + regulator-always-on;
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + regulator-name = "vcc-dsi";
> +};

What is it used for? Is it really necessary to keep it on at all time?

Thanks,
Maxime

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[linux-sunxi] Urgent Requirement--Need SAP Functional Tester or Functional Test Lead

[Bharat Chhibber]

*Hello,*



*This is Bharat from Niyo Infotech.Hope you are doing well. Please find the
JD below and if you have any consultant available then please let me know
ASAP at bhara...@nityo.com .*





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[linux-sunxi] Urgent Requirement--.AngularJS Technical Lead

[Bharat Chhibber]

*Hello,*



*This is Bharat from Niyo Infotech.Hope you are doing well. Please find the
JD below and if you have any consultant available then please let me know
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Knowledge of Insurance domain will be an added benefit

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[linux-sunxi] Urgent Requirement--Oracle Financials Quality Analyst

[Bharat Chhibber]

*Hello,*


*This is Bharat from Niyo Infotech.Hope you are doing well. Please find the
JD below and if you have any consultant available then please let me know
ASAP at bhara...@nityo.com .*

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[linux-sunxi] Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Jean-Francois Moine]

On Tue, 26 Jul 2016 15:04:30 +0800
Chen-Yu Tsai  wrote:

> +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
> + { .index = 0, .div = 750, },
> + { .index = 3, .div = 4, },
> + { .index = 4, .div = 4, },
> +};

No end of table.

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Re: [linux-sunxi] Re: [PATCH v2 06/14] ARM: sun8i: clk: Add clk-factor rate application method

[Ondřej Jirman]

On 26.7.2016 08:32, Maxime Ripard wrote:
> On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
> If so, then yes, trying to switch to the 24MHz oscillator before
> applying the factors, and then switching back when the PLL is stable
> would be a nice solution.
>
> I just checked, and all the SoCs we've had so far have that
> possibility, so if it works, for now, I'd like to stick to that.

 It would need to be tested. U-boot does the change only once, while the
 kernel would be doing it all the time and between various frequencies
 and PLL settings. So the issues may show up with this solution too.
>>>
>>> That would have the benefit of being quite easy to document, not be a
>>> huge amount of code and it would work on all the CPUs PLLs we have so
>>> far, so still, a pretty big win. If it doesn't, of course, we don't
>>> really have the choice.
>>
>> It's probably more code though. It has to access different register from
>> the one that is already defined in dts, which would add a lot of code
>> and require dts changes. The original patch I sent is simpler than that.
> 
> Why?

Because I don't understand internals of clk subsystem that much. :) So
my guess might be wrong.

Wens send patches implementing clock source switching in the new CCU
code, so hopefully it will work. Ultimately it's a hack. Some internal
parts of the soc may still get into out of the bounds operating state
even if they are gated off from other parts of the SoC, via clock
multiplexing, by improper factors change procedure.

So it doesn't really matter which is more concise in code. As long as
one solution is wrong and other is proper.

Anyway, I'll try with wens's patches, later and see if I trigger some
instability or not.

> You can use container_of to retrieve the parent structure of the clock
> notifier, and then you get a ccu_common structure pointer, with the
> CCU base address, the clock register, its lock, etc.
> 
> Look at what is done in drivers/clk/meson/clk-cpu.c. It's like 20 LoC.
> 
> I don't really get why anything should be changed in the DT, or why it
> would add a lot of code. Or maybe we're not talking about the same
> thing?
> 
> Maxime
> 

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[linux-sunxi] Re: [PATCH 2/9] clk: sunxi-ng: nk: Make ccu_nk_find_best static

[Maxime Ripard]

On Tue, Jul 26, 2016 at 03:04:24PM +0800, Chen-Yu Tsai wrote:
> make C=2 reports:
> 
>   CHECK   drivers/clk/sunxi-ng/ccu_nk.c
> drivers/clk/sunxi-ng/ccu_nk.c:17:6: warning: symbol 'ccu_nk_find_best' was
> not declared. Should it be static?
> 
> ccu_nk_find_best is only used within ccu_nk.c. So make it static to get
> rid of this warning.
> 
> Fixes: adbfb0056e03 ("clk: sunxi-ng: Add N-K-factor clock support")
> Signed-off-by: Chen-Yu Tsai 

Applied, thanks

Maxime

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[linux-sunxi] Re: [PATCH resend 1/9] clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock

[Maxime Ripard]

On Tue, Jul 26, 2016 at 03:04:23PM +0800, Chen-Yu Tsai wrote:
> The condition passed to read*_poll_timeout() is the break condition,
> i.e. wait for this condition to happen and return success.
> 
> The original code assumed the opposite, resulting in a warning when
> the PLL clock rate was changed but never lost it's lock as far as
> the readout indicated. This was verified by checking the read out
> register value.
> 
> Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure")
> Signed-off-by: Chen-Yu Tsai 
> Acked-by: Maxime Ripard 

Applied, thanks

Maxime

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[linux-sunxi] [PATCH 7/9] clk: sunxi-ng: mux: Add clk notifier functions

[Chen-Yu Tsai]

On sunxi we support cpufreq by changing the clock rate of PLL-CPU.
It's possible the clock output of the PLL goes out of the CPU's
operational limits when the PLL's multipliers / dividers are changed
and it hasn't stabilized yet. This would result in the CPU hanging.

To circumvent this, we temporarily switch the CPU mux clock to another
stable clock before the rate change, and switch it back after the PLL
stabilizes. This is done with clk notifiers registered on the PLL.

This patch adds common functions for notifiers to reparent mux clocks.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_mux.c | 36 
 drivers/clk/sunxi-ng/ccu_mux.h | 14 ++
 2 files changed, 50 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index f96eabb5d1f3..8a6e9065cb85 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -8,7 +8,9 @@
  * the License, or (at your option) any later version.
  */
 
+#include 
 #include 
+#include 
 
 #include "ccu_gate.h"
 #include "ccu_mux.h"
@@ -199,3 +201,37 @@ const struct clk_ops ccu_mux_ops = {
.determine_rate = __clk_mux_determine_rate,
.recalc_rate= ccu_mux_recalc_rate,
 };
+
+/*
+ * This clock notifier is called when the frequency of the of the parent
+ * PLL clock is to be changed. The idea is to switch the parent to a
+ * stable clock, such as the main oscillator, while the PLL frequency
+ * stabilizes.
+ */
+static int ccu_mux_notifier_cb(struct notifier_block *nb,
+  unsigned long event, void *data)
+{
+   struct ccu_mux_nb *mux = to_ccu_mux_nb(nb);
+   int ret = 0;
+
+   if (event == PRE_RATE_CHANGE) {
+   mux->original_index = ccu_mux_helper_get_parent(mux->common,
+   mux->cm);
+   ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
+   mux->bypass_index);
+   } else if (event == POST_RATE_CHANGE) {
+   ret = ccu_mux_helper_set_parent(mux->common, mux->cm,
+   mux->original_index);
+   }
+
+   udelay(mux->delay_us);
+
+   return notifier_from_errno(ret);
+}
+
+int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb)
+{
+   mux_nb->clk_nb.notifier_call = ccu_mux_notifier_cb;
+
+   return clk_notifier_register(clk, _nb->clk_nb);
+}
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 28d16ec18d55..7ddd9b2c6dbc 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -98,4 +98,18 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
  struct ccu_mux_internal *cm,
  u8 index);
 
+struct ccu_mux_nb {
+   struct notifier_block   clk_nb;
+   struct ccu_common   *common;
+   struct ccu_mux_internal *cm;
+
+   u32 delay_us;   /* How many us to wait after reparenting */
+   u8  bypass_index;   /* Which parent to temporarily use */
+   u8  original_index; /* This is set by the notifier callback */
+};
+
+#define to_ccu_mux_nb(_nb) container_of(_nb, struct ccu_mux_nb, clk_nb)
+
+int ccu_mux_notifier_register(struct clk *clk, struct ccu_mux_nb *mux_nb);
+
 #endif /* _CCU_MUX_H_ */
-- 
2.8.1

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[linux-sunxi] [PATCH 4/9] clk: sunxi-ng: mux: Add support for mux tables

[Chen-Yu Tsai]

Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.

Add support for specifying a mux table to map clock parents to
mux values.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_mux.c | 12 
 drivers/clk/sunxi-ng/ccu_mux.h | 12 ++--
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 1329b9ab481e..68b32f168a74 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -107,6 +107,15 @@ u8 ccu_mux_helper_get_parent(struct ccu_common *common,
parent = reg >> cm->shift;
parent &= (1 << cm->width) - 1;
 
+   if (cm->table) {
+   int num_parents = clk_hw_get_num_parents(>hw);
+   int i;
+
+   for (i = 0; i < num_parents; i++)
+   if (cm->table[i] == parent)
+   return i;
+   }
+
return parent;
 }
 
@@ -117,6 +126,9 @@ int ccu_mux_helper_set_parent(struct ccu_common *common,
unsigned long flags;
u32 reg;
 
+   if (cm->table)
+   index = cm->table[index];
+
spin_lock_irqsave(common->lock, flags);
 
reg = readl(common->base + common->reg);
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index d35ce5e93840..f0078de78712 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -6,8 +6,9 @@
 #include "ccu_common.h"
 
 struct ccu_mux_internal {
-   u8  shift;
-   u8  width;
+   u8  shift;
+   u8  width;
+   const u8*table;
 
struct {
u8  index;
@@ -21,6 +22,13 @@ struct ccu_mux_internal {
} variable_prediv;
 };
 
+#define SUNXI_CLK_MUX_TABLE(_shift, _width, _table)\
+   {   \
+   .shift  = _shift,   \
+   .width  = _width,   \
+   .table  = _table,   \
+   }
+
 #define SUNXI_CLK_MUX(_shift, _width)  \
{   \
.shift  = _shift,   \
-- 
2.8.1

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[linux-sunxi] [PATCH 6/9] clk: sunxi-ng: nkm: Add mux to support multiple parents

[Chen-Yu Tsai]

The MIPI mode of the MIPI-PLL on A31 is an NKM-style PLL with 2
selectable parents.

Add mux support to the NKM clock.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_nkm.c | 40 ++--
 drivers/clk/sunxi-ng/ccu_nkm.h | 23 +++
 2 files changed, 57 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 2071822b1e9c..182452919ede 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -93,19 +93,30 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
return parent_rate * (n + 1) * (k + 1) / (m + 1);
 }
 
-static long ccu_nkm_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
+   unsigned long parent_rate,
+   unsigned long rate,
+   void *data)
 {
-   struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
+   struct ccu_nkm *nkm = data;
struct _ccu_nkm _nkm;
 
_nkm.max_n = 1 << nkm->n.width;
_nkm.max_k = 1 << nkm->k.width;
_nkm.max_m = 1 << nkm->m.width;
 
-   ccu_nkm_find_best(*parent_rate, rate, &_nkm);
+   ccu_nkm_find_best(parent_rate, rate, &_nkm);
 
-   return *parent_rate * _nkm.n * _nkm.k / _nkm.m;
+   return parent_rate * _nkm.n * _nkm.k / _nkm.m;
+}
+
+static int ccu_nkm_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+   struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
+
+   return ccu_mux_helper_determine_rate(>common, >mux,
+req, ccu_nkm_round_rate, nkm);
 }
 
 static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -142,12 +153,29 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned 
long rate,
return 0;
 }
 
+static u8 ccu_nkm_get_parent(struct clk_hw *hw)
+{
+   struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
+
+   return ccu_mux_helper_get_parent(>common, >mux);
+}
+
+static int ccu_nkm_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct ccu_nkm *nkm = hw_to_ccu_nkm(hw);
+
+   return ccu_mux_helper_set_parent(>common, >mux, index);
+}
+
 const struct clk_ops ccu_nkm_ops = {
.disable= ccu_nkm_disable,
.enable = ccu_nkm_enable,
.is_enabled = ccu_nkm_is_enabled,
 
+   .get_parent = ccu_nkm_get_parent,
+   .set_parent = ccu_nkm_set_parent,
+
+   .determine_rate = ccu_nkm_determine_rate,
.recalc_rate= ccu_nkm_recalc_rate,
-   .round_rate = ccu_nkm_round_rate,
.set_rate   = ccu_nkm_set_rate,
 };
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.h b/drivers/clk/sunxi-ng/ccu_nkm.h
index 1936ac1c6b37..fcb152fc4eda 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.h
+++ b/drivers/clk/sunxi-ng/ccu_nkm.h
@@ -32,10 +32,33 @@ struct ccu_nkm {
struct _ccu_multn;
struct _ccu_multk;
struct _ccu_div m;
+   struct ccu_mux_internal mux;
 
struct ccu_common   common;
 };
 
+#define SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(_struct, _name, _parents, _reg, \
+_nshift, _nwidth,  \
+_kshift, _kwidth,  \
+_mshift, _mwidth,  \
+_muxshift, _muxwidth,  \
+_gate, _lock, _flags)  \
+   struct ccu_nkm _struct = {  \
+   .enable = _gate,\
+   .lock   = _lock,\
+   .k  = _SUNXI_CCU_MULT(_kshift, _kwidth),\
+   .n  = _SUNXI_CCU_MULT(_nshift, _nwidth),\
+   .m  = _SUNXI_CCU_DIV(_mshift, _mwidth), \
+   .mux= SUNXI_CLK_MUX(_muxshift, _muxwidth),  \
+   .common = { \
+   .reg= _reg, \
+   .hw.init= CLK_HW_INIT_PARENTS(_name,\
+ _parents, \
+ _nkm_ops, \
+ _flags),  \
+   },  \
+   }
+
 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg,\
 _nshift, _nwidth,  \
 _kshift, _kwidth,  \
-- 
2.8.1

-- 
You received 

[linux-sunxi] [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Chen-Yu Tsai]

Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

- EMAC clock

Signed-off-by: Chen-Yu Tsai 
---
 .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-
 drivers/clk/sunxi-ng/Kconfig   |   10 +
 drivers/clk/sunxi-ng/Makefile  |1 +
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
 include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
 include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
 7 files changed, 1608 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
 create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
 create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index cb91507ffb1e..eac458720b28 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -2,7 +2,8 @@ Allwinner Clock Control Unit Binding
 
 
 Required properties :
-- compatible: must contain one of the following compatible:
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-h3-ccu"
 
 - reg: Must contain the registers base address and length
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 2afcbd39e41e..a1dee861474c 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -51,6 +51,16 @@ config SUNXI_CCU_MP
 
 # SoC Drivers
 
+config SUN6I_A31_CCU
+   bool "Support for the Allwinner A31/A31s CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN6I
+
 config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 633ce642ffae..261438b00215 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_SUNXI_CCU_NM)+= ccu_nm.o
 obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
 
 # SoC support
+obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
new file mode 100644
index ..ee1208aa9c0a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -0,0 +1,1230 @@
+/*
+ * Copyright (c) 2016 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * Based on ccu-sun8i-h3.c by Maxime Ripard.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_mux.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun6i-a31.h"
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
+"osc24M", 0x000,
+8, 5,  /* N */
+4, 2,  /* K */
+0, 2,  /* M */
+BIT(31),   /* gate */
+BIT(28),   /* lock */
+0);
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN6I_A31_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,/* M */
+  BIT(31), /* gate */
+  BIT(28), /* lock */
+  0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, 

[linux-sunxi] [PATCH 3/9] clk: sunxi-ng: mux: Increase fixed pre-divider div size

[Chen-Yu Tsai]

Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.

Increase the size of the div field to u16.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_mux.c | 2 +-
 drivers/clk/sunxi-ng/ccu_mux.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 58fc36e7dcce..1329b9ab481e 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -18,7 +18,7 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct 
ccu_common *common,
 int parent_index,
 unsigned long *parent_rate)
 {
-   u8 prediv = 1;
+   u16 prediv = 1;
u32 reg;
 
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index 945082631e7d..d35ce5e93840 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -11,7 +11,7 @@ struct ccu_mux_internal {
 
struct {
u8  index;
-   u8  div;
+   u16 div;
} fixed_prediv;
 
struct {
-- 
2.8.1

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[linux-sunxi] [PATCH 2/9] clk: sunxi-ng: nk: Make ccu_nk_find_best static

[Chen-Yu Tsai]

make C=2 reports:

  CHECK   drivers/clk/sunxi-ng/ccu_nk.c
drivers/clk/sunxi-ng/ccu_nk.c:17:6: warning: symbol 'ccu_nk_find_best' was
not declared. Should it be static?

ccu_nk_find_best is only used within ccu_nk.c. So make it static to get
rid of this warning.

Fixes: adbfb0056e03 ("clk: sunxi-ng: Add N-K-factor clock support")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_nk.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index 4470ffc8cf0d..d6fafb397489 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -14,9 +14,9 @@
 #include "ccu_gate.h"
 #include "ccu_nk.h"
 
-void ccu_nk_find_best(unsigned long parent, unsigned long rate,
- unsigned int max_n, unsigned int max_k,
- unsigned int *n, unsigned int *k)
+static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
+unsigned int max_n, unsigned int max_k,
+unsigned int *n, unsigned int *k)
 {
unsigned long best_rate = 0;
unsigned int best_k = 0, best_n = 0;
-- 
2.8.1

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[linux-sunxi] [PATCH 9/9] ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings

[Chen-Yu Tsai]

Now that we have a different clock representation, switch to it.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 424 +--
 1 file changed, 97 insertions(+), 327 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1867af24ff52..6a84fe7e9ab2 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -47,7 +47,9 @@
 #include 
 #include 
 
+#include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -65,7 +67,10 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
-   clocks = < 0>;
+   clocks = < CLK_AHB1_BE0>, < CLK_AHB1_LCD0>,
+< CLK_AHB1_HDMI>, < CLK_DRAM_BE0>,
+< CLK_IEP_DRC0>, < CLK_BE0>,
+< CLK_LCD0_CH1>, < CLK_HDMI>;
status = "disabled";
};
 
@@ -73,7 +78,9 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = < 0>;
+   clocks = < CLK_AHB1_BE0>, < CLK_AHB1_LCD0>,
+< CLK_DRAM_BE0>, < CLK_IEP_DRC0>,
+< CLK_BE0>, < CLK_LCD0_CH0>;
status = "disabled";
};
};
@@ -97,7 +104,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
-   clocks = <>;
+   clocks = < CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHzuV */
@@ -192,235 +199,6 @@
clock-output-names = "osc32k";
};
 
-   pll1: clk@01c2 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun6i-a31-pll1-clk";
-   reg = <0x01c2 0x4>;
-   clocks = <>;
-   clock-output-names = "pll1";
-   };
-
-   pll6: clk@01c20028 {
-   #clock-cells = <1>;
-   compatible = "allwinner,sun6i-a31-pll6-clk";
-   reg = <0x01c20028 0x4>;
-   clocks = <>;
-   clock-output-names = "pll6", "pll6x2";
-   };
-
-   cpu: cpu@01c20050 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-cpu-clk";
-   reg = <0x01c20050 0x4>;
-
-   /*
-* PLL1 is listed twice here.
-* While it looks suspicious, it's actually documented
-* that way both in the datasheet and in the code from
-* Allwinner.
-*/
-   clocks = <>, <>, <>, <>;
-   clock-output-names = "cpu";
-   };
-
-   axi: axi@01c20050 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-axi-clk";
-   reg = <0x01c20050 0x4>;
-   clocks = <>;
-   clock-output-names = "axi";
-   };
-
-   ahb1: ahb1@01c20054 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun6i-a31-ahb1-clk";
-   reg = <0x01c20054 0x4>;
-   clocks = <>, <>, <>, < 0>;
-   clock-output-names = "ahb1";
-
-   /*
-* Clock AHB1 from PLL6, instead of CPU/AXI which
-* has rate changes due to cpufreq. Also the DMA
-* controller requires AHB1 clocked from PLL6.
-*/
-   assigned-clocks = <>;
-   assigned-clock-parents = < 0>;
-   };
-
-   ahb1_gates: clk@01c20060 {
-   #clock-cells = <1>;
-   compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
-   reg = <0x01c20060 0x8>;
-   clocks = <>;
-   clock-indices = <1>, <5>,
-   <6>, <8>, <9>,
-   <10>, <11>, <12>,
-   <13>, <14>,
-   <17>, <18>, <19>,
-   <20>, <21>, <22>,
-   

[linux-sunxi] [PATCH resend 1/9] clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock

[Chen-Yu Tsai]

The condition passed to read*_poll_timeout() is the break condition,
i.e. wait for this condition to happen and return success.

The original code assumed the opposite, resulting in a warning when
the PLL clock rate was changed but never lost it's lock as far as
the readout indicated. This was verified by checking the read out
register value.

Fixes: 1d80c14248d6 ("clk: sunxi-ng: Add common infrastructure")
Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
---
 drivers/clk/sunxi-ng/ccu_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu_common.c 
b/drivers/clk/sunxi-ng/ccu_common.c
index fc17b5295e16..51d4bac97ab3 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -31,7 +31,7 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 
lock)
return;
 
WARN_ON(readl_relaxed_poll_timeout(common->base + common->reg, reg,
-  !(reg & lock), 100, 7));
+  reg & lock, 100, 7));
 }
 
 int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
-- 
2.8.1

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[linux-sunxi] [PATCH 0/9] clk: sunxi-ng: Support A31/A31s CCU

[Chen-Yu Tsai]

Hi everyone,

This series adds support for the A31/A31s CCU (clock control unit) with
the new sunxi-ng binding/driver. This is a near complete driver, with a
few features unimplemented or might need reworking:

  - The HDMI mode of the PLL-MIPI clock is unsupported.

  - The EMAC clock is unimplemented. In the past we modelled this as a
clock. Unforunately that doesn't work very well. While it is sort
of a clock control, with clock inverters and delay chains, it also
controls the interface mode of the EMAC. On later SoCs this register
is moved out of the CCU, into the system control register range.
Other platforms consider this a part of the ethernet controller glue
logic, and map and use it directly as part of the controller bindings.
I would like to do the same.

  - The A31 has 2 SDRAM clocks and 2 MBUS clocks. As such we can't have
them all as the DRAM gate clocks' parent. Instead I'm using the MDFS
clock as their parent. It is unclear what MDFS actually is, but the
close proximity of the registers to the DRAM bits, and hints about
this tied to DRAM DVFS suggest this is a common memory bus. If we're
wrong we can always fix this as the relationship is part of the driver,
not the binding. Also, all 5 clocks are marked as critical.

Various changes were made to the common (to sunxi-ng) clock types to make
them compatible with the A31/A31s' CCU's design.

Also new is support for clk notifiers for mux clocks. This is needed for
the cpu clock, which should be muxed to the stable main oscillator when
the PLL-CPU clock rate is changed, to avoid any instabilities in the PLL
which result in the CPU crashing. This is similar to what the meson
platform does.


Regards
ChenYu

Chen-Yu Tsai (9):
  clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
  clk: sunxi-ng: nk: Make ccu_nk_find_best static
  clk: sunxi-ng: mux: Increase fixed pre-divider div size
  clk: sunxi-ng: mux: Add support for mux tables
  clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents
  clk: sunxi-ng: nkm: Add mux to support multiple parents
  clk: sunxi-ng: mux: Add clk notifier functions
  clk: sunxi-ng: Add A31/A31s clocks
  ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings

 .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-
 arch/arm/boot/dts/sun6i-a31.dtsi   |  424 ++-
 drivers/clk/sunxi-ng/Kconfig   |   10 +
 drivers/clk/sunxi-ng/Makefile  |1 +
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c|9 +-
 drivers/clk/sunxi-ng/ccu_common.c  |2 +-
 drivers/clk/sunxi-ng/ccu_mux.c |   56 +-
 drivers/clk/sunxi-ng/ccu_mux.h |   36 +-
 drivers/clk/sunxi-ng/ccu_nk.c  |6 +-
 drivers/clk/sunxi-ng/ccu_nkm.c |   40 +-
 drivers/clk/sunxi-ng/ccu_nkm.h |   23 +
 include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
 include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
 15 files changed, 1854 insertions(+), 351 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
 create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
 create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

-- 
2.8.1

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[linux-sunxi] [PATCH 5/9] clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents

[Chen-Yu Tsai]

Some clocks on the A31 have fixed pre-dividers on multiple parents.
Add support for them.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c |  9 +
 drivers/clk/sunxi-ng/ccu_mux.c  |  6 --
 drivers/clk/sunxi-ng/ccu_mux.h  | 10 ++
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 9af359544110..5f5c900c235b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -184,15 +184,16 @@ static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", 
apb2_parents, 0x058,
 0);
 
 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
+static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
+   { .index = 1, .div = 2},
+   { },
+};
 static struct ccu_mux ahb2_clk = {
.mux= {
.shift  = 0,
.width  = 1,
 
-   .fixed_prediv   = {
-   .index  = 1,
-   .div= 2,
-   },
+   .fixed_predivs  = ahb2_fixed_predivs,
},
 
.common = {
diff --git a/drivers/clk/sunxi-ng/ccu_mux.c b/drivers/clk/sunxi-ng/ccu_mux.c
index 68b32f168a74..f96eabb5d1f3 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.c
+++ b/drivers/clk/sunxi-ng/ccu_mux.c
@@ -20,6 +20,7 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct 
ccu_common *common,
 {
u16 prediv = 1;
u32 reg;
+   int i;
 
if (!((common->features & CCU_FEATURE_FIXED_PREDIV) ||
  (common->features & CCU_FEATURE_VARIABLE_PREDIV)))
@@ -32,8 +33,9 @@ void ccu_mux_helper_adjust_parent_for_prediv(struct 
ccu_common *common,
}
 
if (common->features & CCU_FEATURE_FIXED_PREDIV)
-   if (parent_index == cm->fixed_prediv.index)
-   prediv = cm->fixed_prediv.div;
+   for (i = 0; cm->fixed_predivs[i].div; i++)
+   if (parent_index == cm->fixed_predivs[i].index)
+   prediv = cm->fixed_predivs[i].div;
 
if (common->features & CCU_FEATURE_VARIABLE_PREDIV)
if (parent_index == cm->variable_prediv.index) {
diff --git a/drivers/clk/sunxi-ng/ccu_mux.h b/drivers/clk/sunxi-ng/ccu_mux.h
index f0078de78712..28d16ec18d55 100644
--- a/drivers/clk/sunxi-ng/ccu_mux.h
+++ b/drivers/clk/sunxi-ng/ccu_mux.h
@@ -5,15 +5,17 @@
 
 #include "ccu_common.h"
 
+struct ccu_mux_fixed_prediv {
+   u8  index;
+   u16 div;
+};
+
 struct ccu_mux_internal {
u8  shift;
u8  width;
const u8*table;
 
-   struct {
-   u8  index;
-   u16 div;
-   } fixed_prediv;
+   const struct ccu_mux_fixed_prediv   *fixed_predivs;
 
struct {
u8  index;
-- 
2.8.1

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[linux-sunxi] Re: [PATCH v2 06/14] ARM: sun8i: clk: Add clk-factor rate application method

[Maxime Ripard]

On Thu, Jul 21, 2016 at 11:52:15AM +0200, Ondřej Jirman wrote:
> >>> If so, then yes, trying to switch to the 24MHz oscillator before
> >>> applying the factors, and then switching back when the PLL is stable
> >>> would be a nice solution.
> >>>
> >>> I just checked, and all the SoCs we've had so far have that
> >>> possibility, so if it works, for now, I'd like to stick to that.
> >>
> >> It would need to be tested. U-boot does the change only once, while the
> >> kernel would be doing it all the time and between various frequencies
> >> and PLL settings. So the issues may show up with this solution too.
> > 
> > That would have the benefit of being quite easy to document, not be a
> > huge amount of code and it would work on all the CPUs PLLs we have so
> > far, so still, a pretty big win. If it doesn't, of course, we don't
> > really have the choice.
> 
> It's probably more code though. It has to access different register from
> the one that is already defined in dts, which would add a lot of code
> and require dts changes. The original patch I sent is simpler than that.

Why?

You can use container_of to retrieve the parent structure of the clock
notifier, and then you get a ccu_common structure pointer, with the
CCU base address, the clock register, its lock, etc.

Look at what is done in drivers/clk/meson/clk-cpu.c. It's like 20 LoC.

I don't really get why anything should be changed in the DT, or why it
would add a lot of code. Or maybe we're not talking about the same
thing?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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