[linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-28 Thread Chen-Yu Tsai 
On Sat, Oct 29, 2016 at 1:30 AM, Hans de Goede  wrote:
> Hi Chen-Yu,
>
> On 28-10-16 12:21, Chen-Yu Tsai wrote:
>>
>> Hi everyone,
>>
>> This series adds full SPL with DRAM initialization for sun9i (A80).
>> The bulk of the work was done by the people at Theobroma Systems.
>> Their work can be found here:
>>
>> https://git.theobroma-systems.com/armadillo-u-boot.git/
>>
>> I picked the essential patches and cleaned them up a bit more,
>> and added commit messages if they were missing.
>>
>> As the DRAM bits are essentially a code dump with some cleanups and
>> some bits disabled, expect many warnings. Checkpatch is still not
>> happy with it.
>>
>> I've tested the series on both my A80 boards, which I've added
>> defconfigs for in the last 2 patches. My A80 Optimus does not
>> boot from micro SD, so I'm still FEL booting that one. But my
>> Cubieboard 4 is now standalone.
>>
>> As usual, please have a look, test if possible.
>
>
> Awesome, thanks for doing this and it was good to have
> some face2face time at ELCE.
>
> I've merged this into my personal sunxi-wip u-boot branch,
> I've made 2 changes:
>
> 1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
> lot of #if 0 #endif blocks, most of these document some features
> which we may want to enable in the future, but a few were just
> dead weight IMHO, so I've pruned a few

Thanks. I suppose some of the testing and verbose debug calls
aren't needed. Most of the #if 0 blocks within data structures
were C99 // comments that I fixed up to get checkpatch happy.

About the features, I was already half way through the clock
code cleanup when Maxime pointed me to Theobroma's repository,
so I could add and test sigma delta modulation for PLL DDR.

For the other types of DRAM we could clean it up, but there's
really no hardware to test it on.

> 2) in : "sunxi: Add support for A80 Optimus board", we already
> have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
> update that instead of adding a new defconfig

Cool. I didn't notice.

> I have not tested this yet, I will do tomorrow, assuming it
> works for me too I will include it in my next pull-req (*) and
> try to get it included in the 2016.11 release, yes the merge
> window has closed, but the changes here are very isolated so
> I will try and see what Tom says :)

Do you need me to send a v2 addressing review comments?

Thanks
ChenYu

>
> Regards,
>
> Hans
>
>
> *) Which I hope to send out this weekend
>
>
>
>
>>
>>
>> Regards
>> ChenYu
>>
>>
>> Chen-Yu Tsai (5):
>>   sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
>>   sunxi: Add support for SID e-fuses on sun9i
>>   sunxi: Add default zq value for sun9i (A80)
>>   sunxi: Add support for A80 Optimus board
>>   sunxi: Add support for Cubieboard4
>>
>> Philipp Tomsich (6):
>>   sunxi: DRAM initialisation for sun9i
>>   sunxi: add gtbus-initialisation for sun9i
>>   sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
>>   sunxi: add initial clock setup for sun9i for SPL
>>   sunxi: enable SPL for sun9i
>>   sunxi: add MMC pinmux setup for SDC2 on sun9i
>>
>>  arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
>>  arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
>>  arch/arm/include/asm/arch-sunxi/dram.h|2 +
>>  arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
>>  arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
>>  arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
>>  arch/arm/mach-sunxi/Makefile  |2 +
>>  arch/arm/mach-sunxi/board.c   |3 +-
>>  arch/arm/mach-sunxi/clock.c   |6 +
>>  arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
>>  arch/arm/mach-sunxi/dram_sun9i.c  | 1059
>> +
>>  arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
>>  board/sunxi/Kconfig   |   10 +-
>>  board/sunxi/MAINTAINERS   |   10 +
>>  board/sunxi/board.c   |7 +
>>  configs/A80_Optimus_defconfig |   18 +
>>  configs/Cubieboard4_defconfig |   18 +
>>  17 files changed, 1818 insertions(+), 22 deletions(-)
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
>>  create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
>>  create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
>>  create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
>>  create mode 100644 configs/A80_Optimus_defconfig
>>  create mode 100644 configs/Cubieboard4_defconfig
>>
>

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[linux-sunxi] Re: [PATCH v2] phy: sun4i: check PMU presence when poking unknown bit of pmu

2016-10-28 Thread Hans de Goede 

Hi,

On 28-10-16 18:27, Icenowy Zheng wrote:

Allwinner SoC's PHY 0, when used as OTG controller, have no pmu part.
The code that poke some unknown bit of PMU for H3/A64 didn't check
the PHY, and will cause kernel oops when PHY 0 is used.

This patch will check whether the pmu is not NULL before poking.

Fixes: b3e0d141ca9f (phy: sun4i: add support for A64 usb phy)

Signed-off-by: Icenowy Zheng 
Acked-by: Maxime Ripard 


Patch LGTM too:

Reviewed-by: Hans de Goede 

Regards,

Hans



---
 drivers/phy/phy-sun4i-usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index b9342a2..fec34f5 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -264,7 +264,7 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}

-   if (data->cfg->enable_pmu_unk1) {
+   if (phy->pmu && data->cfg->enable_pmu_unk1) {
val = readl(phy->pmu + REG_PMU_UNK1);
writel(val & ~2, phy->pmu + REG_PMU_UNK1);
}



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Re: [linux-sunxi] [PATCH RESEND 1/2] dt: bindings: add allwinner,otg-routed property for phy-sun4i-usb

2016-10-28 Thread Hans de Goede 

HI,

On 26-10-16 12:14, Hans de Goede wrote:

Hi,

On 26-10-16 10:52, Icenowy Zheng wrote:



26.10.2016, 16:28, "Hans de Goede" :

Hi,

On 25-10-16 06:11, Icenowy Zheng wrote:

 On some newer Allwinner SoCs (H3 or A64), the PHY0 can be either routed to
 the MUSB controller (which is an OTG controller) or the OHCI/EHCI pair
 (which is a Host-only controller, but more stable and easy to implement).

 This property marks whether on a certain board which controller should be
 attached to the PHY.

 Signed-off-by: Icenowy Zheng 


Icenowy, I appreciate your work on this, but we really need full otg
support with dynamic switching rather then hardwiring the routing, so
this cannot go in as is.


Now I have both PHY0 controllers' drivers.

In the tree of https://github.com/Icenowy/linux/tree/ice-a64-v6.1 , I have 
already
enabled MUSB controller.

And this patchset is for those prefer a stable USB host implement to dual-role
implementation. MUSB is a good UDC, but not a good host controller. My USB
sound card cannot work on MUSB on A33. Even connecting a R8's MUSB (Serial
Gadget) to an A33's MUSB cannot work.


The idea is for dual-role setups to used the MUSB in gadget mode and the 
EHCI/OHCI
pair when in host mode. So for otg setups you would runtime change the mux
from one controller to the other based on the id pin value.

Take a look at drivers/phy/phy-sun4i-usb.c, around line 512:

if (id_det != data->id_det) {
...
}

This deals with id_det changes (including the initial id_det "change"
for hardwired host-only ports). This currently assumes that the musb
will be used for host mode too, we will want to change this to
something like this:

if (id_det != data->id_det) {
if (data->cfg->separate_phy0_host_controller) {
if (id_det) {
/* Change to gadget mode (id_det == 1), switch phy mux to musb 
*/
actual code to switch phy mux to musb...
} else {
/* Change to host mode (id_det == 0), switch phy mux to 
ehci/ohci */
actual code to switch phy mux to ehci/ohci...
}
}
/* old code */
}

Note this will then still rely on the musb code to actually turn
the regulator on, so you do need to have the musb driver build and
loaded. This can be fixed but lets start with the above.

If you combine this with dr_mode = "host"; in the dts, then
sun4i_usb_phy0_get_id_det() will return 0 so on its first run
sun4i_usb_phy0_id_vbus_det_scan() will throw the mux to the ehci/ohci
and everything should work as you want without needing the custom
"allwinner,otg-routed" property, and we should be more or less
ready to support full otg on other boards.


I've just found further proof that the musb on the H3 at least
only is intended for gadget mode and that we must dynamically
switch for host-mode. If you look at:

drivers/usb/sunxi_usb/include/sunxi_udc.h

In the h3 sdk then you will see that for the H3 a different fifo
endpoint table is used, as the total fifo space is only 4k where
as previous SoCs had 8k. This means that we need to have 2
different ep tables in drivers/usb/musb/sunxi.c and select by
compatible.

Regards,

Hans

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[linux-sunxi] Re: [PATCH v5 1/7] drm: sunxi: Add a basic DRM driver for Allwinner DE2

2016-10-28 Thread Jean-Francois Moine 
On Fri, 28 Oct 2016 00:03:16 +0200
Maxime Ripard  wrote:

> On Tue, Oct 25, 2016 at 04:14:41PM +0200, Jean-Francois Moine wrote:
> > > > +Display controller
> > > > +==
> > > > +
> > > > +Required properties:
> > > > +
> > > > +- compatible: value should be one of the following
> > > > +   "allwinner,sun8i-a83t-display-engine"
> > > > +   "allwinner,sun8i-h3-display-engine"
> > > > +
> > > > +- clocks: must include clock specifiers corresponding to entries in the
> > > > +   clock-names property.
> > > > +
> > > > +- clock-names: must contain
> > > > +   "gate": for DE activation
> > > > +   "clock": DE clock
> > > 
> > > We've been calling them bus and mod.
> > 
> > I can understand "bus" (which is better than "apb"), but why "mod"?
> 
> Allwinner has been calling the clocks that are supposed to generate
> the external signals (depending on where you were looking) module or
> mod clocks (which is also why we have mod in the clock
> compatibles). The module 1 clocks being used for the audio and the
> module 0 for the rest (SPI, MMC, NAND, display, etc.)

I did not find any 'module' in the H3 documentation.
So, is it really a good name?

> > > > +
> > > > +- resets: phandle to the reset of the device
> > > > +
> > > > +- ports: phandle's to the LCD ports
> > > 
> > > Please use the OF graph.
> > 
> > These ports are references to the graph of nodes. See
> > http://www.kernelhub.org/?msg=911825=2
> 
> In an OF-graph, your phandle to the LCD controller would be replaced
> by an output endpoint.

This is the DE controller. There is no endpoint link at this level.
The Device Engine just handles the planes of the LCDs, but, indeed,
the LCDs must know about the DE and the DE must know about the LCDs.
There are 2 ways to realize this knowledge in the DT:
1) either the DE has one or two phandle's to the LCDs,
2) or the LCDs have a phandle to the DE.

I chose the 1st way, the DE ports pointing to the endpoint of the LCDs
which is part of the video link (OF-graph LCD <-> connector).
It would be possible to have phandles to the LCDs themselves, but this
asks for more code.

The second way is also possible, but it also complexifies a bit the
exchanges DE <-> LCD.

> > [snip]
> > > > +struct tcon {
> > > > +   u32 gctl;
> > > > +#defineTCON_GCTL_TCON_En BIT(31)
[snip]
> > > > +   u32 fill_ctl;   /* 0x300 */
> > > > +   u32 fill_start0;
> > > > +   u32 fill_end0;
> > > > +   u32 fill_data0;
> > > > +};
> > > 
> > > Please use defines instead of the structures.
> > 
> > I think that structures are more readable.
> 
> That's not really the point. No one in the kernel uses it (and even
> you use defines for registers offset in some places of that
> patch). And then you have André arguments.

I am not convinced, but I'll do as you said.

> > > > +void de2_disable_vblank(struct drm_device *drm, unsigned crtc)
> > > > +{
> > > > +   struct priv *priv = drm->dev_private;
> > > > +   struct lcd *lcd = priv->lcds[crtc];
> > > > +
> > > > +   tcon_write(lcd->mmio, gint0,
> > > > +tcon_read(lcd->mmio, gint0) &
> > > > +   ~TCON_GINT0_TCON1_Vb_Int_En);
> > > > +}
> > > > +
> > > > +/* panel functions */
> > > 
> > > Panel functions? In the CRTC driver?
> > 
> > Yes, dumb panel.
> 
> What do you mean by that? Using a Parallel/RGB interface?

Sorry, I though this was a well-known name. The 'dump panel' was used
in the documentation of my previous ARM machine as the video frame sent
to the HDMI controller. 'video_frame' is OK for you?

[snip]
> > > > +   ret = clk_prepare_enable(lcd->clk);
> > > > +   if (ret)
> > > > +   goto err2;
> > > 
> > > Is there any reason not to do that in the enable / disable? Leaving
> > > clocks running while the device has no guarantee that it's going to be
> > > used seems like a waste of resources.
> > 
> > If the machine does not need video (network server, router..), it is simpler
> > to prevent the video driver to be loaded (DT, module black list...).
> 
> You might not have control on any of it, or you might just have no
> monitor attached for example. Recompiling the kernel or updating the
> DT when you want to plug an HDMI monitor seems like a poor UX :)

OK, I will check if this works.

> > > > +static const struct {
> > > > +   char chan;
> > > > +   char layer;
> > > > +   char pipe;
> > > > +} plane2layer[DE2_N_PLANES] = {
> > > > +   [DE2_PRIMARY_PLANE] =   {0, 0, 0},
> > > > +   [DE2_CURSOR_PLANE] ={1, 0, 1},
> > > > +   [DE2_VI_PLANE] ={0, 1, 0},
> > > > +};
> > > 
> > > Comments?
> > 
> > This
> > primary plane is channel 0 (VI), layer 0, pipe 0
> > cursor plane is channel 1 (UI), layer 0, pipe 1
> > overlay plane is channel 0 (VI), layer 1, pipe 0
> > or the

[linux-sunxi] [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

2016-10-28 Thread Chen-Yu Tsai 
Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.


Regards
ChenYu


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Add support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  116 ++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |   10 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/include/asm/arch-sunxi/gtbus.h   |   21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |   89 +++
 arch/arm/mach-sunxi/Makefile  |2 +
 arch/arm/mach-sunxi/board.c   |3 +-
 arch/arm/mach-sunxi/clock.c   |6 +
 arch/arm/mach-sunxi/clock_sun9i.c |  146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 arch/arm/mach-sunxi/gtbus_sun9i.c |   48 ++
 board/sunxi/Kconfig   |   10 +-
 board/sunxi/MAINTAINERS   |   10 +
 board/sunxi/board.c   |7 +
 configs/A80_Optimus_defconfig |   18 +
 configs/Cubieboard4_defconfig |   18 +
 17 files changed, 1818 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
 create mode 100644 configs/A80_Optimus_defconfig
 create mode 100644 configs/Cubieboard4_defconfig

-- 
2.9.3

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[linux-sunxi] [PATCH 08/11] sunxi: Add support for SID e-fuses on sun9i

2016-10-28 Thread Chen-Yu Tsai 
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses
are at an offset of 0x200 within the SID address space.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index ba18a0f551ad..c775bcc515a0 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -24,6 +24,8 @@
 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
 
 #define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
+/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200)
 
 #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
 #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
-- 
2.9.3

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[linux-sunxi] [PATCH 10/11] sunxi: Add support for A80 Optimus board

2016-10-28 Thread Chen-Yu Tsai 
The A80 Optimus Board was launched with the Allwinner A80 SoC.
It was jointly developed by Allwinner and Merrii.

This board has a UART port, a JTAG connector, 2 USB host ports, a USB
3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash,
2G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone
jack, IR receiver, and additional GPIO headers.

Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/MAINTAINERS   |  5 +
 configs/A80_Optimus_defconfig | 18 ++
 2 files changed, 23 insertions(+)
 create mode 100644 configs/A80_Optimus_defconfig

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index f7129b7d53a5..6e0aa24eb859 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -94,6 +94,11 @@ M:   Stefan Mavrodiev 
 S: Maintained
 F: configs/A33-OLinuXino_defconfig
 
+A80 OPTIMUS BOARD
+M: Chen-Yu Tsai 
+S: Maintained
+F: configs/A80_Optimus_defconfig
+
 AINOL AW1 BOARD
 M: Paul Kocialkowski 
 S: Maintained
diff --git a/configs/A80_Optimus_defconfig b/configs/A80_Optimus_defconfig
new file mode 100644
index ..6397de5de5fd
--- /dev/null
+++ b/configs/A80_Optimus_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN9I=y
+CONFIG_DRAM_CLK=672
+CONFIG_MMC0_CD_PIN="PH18"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH3"
+CONFIG_USB1_VBUS_PIN="PH4"
+CONFIG_USB3_VBUS_PIN="PH5"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP809_POWER=y
-- 
2.9.3

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[linux-sunxi] [PATCH 05/11] sunxi: enable SPL for sun9i

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

Now that DRAM initialization and clock setup is supported,
we can enable SPL for the A80.

[w...@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index a126c3e30140..ee6ae37fb7ef 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -119,6 +119,7 @@ config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
select SUNXI_GEN_SUN6I
+   select SUPPORT_SPL
 
 config MACH_SUN50I
bool "sun50i (Allwinner A64)"
-- 
2.9.3

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[linux-sunxi] [PATCH 02/11] sunxi: add gtbus-initialisation for sun9i

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

On sun9i, the GTBUS manages transaction priority and bandwidth
for multiple read ports when accessing DRAM. The initialisation
mirrors the settings from Allwinner's boot0 for now, even though
this may not be optimal for all applications (e.g. headless
systems might want to give priority to IO modules).

Adding a common callout to gtbus_init() from the SPL clock init
with a weakly defined implementation in sunxi/clock.c to fallback
to for platforms that don't require this.

[w...@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  2 +
 arch/arm/include/asm/arch-sunxi/gtbus.h   | 21 +++
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h | 89 +++
 arch/arm/mach-sunxi/Makefile  |  1 +
 arch/arm/mach-sunxi/clock.c   |  6 ++
 arch/arm/mach-sunxi/gtbus_sun9i.c | 48 +++
 6 files changed, 167 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index acbc94f4c3b8..ba18a0f551ad 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,8 @@
 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
 
+#define SUNXI_GTBUS_BASE   (REGS_AHB0_BASE + 0x9000)
+
 #define SUNXI_MMC0_BASE(REGS_AHB0_BASE + 0x0f000)
 #define SUNXI_MMC1_BASE(REGS_AHB0_BASE + 0x1)
 #define SUNXI_MMC2_BASE(REGS_AHB0_BASE + 0x11000)
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h 
b/arch/arm/include/asm/arch-sunxi/gtbus.h
new file mode 100644
index ..b8308d513545
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus.h
@@ -0,0 +1,21 @@
+/*
+ * GTBUS initialisation
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_H
+#define _SUNXI_GTBUS_H
+
+#if defined(CONFIG_MACH_SUN9I)
+#include 
+#endif
+
+#ifndef __ASSEMBLY__
+void gtbus_init(void);
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
new file mode 100644
index ..91bc2bdb5103
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
@@ -0,0 +1,89 @@
+/*
+ * GTBUS initialisation for sun9i
+ *
+ * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH
+ *Philipp Tomsich 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_GTBUS_SUN9I_H
+#define _SUNXI_GTBUS_SUN9I_H
+
+#include 
+
+struct sunxi_gtbus_reg {
+   u32 mst_cfg[36];   /* 0x000 */
+   u8  reserved1[0x70];   /* 0x090 */
+   u32 bw_wdw_cfg;/* 0x100 */
+   u32 mst_read_prio_cfg[2];  /* 0x104 */
+   u32 lvl2_mst_cfg;  /* 0x10c */
+   u32 sw_clk_on; /* 0x110 */
+   u32 sw_clk_off;/* 0x114 */
+   u32 pmu_mst_en;/* 0x118 */
+   u32 pmu_cfg;   /* 0x11c */
+   u32 pmu_cnt[19];   /* 0x120 */
+   u32 reserved2[0x94];   /* 0x16c */
+   u32 cci400_config[3];  /* 0x200 */
+   u32 cci400_status[2];  /* 0x20c */
+};
+
+/* for register GT_MST_CFG_REG(n) */
+#define GT_ENABLE_REQ   (1<<31) /* clock on */
+#define GT_DISABLE_REQ  (1<<30) /* clock off */
+#define GT_QOS_SHIFT28
+#define GT_THD1_SHIFT   16
+#define GT_REQN_MAX 0xf /* max number master requests in one 
cycle */
+#define GT_REQN_SHIFT   12
+#define GT_THD0_SHIFT   0
+
+#define GT_QOS_MAX  0x3
+#define GT_THD_MAX  0xfff
+#define GT_BW_WDW_MAX   0x
+
+/* mst_read_prio_cfg */
+#define GT_PRIO_LOW 0
+#define GT_PRIO_HIGH1
+
+/* GTBUS port ids */
+#define GT_PORT_CPUM1   0
+#define GT_PORT_CPUM2   1
+#define GT_PORT_SATA2
+#defineGT_PORT_USB33
+#defineGT_PORT_FE0 4
+#defineGT_PORT_BE1 5
+#defineGT_PORT_BE2 6
+#defineGT_PORT_IEP07
+#defineGT_PORT_FE1 8
+#defineGT_PORT_BE0 9
+#defineGT_PORT_FE2 10
+#defineGT_PORT_IEP111
+#defineGT_PORT_VED 12
+#defineGT_PORT_VEE 13
+#defineGT_PORT_FD  14
+#defineGT_PORT_CSI 15
+#defineGT_PORT_MP  16
+#defineGT_PORT_HSI 17
+#define

[linux-sunxi] [PATCH 09/11] sunxi: Add default zq value for sun9i (A80)

2016-10-28 Thread Chen-Yu Tsai 
Both the A80 Optimus board and the Cubieboard 4 use a zq value of
4145117, or 0x3f3fdd.

Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 5cca1eae73b3..e1d4ab148f08 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -163,6 +163,7 @@ config DRAM_ZQ
int "sunxi dram zq value"
default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
default 127 if MACH_SUN7I
+   default 4145117 if MACH_SUN9I
---help---
Set the dram zq value.
 
-- 
2.9.3

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[linux-sunxi] [PATCH 06/11] sunxi: add MMC pinmux setup for SDC2 on sun9i

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

The A80 can support 8-bit eMMC with reset on the PC pingroups.

Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/board.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 6281c9d70379..53656383d512 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -307,6 +307,13 @@ static void mmc_pinmux_setup(int sdc)
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#elif defined(CONFIG_MACH_SUN9I)
+   /* SDC2: PC6-PC16 */
+   for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
+   sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
+   sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+   sunxi_gpio_set_drv(pin, 2);
+   }
 #endif
break;
 
-- 
2.9.3

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[linux-sunxi] [PATCH 03/11] sunxi: Enable SMP mode for the boot CPU on sun9i (A80)

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

Since the A80 has many cores which we intend to use in SMP fashion,
we should set the SMP bit for the boot CPU.

[w...@csie.org: Added commit message]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/mach-sunxi/board.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 7713813a68a8..0f8ead980cdc 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -182,7 +182,8 @@ void s_init(void)
 
 #if defined CONFIG_MACH_SUN6I || \
 defined CONFIG_MACH_SUN7I || \
-defined CONFIG_MACH_SUN8I
+defined CONFIG_MACH_SUN8I || \
+defined CONFIG_MACH_SUN9I
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
-- 
2.9.3

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[linux-sunxi] [PATCH 11/11] sunxi: Add support for Cubieboard4

2016-10-28 Thread Chen-Yu Tsai 
The Cubieboard4 is an A80 SoC based development board from Cubietech.

This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector,
HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT
combo chip, headphone and microphone jacks, IR receiver, and GPIO headers.

Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/MAINTAINERS   |  5 +
 configs/Cubieboard4_defconfig | 18 ++
 2 files changed, 23 insertions(+)
 create mode 100644 configs/Cubieboard4_defconfig

diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 6e0aa24eb859..df05b3284807 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -122,6 +122,11 @@ F: include/configs/sun7i.h
 F: configs/Cubieboard2_defconfig
 F: configs/Cubietruck_defconfig
 
+CUBIEBOARD4 BOARD
+M: Chen-Yu Tsai 
+S: Maintained
+F: configs/Cubieboard4_defconfig
+
 CUBIETRUCK-PLUS BOARD
 M: Chen-Yu Tsai 
 S: Maintained
diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig
new file mode 100644
index ..4d36d39e5974
--- /dev/null
+++ b/configs/Cubieboard4_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN9I=y
+CONFIG_DRAM_CLK=672
+CONFIG_MMC0_CD_PIN="PH18"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
+CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
+CONFIG_USB0_ID_DET="PH16"
+CONFIG_USB1_VBUS_PIN="PH14"
+CONFIG_USB3_VBUS_PIN="PH15"
+CONFIG_AXP_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-cubieboard4"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_AXP809_POWER=y
-- 
2.9.3

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[linux-sunxi] [PATCH 07/11] sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)

2016-10-28 Thread Chen-Yu Tsai 
In Allwinner's SDK the A80 is clocked to 1008 MHz by default.

Signed-off-by: Chen-Yu Tsai 
---
 board/sunxi/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ee6ae37fb7ef..5cca1eae73b3 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -255,7 +255,7 @@ endif
 config SYS_CLK_FREQ
default 81600 if MACH_SUN50I
default 91200 if MACH_SUN7I
-   default 100800 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || 
MACH_SUN8I
+   default 100800 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || 
MACH_SUN8I || MACH_SUN9I
 
 config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
-- 
2.9.3

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[linux-sunxi] [PATCH 01/11] sunxi: DRAM initialisation for sun9i

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

This adds DRAM initialisation code for sun9i, which calculates the
appropriate timings based on timing information for the supplied
DDR3 bin and the clock speeds used.

With this DRAM setup, we have verified DDR3 clocks of up to 792MHz
(i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration.

[w...@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |   34 +-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |6 +
 arch/arm/include/asm/arch-sunxi/dram.h|2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  |  275 +++
 arch/arm/mach-sunxi/Makefile  |1 +
 arch/arm/mach-sunxi/dram_sun9i.c  | 1059 +
 board/sunxi/Kconfig   |6 +-
 7 files changed, 1368 insertions(+), 15 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index a61934fb3661..82881ff8bdaf 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -37,57 +37,61 @@ struct sunxi_ccm_reg {
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg;/* 0x80 ats clock configuration */
u32 trace_cfg;  /* 0x84 trace clock configuration */
-   u8 reserved4[0xf8]; /* 0x88 */
+   u8 reserved4[0x14]; /* 0x88 */
+   u32 pll_stable_status;  /* 0x9c */
+   u8 reserved5[0xe0]; /* 0xa0 */
u32 clk_output_a;   /* 0x180 clk_output_a */
u32 clk_output_b;   /* 0x184 clk_output_a */
-   u8 reserved5[0x278];/* 0x188 */
+   u8 reserved6[0x278];/* 0x188 */
 
u32 nand0_clk_cfg;  /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
-   u8 reserved6[0x08]; /* 0x408 */
+   u8 reserved7[0x08]; /* 0x408 */
u32 sd0_clk_cfg;/* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg;/* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg;/* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg;/* 0x41c sd3 clock configuration */
-   u8 reserved7[0x08]; /* 0x420 */
+   u8 reserved8[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg;   /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg;   /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg;   /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg;   /* 0x43c spi3 clock configuration */
-   u8 reserved8[0x50]; /* 0x440 */
+   u8 reserved9[0x44]; /* 0x440 */
+   u32 dram_clk_cfg;   /* 0x484 DRAM (controller) clock configuration 
*/
+   u8 reserved10[0x8]; /* 0x488 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
-   u8 reserved9[0x04]; /* 0x494 */
+   u8 reserved11[0x04];/* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg;   /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg;   /* 0x4a0 LCD1 module clock */
-   u8 reserved10[0x1c];/* 0x4a4 */
+   u8 reserved12[0x1c];/* 0x4a4 */
u32 csi_isp_clk_cfg;/* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg;   /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg;   /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg;/* 0x4d4 AVS module clock */
-   u8 reserved11[0x18];/* 0x4d8 */
+   u8 reserved13[0x18];/* 0x4d8 */
u32 gpu_core_clk_cfg;   /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg;/* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg;/* 0x4f8 GPU AXI clock config */
-   u8 reserved12[0x10];/* 0x4fc */
+   u8 reserved14[0x10];/* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
-   u8 reserved13[0x70];/* 0x510 */
+   u8 reserved15[0x70];/* 0x510 */
 
u32 ahb_gate0;  /* 0x580 AHB0 Gating Register */
u32 ahb_gate1;  /* 0x584 AHB1 Gating Register */
u32 ahb_gate2;  /* 0x588 AHB2 Gating Register */
-   u8 reserved14[0x04];/* 0x58c */
+   u8 reserved16[0x04];/* 0x58c */
u32 apb0_gate;  /* 0x590 APB0 Clock Gating Register */
u32 apb1_gate;  /* 0x594 APB1 Clock Gating Register */
-   u8 reserved15[0x08];/* 0x598 */
+   u8

[linux-sunxi] [PATCH 04/11] sunxi: add initial clock setup for sun9i for SPL

2016-10-28 Thread Chen-Yu Tsai 
From: Philipp Tomsich 

This is a cleaned up version set_pll() from Allwinner's boot0 source
(bootloader/basic_loader/bsp/bsp_for_a80/common/common.c).

[w...@csie.org: Added commit message; style cleanup]
Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/include/asm/arch-sunxi/clock_sun9i.h |  82 ++-
 arch/arm/mach-sunxi/clock_sun9i.c | 146 +-
 2 files changed, 223 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
index 82881ff8bdaf..acff26126178 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -96,9 +96,6 @@ struct sunxi_ccm_reg {
u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
 };
 
-/* pll4_periph0_cfg */
-#define PLL4_CFG_DEFAULT   0x90002800 /* 960 MHz */
-
 #define CCM_PLL4_CTRL_N_SHIFT  8
 #define CCM_PLL4_CTRL_N_MASK   (0xff << CCM_PLL4_CTRL_N_SHIFT)
 #define CCM_PLL4_CTRL_P_SHIFT  16
@@ -106,6 +103,80 @@ struct sunxi_ccm_reg {
 #define CCM_PLL4_CTRL_M_SHIFT  18
 #define CCM_PLL4_CTRL_M_MASK   (0x1 << CCM_PLL4_CTRL_M_SHIFT)
 
+/* pllx_cfg bits */
+#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL1_CTRL_EN   (1 << 31)
+#define CCM_PLL1_CLOCK_TIME_2  (2 << 24)
+
+#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16)
+#define CCM_PLL2_CTRL_EN   (1 << 31)
+#define CCM_PLL2_CLOCK_TIME_2  (2 << 24)
+
+#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL4_CTRL_EN   (1 << 31)
+
+#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8)
+#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16)
+#define CCM_PLL6_CTRL_EN   (1 << 31)
+#define CCM_PLL6_CFG_UPDATE (1 << 30)
+
+#define CCM_PLL12_CTRL_N(n)(((n) & 0xff) << 8)
+#define CCM_PLL12_CTRL_EN  (1 << 31)
+
+#define PLL_C0CPUX_STATUS   (1 << 0)
+#define PLL_C1CPUX_STATUS   (1 << 1)
+#define PLL_DDR_STATUS  (1 << 5)
+#define PLL_PERIPH1_STATUS  (1 << 11)
+
+/* cpu_clk_source bits */
+#define C0_CPUX_CLK_SRC_SHIFT   0
+#define C1_CPUX_CLK_SRC_SHIFT   8
+#define C0_CPUX_CLK_SRC_MASK(1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_MASK(1 << C1_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT)
+#define C0_CPUX_CLK_SRC_PLL1   (1 << C0_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT)
+#define C1_CPUX_CLK_SRC_PLL2   (1 << C1_CPUX_CLK_SRC_SHIFT)
+
+/* c0_cfg */
+#define C0_CFG_AXI0_CLK_DIV_RATIO(n)(((n - 1) & 0x3) << 0)
+#define C0_CFG_APB0_CLK_DIV_RATIO(n)(((n - 1) & 0x3) << 8)
+
+/* ahbx_cfg */
+#define AHBx_SRC_CLK_SELECT_SHIFT   24
+#define AHBx_SRC_MASK   (0x3 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB0_SRC_GTBUS_CLK  (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB1_SRC_GTBUS_CLK  (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH0(0x1 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_SRC_PLL_PERIPH1(0x2 << AHBx_SRC_CLK_SELECT_SHIFT)
+#define AHBx_CLK_DIV_RATIO(n)   (((ffs(n) - 1) & 0x3) << 0)
+
+/* apb0_cfg */
+#define APB0_SRC_CLK_SELECT_SHIFT   24
+#define APB0_SRC_MASK   (0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_SRC_PLL_PERIPH0(0x1 << APB0_SRC_CLK_SELECT_SHIFT)
+#define APB0_CLK_DIV_RATIO(n)   (((ffs(n) - 1) & 0x3) << 0)
+
+/* gtbus_clk_cfg */
+#define GTBUS_SRC_CLK_SELECT_SHIFT  24
+#define GTBUS_SRC_MASK  (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_OSC24M(0x0 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH0   (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_SRC_PLL_PERIPH1   (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT)
+#define GTBUS_CLK_DIV_RATIO(n)  (((n - 1) & 0x3) << 0)
+
+/* cci400_clk_cfg */
+#define CCI400_SRC_CLK_SELECT_SHIFT 24
+#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_OSC24M   (0x0 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH0  (0x1 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_SRC_PLL_PERIPH1  (0x2 << CCI400_SRC_CLK_SELECT_SHIFT)
+#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0)
+
 /* sd#_clk_cfg fields */
 #define CCM_MMC_CTRL_M(x)  ((x) - 1)
 #define

Re: [linux-sunxi] ISP scaling A20

2016-10-28 Thread Milos Ladni 
It works now.
I forgot to set MACC_ISP_OUTPIC_STRIDE, just MACC_ISP_PIC_STRIDE. 
I do not know how i did not see that, sorry and thank you very much again.

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Milos Ladicorbic

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[linux-sunxi] Re: BananPro WiFi Module (ap6181) Problems

2016-10-28 Thread Ftts Ftts 
try this code.
drivers\net\wireless\broadcom\brcm80211\brcmfmac\bcmsdh.c

static int brcmf_sdiod_buffrw(struct brcmf_sdio_dev *sdiodev, uint fn,
bool write, u32 addr, struct sk_buff *pkt)
{
unsigned int req_sz;
int err;

/* Single skb use the standard mmc interface */
req_sz = pkt->len + 3;
req_sz &= (uint)~3;

   //check if device is busy.
if (sw_mci_check_r1_ready(sdiodev->func[fn]->card->host, 1000) != 0)
brcmf_err("sw_mci_check_r1_ready data timeout.\n");

if (write)
err = sdio_memcpy_toio(sdiodev->func[fn], addr,
  ((u8 *)(pkt->data)), req_sz);
else if (fn == 1)
err = sdio_memcpy_fromio(sdiodev->func[fn], ((u8 *)(pkt->data)),
addr, req_sz);
else
/* function 2 read is FIFO operation */
err = sdio_readsb(sdiodev->func[fn], ((u8 *)(pkt->data)), addr,
 req_sz);
if (err == -ENOMEDIUM)
brcmf_sdiod_change_state(sdiodev, BRCMF_SDIOD_NOMEDIUM);
return err;
}


在 2016年9月16日星期五 UTC+8下午4:25:51，Sławomir Paszko写道：
>
> I have merged 4.6 mainline *drivers/wireless/broadcom *and *drivers/mmc* 
> into imx6 4.1 kernel and this was a partial solution for my problem. Key 
> part was newer sdhci driver(drivers/mmc/host). Before merge, RXHEADER 
> FAILED caused a break and reset of connection. It was a ~18s break of no 
> transfer. Now errors occur but they don't stop connection and transmission 
> continues.
>
> W dniu poniedziałek, 12 września 2016 23:43:24 UTC+2 użytkownik Sławomir 
> Paszko napisał:
>>
>> I tried to implement sigint patch in freescale imx6 4.1 kernel(
>> http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/, branch 
>> imx_4.1.15_1.0.0_ga), but it's not working. I have added these same changes 
>> in bcmsdh.c and i've made my sw_mci_check_r1_ready() function in sdhci.c 
>> based on 
>>
>> static int sdhci_card_busy(struct mmc_host *mmc)
>> {
>> struct sdhci_host *host = mmc_priv(mmc);
>> u32 present_state;
>>
>> sdhci_runtime_pm_get(host);
>> /* Check whether DAT[3:0] is  */
>> present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
>> sdhci_runtime_pm_put(host);
>>
>> return !(present_state & SDHCI_DATA_LVL_MASK);
>> }
>>
>> Unfortunately this doesn't helped. Is there any official solution? Maybe 
>> you can give me some advice how to implement this in 4.1 freescale kernel.
>>
>> W dniu czwartek, 9 lipca 2015 10:10:12 UTC+2 użytkownik sigint napisał:
>>>
>>> ..something like this:
>>> (v4.0.5. mainline)
>>>
>>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>> index 459ed1b..82f41e3 100644
>>> --- a/drivers/mmc/host/sunxi-mmc.c
>>> +++ b/drivers/mmc/host/sunxi-mmc.c
>>> @@ -1082,6 +1082,23 @@ static struct platform_driver sunxi_mmc_driver = {
>>>  };
>>>  module_platform_driver(sunxi_mmc_driver);
>>>  
>>> +int sw_mci_check_r1_ready(struct mmc_host* mmc, unsigned ms)
>>> +{
>>> +struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
>>> +unsigned expire = jiffies + msecs_to_jiffies(ms);
>>> +do {
>>> +if (!(mmc_readl(smc_host, REG_STAS) & SDXC_CARD_DATA_BUSY))
>>> +break;
>>> +} while (jiffies < expire);
>>> +
>>> +if ((mmc_readl(smc_host, REG_STAS) & SDXC_CARD_DATA_BUSY)) {
>>> +dev_err(mmc_dev(mmc), "wait r1 rdy %d ms timeout\n", ms);
>>> +return -1;
>>> +} else
>>> +return 0;
>>> +}
>>> +EXPORT_SYMBOL_GPL(sw_mci_check_r1_ready);
>>> +
>>>  MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
>>>  MODULE_LICENSE("GPL v2");
>>>  MODULE_AUTHOR("David Lanzend�rfer ");
>>> diff --git a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
>>> b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
>>> index 7944224..ff63927 100644
>>> --- a/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
>>> +++ b/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
>>> @@ -58,6 +58,8 @@
>>>  #define BRCMF_DEFAULT_TXGLOM_SIZE32  /* max tx frames in glom 
>>> chain */
>>>  #define BRCMF_DEFAULT_RXGLOM_SIZE32  /* max rx frames in glom 
>>> chain */
>>>  
>>> +extern int sw_mci_check_r1_ready(struct mmc_host* mmc, unsigned ms);
>>> +
>>>  static int brcmf_sdiod_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
>>>  module_param_named(txglomsz, brcmf_sdiod_txglomsz, int, 0);
>>>  MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
>>> @@ -266,6 +268,10 @@ static int brcmf_sdiod_request_data(struct
>>> brcmf_sdio_dev *sdiodev, u8 fn,
>>>  brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: 
>>> %d\n",
>>>write ? "write" : "read", fn, addr, ret);
>>>  
>>> +//AW judge sdio read write timeout, 1s
>>> +if (sw_mci_check_r1_ready(sdiodev->func[fn]->card->host, 1000) 
>>> != 0)
>>> +brcmf_err("sw_mci_check_r1_ready data timeout.\n");
>>> +
>>>  return ret;
>>>  }
>>>  
>>> @@ -322,6 +328,11 @@ static int brcmf_sdiod_regrw_helper(struct
>>> brcmf_sdio_dev *sdiodev, u32 addr,
>>>  brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, 
>>> err: %d\n",
>>>