[linux-sunxi] GPIO input sysfs

[David H. Lynch Jr.]

Is there a means to set a gpio on an H3 to input and specify pull up or
pull down with 4.x kernels ?

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[linux-sunxi] Re: [PATCH v7 0/8] drm: sun8i: Add DE2 HDMI video support

[Jernej Skrabec]

Hi Laurent,

Dne torek, 29. november 2016 23.56.31 UTC+1 je oseba Laurent Pinchart 
napisala:
>
> Hi Jernej, 
>
> (CC'ing Kieran Bingham) 
>
> On Tuesday 29 Nov 2016 14:47:20 Jernej Skrabec wrote: 
> > Dne torek, 29. november 2016 22.37.03 UTC+1 je oseba Maxime Ripard 
> napisala: 
> > > On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote: 
> > >> This patchset series adds HDMI video support to the Allwinner 
> > >> sun8i SoCs which include the display engine 2 (DE2). 
> > >> The driver contains the code for the A83T and H3 SoCs, and 
> > >> some H3 boards, but it could be used/extended for other SoCs 
> > >> (A64, H2, H5) and boards (Banana PIs, Orange PIs). 
> > > 
> > > Honestly, I'm getting a bit worried by the fact that you ignore 
> > > reviews. 
> > > 
> > > On the important reviews that you got that are to be seen as major 
> > > 
> > > issues that block the inclusion, we have: 
> > >   - The fact that the HDMI driver is actually just a designware IP, 
> > > and while you should use the driver that already exists, you just 
> > > duplicated all that code. 
> > 
> > That might be hard thing to do. A83T fits perfectly, but H3 and newer 
> SoCs 
> > do not. They are using completely different HDMI phy. Decoupling 
> controller 
> > and phy code means rewritting a good portion of the code, unless some 
> tricks 
> > are applied, like calling phy function pointers, if they are defined. 
>
> Same HDMI TX but different HDMI TX PHY ? Kieran is working on decoupling 
> the 
> PHY configuration code for a Renesas SoC, that might be of interest to 
> you. 
>

Exactly. I'm developing only U-Boot driver, but Jean-Francois will probably
have more interest in this.
 

>
> > Register addresses also differ, but that can be easily solved by using 
> > undocumented magic value to restore them. 
>
> I love that :-) 
>
>
Is it allowed to use magic number which was found in binary blob? I'm new in
all this.
 

> > >   - The fact that you ignored Rob (v6) and I (v5) comment on using OF 
> > > graph to model the connection between the display engine and the 
> > > TCON. Something that Laurent also pointed out in this version. 
> > >   
> > >   - The fact that you ignored that you needed an HDMI connector node 
> > > as a child of the HDMI controller. This has been reported by Rob 
> > > (v6) and yet again in this version by Laurent. 
> > >   
> > >   - And finally the fact that we can't have several display engine in 
> > > parallel, if needs be. This has happened in the past already on 
> > > Allwinner SoCs, so it's definitely something we should consider in 
> > > the DT bindings, since we can't break them. 
> > > 
> > > Until those are fixed, I cannot see how this driver can be merged, 
> > > unfortunately. 
>
> -- 
> Regards, 
>
> Laurent Pinchart 
>
>
Best regards,
Jernej Škrabec 

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[linux-sunxi] Re: [PATCH v7 0/8] drm: sun8i: Add DE2 HDMI video support

[Laurent Pinchart]

Hi Jernej,

(CC'ing Kieran Bingham)

On Tuesday 29 Nov 2016 14:47:20 Jernej Skrabec wrote:
> Dne torek, 29. november 2016 22.37.03 UTC+1 je oseba Maxime Ripard napisala:
> > On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote:
> >> This patchset series adds HDMI video support to the Allwinner
> >> sun8i SoCs which include the display engine 2 (DE2).
> >> The driver contains the code for the A83T and H3 SoCs, and
> >> some H3 boards, but it could be used/extended for other SoCs
> >> (A64, H2, H5) and boards (Banana PIs, Orange PIs).
> > 
> > Honestly, I'm getting a bit worried by the fact that you ignore
> > reviews.
> > 
> > On the important reviews that you got that are to be seen as major
> > 
> > issues that block the inclusion, we have:
> >   - The fact that the HDMI driver is actually just a designware IP,
> > and while you should use the driver that already exists, you just
> > duplicated all that code.
> 
> That might be hard thing to do. A83T fits perfectly, but H3 and newer SoCs
> do not. They are using completely different HDMI phy. Decoupling controller
> and phy code means rewritting a good portion of the code, unless some tricks
> are applied, like calling phy function pointers, if they are defined.

Same HDMI TX but different HDMI TX PHY ? Kieran is working on decoupling the 
PHY configuration code for a Renesas SoC, that might be of interest to you.

> Register addresses also differ, but that can be easily solved by using
> undocumented magic value to restore them.

I love that :-)

> >   - The fact that you ignored Rob (v6) and I (v5) comment on using OF
> > graph to model the connection between the display engine and the
> > TCON. Something that Laurent also pointed out in this version.
> >   
> >   - The fact that you ignored that you needed an HDMI connector node
> > as a child of the HDMI controller. This has been reported by Rob
> > (v6) and yet again in this version by Laurent.
> >   
> >   - And finally the fact that we can't have several display engine in
> > parallel, if needs be. This has happened in the past already on
> > Allwinner SoCs, so it's definitely something we should consider in
> > the DT bindings, since we can't break them.
> > 
> > Until those are fixed, I cannot see how this driver can be merged,
> > unfortunately.

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Regards,

Laurent Pinchart

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[linux-sunxi] Re: [PATCH v7 0/8] drm: sun8i: Add DE2 HDMI video support

[Jernej Skrabec]

Hi Maxime,

Dne torek, 29. november 2016 22.37.03 UTC+1 je oseba Maxime Ripard napisala:
>
> On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote: 
> > This patchset series adds HDMI video support to the Allwinner 
> > sun8i SoCs which include the display engine 2 (DE2). 
> > The driver contains the code for the A83T and H3 SoCs, and 
> > some H3 boards, but it could be used/extended for other SoCs 
> > (A64, H2, H5) and boards (Banana PIs, Orange PIs). 
>
> Honestly, I'm getting a bit worried by the fact that you ignore 
> reviews. 
>
> On the important reviews that you got that are to be seen as major 
> issues that block the inclusion, we have: 
>   - The fact that the HDMI driver is actually just a designware IP, 
> and while you should use the driver that already exists, you just 
> duplicated all that code. 
>
>  
That might be hard thing to do. A83T fits perfectly, but H3 and newer SoCs 
do
not. They are using completely different HDMI phy. Decoupling controller and
phy code means rewritting a good portion of the code, unless some tricks are
applied, like calling phy function pointers, if they are defined.

Register addresses also differ, but that can be easily solved by using
undocumented magic value to restore them.
 

>   - The fact that you ignored Rob (v6) and I (v5) comment on using OF 
> graph to model the connection between the display engine and the 
> TCON. Something that Laurent also pointed out in this version. 
>
>   - The fact that you ignored that you needed an HDMI connector node 
> as a child of the HDMI controller. This has been reported by Rob 
> (v6) and yet again in this version by Laurent. 
>
>   - And finally the fact that we can't have several display engine in 
> parallel, if needs be. This has happened in the past already on 
> Allwinner SoCs, so it's definitely something we should consider in 
> the DT bindings, since we can't break them. 
>
> Until those are fixed, I cannot see how this driver can be merged, 
> unfortunately. 
>
> Maxime 
>
> -- 
> Maxime Ripard, Free Electrons 
> Embedded Linux and Kernel engineering 
> http://free-electrons.com


Best regards,
Jernej Škrabec 

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[linux-sunxi] Re: [PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

[Jernej Skrabec]

Hi Jean-François,

Dne petek, 25. november 2016 11.22.20 UTC+1 je oseba Jean-François Moine 
napisala:
>
> On Fri, 25 Nov 2016 17:41:51 +0800 
> Icenowy Zheng  wrote: 
>
> > After removing CLK_PLL_DE's assigned-clock, the kernel passes 
> compilation. 
>
> The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not 
> use the legacy u-boot, I don't know which can be the rate of the DE. 
>
> > However, it cannot recognize any HDMI screen... 
> > 
> > (My board is Orange Pi One, and I manually added status="okay"; to 
> , , ) 
> > 
> > [   16.507802] sun8i-de2 100.de-controller: bound 
> 1c0c000.lcd-controller (ops de2_lcd_ops [sun8i_de2_drm]) 
> > [   16.675948] sun8i-de2 100.de-controller: bound 1ee.hdmi (ops 
> de2_hdmi_fini [sun8i_de2_hdmi]) 
> > [   16.685120] [drm] Supports vblank timestamp caching Rev 2 
> (21.10.2013). 
> > [   16.695876] [drm] No driver support for vblank timestamp query. 
> > [   16.701862] sun8i-de2 100.de-controller: No connectors reported 
> connected with modes 
> > [   16.713061] [drm] Cannot find any crtc or sizes - going 1024x768 
> > [   16.734214] Console: switching to colour frame buffer device 128x48 
> > [   16.751022] sun8i-de2 100.de-controller: fb0:  frame buffer 
> device 
>
> I put a 'pr_warn' message is case the EDID cannot be read. 
> Have you this message? 
>
> Anyway, there is a problem with the EDID: 
> - my Orange Pi 2 (H3) randomly fails to read it. But this succeeds after 
>   rebooting once or twice. 
>

My U-Boot driver never exhibited a problem with reading EDID on OPi2. 
However,
I'm reusing code from Rockchip HDMI U-Boot driver for this (with some 
Allwinner
adjustments).
 

> - my Banana Pi M2+ (H3) reads it correctly each time. 
> - my Banana Pi M3 (A83T) can never read it. 
>
> BTW, on first tries, I was forcing a CEA mode thru the kernel command 
> line. This was working with the OPi2 and BPiM3, but there was no sound. 
> In the last version, I use a EDID in edid_firmware for having sound 
> with the BPiM3. This works fine. 
> But, forcing a CEA mode is no more possible, so, when the OPi2 cannot 
> read the EDID, the system switches to a VGA mode (default 1024x768) 
> which is not supported. It seems that this is your case. 
>
> So, in brief, if your board cannot read the EDID, put a EDID somewhere 
> and its path in /sys/module/drm_kms_helper/parameters/edid_firmware. 
> There will be no console, but X11 will work correctly. 
>
> -- 
> Ken ar c'hentañ|  ** Breizh ha Linux atav! ** 
> Jef|http://moinejf.free.fr/


Best regards,
Jernej Škrabec 

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[linux-sunxi] Re: [RFC PATCH] ARM: dts: sun8i: add simplefb node for H3

[Maxime Ripard]

On Mon, Nov 28, 2016 at 11:42:18AM +0100, Jean-Francois Moine wrote:
> On Mon, 28 Nov 2016 17:59:00 +0800
> Icenowy Zheng  wrote:
> 
> > As there's currently a fork of U-Boot which provides simplefb support
> > for H3, a simplefb node can be added to the device tree.
> > 
> > Signed-off-by: Icenowy Zheng 
> > ---
> > 
> > I'm still not sure which pipeline should I use.
> > 
> > And, it seems that HDMI Slow Clock is not needed?
> > 
> > (seems that it's only for EDID, but simplefb won't use EDID)
> 
> So, I don't see how this may work.
> How can the u-boot know the resolutions of the HDMI display device?
> 
> In other words: I have a new H3 board with the last u-boot and kernel.
> I plug my (rather old or brand new) HDMI display device.
> After powering on the system, I hope to get something on the screen.
> How?

If it works like the driver for the first display engine in U-Boot, it
will use the preferred mode reported by the EDID, and will fallback to
1024x768 if it cannot access it.

Maybe it would be worth exchanging on the EDID code that has been done
for the u-boot driver too, so that it can be fixed in your driver.

Maxime

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[linux-sunxi] Re: [PATCH v6 3/5] ARM: dts: sun8i-h3: add HDMI video nodes

[Maxime Ripard]

On Fri, Nov 25, 2016 at 11:22:13AM +0100, Jean-Francois Moine wrote:
> On Fri, 25 Nov 2016 17:41:51 +0800
> Icenowy Zheng  wrote:
> 
> > After removing CLK_PLL_DE's assigned-clock, the kernel passes compilation.
> 
> The 'pll-de' and 'de' must have a fixed rate. Otherwise, if you do not
> use the legacy u-boot, I don't know which can be the rate of the DE.
> 
> > However, it cannot recognize any HDMI screen...
> > 
> > (My board is Orange Pi One, and I manually added status="okay"; to , 
> > , )
> > 
> > [   16.507802] sun8i-de2 100.de-controller: bound 
> > 1c0c000.lcd-controller (ops de2_lcd_ops [sun8i_de2_drm])
> > [   16.675948] sun8i-de2 100.de-controller: bound 1ee.hdmi (ops 
> > de2_hdmi_fini [sun8i_de2_hdmi])
> > [   16.685120] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
> > [   16.695876] [drm] No driver support for vblank timestamp query.
> > [   16.701862] sun8i-de2 100.de-controller: No connectors reported 
> > connected with modes
> > [   16.713061] [drm] Cannot find any crtc or sizes - going 1024x768
> > [   16.734214] Console: switching to colour frame buffer device 128x48
> > [   16.751022] sun8i-de2 100.de-controller: fb0:  frame buffer device
> 
> I put a 'pr_warn' message is case the EDID cannot be read.
> Have you this message?
> 
> Anyway, there is a problem with the EDID:
> - my Orange Pi 2 (H3) randomly fails to read it. But this succeeds after
>   rebooting once or twice.
> - my Banana Pi M2+ (H3) reads it correctly each time.
> - my Banana Pi M3 (A83T) can never read it.
> 
> BTW, on first tries, I was forcing a CEA mode thru the kernel command
> line. This was working with the OPi2 and BPiM3, but there was no sound.
> In the last version, I use a EDID in edid_firmware for having sound
> with the BPiM3. This works fine.
> But, forcing a CEA mode is no more possible, so, when the OPi2 cannot
> read the EDID, the system switches to a VGA mode (default 1024x768)
> which is not supported. It seems that this is your case.
> 
> So, in brief, if your board cannot read the EDID, put a EDID somewhere
> and its path in /sys/module/drm_kms_helper/parameters/edid_firmware.
> There will be no console, but X11 will work correctly.

This is one of the things that are usually very helpful to put in a
cover letter. This is obviously also a blocker for the merge of the
driver, and should be dealt with.

Maxime

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Re: [linux-sunxi] Re: [RFC PATCH] ARM: dts: sun8i: add simplefb node for H3

[Maxime Ripard]

On Mon, Nov 28, 2016 at 06:24:24PM +0800, Chen-Yu Tsai wrote:
> On Mon, Nov 28, 2016 at 6:19 PM, Icenowy Zheng  wrote:
> >
> >
> > 28.11.2016, 18:07, "Chen-Yu Tsai" :
> >> On Mon, Nov 28, 2016 at 5:59 PM, Icenowy Zheng  wrote:
> >>>  As there's currently a fork of U-Boot which provides simplefb support
> >>
> >> Please add it when its finalized...
> >>
> >>>  for H3, a simplefb node can be added to the device tree.
> >>>
> >>>  Signed-off-by: Icenowy Zheng 
> >>>  ---
> >>>
> >>>  I'm still not sure which pipeline should I use.
> >>
> >> You are supposed to add _all_ the pipelines that are available and
> >> supported by U-boot. U-boot is then supposed to enable and update
> >> the one it set up.
> >
> > I mean the pipeline string ;-)
> 
> Looks good to me. There's no separate frontend/backend in DE 2.0.

It looks good to me too.

Maxime

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[linux-sunxi] Re: [U-Boot] [PATCH 1/6] net: dw: Add read_rom_hwaddr net_op hook

[Simon Glass]

Hi Oliver,

On 28 November 2016 at 03:38, Olliver Schinagl  wrote:
> On 27-11-16 18:02, Simon Glass wrote:
>>
>> Hi,
>>
>> On 25 November 2016 at 08:38, Olliver Schinagl  wrote:
>>>
>>> Add the read_rom_hwaddr net_op hook so that it can be called from boards
>>> to read the mac from a ROM chip.
>>>
>>> Signed-off-by: Olliver Schinagl 
>>> ---
>>>   drivers/net/designware.c | 16 
>>>   1 file changed, 16 insertions(+)
>>>
>>> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
>>> index 9e6d726..3f2f67c 100644
>>> --- a/drivers/net/designware.c
>>> +++ b/drivers/net/designware.c
>>> @@ -230,6 +230,21 @@ static int _dw_write_hwaddr(struct dw_eth_dev *priv,
>>> u8 *mac_id)
>>>  return 0;
>>>   }
>>>
>>> +__weak int dw_board_read_rom_hwaddr(unsigned char *enetaddr, int id)
>>> +{
>>> +   return -ENOSYS;
>>> +}
>>> +
>>> +static int designware_eth_read_rom_hwaddr(struct udevice *dev)
>>> +{
>>> +   struct eth_pdata *pdata = dev_get_platdata(dev);
>>> +
>>> +   if (!dev)
>>> +   return -ENOSYS;
>>> +
>>> +   return dw_board_read_rom_hwaddr(pdata->enetaddr, dev->seq);
>>> +}
>>> +
>>>   static void dw_adjust_link(struct eth_mac_regs *mac_p,
>>> struct phy_device *phydev)
>>>   {
>>> @@ -685,6 +700,7 @@ static const struct eth_ops designware_eth_ops = {
>>>  .free_pkt   = designware_eth_free_pkt,
>>>  .stop   = designware_eth_stop,
>>>  .write_hwaddr   = designware_eth_write_hwaddr,
>>> +   .read_rom_hwaddr= designware_eth_read_rom_hwaddr,
>>>   };
>>>
>>>   static int designware_eth_ofdata_to_platdata(struct udevice *dev)
>>
>> You should not call board code from a driver. But since this is a
>> sunxi driver, why not move all the code that reads the serial number
>> into this file?
>
> Hey Simon,
>
> unless I missunderstand, this is how Joe suggested in a while ago, and how
> it has been implemented in a few other drivers. Can you elaborate a bit
> more?

Yes...drivers must not call into board-specific code, nor have
board-specific #defines. This limits their usefulness for other
boards.

Adding hooks like this (particularly with the word 'board' in the
name) should be avoided.

We end up with bidirectional coupling between the board and the
driver. The board should use the driver but not the other way around.
I understand that you are trying to get around this by using a weak
function, but with driver model I'm really trying hard to avoid weak
functions. They normally indicate an ad-hoc API and can generally be
avoided with a bit more design thought.

If you have a standard way of reading the serial number which is
supported by all sunxi boards, then you should be able to add your
changes to the sunxi Ethernet driver (which uses designware.c?). Then
you can leave the designware.c code alone and avoid adding a hook.

In a sense you end up subclassing the designware driver.

Also see this series which deals with a similar problem with rockchip:

http://lists.denx.de/pipermail/u-boot/2016-November/274256.html

Regards,
Simon

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[linux-sunxi] Re: [U-Boot] [PATCH 01/11] net: dw: Add read_rom_hwaddr net_op hook

[Simon Glass]

Hi Joe,

On 29 November 2016 at 14:24, Joe Hershberger  wrote:
>
> Hi Simon,
>
> On Thu, Nov 17, 2016 at 7:13 PM, Simon Glass  wrote:
> > Hi Oliver,
> >
> > On 8 November 2016 at 08:54, Olliver Schinagl  wrote:
> >> Add the read_rom_hwaddr net_op hook so that it can be called from boards
> >> to read the mac from a ROM chip.
> >>
> >> Signed-off-by: Olliver Schinagl 
> >> ---
> >>  drivers/net/designware.c | 18 ++
> >>  1 file changed, 18 insertions(+)
> >>
> >> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> >> index 9e6d726..aa87f30 100644
> >> --- a/drivers/net/designware.c
> >> +++ b/drivers/net/designware.c
> >> @@ -230,6 +230,23 @@ static int _dw_write_hwaddr(struct dw_eth_dev *priv, 
> >> u8 *mac_id)
> >> return 0;
> >>  }
> >>
> >> +__weak int dw_board_read_rom_hwaddr(unsigned char *enetaddr)
> >> +{
> >> +   return -ENOSYS;
> >> +}
> >
> > Instead of a weak function I think this should use driver model, with
> > a driver supplied by the board to read this value. It should be
> > possible to supply the 'hardware-address reading' device to any
> > Ethernet driver, not just dwmmc.
>
> How do we reconcile something like that with the concern of using the
> device tree for boards using only Linux bindings, and sharing the
> device tree with Linux? Linux probably doesn't care about this and so
> won't have a binding for defining this relationship. This is a fairly
> generic question. Where have we landed on this?

So far I have not seen something that cannot be solved either as I
suggest above or with platform data.

Often you can pass platform data to the driver - e.g. see the end of
board_init() in gurnard.c which tells the video driver which LCD to
use.

Is there another case? I certainly have ideas but don't want to create
something without a solid case.

Regards,
Simon

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[linux-sunxi] Re: [PATCH v7 0/8] drm: sun8i: Add DE2 HDMI video support

[Maxime Ripard]

On Tue, Nov 29, 2016 at 11:18:35AM +0100, Jean-Francois Moine wrote:
> This patchset series adds HDMI video support to the Allwinner
> sun8i SoCs which include the display engine 2 (DE2).
> The driver contains the code for the A83T and H3 SoCs, and
> some H3 boards, but it could be used/extended for other SoCs
> (A64, H2, H5) and boards (Banana PIs, Orange PIs).

Honestly, I'm getting a bit worried by the fact that you ignore
reviews.

On the important reviews that you got that are to be seen as major
issues that block the inclusion, we have:
  - The fact that the HDMI driver is actually just a designware IP,
and while you should use the driver that already exists, you just
duplicated all that code.

  - The fact that you ignored Rob (v6) and I (v5) comment on using OF
graph to model the connection between the display engine and the
TCON. Something that Laurent also pointed out in this version.

  - The fact that you ignored that you needed an HDMI connector node
as a child of the HDMI controller. This has been reported by Rob
(v6) and yet again in this version by Laurent.

  - And finally the fact that we can't have several display engine in
parallel, if needs be. This has happened in the past already on
Allwinner SoCs, so it's definitely something we should consider in
the DT bindings, since we can't break them.

Until those are fixed, I cannot see how this driver can be merged,
unfortunately.

Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] Re: [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Laurent Pinchart]

Hi Jean-François,

On Tuesday 29 Nov 2016 21:04:55 Jean-Francois Moine wrote:
> On Tue, 29 Nov 2016 21:33 +0200 Laurent Pinchart wrote:
> >>> You need a third port for the HDMI encoder output, connected to an
> >>> HDMI connector DT node.
> >> 
> >> I don't see what you mean. The HDMI device is both the encoder
> >> and connector (as the TDA998x):
> >
> > The driver might create both an encoder and a connector, but I very much
> > doubt that the "allwinner,sun8i-a83t-hdmi" hardware contains a connector,
> > unless the SoC package has an HDMI connector coming out of it :-)
> > 
> >> plane -> DE2 mixer ---> TCON -> HDMI -> display device
> >> - plane --- CRTC -   - encoder  \
> >>connector -- (HDMI cable)
> >>  audio-controller -   - audio-codec /
> 
> The schema is the same as the Dove Cubox: the TDA998x is just a chip
> with some wires going out and the physical connector is supposed to be
> at the end of the wires.

I've missed the Dove Cubox DT bindings when they were submitted. Fortunately 
(or unfortunately for you, depending on how you look at it ;-)) I've paid more 
attention this time.

> Here, the HDMI pins of the SoC go to a pure hardware chip and then to
> the physical connector. Which software entity do you want to add?

I don't want to add a software entity, I just want to model the connector in 
DT as it's present in the system. Even though that's more common for other bus 
types than HDMI (LVDS for instance) it wouldn't be inconceivable to connect 
the HDMI signals to an on-board chim instead of an HDMI connector, so the HDMI 
encoder output should be modelled by a port and connected to a connector DT 
node in this case.

-- 
Regards,

Laurent Pinchart

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[linux-sunxi] Re: [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Jean-Francois Moine]

On Tue, 29 Nov 2016 21:33 +0200
Laurent Pinchart  wrote:

> > > You need a third port for the HDMI encoder output, connected to an HDMI
> > > connector DT node.
> > 
> > I don't see what you mean. The HDMI device is both the encoder
> > and connector (as the TDA998x):
> 
> The driver might create both an encoder and a connector, but I very much 
> doubt 
> that the "allwinner,sun8i-a83t-hdmi" hardware contains a connector, unless 
> the 
> SoC package has an HDMI connector coming out of it :-)
> 
> > plane -> DE2 mixer ---> TCON -> HDMI -> display device
> > - plane --- CRTC -   - encoder  \
> >connector -- (HDMI cable)
> >  audio-controller -   - audio-codec /

The schema is the same as the Dove Cubox: the TDA998x is just a chip
with some wires going out and the physical connector is supposed to be
at the end of the wires.

Here, the HDMI pins of the SoC go to a pure hardware chip and then to
the physical connector. Which software entity do you want to add?

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Laurent Pinchart]

Hi Jean-François,

On Tuesday 29 Nov 2016 20:27:51 Jean-Francois Moine wrote:
> On Tue, 29 Nov 2016 20:46:22 +0200 Laurent Pinchart wrote:
> [snip]
> 
> >> +Example:
> >> +
> >> +  hdmi: hdmi@01ee {
> >> +  compatible = "allwinner,sun8i-a83t-hdmi";
> >> +  reg = <0x01ee 0x2>;
> >> +  clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
> >> +   < CLK_HDMI_DDC>;
> >> +  clock-names = "bus", "clock", "ddc-clock";
> >> +  resets = < RST_HDMI0>, < RST_HDMI1>;
> >> +  reset-names = "hdmi0", "hdmi1";
> >> +  pinctrl-names = "default";
> >> +  pinctrl-0 = <_pins_a>;
> >> +  status = "disabled";
> >> +  #address-cells = <1>;
> >> +  #size-cells = <0>;
> >> +  port@0 {/* video */
> >> +  reg = <0>;
> >> +  hdmi_tcon1: endpoint {
> >> +  remote-endpoint = <_hdmi>;
> >> +  };
> >> +  };
> >> +  port@1 {/* audio */
> >> +  reg = <1>;
> >> +  hdmi_i2s2: endpoint {
> >> +  remote-endpoint = <_hdmi>;
> >> +  };
> >> +  };
> > 
> > You need a third port for the HDMI encoder output, connected to an HDMI
> > connector DT node.
> 
> I don't see what you mean. The HDMI device is both the encoder
> and connector (as the TDA998x):

The driver might create both an encoder and a connector, but I very much doubt 
that the "allwinner,sun8i-a83t-hdmi" hardware contains a connector, unless the 
SoC package has an HDMI connector coming out of it :-)

> plane -> DE2 mixer ---> TCON -> HDMI -> display device
> - plane --- CRTC -   - encoder  \
>connector -- (HDMI cable)
>  audio-controller -   - audio-codec /
> 
> > > + };

-- 
Regards,

Laurent Pinchart

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[linux-sunxi] Re: [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Jean-Francois Moine]

On Tue, 29 Nov 2016 20:46:22 +0200
Laurent Pinchart  wrote:
[snip]
> > +Example:
> > +
> > +   hdmi: hdmi@01ee {
> > +   compatible = "allwinner,sun8i-a83t-hdmi";
> > +   reg = <0x01ee 0x2>;
> > +   clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
> > +< CLK_HDMI_DDC>;
> > +   clock-names = "bus", "clock", "ddc-clock";
> > +   resets = < RST_HDMI0>, < RST_HDMI1>;
> > +   reset-names = "hdmi0", "hdmi1";
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <_pins_a>;
> > +   status = "disabled";
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   port@0 {/* video */
> > +   reg = <0>;
> > +   hdmi_tcon1: endpoint {
> > +   remote-endpoint = <_hdmi>;
> > +   };
> > +   };
> > +   port@1 {/* audio */
> > +   reg = <1>;
> > +   hdmi_i2s2: endpoint {
> > +   remote-endpoint = <_hdmi>;
> > +   };
> > +   };
> 
> You need a third port for the HDMI encoder output, connected to an HDMI 
> connector DT node.

I don't see what you mean. The HDMI device is both the encoder
and connector (as the TDA998x):

plane -> DE2 mixer ---> TCON -> HDMI -> display device
- plane --- CRTC -   - encoder  \
   connector -- (HDMI cable)
 audio-controller -   - audio-codec /

> > +   };

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Laurent Pinchart]

Hi Jean-François,

Thank you for the patch.

On Tuesday 29 Nov 2016 10:08:25 Jean-Francois Moine wrote:
> Signed-off-by: Jean-Francois Moine 
> ---
>  .../devicetree/bindings/display/sunxi/hdmi.txt | 56 +++
>  1 file changed, 56 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
> b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt new file mode
> 100644
> index 000..1e107cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
> @@ -0,0 +1,56 @@
> +Allwinner HDMI Transmitter
> +==
> +
> +The Allwinner HDMI transmitters are included in the SoCs.
> +They support audio and video.
> +
> +Required properties:
> + - compatible : should be one of
> + "allwinner,sun8i-a83t-hdmi"
> + "allwinner,sun8i-h3-hdmi"
> + - reg: base address and size of the I/O memory
> + - clocks : phandles to the HDMI clocks as described in
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + - clock-names : must be
> + "bus" : bus gate
> + "clock" : streaming clock
> + "ddc-clock" : DDC clock
> + - resets : One or two phandles to the HDMI resets
> + - reset-names : when 2 phandles, must be
> + "hdmi0" and "hdmi1"
> + - #address-cells : should be <1>
> + - #size-cells : should be <0>
> +
> +Required nodes:
> + - port: Audio and video input port nodes with endpoint definitions
> + as defined in Documentation/devicetree/bindings/graph.txt.
> + port@0 is video and port@1 is audio.
> +
> +Example:
> +
> + hdmi: hdmi@01ee {
> + compatible = "allwinner,sun8i-a83t-hdmi";
> + reg = <0x01ee 0x2>;
> + clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
> +  < CLK_HDMI_DDC>;
> + clock-names = "bus", "clock", "ddc-clock";
> + resets = < RST_HDMI0>, < RST_HDMI1>;
> + reset-names = "hdmi0", "hdmi1";
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_a>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {/* video */
> + reg = <0>;
> + hdmi_tcon1: endpoint {
> + remote-endpoint = <_hdmi>;
> + };
> + };
> + port@1 {/* audio */
> + reg = <1>;
> + hdmi_i2s2: endpoint {
> + remote-endpoint = <_hdmi>;
> + };
> + };

You need a third port for the HDMI encoder output, connected to an HDMI 
connector DT node.

> + };

-- 
Regards,

Laurent Pinchart

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[linux-sunxi] Re: [PATCH v7 2/8] drm/sun8i: Add DT bindings documentation of Allwinner DE2

[Laurent Pinchart]

Hi Jean-François,

A brief update.

On Tuesday 29 Nov 2016 20:41:30 Laurent Pinchart wrote:
> On Monday 28 Nov 2016 19:02:39 Jean-Francois Moine wrote:
> > Signed-off-by: Jean-Francois Moine 
> > ---
> > 
> >  .../bindings/display/sunxi/sun8i-de2.txt   | 121 
> >  1 file changed, 121 insertions(+)
> >  create mode 100644
> > 
> > Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> > b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt new file
> > mode 100644
> > index 000..edf38b8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> > @@ -0,0 +1,121 @@
> > +Allwinner sun8i Display Engine 2 subsystem
> > +==
> > +
> > +The Allwinner DE2 subsystem contains a display controller (DE2),
> > +one or two LCD controllers (Timing CONtrollers) and their external
> > +interfaces (encoders/connectors).
> > +
> > +  +---+
> > +  | DE2   |
> > +  |   |
> > +  | +---+ |
> > +  plane --->|   | |   +--+
> > +  | | mixer |>| TCON |---> encoder  ---> display
> > +  plane --->|   | |   +--+ connector device
> > +  | +---+ |
> > +  |   |
> > +  | +---+ |
> > +  plane --->|   | |   +--+
> > +  | | mixer |>| TCON |---> encoder  ---> display
> > +  plane --->|   | |   +--+ connector device
> > +  | +---+ |
> > +  +---+
> > +
> > +The DE2 contains a processor which mixes the input planes and creates
> > +the images which are sent to the TCONs.
> > +From the software point of vue, there are 2 independent real-time
> > +mixers, each one being statically associated to one TCON.
> > +
> > +The TCONs adjust the image format to the one of the display device.
> > +
> > +Display controller (DE2)
> > +
> > +
> > +Required properties:
> > +
> > +- compatible: value should be one of the following
> > +   "allwinner,sun8i-a83t-display-engine"
> > +   "allwinner,sun8i-h3-display-engine"
> > +
> > +- reg: base address and size of the I/O memory
> > +
> > +- clocks: must include clock specifiers corresponding to entries in the
> > +   clock-names property.
> > +
> > +- clock-names: must contain
> > +   "bus": bus gate
> > +   "clock": clock
> > +
> > +- resets: phandle to the reset of the device
> > +
> > +- ports: must contain a list of 2 phandles, indexed by mixer number,
> > +   and pointing to display interface ports of TCONs
> > +
> > +LCD controller (TCON)
> > +=
> > +
> > +Required properties:
> > +
> > +- compatible: should be
> > +   "allwinner,sun8i-a83t-tcon"
> > +
> > +- reg: base address and size of the I/O memory
> > +
> > +- clocks: must include clock specifiers corresponding to entries in the
> > +   clock-names property.
> > +
> > +- clock-names: must contain
> > +   "bus": bus gate
> > +   "clock": pixel clock
> > +
> > +- resets: phandle to the reset of the device
> > +
> > +- interrupts: interrupt number for the TCON
> > +
> > +- port: port node with endpoint definitions as defined in
> > +   Documentation/devicetree/bindings/media/video-interfaces.txt
> > +
> > +Example:
> > +
> > +   de: de-controller@0100 {
> > +   compatible = "allwinner,sun8i-h3-display-engine";
> > +   reg = <0x0100 0x40>;
> > +   clocks = < CLK_BUS_DE>, < CLK_DE>;
> > +   clock-names = "bus", "clock";
> > +   resets = < RST_BUS_DE>;
> > +   ports = <_p>, <_p>;
> 
> This isn't how the OF graph DT bindings are used. You should instead have
> 
>   ports {
>   #address-cells = <1>;
>   #size-cells = <0>;
>   port@0 {

I forgot to add reg = <0>; (and similarly for port 1).

>   de_out_0: endpoint {
>   remote_endpoint = <_hdmi>;
>   };
>   };
>   port@1 {
>   /* No endpoint as the port is not connected */
>   };
>   };
> 
> > +   };
> > +
> > +   tcon0: lcd-controller@01c0c000 {
> > +   compatible = "allwinner,sun8i-a83t-tcon";
> > +   reg = <0x01c0c000 0x400>;
> > +   clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
> > +   clock-names = "bus", "clock";
> > +   resets = < RST_BUS_TCON0>;
> > +   interrupts = ;
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   tcon0_p: port {
> > +   tcon0_hdmi: endpoint {
> > +   remote-endpoint = <_tcon0>;
> > +   };
> > +   };
> 
> and here
> 
>   port {
>   tcon0_hdmi: endpoint {
>   

[linux-sunxi] Re: [PATCH v7 2/8] drm/sun8i: Add DT bindings documentation of Allwinner DE2

[Laurent Pinchart]

Hi Jean-François,

Thank you for the patch.

On Monday 28 Nov 2016 19:02:39 Jean-Francois Moine wrote:
> Signed-off-by: Jean-Francois Moine 
> ---
>  .../bindings/display/sunxi/sun8i-de2.txt   | 121 ++
>  1 file changed, 121 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt new file
> mode 100644
> index 000..edf38b8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
> @@ -0,0 +1,121 @@
> +Allwinner sun8i Display Engine 2 subsystem
> +==
> +
> +The Allwinner DE2 subsystem contains a display controller (DE2),
> +one or two LCD controllers (Timing CONtrollers) and their external
> +interfaces (encoders/connectors).
> +
> +  +---+
> +  | DE2   |
> +  |   |
> +  | +---+ |
> +  plane --->|   | |   +--+
> +  | | mixer |>| TCON |---> encoder  ---> display
> +  plane --->|   | |   +--+ connector device
> +  | +---+ |
> +  |   |
> +  | +---+ |
> +  plane --->|   | |   +--+
> +  | | mixer |>| TCON |---> encoder  ---> display
> +  plane --->|   | |   +--+ connector device
> +  | +---+ |
> +  +---+
> +
> +The DE2 contains a processor which mixes the input planes and creates
> +the images which are sent to the TCONs.
> +From the software point of vue, there are 2 independent real-time
> +mixers, each one being statically associated to one TCON.
> +
> +The TCONs adjust the image format to the one of the display device.
> +
> +Display controller (DE2)
> +
> +
> +Required properties:
> +
> +- compatible: value should be one of the following
> + "allwinner,sun8i-a83t-display-engine"
> + "allwinner,sun8i-h3-display-engine"
> +
> +- reg: base address and size of the I/O memory
> +
> +- clocks: must include clock specifiers corresponding to entries in the
> + clock-names property.
> +
> +- clock-names: must contain
> + "bus": bus gate
> + "clock": clock
> +
> +- resets: phandle to the reset of the device
> +
> +- ports: must contain a list of 2 phandles, indexed by mixer number,
> + and pointing to display interface ports of TCONs
> +
> +LCD controller (TCON)
> +=
> +
> +Required properties:
> +
> +- compatible: should be
> + "allwinner,sun8i-a83t-tcon"
> +
> +- reg: base address and size of the I/O memory
> +
> +- clocks: must include clock specifiers corresponding to entries in the
> + clock-names property.
> +
> +- clock-names: must contain
> + "bus": bus gate
> + "clock": pixel clock
> +
> +- resets: phandle to the reset of the device
> +
> +- interrupts: interrupt number for the TCON
> +
> +- port: port node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +Example:
> +
> + de: de-controller@0100 {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + reg = <0x0100 0x40>;
> + clocks = < CLK_BUS_DE>, < CLK_DE>;
> + clock-names = "bus", "clock";
> + resets = < RST_BUS_DE>;
> + ports = <_p>, <_p>;

This isn't how the OF graph DT bindings are used. You should instead have

ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
de_out_0: endpoint {
remote_endpoint = <_hdmi>;
};
};
port@1 {
/* No endpoint as the port is not connected */
};
};

> + };
> +
> + tcon0: lcd-controller@01c0c000 {
> + compatible = "allwinner,sun8i-a83t-tcon";
> + reg = <0x01c0c000 0x400>;
> + clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
> + clock-names = "bus", "clock";
> + resets = < RST_BUS_TCON0>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + tcon0_p: port {
> + tcon0_hdmi: endpoint {
> + remote-endpoint = <_tcon0>;
> + };
> + };

and here

port {
tcon0_hdmi: endpoint {
remote-endpoint = <_out_0>;
};
};

> + };
> +
> + /* not used */
> + tcon1: lcd-controller@01c0d000 {
> + compatible = "allwinner,sun8i-h3-tcon";
> + reg = <0x01c0d000 0x400>;
> + clocks = < CLK_BUS_TCON1>,
> +   

[linux-sunxi] Re: [PATCH 09/14] net: Add ability to set MAC address via EEPROM

[Olliver Schinagl]

Hey Michal,


On 28-11-16 09:21, Michal Simek wrote:

On 25.11.2016 16:30, Olliver Schinagl wrote:

This patch allows Kconfig to enable and set parameters to make it
possible to read the MAC address from an EEPROM. The net core layer then
uses this information to read MAC addresses from this EEPROM.

Besides the various tuneables as to how to access the eeprom (bus,
address, addressing mode/length, 2 configurable that are EEPROM generic
(e.g. SPI or some other form of access) which are:

NET_ETHADDR_EEPROM_OFFSET, indicating where in the EEPROM the start of
the MAC address is. The default is 8 allowing for 8 bytes before the MAC
for other purposes (header MAGIC for example).

NET_ETHADDR_EEPROM_CRC8, indicating the MAC is appended with a CRC8-CCIT
checksum that should be verified.

Currently only I2C eeproms have been tested and thus only those options
are available, but shouldn't be a limit. NET_ETHADDR_EEPROM_SPI can be
just as created and added.

The code currently first checks if there is a non-zero MAC address in
the eeprom. If that fails to be the case, the read_rom_hwaddr can be
used by a board to supply the MAC in other ways.

If both these fails, the other code is still in place to query the
environent, which then can be used to override the hardware supplied
data.

Signed-off-by: Olliver Schinagl 
---
  doc/README.enetaddr | 99 +
  include/net.h   | 14 
  net/Kconfig | 59 +++
  net/eth-uclass.c|  9 +++--
  net/eth_common.c| 34 ++
  net/eth_legacy.c|  2 ++
  6 files changed, 214 insertions(+), 3 deletions(-)

diff --git a/doc/README.enetaddr b/doc/README.enetaddr
index 50e4899..89c1f7d 100644
--- a/doc/README.enetaddr
+++ b/doc/README.enetaddr
@@ -47,6 +47,105 @@ Correct flow of setting up the MAC address (summarized):
  Previous behavior had the MAC address always being programmed into hardware
  in the device's init() function.
  
+

+ EEPROM
+
+
+Boards may come with an EEPROM specifically to store configuration bits, such
+as a MAC address. Using CONFIG_NET_ETHADDR_EEPROM enables this feature.
+Depending on the board, the EEPROM may be connected on various methods, but
+currently, only the I2C bus can be used via CONFIG_NET_ETHADDR_EEPROM_I2C.
+
+The following config options are available,
+CONFIG_NET_ETHADDR_EEPROM_I2C_BUS is the I2C bus on which the eeprom is 
present.
+CONFIG_NET_ETHADDR_EEPROM_I2C_ADDR sets the address of the EEPROM, which
+defaults to the very common 0x50. Small size EEPROM's generally use single byte
+addressing but larger EEPROM's may use double byte addressing, which can be
+configured using CONFIG_NET_ETHADDR_EEPROM_ADDRLEN.
+
+Within the EEPROM, the MAC address can be stored on any arbitrary offset,
+CONFIG_NET_ETHADDR_EEPROM_OFFSET sets this to 8 as a default however, allowing
+the first 8 bytes to be used for an optional data, for example a configuration
+struct where the mac address is part of.
+
+Appending the 6 (ARP_HLEN) bytes is a CRC8 byte over the previous ARP_HLEN
+bytes. Whether to check this CRC8 or not is dependent on
+CONFIG_NET_ETHADDR_EEPROM_CRC8.
+
+To keep things nicely aligned, a final 'reserved' byte is added to the mac
+address + crc8 combo.
+
+A board may want to store more information in its eeprom, using the following
+example layout, this can be achieved.
+
+struct mac_addr {
+   uint8_t mac[ARP_HLEN];
+   uint8_t crc8;
+   uint8_t reserved;
+};
+
+struct config_eeprom {
+   uint32_t magic;
+   uint8_t version;
+   uint8_t reserved[2];
+   uint8_t mac_cnt;
+   struct mac_addr[mac_cnt];
+};
+
+Filling this in:
+struct config_eeprom eeprom = {
+   .magic = { 'M', 'g', 'i', 'c' },
+   .reserved = { 0x00, 0x00 },
+   .mac_cnt = 2,
+   .mac_addr = {
+   {
+   .mac = {
+   0x01, 0x23, 0x45,
+   0x67, 0x89, 0xab,
+   },
+   .crc8 = 0xbe,
+   .reserved = 0x00,
+   }, {
+   .mac = {
+   0xba, 0x98, 0x76,
+   0x54, 0x32, 0x10,
+   },
+   .crc8 = 0x82,
+   .reserved = 0x00,
+   },
+   },
+};
+
+The eeprom content would look like this.
+
+  4d 67 69 63 01 00 00 02  01 23 45 67 89 ab be 00 |Mgic.#Eg|
+0010  ba 98 76 54 32 10 82 00  |..vT2...|
+
+This can be done from linux using the i2c-tools:
+
+i2cset I2CBUS 0x50 0x08 0x01
+i2cset I2CBUS 0x50 0x09 0x23
+i2cset I2CBUS 0x50 0x0a 0x45
+i2cset I2CBUS 0x50 0x0b 0x67
+i2cset I2CBUS 0x50 0x0c 0x89
+i2cset I2CBUS 0x50 0x0d 0xab
+i2cset I2CBUS 0x50 0x0e 0xbe
+
+Alternativly this can be done from the u-boot console as:
+
+u-boot> mm.b 0
+: 00 ? 

[linux-sunxi] Re: [PATCH 01/14] net: cosmetic: Do not use magic values for ARP_HLEN

[Olliver Schinagl]

Just a note to myself mostly, I forgot to this one in the patch series, 
son in v2 I'll add that as well.



diff --git a/net/eth_common.c b/net/eth_common.c
index e0d8b62..57ef821 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -51,7 +51,7 @@ void eth_parse_enetaddr(const char *addr, uchar *enetaddr)
char *end;
int i;

-   for (i = 0; i < 6; ++i) {
+   for (i = 0; i < ARP_HLEN; ++i) {
enetaddr[i] = addr ? simple_strtoul(addr, , 16) : 0;
if (addr)
addr = (*end) ? end + 1 : end;


On 25-11-16 16:30, Olliver Schinagl wrote:

Commit 674bb249825a ("net: cosmetic: Replace magic numbers in arp.c with
constants") introduced a nice define to replace the magic value 6 for
the ethernet hardware address. Replace more hardcoded instances of 6
which really reference the ARP_HLEN (iow the MAC/Hardware/Ethernet
address).

Signed-off-by: Olliver Schinagl 
---
  common/fdt_support.c |  2 +-
  include/net.h| 52 +++-
  net/eth-uclass.c | 10 +-
  net/eth_legacy.c | 10 +-
  4 files changed, 38 insertions(+), 36 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index 0609470..b082662 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -471,7 +471,7 @@ void fdt_fixup_ethernet(void *fdt)
char *tmp, *end;
char mac[16];
const char *path;
-   unsigned char mac_addr[6];
+   unsigned char mac_addr[ARP_HLEN];
int offset;
  
  	if (fdt_path_offset(fdt, "/aliases") < 0)

diff --git a/include/net.h b/include/net.h
index 06320c6..8137cf3 100644
--- a/include/net.h
+++ b/include/net.h
@@ -38,6 +38,9 @@
  
  #define PKTALIGN	ARCH_DMA_MINALIGN
  
+/* ARP hardware address length */

+#define ARP_HLEN 6
+
  /* IPv4 addresses are always 32 bits in size */
  struct in_addr {
__be32 s_addr;
@@ -90,7 +93,7 @@ enum eth_state_t {
   */
  struct eth_pdata {
phys_addr_t iobase;
-   unsigned char enetaddr[6];
+   unsigned char enetaddr[ARP_HLEN];
int phy_interface;
int max_speed;
  };
@@ -161,7 +164,7 @@ void eth_halt_state_only(void); /* Set passive state */
  #ifndef CONFIG_DM_ETH
  struct eth_device {
char name[16];
-   unsigned char enetaddr[6];
+   unsigned char enetaddr[ARP_HLEN];
phys_addr_t iobase;
int state;
  
@@ -293,9 +296,9 @@ u32 ether_crc(size_t len, unsigned char const *p);

   */
  
  struct ethernet_hdr {

-   u8  et_dest[6]; /* Destination node */
-   u8  et_src[6];  /* Source node  */
-   u16 et_protlen; /* Protocol or length   */
+   u8  et_dest[ARP_HLEN];  /* Destination node */
+   u8  et_src[ARP_HLEN];   /* Source node  */
+   u16 et_protlen; /* Protocol or length   */
  };
  
  /* Ethernet header size */

@@ -304,16 +307,16 @@ struct ethernet_hdr {
  #define ETH_FCS_LEN   4   /* Octets in the FCS*/
  
  struct e802_hdr {

-   u8  et_dest[6]; /* Destination node */
-   u8  et_src[6];  /* Source node  */
-   u16 et_protlen; /* Protocol or length   */
-   u8  et_dsap;/* 802 DSAP */
-   u8  et_ssap;/* 802 SSAP */
-   u8  et_ctl; /* 802 control  */
-   u8  et_snap1;   /* SNAP */
+   u8  et_dest[ARP_HLEN];  /* Destination node */
+   u8  et_src[ARP_HLEN];   /* Source node  */
+   u16 et_protlen; /* Protocol or length   */
+   u8  et_dsap;/* 802 DSAP */
+   u8  et_ssap;/* 802 SSAP */
+   u8  et_ctl; /* 802 control  */
+   u8  et_snap1;   /* SNAP */
u8  et_snap2;
u8  et_snap3;
-   u16 et_prot;/* 802 protocol */
+   u16 et_prot;/* 802 protocol */
  };
  
  /* 802 + SNAP + ethernet header size */

@@ -323,11 +326,11 @@ struct e802_hdr {
   *Virtual LAN Ethernet header
   */
  struct vlan_ethernet_hdr {
-   u8  vet_dest[6];/* Destination node */
-   u8  vet_src[6]; /* Source node  */
-   u16 vet_vlan_type;  /* PROT_VLAN*/
-   u16 vet_tag;/* TAG of VLAN  */
-   u16 vet_type;   /* protocol type*/
+   u8

[linux-sunxi] Banana pi m1+

[krichy]

Dear devs,

I own a BPI-M1+ board, and with latest kernel and device tree files my 
board did not boot up. I had to give it the attached dts file to boot 
up, and make the usb and wifi work.


Please would someone confirm that this is the right way?

Regards,
Richard Kojedzinszky

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#include "sun7i-a20-bananapi-m1-plus.dts"

 {
	compatible = "allwinner,sun5i-a13-mmc";
};

 {
	compatible = "allwinner,sun5i-a13-mmc";
};

 {
	status = "okay";
};

[linux-sunxi] [PATCH v7 3/8] drm: sun8i: add HDMI video support to A83T and H3

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 drivers/gpu/drm/sun8i/Kconfig   |   7 +
 drivers/gpu/drm/sun8i/Makefile  |   2 +
 drivers/gpu/drm/sun8i/de2_hdmi.c| 440 +++
 drivers/gpu/drm/sun8i/de2_hdmi.h|  51 +++
 drivers/gpu/drm/sun8i/de2_hdmi_io.c | 843 
 5 files changed, 1343 insertions(+)
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi_io.c

diff --git a/drivers/gpu/drm/sun8i/Kconfig b/drivers/gpu/drm/sun8i/Kconfig
index 6940895..5c4607b 100644
--- a/drivers/gpu/drm/sun8i/Kconfig
+++ b/drivers/gpu/drm/sun8i/Kconfig
@@ -17,3 +17,10 @@ config DRM_SUN8I_DE2
  Choose this option if your Allwinner chipset has the DE2 interface
  as the A64, A83T and H3. If M is selected the module will be called
  sun8i-de2-drm.
+
+config DRM_SUN8I_DE2_HDMI
+   tristate "Support for DE2 HDMI"
+   depends on DRM_SUN8I_DE2
+   help
+ Choose this option if you use want HDMI on DE2.
+ If M is selected the module will be called sun8i-de2-hdmi.
diff --git a/drivers/gpu/drm/sun8i/Makefile b/drivers/gpu/drm/sun8i/Makefile
index f107919..6ba97c2 100644
--- a/drivers/gpu/drm/sun8i/Makefile
+++ b/drivers/gpu/drm/sun8i/Makefile
@@ -3,5 +3,7 @@
 #
 
 sun8i-de2-drm-objs := de2_drv.o de2_crtc.o de2_plane.o
+sun8i-de2-hdmi-objs := de2_hdmi.o de2_hdmi_io.o
 
 obj-$(CONFIG_DRM_SUN8I_DE2) += sun8i-de2-drm.o
+obj-$(CONFIG_DRM_SUN8I_DE2_HDMI) += sun8i-de2-hdmi.o
diff --git a/drivers/gpu/drm/sun8i/de2_hdmi.c b/drivers/gpu/drm/sun8i/de2_hdmi.c
new file mode 100644
index 000..9ff6132
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/de2_hdmi.c
@@ -0,0 +1,440 @@
+/*
+ * Allwinner DRM driver - HDMI
+ *
+ * Copyright (C) 2016 Jean-Francois Moine 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+#include "de2_hdmi.h"
+
+static const struct of_device_id de2_hdmi_dt_ids[] = {
+   { .compatible = "allwinner,sun8i-a83t-hdmi",
+   .data = (void *) SOC_A83T },
+   { .compatible = "allwinner,sun8i-h3-hdmi",
+   .data = (void *) SOC_H3 },
+   { }
+};
+MODULE_DEVICE_TABLE(of, de2_hdmi_dt_ids);
+
+#define conn_to_priv(x) \
+   container_of(x, struct de2_hdmi_priv, connector)
+
+#define enc_to_priv(x) \
+   container_of(x, struct de2_hdmi_priv, encoder)
+
+/* --- encoder functions --- */
+
+static int de2_hdmi_set_clock(struct de2_hdmi_priv *priv,
+   int rate)
+{
+   struct clk *parent_clk;
+   u32 parent_rate;
+   int ret;
+
+   /* determine and set the best rate for the parent clock (pll-video) */
+   if ((27 * 2) % rate == 0)
+   parent_rate = 27000;
+   else if (297000 % rate == 0)
+   parent_rate = 29700;
+   else
+   return -EINVAL; /* unsupported clock */
+
+   parent_clk = clk_get_parent(priv->clk);
+
+   ret = clk_set_rate(parent_clk, parent_rate);
+   if (ret) {
+   dev_err(priv->dev, "set parent rate failed %d\n", ret);
+   return ret;
+   }
+   ret = clk_set_rate(priv->clk, rate * 1000);
+   if (ret)
+   dev_err(priv->dev, "set rate failed %d\n", ret);
+
+   return ret;
+}
+
+static void de2_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+   struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+
+   priv->cea_mode = drm_match_cea_mode(mode);
+
+   DRM_DEBUG_DRIVER("cea_mode %d\n", priv->cea_mode);
+
+   if (de2_hdmi_set_clock(priv, mode->clock) < 0)
+   return;
+
+   mutex_lock(>mutex);
+   hdmi_io_mode_set(priv, mode);
+   mutex_unlock(>mutex);
+}
+
+static void de2_hdmi_encoder_enable(struct drm_encoder *encoder)
+{
+   struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+
+   mutex_lock(>mutex);
+   hdmi_io_video_on(priv);
+   mutex_unlock(>mutex);
+}
+
+static void de2_hdmi_encoder_disable(struct drm_encoder *encoder)
+{
+   struct de2_hdmi_priv *priv = enc_to_priv(encoder);
+
+   mutex_lock(>mutex);
+   hdmi_io_video_off(priv);
+   mutex_unlock(>mutex);
+}
+
+static const struct drm_encoder_helper_funcs de2_hdmi_encoder_helper_funcs = {
+   .mode_set = de2_hdmi_encoder_mode_set,
+   .enable = de2_hdmi_encoder_enable,
+   .disable = de2_hdmi_encoder_disable,
+};
+

[linux-sunxi] [PATCH v7 2/8] drm/sun8i: Add DT bindings documentation of Allwinner DE2

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 .../bindings/display/sunxi/sun8i-de2.txt   | 121 +
 1 file changed, 121 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt 
b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
new file mode 100644
index 000..edf38b8
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
@@ -0,0 +1,121 @@
+Allwinner sun8i Display Engine 2 subsystem
+==
+
+The Allwinner DE2 subsystem contains a display controller (DE2),
+one or two LCD controllers (Timing CONtrollers) and their external
+interfaces (encoders/connectors).
+
+  +---+
+  | DE2   |
+  |   |
+  | +---+ |
+  plane --->|   | |   +--+
+  | | mixer |>| TCON |---> encoder  ---> display
+  plane --->|   | |   +--+ connector device
+  | +---+ |
+  |   |
+  | +---+ |
+  plane --->|   | |   +--+
+  | | mixer |>| TCON |---> encoder  ---> display
+  plane --->|   | |   +--+ connector device
+  | +---+ |
+  +---+
+
+The DE2 contains a processor which mixes the input planes and creates
+the images which are sent to the TCONs.
+From the software point of vue, there are 2 independent real-time
+mixers, each one being statically associated to one TCON.
+
+The TCONs adjust the image format to the one of the display device.
+
+Display controller (DE2)
+
+
+Required properties:
+
+- compatible: value should be one of the following
+   "allwinner,sun8i-a83t-display-engine"
+   "allwinner,sun8i-h3-display-engine"
+
+- reg: base address and size of the I/O memory
+
+- clocks: must include clock specifiers corresponding to entries in the
+   clock-names property.
+
+- clock-names: must contain
+   "bus": bus gate
+   "clock": clock
+
+- resets: phandle to the reset of the device
+
+- ports: must contain a list of 2 phandles, indexed by mixer number,
+   and pointing to display interface ports of TCONs
+
+LCD controller (TCON)
+=
+
+Required properties:
+
+- compatible: should be
+   "allwinner,sun8i-a83t-tcon"
+
+- reg: base address and size of the I/O memory
+
+- clocks: must include clock specifiers corresponding to entries in the
+   clock-names property.
+
+- clock-names: must contain
+   "bus": bus gate
+   "clock": pixel clock
+
+- resets: phandle to the reset of the device
+
+- interrupts: interrupt number for the TCON
+
+- port: port node with endpoint definitions as defined in
+   Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+
+   de: de-controller@0100 {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   reg = <0x0100 0x40>;
+   clocks = < CLK_BUS_DE>, < CLK_DE>;
+   clock-names = "bus", "clock";
+   resets = < RST_BUS_DE>;
+   ports = <_p>, <_p>;
+   };
+
+   tcon0: lcd-controller@01c0c000 {
+   compatible = "allwinner,sun8i-a83t-tcon";
+   reg = <0x01c0c000 0x400>;
+   clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
+   clock-names = "bus", "clock";
+   resets = < RST_BUS_TCON0>;
+   interrupts = ;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   tcon0_p: port {
+   tcon0_hdmi: endpoint {
+   remote-endpoint = <_tcon0>;
+   };
+   };
+   };
+
+   /* not used */
+   tcon1: lcd-controller@01c0d000 {
+   compatible = "allwinner,sun8i-h3-tcon";
+   reg = <0x01c0d000 0x400>;
+   clocks = < CLK_BUS_TCON1>,
+< CLK_TCON0>;  /* no clock */
+   clock-names = "bus", "clock";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   tcon1_p: port {
+   endpoint {
+   /* empty */
+   };
+   };
+   };
-- 
2.10.2

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[linux-sunxi] [PATCH v7 4/8] drm/sunxi: Add DT bindings documentation of Allwinner HDMI

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 .../devicetree/bindings/display/sunxi/hdmi.txt | 56 ++
 1 file changed, 56 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt

diff --git a/Documentation/devicetree/bindings/display/sunxi/hdmi.txt 
b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
new file mode 100644
index 000..1e107cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sunxi/hdmi.txt
@@ -0,0 +1,56 @@
+Allwinner HDMI Transmitter
+==
+
+The Allwinner HDMI transmitters are included in the SoCs.
+They support audio and video.
+
+Required properties:
+ - compatible : should be one of
+   "allwinner,sun8i-a83t-hdmi"
+   "allwinner,sun8i-h3-hdmi"
+ - reg: base address and size of the I/O memory
+ - clocks : phandles to the HDMI clocks as described in
+   Documentation/devicetree/bindings/clock/clock-bindings.txt
+ - clock-names : must be
+   "bus" : bus gate
+   "clock" : streaming clock
+   "ddc-clock" : DDC clock
+ - resets : One or two phandles to the HDMI resets
+ - reset-names : when 2 phandles, must be
+   "hdmi0" and "hdmi1"
+ - #address-cells : should be <1>
+ - #size-cells : should be <0>
+
+Required nodes:
+ - port: Audio and video input port nodes with endpoint definitions
+   as defined in Documentation/devicetree/bindings/graph.txt.
+   port@0 is video and port@1 is audio.
+
+Example:
+
+   hdmi: hdmi@01ee {
+   compatible = "allwinner,sun8i-a83t-hdmi";
+   reg = <0x01ee 0x2>;
+   clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   clock-names = "bus", "clock", "ddc-clock";
+   resets = < RST_HDMI0>, < RST_HDMI1>;
+   reset-names = "hdmi0", "hdmi1";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   port@0 {/* video */
+   reg = <0>;
+   hdmi_tcon1: endpoint {
+   remote-endpoint = <_hdmi>;
+   };
+   };
+   port@1 {/* audio */
+   reg = <1>;
+   hdmi_i2s2: endpoint {
+   remote-endpoint = <_hdmi>;
+   };
+   };
+   };
-- 
2.10.2

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[linux-sunxi] [PATCH v7 6/8] ARM: dts: sun8i-h3: add HDMI video nodes

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
Note 1:
 The DE clock is not set in the driver. Instead, it is set at system
 startup time by 'assigned-clocks', but there is a problem in sunxi-ng
 which uses readl_relaxed_poll_timeout(), and, as noticed by
 Ondřej Jirman, this function is not available at startup time.
 The fix of this problem is not part of this patchset series.
Note 2:
 The DE clock is set to a high enough rate (432MHz). It seems that
 this is needed to handle 4K video.
 But, as the proposed DE driver does not treat yet 4K video, the clock
 could be set to a lower rate. For example, the default rate for the A83T
 is 250MHz (no 4K video).
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 65 +
 1 file changed, 65 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fca66bf..1aa087d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -140,6 +140,16 @@
#size-cells = <1>;
ranges;
 
+   de: de-controller@0100 {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   reg = <0x0100 0x40>;
+   clocks = < CLK_BUS_DE>, < CLK_DE>;
+   clock-names = "bus", "clock";
+   resets = < RST_BUS_DE>;
+   ports = <_p>, <_p>;
+   status = "disabled";
+   };
+
dma: dma-controller@01c02000 {
compatible = "allwinner,sun8i-h3-dma";
reg = <0x01c02000 0x1000>;
@@ -149,6 +159,37 @@
#dma-cells = <1>;
};
 
+   tcon0: lcd-controller@01c0c000 {
+   compatible = "allwinner,sun8i-a83t-tcon";
+   reg = <0x01c0c000 0x400>;
+   clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
+   clock-names = "bus", "clock";
+   resets = < RST_BUS_TCON0>;
+   interrupts = ;
+   status = "disabled";
+   tcon0_p: port {
+   tcon0_hdmi: endpoint {
+   remote-endpoint = <_tcon0>;
+   };
+   };
+   };
+
+   /* not used */
+   tcon1: lcd-controller@01c0d000 {
+   compatible = "allwinner,sun8i-h3-tcon";
+   reg = <0x01c0d000 0x400>;
+   clocks = < CLK_BUS_TCON1>,
+< CLK_TCON0>;  /* no clock */
+   clock-names = "bus", "clock";
+   interrupts = ;
+   status = "disabled";
+   tcon1_p: port {
+   endpoint {
+   /* empty */
+   };
+   };
+   };
+
mmc0: mmc@01c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -314,6 +355,11 @@
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
+
+   assigned-clocks = < CLK_PLL_DE>,
+ < CLK_DE>;
+   assigned-clock-rates =  <86400>,
+   <43200>;
};
 
pio: pinctrl@01c20800 {
@@ -567,6 +613,25 @@
interrupts = ;
};
 
+   hdmi: hdmi@01ee {
+   compatible = "allwinner,sun8i-h3-hdmi";
+   reg = <0x01ee 0x2>;
+   clocks = < CLK_BUS_HDMI>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   clock-names = "bus", "clock", "ddc-clock";
+   resets = < RST_BUS_HDMI0>, < RST_BUS_HDMI1>;
+   reset-names = "hdmi0", "hdmi1";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   port@0 {/* video */
+   reg = <0>;
+   hdmi_tcon0: endpoint {
+   remote-endpoint = <_hdmi>;
+   };
+   };
+   };
+
rtc: rtc@01f0 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f0 0x54>;
-- 
2.10.2

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[linux-sunxi] [PATCH v7 7/8] ARM: dts: sun8i-h3: Add HDMI video to the Banana Pi M2+

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index c0c49dd..9f3e2f8 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -93,6 +93,10 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
@@ -101,12 +105,20 @@
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
-- 
2.10.2

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[linux-sunxi] [PATCH v7 8/8] ARM: dts: sun8i-h3: Add HDMI video to the Orange PI 2

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 047e9e1..7712972 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -105,16 +105,28 @@
};
 };
 
+ {
+   status = "okay";
+};
+
  {
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
 };
 
+ {
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
-- 
2.10.2

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[linux-sunxi] [PATCH v7 0/8] drm: sun8i: Add DE2 HDMI video support

[Jean-Francois Moine]

This patchset series adds HDMI video support to the Allwinner
sun8i SoCs which include the display engine 2 (DE2).
The driver contains the code for the A83T and H3 SoCs, and
some H3 boards, but it could be used/extended for other SoCs
(A64, H2, H5) and boards (Banana PIs, Orange PIs).

v7:
- more explanations about the DE2 in the DT documentation
- separate patches for DT documentation (Rob Herring)
- show all properties in DT examples (Rob Herring)
- use drm_of_component_probe()
- use the index of the DE 'ports' in the DT as
  the DE mixer number (no alias needed anymore)
- change some 'lcd' to 'tcon' in the DT
- add HDMI module parameter for DVI mode when screen overscan
  problems
- fall back to some CEA modes in case of EDID read failure
- fix some settings (interlace) and simplify code
- fix bug in start of A83T HDMI
- fix lack of CLK_PLL_DE definition in the DT include
  (Icenowy Zheng)
v6:
- remove audio support (other patchset to come)
- use DRM modeset data for HDMI configuration
(thanks to Jernej Škrabec)
- more meaningfull register names
- use a mutex for DE I/O protection
- merge DE and plane into one file
- don't activate the video hardware when video not started
(Maxime Ripard)
- remove 'type = "video" in DT graph ports
(Rob Herring)
- change the I/O accesses by #define instead of struct
(Maxime Ripard, André Przywara)
- remove pm functions (Maxime Ripard)
- set the pll-de/de clocks in the DT (Maxime Ripard)
- use platform_get_irq instead of irq_of_parse_and_map
(Maxime Ripard)
- rename sunxi to sun8i (Maxime Ripard)
- fix coding style errors (Maxime Ripard)
- subclass the drm structure in private data (Daniel Vetter)
- move drm_dev_register at end of init (Daniel Vetter)
v5:
- add overlay plane
- add audio support
- add support for the A83T
- add back the HDMI driver
- many bug fixes
v4: 
- drivers/clk/sunxi/Makefile was missing (Emil Velikov)
v3:
- add the hardware cursor
- simplify and fix the DE2 init sequences
- generation for all SUNXI SoCs (Andre Przywara)
v2:
- remove the HDMI driver
- remarks from Chen-Yu Tsai and Russell King
- DT documentation added

Jean-Francois Moine (8):
  drm: sun8i: Add a basic DRM driver for Allwinner DE2
  drm/sun8i: Add DT bindings documentation of Allwinner DE2
  drm: sun8i: add HDMI video support to A83T and H3
  drm/sunxi: Add DT bindings documentation of Allwinner HDMI
  clk: sunxi-ng: define the PLL DE clock
  ARM: dts: sun8i-h3: add HDMI video nodes
  ARM: dts: sun8i-h3: Add HDMI video to the Banana Pi M2+
  ARM: dts: sun8i-h3: Add HDMI video to the Orange PI 2

 .../devicetree/bindings/display/sunxi/hdmi.txt |  56 ++
 .../bindings/display/sunxi/sun8i-de2.txt   | 121 +++
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts|  12 +
 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts  |  12 +
 arch/arm/boot/dts/sun8i-h3.dtsi|  65 ++
 drivers/gpu/drm/Kconfig|   2 +
 drivers/gpu/drm/Makefile   |   1 +
 drivers/gpu/drm/sun8i/Kconfig  |  26 +
 drivers/gpu/drm/sun8i/Makefile |   9 +
 drivers/gpu/drm/sun8i/de2_crtc.c   | 449 +++
 drivers/gpu/drm/sun8i/de2_crtc.h   |  52 ++
 drivers/gpu/drm/sun8i/de2_drv.c| 317 
 drivers/gpu/drm/sun8i/de2_drv.h|  48 ++
 drivers/gpu/drm/sun8i/de2_hdmi.c   | 440 +++
 drivers/gpu/drm/sun8i/de2_hdmi.h   |  51 ++
 drivers/gpu/drm/sun8i/de2_hdmi_io.c| 842 +
 drivers/gpu/drm/sun8i/de2_plane.c  | 734 ++
 include/dt-bindings/clock/sun8i-h3-ccu.h   |   1 +
 18 files changed, 3238 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/sunxi/hdmi.txt
 create mode 100644 
Documentation/devicetree/bindings/display/sunxi/sun8i-de2.txt
 create mode 100644 drivers/gpu/drm/sun8i/Kconfig
 create mode 100644 drivers/gpu/drm/sun8i/Makefile
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_drv.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_drv.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_hdmi_io.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_plane.c

-- 
2.10.2

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[linux-sunxi] [PATCH v7 1/8] drm: sun8i: Add a basic DRM driver for Allwinner DE2

[Jean-Francois Moine]

Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
engine, DE2.
This patch adds a DRM video driver for this device.

Signed-off-by: Jean-Francois Moine 
---
 drivers/gpu/drm/Kconfig   |   2 +
 drivers/gpu/drm/Makefile  |   1 +
 drivers/gpu/drm/sun8i/Kconfig |  19 +
 drivers/gpu/drm/sun8i/Makefile|   7 +
 drivers/gpu/drm/sun8i/de2_crtc.c  | 449 +++
 drivers/gpu/drm/sun8i/de2_crtc.h  |  50 +++
 drivers/gpu/drm/sun8i/de2_drv.c   | 317 
 drivers/gpu/drm/sun8i/de2_drv.h   |  48 +++
 drivers/gpu/drm/sun8i/de2_plane.c | 734 ++
 9 files changed, 1627 insertions(+)
 create mode 100644 drivers/gpu/drm/sun8i/Kconfig
 create mode 100644 drivers/gpu/drm/sun8i/Makefile
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_drv.c
 create mode 100644 drivers/gpu/drm/sun8i/de2_drv.h
 create mode 100644 drivers/gpu/drm/sun8i/de2_plane.c

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 95fc041..bb1bfbc 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -202,6 +202,8 @@ source "drivers/gpu/drm/shmobile/Kconfig"
 
 source "drivers/gpu/drm/sun4i/Kconfig"
 
+source "drivers/gpu/drm/sun8i/Kconfig"
+
 source "drivers/gpu/drm/omapdrm/Kconfig"
 
 source "drivers/gpu/drm/tilcdc/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 883f3e7..3e1eaa0 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
 obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
 obj-y  += omapdrm/
 obj-$(CONFIG_DRM_SUN4I) += sun4i/
+obj-$(CONFIG_DRM_SUN8I) += sun8i/
 obj-y  += tilcdc/
 obj-$(CONFIG_DRM_QXL) += qxl/
 obj-$(CONFIG_DRM_BOCHS) += bochs/
diff --git a/drivers/gpu/drm/sun8i/Kconfig b/drivers/gpu/drm/sun8i/Kconfig
new file mode 100644
index 000..6940895
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/Kconfig
@@ -0,0 +1,19 @@
+#
+# Allwinner DE2 Video configuration
+#
+
+config DRM_SUN8I
+   bool
+
+config DRM_SUN8I_DE2
+   tristate "Support for Allwinner Video with DE2 interface"
+   depends on DRM && OF
+   depends on ARCH_SUNXI || COMPILE_TEST
+   select DRM_GEM_CMA_HELPER
+   select DRM_KMS_CMA_HELPER
+   select DRM_KMS_HELPER
+   select DRM_SUN8I
+   help
+ Choose this option if your Allwinner chipset has the DE2 interface
+ as the A64, A83T and H3. If M is selected the module will be called
+ sun8i-de2-drm.
diff --git a/drivers/gpu/drm/sun8i/Makefile b/drivers/gpu/drm/sun8i/Makefile
new file mode 100644
index 000..f107919
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for Allwinner's sun8i DRM device driver
+#
+
+sun8i-de2-drm-objs := de2_drv.o de2_crtc.o de2_plane.o
+
+obj-$(CONFIG_DRM_SUN8I_DE2) += sun8i-de2-drm.o
diff --git a/drivers/gpu/drm/sun8i/de2_crtc.c b/drivers/gpu/drm/sun8i/de2_crtc.c
new file mode 100644
index 000..4e94ccc
--- /dev/null
+++ b/drivers/gpu/drm/sun8i/de2_crtc.c
@@ -0,0 +1,449 @@
+/*
+ * Allwinner DRM driver - DE2 CRTC
+ *
+ * Copyright (C) 2016 Jean-Francois Moine 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "de2_drv.h"
+#include "de2_crtc.h"
+
+/* I/O map */
+
+#define TCON_GCTL_REG  0x00
+#defineTCON_GCTL_TCON_ENABLE BIT(31)
+#define TCON_GINT0_REG 0x04
+#defineTCON_GINT0_TCON1_Vb_Int_En BIT(30)
+#defineTCON_GINT0_TCON1_Vb_Int_Flag BIT(14)
+#defineTCON_GINT0_TCON1_Vb_Line_Int_Flag BIT(12)
+#define TCON0_CTL_REG  0x40
+#defineTCON0_CTL_TCON_ENABLE BIT(31)
+#define TCON1_CTL_REG  0x90
+#defineTCON1_CTL_TCON_ENABLE BIT(31)
+#defineTCON1_CTL_INTERLACE_ENABLE BIT(20)
+#defineTCON1_CTL_Start_Delay_SHIFT 4
+#defineTCON1_CTL_Start_Delay_MASK GENMASK(8, 4)
+#define TCON1_BASIC0_REG   0x94/* XI/YI */
+#define TCON1_BASIC1_REG   0x98/* LS_XO/LS_YO */
+#define TCON1_BASIC2_REG   0x9c/* XO/YO */
+#define TCON1_BASIC3_REG   0xa0/* HT/HBP */
+#define TCON1_BASIC4_REG   0xa4/* VT/VBP */
+#define TCON1_BASIC5_REG   0xa8/* HSPW/VSPW */
+#define TCON1_PS_SYNC_REG  0xb0
+#define TCON1_IO_POL_REG   0xf0
+#defineTCON1_IO_POL_IO0_inv BIT(24)
+#defineTCON1_IO_POL_IO1_inv BIT(25)
+#defineTCON1_IO_POL_IO2_inv BIT(26)
+#define TCON1_IO_TRI_REG   0xf4
+#define TCON_CEU_CTL_REG

[linux-sunxi] [PATCH v7 5/8] clk: sunxi-ng: define the PLL DE clock

[Jean-Francois Moine]

Signed-off-by: Jean-Francois Moine 
---
 include/dt-bindings/clock/sun8i-h3-ccu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h 
b/include/dt-bindings/clock/sun8i-h3-ccu.h
index efb7ba2..7af57b7 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -44,6 +44,7 @@
 #define _DT_BINDINGS_CLK_SUN8I_H3_H_
 
 #define CLK_CPUX   14
+#define CLK_PLL_DE 13
 
 #define CLK_BUS_CE 20
 #define CLK_BUS_DMA21
-- 
2.10.2

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