[linux-sunxi] Re: Sunxi FOSDEM dinner, sat 4 Feb @ 8PM

[Artyom Zorin]

I hope I'm not too late, but could you reserve 2 spots for me please

On Tuesday, 10 January 2017 17:01:38 UTC+1, Benjamin Henrion wrote:
>
> Hi, 
>
> Like previous years, I have booked the Amadeo restaurant for the Sunxi 
> FOSDEM dinner: 
>
> http://amadeus-resto.be/en/amadeo-brussel/ 
>
> Please reply to this mail so that I can book a place for you. 
>
> We will leave FOSDEM around 7PM at the O'Reilly booth, if you are 
> bored the last hour I will be speaking at 6PM: 
>
> https://fosdem.org/2017/schedule/event/pieter_hintjens/ 
>
> Best, 
>
> -- 
> Benjamin Henrion  
> FFII Brussels - +32-484-566109 - +32-2-3500762 
> "In July 2005, after several failed attempts to legalise software 
> patents in Europe, the patent establishment changed its strategy. 
> Instead of explicitly seeking to sanction the patentability of 
> software, they are now seeking to create a central European patent 
> court, which would establish and enforce patentability rules in their 
> favor, without any possibility of correction by competing courts or 
> democratically elected legislators." 
>

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Re: [linux-sunxi] Re: [U-Boot] [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Chen-Yu Tsai]

Hi,

On Fri, Feb 3, 2017 at 11:26 PM, Jagan Teki  wrote:
> On Feb 1, 2017 2:37 AM, "Andre Przywara"  wrote:
>
> The DRAM controller in the Allwinner H5 SoC is again very similar to
> the one in the H3 and A64.
> Based on the existing socid parameter, add support for this controller
> by reusing the bulk of the code and only deviating where needed.
> These new bits set or cleared here and there have been mostly found by
> looking at DRAM register dumps after using the H5 boot0 and comparing
> them to what we set in the code. So for now it's mostly unclear what
> those bits actually mean - hence the missing names and comments.
> Also add the delay line parameters taken from the boot0 and libdram
> disassembly.
>
>
> Can you split this patch with delay line params as separate patch.

It looks like the delay lines are for the H5, merely taken from
different sources. They are and should be part of the same patch
adding support for DRAM on the H5.

>
> Register setup differences between H5 and H3 are courtesy of Jens Kuske.
>
> Signed-off-by: Andre Przywara 
> Acked-by: Maxime Ripard 
> ---
>  arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
>  arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97
> +--
>  2 files changed, 82 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
> b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 6f96a97..e8e670e 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -15,5 +15,6 @@
>
>  #define SOCID_A64  0x1689
>  #define SOCID_H3   0x1680
> +#define SOCID_H5   0x1718
>
>  #endif /* _SUNXI_CPU_H */
> diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c
> b/arch/arm/mach-sunxi/dram_sun8i_h3.c
> index 9f7cc7f..d681a9d 100644
> --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
> +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
> @@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
> writel(0x8104, _com->mdfs_bwlr[2]);
>  }
>
> +static void mctl_set_master_priority_h5(void)
> +{
> +   struct sunxi_mctl_com_reg * const mctl_com =
> +   (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
> +
> +   /* enable bandwidth limit windows and set windows size 1us */
> +   writel(399, _com->tmr);
> +   writel((1 << 16), _com->bwcr);
>
>
> I'm not fond of using direct numerical values make code unhealthy please use
> macros with bitops. Note that this comment will apply rest of the code where
> it applies.

I think you are being unreasonable. The commit message clearly states that
the added code either comes from register dumps, disassembled blobs, or
comparison of released code:

"""
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
"""

For this particular instance, see

https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/u-boot-sunxi/arch/arm/cpu/armv7/sun8iw11p1/dram/lib-dram/mctl_hal.c#L197

which gives the exact same comment, and no named macros. Adding a macro
for it and calling it H5_DRAM_BW_UNKNOWN_MAGIC is not an improvement.
Same goes for the next few lines.

Allwinner has _never_ released documents for the DRAM controllers or DRAM PHYs,
and only sometimes releases code for DRAM init for some SoCs, sometimes with
questionable licenses (or lack of), of which some don't match what is actually
seen in provided blobs. Considering what the community has access to. This
patch seems to be quite good.

Regards
ChenYu

>
> +
> +   /* set cpu high priority */
> +   writel(0x0001, _com->mapr);
> +
> +   /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
> +* they initialise it */
> +   MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
> +   MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
> +   MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
> +   MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
> +   MBUS_CONF(VE, true, HIGHEST, 0, 1900, 1500, 1000);
> +   MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
> +   MBUS_CONF(  NAND, true,HIGH, 0,  256,  128,   64);
> +   MBUS_CONF(SS, true, HIGHEST, 0,  256,  128,   64);
> +   MBUS_CONF(TS, true, HIGHEST, 0,  256,  128,   64);
> +   MBUS_CONF(DI, true,HIGH, 0, 1024,  256,   64);
> +   MBUS_CONF(DE, true, HIGHEST, 3, 3400, 2400, 1024);
> +   MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
> +}
> +
>  static void mctl_set_master_priority(uint16_t socid)
>  {
> switch (socid) {
> @@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
> case SOCID_A64:
> mctl_set_master_priority_a64();

[linux-sunxi] Re: [U-Boot] [PATCH v3 09/13] sunxi: DRAM: add Allwinner H5 support

[Jagan Teki]

On Feb 1, 2017 2:37 AM, "Andre Przywara"  wrote:

The DRAM controller in the Allwinner H5 SoC is again very similar to
the one in the H3 and A64.
Based on the existing socid parameter, add support for this controller
by reusing the bulk of the code and only deviating where needed.
These new bits set or cleared here and there have been mostly found by
looking at DRAM register dumps after using the H5 boot0 and comparing
them to what we set in the code. So for now it's mostly unclear what
those bits actually mean - hence the missing names and comments.
Also add the delay line parameters taken from the boot0 and libdram
disassembly.


Can you split this patch with delay line params as separate patch.


Register setup differences between H5 and H3 are courtesy of Jens Kuske.

Signed-off-by: Andre Przywara 
Acked-by: Maxime Ripard 
---
 arch/arm/include/asm/arch-sunxi/cpu.h |  1 +
 arch/arm/mach-sunxi/dram_sun8i_h3.c   | 97 +-
-
 2 files changed, 82 insertions(+), 16 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 6f96a97..e8e670e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -15,5 +15,6 @@

 #define SOCID_A64  0x1689
 #define SOCID_H3   0x1680
+#define SOCID_H5   0x1718

 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_
sun8i_h3.c
index 9f7cc7f..d681a9d 100644
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void)
writel(0x8104, _com->mdfs_bwlr[2]);
 }

+static void mctl_set_master_priority_h5(void)
+{
+   struct sunxi_mctl_com_reg * const mctl_com =
+   (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+   /* enable bandwidth limit windows and set windows size 1us */
+   writel(399, _com->tmr);
+   writel((1 << 16), _com->bwcr);


I'm not fond of using direct numerical values make code unhealthy please
use macros with bitops. Note that this comment will apply rest of the code
where it applies.

+
+   /* set cpu high priority */
+   writel(0x0001, _com->mapr);
+
+   /* Port 2 is reserved per Allwinner's linux-3.10 source, yet
+* they initialise it */
+   MBUS_CONF(   CPU, true, HIGHEST, 0,  300,  260,  150);
+   MBUS_CONF(   GPU, true, HIGHEST, 0,  600,  400,  200);
+   MBUS_CONF(UNUSED, true, HIGHEST, 0,  512,  256,   96);
+   MBUS_CONF(   DMA, true, HIGHEST, 0,  256,  128,   32);
+   MBUS_CONF(VE, true, HIGHEST, 0, 1900, 1500, 1000);
+   MBUS_CONF(   CSI, true, HIGHEST, 0,  150,  120,  100);
+   MBUS_CONF(  NAND, true,HIGH, 0,  256,  128,   64);
+   MBUS_CONF(SS, true, HIGHEST, 0,  256,  128,   64);
+   MBUS_CONF(TS, true, HIGHEST, 0,  256,  128,   64);
+   MBUS_CONF(DI, true,HIGH, 0, 1024,  256,   64);
+   MBUS_CONF(DE, true, HIGHEST, 3, 3400, 2400, 1024);
+   MBUS_CONF(DE_CFD, true, HIGHEST, 0,  600,  400,  200);
+}
+
 static void mctl_set_master_priority(uint16_t socid)
 {
switch (socid) {
@@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid)
case SOCID_A64:
mctl_set_master_priority_a64();
return;
+   case SOCID_H5:
+   mctl_set_master_priority_h5();
+   return;
}
 }

@@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid,
struct dram_para *para)

/* set two rank timing */
clrsetbits_le32(_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
-   (0x66 << 8) | (0x10 << 0));
+   ((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 <<
0));

/* set PHY interface timing, write latency and read latency
configure */
writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
@@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct
dram_para *para)
CCM_DRAMCLK_CFG_DIV(1) |
CCM_DRAMCLK_CFG_SRC_PLL11 |
CCM_DRAMCLK_CFG_UPD);
-   } else if (socid == SOCID_H3) {
+   } else if (socid == SOCID_H3 || socid == SOCID_H5) {
clock_set_pll5(CONFIG_DRAM_CLK * 2 * 100, false);
clrsetbits_le32(>dram_clk_cfg,
CCM_DRAMCLK_CFG_DIV_MASK |
@@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct
dram_para *para)
setbits_le32(>dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
udelay(10);

-   writel(0xc00e, _ctl->clken);
+   writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, _ctl->clken);
udelay(500);
 }

@@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)

/* setting VTC, default 

[linux-sunxi] Re: [U-Boot] [PATCH v3 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

[Andre Przywara]

Hi Jagan,

thanks for the review!

On 03/02/17 11:04, Jagan Teki wrote:
> On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
>> Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
>> while the first SRAM region is mapped at address 0.
>> With the extended physical memory support of the A80 this was changed,
>> so the BROM is now at address 0 and the SRAM region starts right behind
>> this at 64KB. This configuration seems to be called "high SRAM".
>> Instead of enumerating the SoCs which have copied this configuration,
>> let's call a spade a spade and introduce a Kconfig option for this setup.
>> SoCs implementing this (A80, A64 and H5, so far), can then select this
>> configuration.
>> Simplify the config header definition on the way.
>>
>> Signed-off-by: Andre Przywara 
>> Acked-by: Maxime Ripard 
>> ---
>>  arch/arm/include/asm/arch-sunxi/spl.h |  2 +-
>>  board/sunxi/Kconfig   |  6 ++
>>  include/configs/sunxi-common.h| 19 +++
>>  3 files changed, 14 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
>> b/arch/arm/include/asm/arch-sunxi/spl.h
>> index 5d7ab55..831d0c0 100644
>> --- a/arch/arm/include/asm/arch-sunxi/spl.h
>> +++ b/arch/arm/include/asm/arch-sunxi/spl.h
>> @@ -12,7 +12,7 @@
>>  #define SPL_SIGNATURE  "SPL" /* marks "sunxi" SPL header */
>>  #define SPL_HEADER_VERSION 1
>>
>> -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
>> +#ifdef CONFIG_SUNXI_HIGH_SRAM
>>  #define SPL_ADDR   0x1
>>  #else
>>  #define SPL_ADDR   0x0
>> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
>> index ea0d658..688cb12 100644
>> --- a/board/sunxi/Kconfig
>> +++ b/board/sunxi/Kconfig
>> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
>>  config SPL_SERIAL_SUPPORT
>> default y
>>
>> +config SUNXI_HIGH_SRAM
>> +   bool
>> +   default n
> 
> Write some help text, once written

I wanted originally, but then saw that none of the invisible options (no
text after bool) have a help text, mainly because it will probably never
be shown.
I can still add some help text here for documentation purposes, or in
some other place. Or leave it up for the commit message to cover that.

Cheers,
Andre.

> 
> Reviewed-by: Jagan Teki 
> 
> thanks!
> 

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[linux-sunxi] Applied "ASoC: sun8i-codec-analog: Add amplifier event to fix first delay" to the asoc tree

[Mark Brown]

The patch

   ASoC: sun8i-codec-analog: Add amplifier event to fix first delay

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From bf14da7e55169964a1e6f35dc9d7428dc9e9013c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?=
 
Date: Thu, 2 Feb 2017 10:24:18 +0100
Subject: [PATCH] ASoC: sun8i-codec-analog: Add amplifier event to fix first
 delay
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

When playing a sound for the first time, a short delay, where the audio
file is not played, can be noticed.
On a second play (right after), the sound is played correctly.
If we wait a short time (~5 sec which corresponds to the aplay
timeout), the delay is back.

This patch fixes it by using an event on headphone amplifier.
It allows to keep the amplifier enable while playing a sound.
A delay of 700ms allows to wait that the amplifier is powered-up
before playing the sound.

Signed-off-by: Mylène Josserand 
Acked-by: Maxime Ripard 
Signed-off-by: Mark Brown 
---
 sound/soc/sunxi/sun8i-codec-analog.c | 30 --
 1 file changed, 28 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun8i-codec-analog.c 
b/sound/soc/sunxi/sun8i-codec-analog.c
index af02290ebe49..72331332b72e 100644
--- a/sound/soc/sunxi/sun8i-codec-analog.c
+++ b/sound/soc/sunxi/sun8i-codec-analog.c
@@ -398,11 +398,37 @@ static const struct snd_kcontrol_new sun8i_codec_hp_src[] 
= {
  sun8i_codec_hp_src_enum),
 };
 
+static int sun8i_headphone_amp_event(struct snd_soc_dapm_widget *w,
+struct snd_kcontrol *k, int event)
+{
+   struct snd_soc_component *component = 
snd_soc_dapm_to_component(w->dapm);
+
+   if (SND_SOC_DAPM_EVENT_ON(event)) {
+   snd_soc_component_update_bits(component, 
SUN8I_ADDA_PAEN_HP_CTRL,
+ 
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
+ 
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN));
+   /*
+* Need a delay to have the amplifier up. 700ms seems the best
+* compromise between the time to let the amplifier up and the
+* time not to feel this delay while playing a sound.
+*/
+   msleep(700);
+   } else if (SND_SOC_DAPM_EVENT_OFF(event)) {
+   snd_soc_component_update_bits(component, 
SUN8I_ADDA_PAEN_HP_CTRL,
+ 
BIT(SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN),
+ 0x0);
+   }
+
+   return 0;
+}
+
 static const struct snd_soc_dapm_widget sun8i_codec_headphone_widgets[] = {
SND_SOC_DAPM_MUX("Headphone Source Playback Route",
 SND_SOC_NOPM, 0, 0, sun8i_codec_hp_src),
-   SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN8I_ADDA_PAEN_HP_CTRL,
-SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN, 0, NULL, 0),
+   SND_SOC_DAPM_OUT_DRV_E("Headphone Amp", SUN8I_ADDA_PAEN_HP_CTRL,
+  SUN8I_ADDA_PAEN_HP_CTRL_HPPAEN, 0, NULL, 0,
+  sun8i_headphone_amp_event,
+  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN8I_ADDA_PAEN_HP_CTRL,
SUN8I_ADDA_PAEN_HP_CTRL_COMPTEN, 0, NULL, 0),
SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN8I_ADDA_PAEN_HP_CTRL,
-- 
2.11.0

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[linux-sunxi] Re: [U-Boot] [PATCH v3 12/13] sunxi: dts: add basic OrangePi PC 2 device tree file

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi
> and changing the differing components accordingly.
> This is a preliminary device tree mostly for U-Boot's own sake, it
> is expected to be updated once the official DT gets accepted upstream.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/dts/Makefile   |   2 +
>  arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 147 
> 

Please squash 13/13 with this, I would see a single patch for initial support.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 08/13] SPI: SPL: sunxi: fix 64-bit build

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> Addresses passed on to readl and writel are expected to be of the same
> size as a pointer. Change the parameter types of sunxi_spi0_read_data()
> to make the compiler happy and allow a warning-free aarch64 compile.
>
> Signed-off-by: Andre Przywara 
> Reviewed-by: Simon Glass 
> Reviewed-by: Maxime Ripard 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 07/13] sunxi: provide ARMv8 mem_map for every ARM64 board

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> Every armv8 board needs the memory map, so change the #ifdef to
> ARM64 to avoid enumerating every single board or SoC.
>
> Signed-off-by: Andre Przywara 
> Acked-by: Maxime Ripard 
> ---
>  arch/arm/mach-sunxi/board.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 06/13] sunxi: Kconfig: introduce CONFIG_SUNXI_HIGH_SRAM

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> Traditionally Allwinner SoCs have their boot ROM mapped just below 4GB,
> while the first SRAM region is mapped at address 0.
> With the extended physical memory support of the A80 this was changed,
> so the BROM is now at address 0 and the SRAM region starts right behind
> this at 64KB. This configuration seems to be called "high SRAM".
> Instead of enumerating the SoCs which have copied this configuration,
> let's call a spade a spade and introduce a Kconfig option for this setup.
> SoCs implementing this (A80, A64 and H5, so far), can then select this
> configuration.
> Simplify the config header definition on the way.
>
> Signed-off-by: Andre Przywara 
> Acked-by: Maxime Ripard 
> ---
>  arch/arm/include/asm/arch-sunxi/spl.h |  2 +-
>  board/sunxi/Kconfig   |  6 ++
>  include/configs/sunxi-common.h| 19 +++
>  3 files changed, 14 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/spl.h 
> b/arch/arm/include/asm/arch-sunxi/spl.h
> index 5d7ab55..831d0c0 100644
> --- a/arch/arm/include/asm/arch-sunxi/spl.h
> +++ b/arch/arm/include/asm/arch-sunxi/spl.h
> @@ -12,7 +12,7 @@
>  #define SPL_SIGNATURE  "SPL" /* marks "sunxi" SPL header */
>  #define SPL_HEADER_VERSION 1
>
> -#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
> +#ifdef CONFIG_SUNXI_HIGH_SRAM
>  #define SPL_ADDR   0x1
>  #else
>  #define SPL_ADDR   0x0
> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
> index ea0d658..688cb12 100644
> --- a/board/sunxi/Kconfig
> +++ b/board/sunxi/Kconfig
> @@ -27,6 +27,10 @@ config SPL_POWER_SUPPORT
>  config SPL_SERIAL_SUPPORT
> default y
>
> +config SUNXI_HIGH_SRAM
> +   bool
> +   default n

Write some help text, once written

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 05/13] sunxi: configs: merge sun9i and sun50i SPL memory definitions

[Jagan Teki]

On Thu, Feb 2, 2017 at 1:25 PM, Maxime Ripard
 wrote:
> On Wed, Feb 01, 2017 at 01:36:02AM +, Andre Przywara wrote:
>> For some reason we were pretty conservative when defining the maximum
>> SPL size for the Allwinner A80(sun9i) SoC.
>> According to the manual the SRAM A1 is even 40KB, but the BROM
>> probably still has the 32 KiB load limit. For the sake of simplicity,
>> merge the SPL memory definitions for the A64 and A80 SoCs, since both
>> SoC share the BROM/SRAM A1 memory layout.
>> This helps to further simplify this is in the next patch.
>>
>> Signed-off-by: Andre Przywara 
>
> Acked-by: Maxime Ripard 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 04/13] sunxi: simplify ACTLR.SMP bit set #ifdef

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> Instead of enumerating all SoC families that need that bit set, let's
> just express this more clearly: The SMP bits needs to be set on
> SMP capable ARMv7 CPUs. It's much easier in Kconfig to express it the
> other way round, so we use ! CPU_IS_UP and ! ARM64.
>
> Signed-off-by: Andre Przywara 
> Acked-by: Maxime Ripard 
> ---
>  arch/arm/Kconfig| 4 
>  arch/arm/mach-sunxi/board.c | 5 +
>  board/sunxi/Kconfig | 2 ++
>  3 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index fc36723..98791c0 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -126,6 +126,10 @@ config ENABLE_ARM_SOC_BOOT0_HOOK
>   ARM_SOC_BOOT0_HOOK which contains the required assembler
>   preprocessor code.
>
> +config ARM_CORTEX_CPU_IS_UP
> +   bool
> +   default n

Better to place this in sunxi, since no other code using this expect
sunxi and the name CORTEX may also refer arm64 use something 32
related.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] Re: [U-Boot] [PATCH v3 03/13] fsl: ls102x: remove redundant GENERIC_TIMER_CLK

[Jagan Teki]

On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara  wrote:
> Some Freescale boards used an extra version of the constant to hold the
> Generic Timer frequency. This can easily be covered by the now unified
> COUNTER_FREQUENCY constant, so remove this extra variable from those
> boards.
>
> Signed-off-by: Andre Przywara 
> Reviewed-by: York Sun 

Reviewed-by: Jagan Teki 

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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