[linux-sunxi] Re: [PATCH v3 08/10] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)
On Sun, Jan 29, 2017 at 10:33:29AM +0800, Icenowy Zheng wrote: > As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA > driver should be allowed to be built for ARM64, in order to make it work on > H5. Applied, thanks -- ~Vinod -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: Sunxi FOSDEM dinner, sat 4 Feb @ 8PM
What time this will start? On Sat, Feb 4, 2017 at 3:18 PM, Benjamin Henrion wrote: > No problems, still 5 seats left. > > On Feb 4, 2017 14:14, "Mihai Bujanca" wrote: >> >> Looks like we can't stay long after all. We might be able to drop by and >> say hi, but please cancel the two seats for me. >> >> Mihai >> >> On Tuesday, 10 January 2017 16:01:38 UTC, Benjamin Henrion wrote: >>> >>> Hi, >>> >>> Like previous years, I have booked the Amadeo restaurant for the Sunxi >>> FOSDEM dinner: >>> >>> http://amadeus-resto.be/en/amadeo-brussel/ >>> >>> Please reply to this mail so that I can book a place for you. >>> >>> We will leave FOSDEM around 7PM at the O'Reilly booth, if you are >>> bored the last hour I will be speaking at 6PM: >>> >>> https://fosdem.org/2017/schedule/event/pieter_hintjens/ >>> >>> Best, >>> >>> -- >>> Benjamin Henrion >>> FFII Brussels - +32-484-566109 - +32-2-3500762 >>> "In July 2005, after several failed attempts to legalise software >>> patents in Europe, the patent establishment changed its strategy. >>> Instead of explicitly seeking to sanction the patentability of >>> software, they are now seeking to create a central European patent >>> court, which would establish and enforce patentability rules in their >>> favor, without any possibility of correction by competing courts or >>> democratically elected legislators." > > -- > You received this message because you are subscribed to a topic in the > Google Groups "linux-sunxi" group. > To unsubscribe from this topic, visit > https://groups.google.com/d/topic/linux-sunxi/afFMBIR2m_o/unsubscribe. > To unsubscribe from this group and all its topics, send an email to > linux-sunxi+unsubscr...@googlegroups.com. > For more options, visit https://groups.google.com/d/optout. -- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH] Add the Allwinner A31/A31s PWM driver.
From: Siarhei Volkau
A31 SoC have a different map of PWM registers than others Allwinner
SoCs, so the operation of access to the registers reworked for all
existing in driver SoCs.
Tested on Onda V972 (a31) and Marsboard A20, but only PWM
channel 0, because other channels pins are not routed or
have another function on these boards.
Signed-off-by: Siarhei Volkau
---
arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++
drivers/pwm/pwm-sun4i.c | 195 +--
2 files changed, 175 insertions(+), 28 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ee1eb6d..fcba129 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -627,6 +627,14 @@
status = "disabled";
};
+ pwm: pwm@01c21400 {
+ compatible = "allwinner,sun6i-a31-pwm";
+ reg = <0x01c21400 0x400>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lradc: lradc@01c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x100>;
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index b0803f6..bd049c3 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -34,6 +34,7 @@
#define PWM_MODE BIT(7)
#define PWM_PULSE BIT(8)
#define PWM_BYPASS BIT(9)
+#define PWM_CHCTL_MASK GENMASK(9, 0)
#define PWM_RDY_BASE 28
#define PWM_RDY_OFFSET 1
@@ -46,7 +47,13 @@
#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
-static const u32 prescaler_table[] = {
+#define SUN6I_PWM_RDY_BIT PWM_RDY_BASE
+#define SUN6I_PWM_CTL_OFFS 0x0
+#define SUN6I_PWM_PRD_OFFS 0x4
+#define SUN6I_PWM_CH_CTL(ch) (0x10 * (ch) + SUN6I_PWM_CTL_OFFS)
+#define SUN6I_PWM_CH_PRD(ch) (0x10 * (ch) + SUN6I_PWM_PRD_OFFS)
+
+static const u32 sun4i_prescaler_table[] = {
120,
180,
240,
@@ -65,10 +72,41 @@ static const u32 prescaler_table[] = {
0, /* Actually 1 but tested separately */
};
+static const u32 sun6i_prescaler_table[] = {
+ 1,
+ 2,
+ 4,
+ 8,
+ 16,
+ 32,
+ 64,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+};
+
+struct sun4i_pwm_chip;
+
+struct sunxi_reg_ops {
+ int (*ctl_rdy)(struct sun4i_pwm_chip *chip, int npwm);
+ u32 (*ctl_read)(struct sun4i_pwm_chip *chip, int npwm);
+ void (*ctl_write)(struct sun4i_pwm_chip *chip, int npwm, u32 val);
+ u32 (*prd_read)(struct sun4i_pwm_chip *chip, int npwm);
+ void (*prd_write)(struct sun4i_pwm_chip *chip, int npwm, u32 val);
+};
+
struct sun4i_pwm_data {
bool has_prescaler_bypass;
bool has_rdy;
unsigned int npwm;
+ const u32 *prescaler_table;
+ struct sunxi_reg_ops *ops;
};
struct sun4i_pwm_chip {
@@ -96,10 +134,71 @@ static inline void sun4i_pwm_writel(struct sun4i_pwm_chip
*chip,
writel(val, chip->base + offset);
}
+static int sun4i_reg_ctl_rdy(struct sun4i_pwm_chip *chip, int npwm)
+{
+ return PWM_RDY(npwm) & sun4i_pwm_readl(chip, PWM_CTRL_REG);
+}
+
+static int sun6i_reg_ctl_rdy(struct sun4i_pwm_chip *chip, int npwm)
+{
+ u32 val = sun4i_pwm_readl(chip, SUN6I_PWM_CH_CTL(npwm));
+
+ return val & BIT(SUN6I_PWM_RDY_BIT);
+}
+
+static u32 sun4i_reg_ctl_read(struct sun4i_pwm_chip *chip, int npwm)
+{
+ u32 val = sun4i_pwm_readl(chip, PWM_CTRL_REG);
+
+ return val >> (PWMCH_OFFSET * (npwm));
+}
+
+static u32 sun6i_reg_ctl_read(struct sun4i_pwm_chip *chip, int npwm)
+{
+ return sun4i_pwm_readl(chip, SUN6I_PWM_CH_CTL(npwm));
+}
+
+static void sun4i_reg_ctl_write(struct sun4i_pwm_chip *chip, int npwm, u32 val)
+{
+ u32 rd = sun4i_pwm_readl(chip, PWM_CTRL_REG);
+
+ rd &= ~(PWM_CHCTL_MASK << (PWMCH_OFFSET * npwm));
+ val &= (PWM_CHCTL_MASK << (PWMCH_OFFSET * npwm));
+ sun4i_pwm_writel(chip, rd | val, PWM_CTRL_REG);
+}
+
+static void sun6i_reg_ctl_write(struct sun4i_pwm_chip *chip, int npwm, u32 val)
+{
+ return sun4i_pwm_writel(chip, val, SUN6I_PWM_CH_CTL(npwm));
+}
+
+static u32 sun4i_reg_prd_read(struct sun4i_pwm_chip *chip, int npwm)
+{
+ return sun4i_pwm_readl(chip, PWM_CH_PRD(npwm));
+}
+
+static u32 sun6i_reg_prd_read(struct sun4i_pwm_chip *chip, int npwm)
+{
+ return sun4i_pwm_readl(chip, SUN6I_PWM_CH_PRD(npwm));
+}
+
+static void sun4i_reg_prd_write(struct sun4i_pwm_chip *chip, int npwm, u32 val)
+{
+ sun4i_pwm_writel(chip, val, PWM_CH_PRD(npwm));
+}
+
+static void sun6i_reg_prd_write(struct sun4i_pwm_chip *chip, int npwm, u32 val)
+{
+ return sun4i_pwm_writel(chip, val, SUN6I_PWM_CH_PRD(npwm));
+}
+
static int sun4i_pwm_config(struct pwm_chi
[linux-sunxi] Re: Sunxi FOSDEM dinner, sat 4 Feb @ 8PM
No problems, still 5 seats left. On Feb 4, 2017 14:14, "Mihai Bujanca" wrote: > Looks like we can't stay long after all. We might be able to drop by and > say hi, but please cancel the two seats for me. > > Mihai > > On Tuesday, 10 January 2017 16:01:38 UTC, Benjamin Henrion wrote: >> >> Hi, >> >> Like previous years, I have booked the Amadeo restaurant for the Sunxi >> FOSDEM dinner: >> >> http://amadeus-resto.be/en/amadeo-brussel/ >> >> Please reply to this mail so that I can book a place for you. >> >> We will leave FOSDEM around 7PM at the O'Reilly booth, if you are >> bored the last hour I will be speaking at 6PM: >> >> https://fosdem.org/2017/schedule/event/pieter_hintjens/ >> >> Best, >> >> -- >> Benjamin Henrion >> FFII Brussels - +32-484-566109 <+32%20484%2056%2061%2009> - +32-2-3500762 >> <+32%202%20350%2007%2062> >> "In July 2005, after several failed attempts to legalise software >> patents in Europe, the patent establishment changed its strategy. >> Instead of explicitly seeking to sanction the patentability of >> software, they are now seeking to create a central European patent >> court, which would establish and enforce patentability rules in their >> favor, without any possibility of correction by competing courts or >> democratically elected legislators." >> > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: Sunxi FOSDEM dinner, sat 4 Feb @ 8PM
Looks like we can't stay long after all. We might be able to drop by and say hi, but please cancel the two seats for me. Mihai On Tuesday, 10 January 2017 16:01:38 UTC, Benjamin Henrion wrote: > > Hi, > > Like previous years, I have booked the Amadeo restaurant for the Sunxi > FOSDEM dinner: > > http://amadeus-resto.be/en/amadeo-brussel/ > > Please reply to this mail so that I can book a place for you. > > We will leave FOSDEM around 7PM at the O'Reilly booth, if you are > bored the last hour I will be speaking at 6PM: > > https://fosdem.org/2017/schedule/event/pieter_hintjens/ > > Best, > > -- > Benjamin Henrion > FFII Brussels - +32-484-566109 - +32-2-3500762 > "In July 2005, after several failed attempts to legalise software > patents in Europe, the patent establishment changed its strategy. > Instead of explicitly seeking to sanction the patentability of > software, they are now seeking to create a central European patent > court, which would establish and enforce patentability rules in their > favor, without any possibility of correction by competing courts or > democratically elected legislators." > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
