[linux-sunxi] Re: [PATCH v2 08/11] iio: adc: sun4i-gpadc-iio: add support for A33 thermal sensor

2017-03-13 Thread Icenowy Zheng 


14.03.2017, 05:08, "Jonathan Cameron" :
> On 10/03/17 10:39, Quentin Schulz wrote:
>>  This adds support for the Allwinner A33 thermal sensor.
>>
>>  Unlike the A10, A13 and A31, the Allwinner A33 only has one channel
>>  which is dedicated to the thermal sensor. Moreover, its thermal sensor
>>  does not generate interruptions, thus we only need to directly read the
>>  register storing the temperature value.
>>
>>  The MFD used by the A10, A13 and A31, was created to avoid breaking the
>>  DT binding, but since the nodes for the ADC weren't there for the A33,
>>  it is not needed.
>>
>>  Signed-off-by: Quentin Schulz 
>
> Talk me through why it makes sense to do this rather than simply spin out
> a really simple thermal driver for the A33?

According to him the A33 thermal sensor is a simplified version of the GPADC.

I have already did a simple thermal driver ~8 months ago, but is rejected for
this reason.

>
> I'm not against what you have here, but don't feel it has been fully argued.
>
> Jonathan
>>  ---
>>
>>  v2:
>>    - removed added comments in Kconfig,
>>    - simplified Kconfig depends on condition,
>>    - removed THERMAL_OF requirement for sun8i,
>>    - renamed sun8i_gpadc_channels to sun8i_a33_gpadc_channels,
>>    - renamed use_dt boolean in no_irq as it reflects better why we need it,
>>    - removed spurious/unneeded modifications done in v1,
>>
>>   drivers/iio/adc/Kconfig | 2 +-
>>   drivers/iio/adc/sun4i-gpadc-iio.c | 100 
>> --
>>   include/linux/mfd/sun4i-gpadc.h | 4 ++
>>   3 files changed, 102 insertions(+), 4 deletions(-)
>>
>>  diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>  index 9f8b4b1..8c8ead6 100644
>>  --- a/drivers/iio/adc/Kconfig
>>  +++ b/drivers/iio/adc/Kconfig
>>  @@ -562,7 +562,7 @@ config STX104
>>   config SUN4I_GPADC
>>   tristate "Support for the Allwinner SoCs GPADC"
>>   depends on IIO
>>  - depends on MFD_SUN4I_GPADC
>>  + depends on MFD_SUN4I_GPADC || MACH_SUN8I
>>   help
>> Say yes here to build support for Allwinner (A10, A13 and A31) 
>> SoCs
>> GPADC. This ADC provides 4 channels which can be used as an ADC 
>> or as
>>  diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
>> b/drivers/iio/adc/sun4i-gpadc-iio.c
>>  index 7cb997a..70684cd 100644
>>  --- a/drivers/iio/adc/sun4i-gpadc-iio.c
>>  +++ b/drivers/iio/adc/sun4i-gpadc-iio.c
>>  @@ -85,6 +85,12 @@ static const struct gpadc_data sun6i_gpadc_data = {
>>   .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
>>   };
>>
>>  +static const struct gpadc_data sun8i_a33_gpadc_data = {
>>  + .temp_offset = -1662,
>>  + .temp_scale = 162,
>>  + .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
>>  +};
>>  +
>>   struct sun4i_gpadc_iio {
>>   struct iio_dev *indio_dev;
>>   struct completion completion;
>>  @@ -96,6 +102,7 @@ struct sun4i_gpadc_iio {
>>   unsigned int temp_data_irq;
>>   atomic_t ignore_temp_data_irq;
>>   const struct gpadc_data *data;
>>  + bool no_irq;
>>   /* prevents concurrent reads of temperature and ADC */
>>   struct mutex mutex;
>>   };
>>  @@ -138,6 +145,23 @@ static const struct iio_chan_spec 
>> sun4i_gpadc_channels_no_temp[] = {
>>   SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
>>   };
>>
>>  +static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
>>  + {
>>  + .type = IIO_TEMP,
>>  + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
>>  + BIT(IIO_CHAN_INFO_SCALE) |
>>  + BIT(IIO_CHAN_INFO_OFFSET),
>>  + .datasheet_name = "temp_adc",
>>  + },
>>  +};
>>  +
>>  +static const struct regmap_config sun4i_gpadc_regmap_config = {
>>  + .reg_bits = 32,
>>  + .val_bits = 32,
>>  + .reg_stride = 4,
>>  + .fast_io = true,
>>  +};
>>  +
>>   static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
>>    unsigned int irq)
>>   {
>>  @@ -247,6 +271,17 @@ static int sun4i_gpadc_temp_read(struct iio_dev 
>> *indio_dev, int *val)
>>   {
>>   struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
>>
>>  + if (info->no_irq) {
>>  + pm_runtime_get_sync(indio_dev->dev.parent);
>>  +
>>  + regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
>>  +
>>  + pm_runtime_mark_last_busy(indio_dev->dev.parent);
>>  + pm_runtime_put_autosuspend(indio_dev->dev.parent);
>>  +
>>  + return 0;
>>  + }
>>  +
>>   return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq);
>>   }
>>
>>  @@ -454,6 +489,58 @@ static int sun4i_irq_init(struct platform_device 
>> *pdev, const char *name,
>>   return 0;
>>   }
>>
>>  +static const struct of_device_id sun4i_gpadc_of_id[] = {
>>  + {
>>  + .compatible = "allwinner,sun8i-a33-gpadc-iio",
>>  + .data = _a33_gpadc_data,
>>  + },
>>  + { /* sentinel */ }
>>  +};
>>  +
>>  +static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
>>  + struct iio_dev *indio_dev)
>>  +{
>>  + struct

[linux-sunxi] [PATCH 6/6] sunxi: enable dual rank detection in DesignWare-like DRAM code

2017-03-13 Thread Icenowy Zheng 
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).

Signed-off-by: Icenowy Zheng 
---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 3629d34f71..e1ea6845df 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -543,7 +543,7 @@ unsigned long sunxi_dram_init(void)
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 
struct dram_para para = {
-   .dual_rank = 0,
+   .dual_rank = 1,
.bus_full_width = 1,
.row_bits = 15,
.bank_bits = 3,
-- 
2.12.0

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[linux-sunxi] [PATCH 5/6] sunxi: Add selective DRAM type and timing

2017-03-13 Thread Icenowy Zheng 
DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h |  30 ++
 arch/arm/mach-sunxi/Makefile|   1 +
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 116 ++--
 arch/arm/mach-sunxi/dram_timings/Makefile   |   1 +
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c|  84 +
 board/sunxi/Kconfig |  18 
 6 files changed, 140 insertions(+), 110 deletions(-)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h 
b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index 48bd6f7c0f..61da150c14 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -191,4 +191,34 @@ struct sunxi_mctl_ctl_reg {
 #define DXBDLR_WRITE_DELAY(x)  ((x) << 8)
 #define DXBDLR_READ_DELAY(x)   ((x) << 0)
 
+/*
+ * The delay parameters below allow to allegedly specify delay times of some
+ * unknown unit for each individual bit trace in each of the four data bytes
+ * the 32-bit wide access consists of. Also three control signals can be
+ * adjusted individually.
+ */
+#define BITS_PER_BYTE  8
+#define NR_OF_BYTE_LANES   (32 / BITS_PER_BYTE)
+/* The eight data lines (DQn) plus DM, DQS and DQSN */
+#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
+struct dram_para {
+   u16 page_size;
+   u8 bus_full_width;
+   u8 dual_rank;
+   u8 row_bits;
+   u8 bank_bits;
+   const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
+   const u8 ac_delays[31];
+};
+
+static inline int ns_to_t(int nanoseconds)
+{
+   const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
+
+   return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
+}
+
+void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
+
 #endif /* _SUNXI_DRAM_SUN8I_H3_H */
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index b8f01e3b61..e1b6fe8d5c 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MACH_SUN8I_A23)  += dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)   += dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += dram_sun8i_a83t.o
 obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_sunxi_dw.o
+obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_timings/
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index bb4457d2b8..3629d34f71 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -16,34 +16,6 @@
 #include 
 #include 
 
-/*
- * The delay parameters below allow to allegedly specify delay times of some
- * unknown unit for each individual bit trace in each of the four data bytes
- * the 32-bit wide access consists of. Also three control signals can be
- * adjusted individually.
- */
-#define BITS_PER_BYTE  8
-#define NR_OF_BYTE_LANES   (32 / BITS_PER_BYTE)
-/* The eight data lines (DQn) plus DM, DQS and DQSN */
-#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
-struct dram_para {
-   u16 page_size;
-   u8 bus_full_width;
-   u8 dual_rank;
-   u8 row_bits;
-   u8 bank_bits;
-   const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
-   const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
-   const u8 ac_delays[31];
-};
-
-static inline int ns_to_t(int nanoseconds)
-{
-   const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
-
-   return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
-}
-
 static void mctl_phy_init(u32 val)
 {
struct sunxi_mctl_ctl_reg * const mctl_ctl =
@@ -190,87 +162,6 @@ static void mctl_set_master_priority(uint16_t socid)
}
 }
 
-static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
-{
-   struct sunxi_mctl_ctl_reg * const mctl_ctl =
-   (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
-
-   u8 tccd = 2;
-   u8 tfaw = ns_to_t(50);
-   u8 trrd = max(ns_to_t(10), 4);
-   u8 trcd = ns_to_t(15);
-   u8 trc  = ns_to_t(53);
-   u8 txp  = max(ns_to_t(8), 3);
-   u8 twtr = max(ns_to_t(8), 4);
-   u8 trtp = max(ns_to_t(8), 4);
-   u8 twr  = max(ns_to_t(15), 3);
-   u8 trp  = ns_to_t(15);
-   u8 tras = ns_to_t(38);
-   u16 trefi   = ns_to_t(7800) / 32;
-   u16 trfc= ns_to_t(350);
-
-   u8 tmrw = 0;
-   u8 tmrd = 4;
-

[linux-sunxi] [PATCH 4/6] sunxi: add bank detection code to H3 DRAM initialization code

2017-03-13 Thread Icenowy Zheng 
Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index b08998c0d1..bb4457d2b8 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -31,6 +31,7 @@ struct dram_para {
u8 bus_full_width;
u8 dual_rank;
u8 row_bits;
+   u8 bank_bits;
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 ac_delays[31];
@@ -367,7 +368,7 @@ static void mctl_set_cr(struct dram_para *para)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
-  MCTL_CR_EIGHT_BANKS |
+  (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : 
MCTL_CR_FOUR_BANKS) |
   MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
   (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
   MCTL_CR_PAGE_SIZE(para->page_size) |
@@ -575,10 +576,19 @@ static void mctl_auto_detect_dram_size(struct dram_para 
*para)
/* detect row address bits */
para->page_size = 512;
para->row_bits = 16;
+   para->bank_bits = 2;
mctl_set_cr(para);
 
for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
-   if (mctl_mem_matches((1 << (para->row_bits + 3)) * 
para->page_size))
+   if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) 
* para->page_size))
+   break;
+
+   /* detect bank address bits */
+   para->bank_bits = 3;
+   mctl_set_cr(para);
+
+   for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
+   if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
break;
 
/* detect page size */
@@ -640,6 +650,7 @@ unsigned long sunxi_dram_init(void)
.dual_rank = 0,
.bus_full_width = 1,
.row_bits = 15,
+   .bank_bits = 3,
.page_size = 4096,
 
 #if defined(CONFIG_MACH_SUN8I_H3)
@@ -689,6 +700,6 @@ unsigned long sunxi_dram_init(void)
mctl_auto_detect_dram_size();
mctl_set_cr();
 
-   return (1UL << (para.row_bits + 3)) * para.page_size *
-   (para.dual_rank ? 2 : 1);
+   return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
+  (para.dual_rank ? 2 : 1);
 }
-- 
2.12.0

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[linux-sunxi] [PATCH 3/6] sunxi: add option for 16-bit DW DRAM controller

2017-03-13 Thread Icenowy Zheng 
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.

Add support for them.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 34 +-
 board/sunxi/Kconfig | 16 
 2 files changed, 45 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 0c73a43075..b08998c0d1 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -298,6 +298,13 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para 
*para)
 {
struct sunxi_mctl_ctl_reg * const mctl_ctl =
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+   int zq_count;
+
+#if defined CONFIG_SUNXI_DRAM_DW_16BIT
+   zq_count = 4;
+#else
+   zq_count = 6;
+#endif
 
if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
(readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
@@ -326,7 +333,7 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para 
*para)
 
writel(0x0a0a0a0a, _ctl->zqdr[2]);
 
-   for (i = 0; i < 6; i++) {
+   for (i = 0; i < zq_count; i++) {
u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
 
writel((zq << 20) | (zq << 16) | (zq << 12) |
@@ -348,7 +355,9 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para 
*para)
 
writel((zq_val[1] << 16) | zq_val[0], _ctl->zqdr[0]);
writel((zq_val[3] << 16) | zq_val[2], _ctl->zqdr[1]);
-   writel((zq_val[5] << 16) | zq_val[4], _ctl->zqdr[2]);
+   if (zq_count > 4)
+   writel((zq_val[5] << 16) | zq_val[4],
+  _ctl->zqdr[2]);
}
 }
 
@@ -473,8 +482,14 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
 
/* set half DQ */
if (!para->bus_full_width) {
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
writel(0x0, _ctl->dx[2].gcr);
writel(0x0, _ctl->dx[3].gcr);
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+   writel(0x0, _ctl->dx[1].gcr);
+#else
+#error Unsupported DRAM bus width!
+#endif
}
 
/* data training configuration */
@@ -499,20 +514,29 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
/* detect ranks and bus width */
if (readl(_ctl->pgsr[0]) & (0xfe << 20)) {
/* only one rank */
-   if (((readl(_ctl->dx[0].gsr[0]) >> 24) & 0x2) ||
-   ((readl(_ctl->dx[1].gsr[0]) >> 24) & 0x2)) {
+   if (((readl(_ctl->dx[0].gsr[0]) >> 24) & 0x2)
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
+   || ((readl(_ctl->dx[1].gsr[0]) >> 24) & 0x2)
+#endif
+   ) {
clrsetbits_le32(_ctl->dtcr, 0xf << 24, 0x1 << 24);
para->dual_rank = 0;
}
 
/* only half DQ width */
+#if defined CONFIG_SUNXI_DRAM_DW_32BIT
if (((readl(_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
((readl(_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
writel(0x0, _ctl->dx[2].gcr);
writel(0x0, _ctl->dx[3].gcr);
para->bus_full_width = 0;
}
-
+#elif defined CONFIG_SUNXI_DRAM_DW_16BIT
+   if ((readl(_ctl->dx[1].gsr[0]) >> 24) & 0x1) {
+   writel(0x0, _ctl->dx[1].gcr);
+   para->bus_full_width = 0;
+   }
+#endif
mctl_set_cr(para);
udelay(20);
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index e71fdaee86..d8a1e341e8 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -50,6 +50,20 @@ config SUNXI_DRAM_DW
not have official open-source DRAM initialization code, but can
use modified H3 DRAM initialization code.
 
+if SUNXI_DRAM_DW
+config SUNXI_DRAM_DW_16BIT
+   bool
+   ---help---
+   Select this for sunxi SoCs with DesignWare DRAM controller and
+   have only 16-bit memory buswidth.
+
+config SUNXI_DRAM_DW_32BIT
+   bool
+   ---help---
+   Select this for sunxi SoCs with DesignWare DRAM controller with
+   32-bit memory buswidth.
+endif
+
 choice
prompt "Sunxi SoC Variant"
optional
@@ -121,6 +135,7 @@ config MACH_SUN8I_H3
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SUNXI_DRAM_DW
+   select SUNXI_DRAM_DW_32BIT
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I_V3S
@@ -144,6 +159,7 @@ config MACH_SUN50I
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
select SUNXI_DRAM_DW
+   select SUNXI_DRAM_DW_32BIT
 
 endchoice
 
-- 
2.12.0

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[linux-sunxi] [PATCH 1/6] sunxi: makes an invisible option for H3-like DRAM controllers

2017-03-13 Thread Icenowy Zheng 
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng 
Acked-by: Maxime Ripard 
---
 arch/arm/include/asm/arch-sunxi/dram.h   | 4 ++--
 .../include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h}  | 0
 arch/arm/mach-sunxi/Makefile | 2 +-
 arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} | 0
 board/sunxi/Kconfig  | 9 +
 5 files changed, 12 insertions(+), 3 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} 
(100%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (100%)

diff --git a/arch/arm/include/asm/arch-sunxi/dram.h 
b/arch/arm/include/asm/arch-sunxi/dram.h
index 53e6d471d2..80abac95b8 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -24,8 +24,8 @@
 #include 
 #elif defined(CONFIG_MACH_SUN8I_A83T)
 #include 
-#elif defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
-#include 
+#elif defined(CONFIG_SUNXI_DRAM_DW)
+#include 
 #elif defined(CONFIG_MACH_SUN9I)
 #include 
 #else
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h 
b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
similarity index 100%
rename from arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h
rename to arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index 7daba1169c..b8f01e3b61 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -48,7 +48,7 @@ obj-$(CONFIG_MACH_SUN7I)  += dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I_A23)   += dram_sun8i_a23.o
 obj-$(CONFIG_MACH_SUN8I_A33)   += dram_sun8i_a33.o
 obj-$(CONFIG_MACH_SUN8I_A83T)  += dram_sun8i_a83t.o
-obj-$(CONFIG_MACH_SUN8I_H3)+= dram_sun8i_h3.o
+obj-$(CONFIG_SUNXI_DRAM_DW)+= dram_sunxi_dw.o
 obj-$(CONFIG_MACH_SUN9I)   += dram_sun9i.o
 obj-$(CONFIG_MACH_SUN50I)  += dram_sun8i_h3.o
 endif
diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
similarity index 100%
rename from arch/arm/mach-sunxi/dram_sun8i_h3.c
rename to arch/arm/mach-sunxi/dram_sunxi_dw.c
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 56b7513fe3..e71fdaee86 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -42,6 +42,13 @@ config SUNXI_GEN_SUN6I
separate ahb reset control registers, custom pmic bus, new style
watchdog, etc.
 
+config SUNXI_DRAM_DW
+   bool
+   ---help---
+   Select this for sunxi SoCs which uses a DRAM controller like the
+   DesignWare controller used in H3, mainly SoCs after H3, which do
+   not have official open-source DRAM initialization code, but can
+   use modified H3 DRAM initialization code.
 
 choice
prompt "Sunxi SoC Variant"
@@ -113,6 +120,7 @@ config MACH_SUN8I_H3
select ARCH_SUPPORT_PSCI
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select SUNXI_DRAM_DW
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
 config MACH_SUN8I_V3S
@@ -135,6 +143,7 @@ config MACH_SUN50I
select ARM64
select SUNXI_GEN_SUN6I
select SUPPORT_SPL
+   select SUNXI_DRAM_DW
 
 endchoice
 
-- 
2.12.0

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[linux-sunxi] [PATCH 2/6] sunxi: Rename bus-width related macros in H3 DRAM code

2017-03-13 Thread Icenowy Zheng 
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h |  6 +++---
 arch/arm/mach-sunxi/dram_sunxi_dw.c | 11 ++-
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h 
b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index 25d07d9863..48bd6f7c0f 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -52,9 +52,9 @@ struct sunxi_mctl_com_reg {
 #define MCTL_CR_SEQUENTIAL (0x1 << 15)
 #define MCTL_CR_INTERLEAVED(0x0 << 15)
 
-#define MCTL_CR_32BIT  (0x1 << 12)
-#define MCTL_CR_16BIT  (0x0 << 12)
-#define MCTL_CR_BUS_WIDTH(x)   ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT)
+#define MCTL_CR_FULL_WIDTH (0x1 << 12)
+#define MCTL_CR_HALF_WIDTH (0x0 << 12)
+#define MCTL_CR_BUS_FULL_WIDTH(x)  ((x) << 12)
 
 #define MCTL_CR_PAGE_SIZE(x)   ((fls(x) - 4) << 8)
 #define MCTL_CR_ROW_BITS(x)(((x) - 1) << 4)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c 
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 9f7cc7fd4c..0c73a43075 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -28,7 +28,7 @@
 #define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
 struct dram_para {
u16 page_size;
-   u8 bus_width;
+   u8 bus_full_width;
u8 dual_rank;
u8 row_bits;
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
@@ -358,7 +358,8 @@ static void mctl_set_cr(struct dram_para *para)
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
-  MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
+  MCTL_CR_EIGHT_BANKS |
+  MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
   (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
   MCTL_CR_PAGE_SIZE(para->page_size) |
   MCTL_CR_ROW_BITS(para->row_bits), _com->cr);
@@ -471,7 +472,7 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
}
 
/* set half DQ */
-   if (para->bus_width != 32) {
+   if (!para->bus_full_width) {
writel(0x0, _ctl->dx[2].gcr);
writel(0x0, _ctl->dx[3].gcr);
}
@@ -509,7 +510,7 @@ static int mctl_channel_init(uint16_t socid, struct 
dram_para *para)
((readl(_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
writel(0x0, _ctl->dx[2].gcr);
writel(0x0, _ctl->dx[3].gcr);
-   para->bus_width = 16;
+   para->bus_full_width = 0;
}
 
mctl_set_cr(para);
@@ -613,7 +614,7 @@ unsigned long sunxi_dram_init(void)
 
struct dram_para para = {
.dual_rank = 0,
-   .bus_width = 32,
+   .bus_full_width = 1,
.row_bits = 15,
.page_size = 4096,
 
-- 
2.12.0

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[linux-sunxi] [PATCH 0/6] Allwinner DesignWare-like DRAM controllers refactor

2017-03-13 Thread Icenowy Zheng 
Allwinner SoCs after H3 (including H3) seems to use similar DRAM
controllers, which seems to originate from DesignWare.

This patchset did a series of refactors on it, which makes it possible
to support more situations (Allwinner V3s' 16-bit controller and DDR2
DRAM, Pinebook early prototype's dual-rank DDR3, SoPine/Pinebook production
batch's dual-rank LPDDR3). For extra DRAM types (DDR2/LPDDR3) additional
patches are needed, but they are now much easier to write.

This patchset is only part of the original patchset by me which adds V3s
DRAM support. It's taken out because supporting LPDDR3 needs this patchset.
For V3s SPL support I will have another patchset, which depends on the
not-yet-merged V3s support w/o SPL patchset.

Icenowy Zheng (6):
  sunxi: makes an invisible option for H3-like DRAM controllers
  sunxi: Rename bus-width related macros in H3 DRAM code
  sunxi: add option for 16-bit DW DRAM controller
  sunxi: add bank detection code to H3 DRAM initialization code
  sunxi: Add selective DRAM type and timing
  sunxi: enable dual rank detection in DesignWare-like DRAM code

 arch/arm/include/asm/arch-sunxi/dram.h |   4 +-
 .../{dram_sun8i_h3.h => dram_sunxi_dw.h}   |  36 -
 arch/arm/mach-sunxi/Makefile   |   3 +-
 .../{dram_sun8i_h3.c => dram_sunxi_dw.c}   | 176 +++--
 arch/arm/mach-sunxi/dram_timings/Makefile  |   1 +
 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c   |  84 ++
 board/sunxi/Kconfig|  43 +
 7 files changed, 219 insertions(+), 128 deletions(-)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i_h3.h => dram_sunxi_dw.h} 
(85%)
 rename arch/arm/mach-sunxi/{dram_sun8i_h3.c => dram_sunxi_dw.c} (79%)
 create mode 100644 arch/arm/mach-sunxi/dram_timings/Makefile
 create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_1333.c

-- 
2.12.0

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[linux-sunxi] [PATCH v5 0/3] Allwinner V3s and Lichee Pi Zero support (w/o SPL)

2017-03-13 Thread Icenowy Zheng 
Allwinner V3s is a SoC with single-core Cortex-A7 and 64MiB DRAM co-packaged
in a eLQFP package, which is suitable for manual soldering.

This patchset adds basic support for it. SPL support is still missing, due
to some reworks on DRAM initialization code is needed.(the co-packaged DRAM
is DDR2, but the DRAM initialization code currently only support DDR3.)

Icenowy Zheng (3):
  sunxi: add basic V3s support
  sunxi: add DTSI file for V3s
  sunxi: add support for Lichee Pi Zero

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts  |  83 +
 arch/arm/dts/sun8i-v3s.dtsi   | 284 ++
 arch/arm/include/asm/arch-sunxi/gpio.h|   1 +
 arch/arm/mach-sunxi/board.c   |   4 +
 arch/arm/mach-sunxi/cpu_info.c|   2 +
 board/sunxi/Kconfig   |  15 +-
 board/sunxi/MAINTAINERS   |   5 +
 configs/LicheePi_Zero_defconfig   |  12 ++
 include/configs/sun8i.h   |   2 +
 include/configs/sunxi-common.h|  31 +++-
 include/dt-bindings/clock/sun8i-v3s-ccu.h | 107 +++
 include/dt-bindings/reset/sun8i-v3s-ccu.h |  78 
 13 files changed, 621 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
 create mode 100644 arch/arm/dts/sun8i-v3s.dtsi
 create mode 100644 configs/LicheePi_Zero_defconfig
 create mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h

-- 
2.12.0

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[linux-sunxi] [PATCH v5 2/3] sunxi: add DTSI file for V3s

2017-03-13 Thread Icenowy Zheng 
As we have now V3s support in board code, the V3s DTSI file should also
be added.

Add also some CCU include headers to satisfy the DTSI file.

Signed-off-by: Icenowy Zheng 
Acked-by: Maxime Ripard 
---
Changes in v4:
- Add Maxime's ACK.

 arch/arm/dts/sun8i-v3s.dtsi   | 284 ++
 include/dt-bindings/clock/sun8i-v3s-ccu.h | 107 +++
 include/dt-bindings/reset/sun8i-v3s-ccu.h |  78 
 3 files changed, 469 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-v3s.dtsi
 create mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h

diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
new file mode 100644
index 00..ebefc0fefe
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -0,0 +1,284 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   clocks = < CLK_CPU>;
+   };
+   };
+
+   timer {
+   compatible = "arm,armv7-timer";
+   interrupts = ,
+,
+,
+;
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+   };
+
+   soc {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   mmc0: mmc@01c0f000 {
+   compatible = "allwinner,sun7i-a20-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = < CLK_BUS_MMC0>,
+< CLK_MMC0>,
+< CLK_MMC0_OUTPUT>,
+< CLK_MMC0_SAMPLE>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = < RST_BUS_MMC0>;
+

[linux-sunxi] [PATCH v5 3/3] sunxi: add support for Lichee Pi Zero

2017-03-13 Thread Icenowy Zheng 
Lichee Pi Zero is a development board with a V3s SoC, which features
64MiB DRAM co-packaged within the SoC, a TF slot, a SPI NOR slot (not
soldered in production batch), a 40-pin RGB LCD connector and some extra
pins available as 2.54mm pins or stamp holes.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v4:
- Removed NONSEC disabling for Lichee Pi Zero board.
- Enriched commit message.

 arch/arm/dts/Makefile|  2 +
 arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 83 
 board/sunxi/MAINTAINERS  |  5 ++
 configs/LicheePi_Zero_defconfig  | 12 +
 4 files changed, 102 insertions(+)
 create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero.dts
 create mode 100644 configs/LicheePi_Zero_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index eb68c204bb..83df114dd8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-nanopi-neo.dtb
+dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+   sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts 
b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
new file mode 100644
index 00..3d9168cbae
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-v3s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+   model = "Lichee Pi Zero";
+   compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
+
+   aliases {
+   serial0 = 
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   broken-cd;
+   bus-width = <4>;
+   vmmc-supply = <_vcc3v3>;
+   status = "okay";
+};
+
+ {
+   pinctrl-0 = <_pins_a>;
+   pinctrl-names = "default";
+   status = "okay";
+};
+
+_otg {
+   dr_mode = "otg";
+   status = "okay";
+};
+
+ {
+   usb0_id_det-gpio = < 5 6 GPIO_ACTIVE_HIGH>;
+   status = "okay";
+};
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 2321b8b08f..640c26328a 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -182,6 +182,11 @@ M: Jelle de Jong 
 S: Maintained
 F: configs/Lamobo_R1_defconfig
 
+LICHEEPI-ZERO BOARD
+M: Icenowy Zheng 
+S: Maintained
+F: configs/LicheePi_Zero_defconfig
+
 LINKSPRITE-PCDUINO BOARD
 M: Zoltan Herpai 
 S: Maintained
diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig
new file mode 100644
index 00..c147084849
--- /dev/null
+++ b/configs/LicheePi_Zero_defconfig
@@ -0,0 +1,12

[linux-sunxi] [PATCH v5 1/3] sunxi: add basic V3s support

2017-03-13 Thread Icenowy Zheng 
Basic U-Boot support is now present for V3s.

Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.

As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.

Signed-off-by: Icenowy Zheng 
Acked-by: Maxime Ripard 
Reviewed-by: Jagan Teki 
---
Changes in v5:
- Fixed a regression issue on AArch64 sunxi build.
Changes in v4:
- Enable PSCI for the SoC. (For virtualization support, although it
  seems to be a joke to use virtualization on systems with 64MiB DRAM)
- Add Maxime's ACK and Jagan's Reviewed-By.

Changes in v3:
- Remove some dead codes.

 arch/arm/include/asm/arch-sunxi/gpio.h |  1 +
 arch/arm/mach-sunxi/board.c|  4 
 arch/arm/mach-sunxi/cpu_info.c |  2 ++
 board/sunxi/Kconfig| 15 +--
 include/configs/sun8i.h|  2 ++
 include/configs/sunxi-common.h | 31 ---
 6 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 85a4ec3b0e..24f85206c8 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -161,6 +161,7 @@ enum sunxi_gpio_number {
 #define SUN8I_GPB_UART22
 #define SUN8I_A33_GPB_UART03
 #define SUN8I_A83T_GPB_UART0   2
+#define SUN8I_V3S_GPB_UART03
 #define SUN50I_GPB_UART0   4
 
 #define SUNXI_GPC_NAND 2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 52be5b0551..90b3b94e51 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -110,6 +110,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
+   sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
+   sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index f1f6fd5ba4..15f1e0e45a 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -87,6 +87,8 @@ int print_cpuinfo(void)
printf("CPU:   Allwinner A83T (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN8I_H3
printf("CPU:   Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
+#elif defined CONFIG_MACH_SUN8I_V3S
+   printf("CPU:   Allwinner V3s (SUN8I %04x)\n", sunxi_get_sram_id());
 #elif defined CONFIG_MACH_SUN9I
puts("CPU:   Allwinner A80 (SUN9I)\n");
 #elif defined CONFIG_MACH_SUN50I
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 37b42521a4..56b7513fe3 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -115,6 +115,15 @@ config MACH_SUN8I_H3
select SUPPORT_SPL
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
+config MACH_SUN8I_V3S
+   bool "sun8i (Allwinner V3s)"
+   select CPU_V7
+   select CPU_V7_HAS_NONSEC
+   select CPU_V7_HAS_VIRT
+   select ARCH_SUPPORT_PSCI
+   select SUNXI_GEN_SUN6I
+   select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
+
 config MACH_SUN9I
bool "sun9i (Allwinner A80)"
select CPU_V7
@@ -132,7 +141,8 @@ endchoice
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 config MACH_SUN8I
bool
-   default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || 
MACH_SUN8I_A83T
+   default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || \
+   MACH_SUN8I_A83T || MACH_SUN8I_V3S
 
 config RESERVE_ALLWINNER_BOOT0_HEADER
bool "reserve space for Allwinner boot0 header"
@@ -485,7 +495,8 @@ config AXP_GPIO
 
 config VIDEO
bool "Enable graphical uboot console on HDMI, LCD or VGA"
-   depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && 
!MACH_SUN50I
+   depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN8I_V3S && \
+   !MACH_SUN9I && !MACH_SUN50I
default y
---help---
Say Y here to add support for using a cfb console on the HDMI, LCD
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index a4c3fb69e4..6ac42acaea 100644
--- a/include/configs/sun8i.h
+++ b/include/configs/sun8i.h
@@ -21,6 +21,8 @@
#define CONFIG_SUNXI_USB_PHYS   4
 #elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS   3
+#elif defined CONFIG_MACH_SUN8I_V3S
+   #define CONFIG_SUNXI_USB_PHYS   1

[linux-sunxi] Re: [PATCH 3/8] rockchip: video: Split out HDMI controller code

2017-03-13 Thread Simon Glass 
On 8 March 2017 at 16:34, Jernej Skrabec  wrote:
> Designware HDMI controller and phy are used in other SoCs as well. Split
> out platform independent code.
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit
> registers as well. Add support to select access mode.
>
> EDID reading code use reading by blocks which is not supported by other
> SoCs in general. Make it more general using byte by byte approach, which
> is also used in Linux driver.
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> Support custom phys by making controller code independent from phy code.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --
>  drivers/video/dw_hdmi.c  | 764 
> +++
>  drivers/video/rockchip/Makefile  |   2 +-
>  drivers/video/rockchip/rk_hdmi.c | 757 +-
>  drivers/video/rockchip/rk_vop.c  |   1 -
>  include/dw_hdmi.h| 486 ++
>  6 files changed, 1275 insertions(+), 1191 deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
>  create mode 100644 drivers/video/dw_hdmi.c
>  create mode 100644 include/dw_hdmi.h

Reviewed-by: Simon Glass 

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[linux-sunxi] Re: [PATCH 5/8] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

2017-03-13 Thread Simon Glass 
Hi,

On 8 March 2017 at 16:34, Jernej Skrabec  wrote:
> This is needed for HDMI, which will be added later.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 54 
> +++
>  arch/arm/mach-sunxi/clock_sun6i.c | 40 +++-
>  drivers/video/sunxi/lcdc.c|  4 ++
>  include/configs/sun50i.h  |  2 +
>  include/configs/sun8i.h   |  4 ++
>  scripts/config_whitelist.txt  |  1 +
>  6 files changed, 104 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass 

Please see below.

>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 1aefd5a64c..ebb642747b 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
> u32 dram_pll_cfg;   /* 0xf8 PLL_DDR cfg register, A33 only */
> u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
> u32 dram_clk_gate;  /* 0x100 DRAM module gating */
> +#ifdef CONFIG_SUNXI_DE2
> +   u32 de_clk_cfg; /* 0x104 DE module clock */
> +#else
> u32 be0_clk_cfg;/* 0x104 BE0 module clock */
> +#endif
> u32 be1_clk_cfg;/* 0x108 BE1 module clock */
> u32 fe0_clk_cfg;/* 0x10c FE0 module clock */
> u32 fe1_clk_cfg;/* 0x110 FE1 module clock */
> u32 mp_clk_cfg; /* 0x114 MP module clock */
> +#ifdef CONFIG_SUNXI_DE2
> +   u32 lcd0_clk_cfg;   /* 0x118 LCD0 module clock */
> +   u32 lcd1_clk_cfg;   /* 0x11c LCD1 module clock */
> +#else
> u32 lcd0_ch0_clk_cfg;   /* 0x118 LCD0 CH0 module clock */
> u32 lcd1_ch0_clk_cfg;   /* 0x11c LCD1 CH0 module clock */
> +#endif
> u32 reserved14[3];
> u32 lcd0_ch1_clk_cfg;   /* 0x12c LCD0 CH1 module clock */
> u32 lcd1_ch1_clk_cfg;   /* 0x130 LCD1 CH1 module clock */
> @@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
> u32 dmic_clk_cfg;   /* 0x148 Digital Mic module clock*/
> u32 reserved15;
> u32 hdmi_clk_cfg;   /* 0x150 HDMI module clock */
> +#ifdef CONFIG_SUNXI_DE2
> +   u32 hdmi_slow_clk_cfg;  /* 0x154 HDMI slow module clock */
> +#else
> u32 ps_clk_cfg; /* 0x154 PS module clock */
> +#endif
> u32 mtc_clk_cfg;/* 0x158 MTC module clock */
> u32 mbus0_clk_cfg;  /* 0x15c MBUS0 module clock */
> u32 mbus1_clk_cfg;  /* 0x160 MBUS1 module clock */
> @@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL3_CTRL_N_MASK   (0x7f << CCM_PLL3_CTRL_N_SHIFT)
>  #define CCM_PLL3_CTRL_N(n) n) - 1) & 0x7f) << 8)
>  #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
> +#define CCM_PLL3_CTRL_LOCK (0x1 << 28)
>  #define CCM_PLL3_CTRL_EN   (0x1 << 31)
>
>  #define CCM_PLL5_CTRL_M(n) n) - 1) & 0x3) << 0)
> @@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
>  #define CCM_MIPI_PLL_CTRL_LDO_EN   (0x3 << 22)
>  #define CCM_MIPI_PLL_CTRL_EN   (0x1 << 31)
>
> +#define CCM_PLL10_CTRL_M_SHIFT 0
> +#define CCM_PLL10_CTRL_M_MASK  (0xf << CCM_PLL10_CTRL_M_SHIFT)
> +#define CCM_PLL10_CTRL_M(n)n) - 1) & 0xf) << 0)
> +#define CCM_PLL10_CTRL_N_SHIFT 8
> +#define CCM_PLL10_CTRL_N_MASK  (0x7f << CCM_PLL10_CTRL_N_SHIFT)
> +#define CCM_PLL10_CTRL_N(n)n) - 1) & 0x7f) << 8)
> +#define CCM_PLL10_CTRL_INTEGER_MODE(0x1 << 24)
> +#define CCM_PLL10_CTRL_LOCK(0x1 << 28)
> +#define CCM_PLL10_CTRL_EN  (0x1 << 31)
> +
>  #define CCM_PLL11_CTRL_N(n)n) - 1) & 0x3f) << 8)
>  #define CCM_PLL11_CTRL_SIGMA_DELTA_EN  (0x1 << 24)
>  #define CCM_PLL11_CTRL_UPD (0x1 << 30)
> @@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
>  #define AHB_GATE_OFFSET_DRC0   25
>  #define AHB_GATE_OFFSET_DE_FE0 14
>  #define AHB_GATE_OFFSET_DE_BE0 12
> +#define AHB_GATE_OFFSET_DE 12
>  #define AHB_GATE_OFFSET_HDMI   11
> +#ifndef CONFIG_SUNXI_DE2
>  #define AHB_GATE_OFFSET_LCD1   5
>  #define AHB_GATE_OFFSET_LCD0   4
> +#else
> +#define AHB_GATE_OFFSET_LCD1   4
> +#define AHB_GATE_OFFSET_LCD0   3
> +#endif
>
>  #define CCM_MMC_CTRL_M(x)  ((x) - 1)
>  #define CCM_MMC_CTRL_OCLK_DLY(x)   ((x) << 8)
> @@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
>  #define CCM_LCD_CH1_CTRL_PLL7_2X   (3 << 24)
>  #define CCM_LCD_CH1_CTRL_GATE  (0x1 << 31)
>
> +#define CCM_LCD0_CTRL_GATE (0x1 << 31)
> +#define CCM_LCD0_CTRL_M(n) n) - 1) & 0xf) << 0)
> +
> +#define CCM_LCD1_CTRL_GATE (0x1 << 31)
> +#define CCM_LCD1_CTRL_M(n) n) - 1) & 0xf) << 0)
> +
>

[linux-sunxi] Re: [PATCH 6/8] sunxi: video: Add A64/H3/H5 HDMI driver

2017-03-13 Thread Simon Glass 
On 8 March 2017 at 16:34, Jernej Skrabec  wrote:
> This commit adds support for HDMI output.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |   8 +
>  arch/arm/include/asm/arch-sunxi/display2.h  | 124 +
>  board/sunxi/Kconfig |  10 +
>  drivers/video/sunxi/Makefile|   1 +
>  drivers/video/sunxi/sunxi_de2.c | 258 ++
>  drivers/video/sunxi/sunxi_dw_hdmi.c | 389 
> 
>  include/configs/sunxi-common.h  |   5 +
>  7 files changed, 795 insertions(+)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/display2.h
>  create mode 100644 drivers/video/sunxi/sunxi_de2.c
>  create mode 100644 drivers/video/sunxi/sunxi_dw_hdmi.c

Reviewed-by: Simon Glass 

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[linux-sunxi] Re: [PATCH 1/8] rockchip: video: Fix HDMI audio clocks

2017-03-13 Thread Simon Glass 
On 8 March 2017 at 16:34, Jernej Skrabec  wrote:
> Function hdmi_lookup_n_cts() is feed with clock in Hz, which gets
> compared with clocks in kHz. Fix that by converting all clocks to Hz.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  drivers/video/rockchip/rk_hdmi.c | 32 
>  1 file changed, 16 insertions(+), 16 deletions(-)

Reviewed-by: Simon Glass 

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[linux-sunxi] Re: [PATCH 2/8] rockchip: video: Remove CSC initialization (HDMI)

2017-03-13 Thread Simon Glass 
On 8 March 2017 at 16:34, Jernej Skrabec  wrote:
> Despite the comment in the code, CSC unit is never used. According to
> the only public description of DW HDMI controller (i.MX6 manual), CSC
> unit is bypassed in MC_FLOWCTRL register and then actually powered
> down in MC_CLKDIS register.
>
> Signed-off-by: Jernej Skrabec 
> ---
>
>  drivers/video/rockchip/rk_hdmi.c | 39 ---
>  1 file changed, 39 deletions(-)

Reviewed-by: Simon Glass 

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