date:20170324

Re: [linux-sunxi] sun8iw3_thermal sensor problems

2017-03-24 Thread Eyad Majali

ok I will thanks :)

On Friday, March 24, 2017 at 10:24:36 PM UTC+2, Icenowy Zheng wrote:
>
>
> 2017年3月25日 上午3:07于 Eyad Majali 写道：
> >
> > Hi
> > I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it 
> compiles OK , but when enabling clk-a31-pll2 the kernel hangs and doesnt 
> boot , any help how to fix that ??
>
> Please wait for Quentin Schulz's new thermal sensor driver ;-)
>
> >
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Re: [linux-sunxi] sun8iw3_thermal sensor problems

2017-03-24 Thread Icenowy Zheng


2017年3月25日 上午3:07于 Eyad Majali 写道：
>
> Hi
> I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it compiles OK , but when enabling clk-a31-pll2 the kernel hangs and doesnt boot , any help how to fix that ??
Please wait for Quentin Schulz's new thermal sensor driver ;-)
>
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[linux-sunxi] sun8iw3_thermal sensor problems

2017-03-24 Thread Eyad Majali

Hi
I followed Icenowy Zheng's patches to enable sun8iw3 thermal sensor , it 
compiles OK , but when enabling clk-a31-pll2 the kernel hangs and doesnt 
boot , any help how to fix that ??

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Re: [linux-sunxi] Backlight problems on A23 Q8 Tablet

2017-03-24 Thread Eyad Majali


I fixed the problem by modifying drivers/pwm/core.c as following:
in function pwmchip_add_with_polarity

for (i = 0; i < chip->npwm; i++) {
pwm = >pwms[i];

pwm->chip = chip;
pwm->pwm = chip->base + i;
pwm->hwpwm = i;
pwm->state.polarity = polarity;
  +pwm->state.period = 5;
  +pwm->state.duty_cycle = 5;
  +pwm->state.enabled = true;
if (chip->ops->get_state)
chip->ops->get_state(chip, pwm, >state);

radix_tree_insert(_tree, pwm->pwm, pwm);
}

It's a hack but its working

On Monday, March 20, 2017 at 11:39:43 AM UTC+2, Eyad Majali wrote:
>
> Yes it did , I think I have to modify the source code of pwm-sun4i and 
> init it to 100% duty cycle , is there any easier solution ?
>
> On Monday, March 20, 2017 at 6:25:49 AM UTC+2, Icenowy Zheng wrote:
>>
>>
>>
>> 20.03.2017, 04:21, "Eyad Majali" : 
>> > I did these changes before I know about the patch to prevent complete 
>> lcd turn off , yes I'm on 4.11-rc , the problem is mainly with pwm-sun4i 
>> > when its enabled alone without pwm_bl the screen brightness is very 
>> low, enabling pwm_bl doesnt solve the problem until i rmmod it the load it 
>> again 
>>
>> Does it really prevented complete LCD blacklight turn off on your tablet? 
>> At least it worked on my A33 ;-) 
>>
>> > On Sunday, March 19, 2017 at 6:29:35 PM UTC+2, Icenowy Zheng wrote: 
>> > 
>> >> 20.03.2017, 00:08, "Quentin Schulz" : 
>> >>> Hi, 
>> >>> 
>> >>> On 19/03/2017 15:59, Eyad Majali wrote: 
>>   Hi, 
>>   pwm is configured in dtsi , when the module loads screen brightness 
>>   decrease to minimum ( barely sees anything) how to fix that ? 
>>   also when i enable pwm-bl it turns off the screen completely , but 
>> when 
>>   i removed the enable-gpios the result was the same with pwm-sun4i 
>> alone but 
>>   if i rmmod pwm-bl and then modprobe pwm-bl it will load the default 
>>   brightness level correctly 
>>   any help is apreciated , Thanks 
>> >>> 
>> >>> I think this patch can help you: 
>> https://patchwork.kernel.org/patch/9631655/ 
>> >> 
>> >> P.S. are you using 4.11-rc now? 
>> >> 
>> >> This patch only takes effect on 4.11-rc. 
>> >> 
>> >>> 
>> >>> Quentin 
>> >>> 
>>   -- 
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>> >>> 
>> >>> -- 
>> >>> Quentin Schulz, Free Electrons 
>> >>> Embedded Linux and Kernel engineering 
>> >>> http://free-electrons.com 
>> >>> 
>> >>> -- 
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>>
>

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[linux-sunxi] Re: [PATCH v2 4/7] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

2017-03-24 Thread Jernej Škrabec

Dne petek, 24. marec 2017 ob 16:53:07 CET je Maxime Ripard napisal(a):
> On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> > Hi,
> > 
> > Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > > On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> > > > Hi,
> > > > 
> > > > Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard napisal(a):
> > > > > Hi,
> > > > > 
> > > > > On Mon, Mar 20, 2017 at 11:01:25PM +0100, Jernej Skrabec wrote:
> > > > > > diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
> > > > > > index 1b7bfb6c22..146f7f4e1b 100644
> > > > > > --- a/include/configs/sun50i.h
> > > > > > +++ b/include/configs/sun50i.h
> > > > > > @@ -21,6 +21,8 @@
> > > > > > 
> > > > > >  #define GICD_BASE  0x1c81000
> > > > > >  #define GICC_BASE  0x1c82000
> > > > > > 
> > > > > > +#define CONFIG_SUNXI_DE2
> > > > > > +
> > > > > > 
> > > > > >  /*
> > > > > >  
> > > > > >   * Include common sunxi configuration where most the settings are
> > > > > >   */
> > > > > > 
> > > > > > diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
> > > > > > index a4c3fb69e4..c42b901107 100644
> > > > > > --- a/include/configs/sun8i.h
> > > > > > +++ b/include/configs/sun8i.h
> > > > > > @@ -25,6 +25,10 @@
> > > > > > 
> > > > > > #define CONFIG_SUNXI_USB_PHYS   2
> > > > > >  
> > > > > >  #endif
> > > > > > 
> > > > > > +#ifdef CONFIG_MACH_SUNXI_H3_H5
> > > > > > +#define CONFIG_SUNXI_DE2
> > > > > > +#endif
> > > > > > +
> > > > > > 
> > > > > >  /*
> > > > > >  
> > > > > >   * Include common sunxi configuration where most the settings are
> > > > > >   */
> > > > > > 
> > > > > > diff --git a/scripts/config_whitelist.txt
> > > > > > b/scripts/config_whitelist.txt
> > > > > > index 8e5dc36fa7..ba0eb12665 100644
> > > > > > --- a/scripts/config_whitelist.txt
> > > > > > +++ b/scripts/config_whitelist.txt
> > > > > > @@ -3102,6 +3102,7 @@ CONFIG_STV0991_HZ_CLOCK
> > > > > > 
> > > > > >  CONFIG_ST_SMI
> > > > > >  CONFIG_SUN4
> > > > > >  CONFIG_SUNXI_AHCI
> > > > > > 
> > > > > > +CONFIG_SUNXI_DE2
> > > > > > 
> > > > > >  CONFIG_SUNXI_EMAC
> > > > > >  CONFIG_SUNXI_GMAC
> > > > > >  CONFIG_SUNXI_GPIO
> > > > > 
> > > > > This should be a Kconfig option.
> > > > 
> > > > So hidden option in board/sunxi/Kconfig will probably be the best
> > > > then?
> > > 
> > > Yes, I guess, but I'm not entirely sure why you need two different
> > > options there?
> > 
> > I used define for CONFIG_SUNXI_DE2 here because SoC has or has not DE2 IP
> > block and that is not a choice. Option in patch 5 is configurable and
> > gives opportunity to build video driver or skip it, whithout influencing
> > clock structure.
> > 
> > I could make only one option, but then it would have to be configurable,
> > which doesn't really make sense from patch 4 perspective, because, as I
> > already stated before, this is property of the SoC.
> > 
> > Which solution do you prefer? One option, define and option (as it is now)
> > or two options?
> > 
> > Frankly, none of them is ideal. Best solution would be to convert clocks
> > to
> > use driver model framework.
> 
> I guess you could make a hidden Kconfig option selected by the
> relevant MACH_ options.
> 
> As a general basis, we move away from the old-style config options, so
> adding any new !Kconfig options isn't really an option.

Ok.

Do you mind if I switch from 16 BPP to 32 BPP in patch 5? efifb linux driver 
doesn't work well with 16 BPP.

Regards,
Jernej

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[linux-sunxi] Re: [PATCH 3/3] ARM: dts: sun8i: add device tree for Lichee Pi Zero with Dock

2017-03-24 Thread Maxime Ripard

On Thu, Mar 23, 2017 at 03:34:18AM +0800, Icenowy Zheng wrote:
> 
> 2017年3月23日 03:24于 Maxime Ripard 写道：
> >
> > On Fri, Mar 17, 2017 at 11:43:43PM +0800, Icenowy Zheng wrote: 
> > > Lichee Pi Zero features a dock, which adds some functions, and should be 
> > > soldered with the core board of Lichee Pi Zero. 
> > > 
> > > Add support for the dock as a new dts, as soldering is needed to make 
> > > the dock usable and there's functions enabled on the dock that is 
> > > unavailable at the 2.54mm pins of the core board. 
> > > 
> > > Signed-off-by: Icenowy Zheng  
> > > --- 
> > >  arch/arm/boot/dts/Makefile |  3 +- 
> > >  arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 98 
> > >++ 
> > >  2 files changed, 100 insertions(+), 1 deletion(-) 
> > >  create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts 
> > > 
> > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile 
> > > index 43c27b624f94..de52d403f818 100644 
> > > --- a/arch/arm/boot/dts/Makefile 
> > > +++ b/arch/arm/boot/dts/Makefile 
> > > @@ -878,7 +878,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ 
> > >  sun8i-h3-orangepi-plus.dtb \ 
> > >  sun8i-h3-orangepi-plus2e.dtb \ 
> > >  sun8i-r16-parrot.dtb \ 
> > > - sun8i-v3s-licheepi-zero.dtb 
> > > + sun8i-v3s-licheepi-zero.dtb \ 
> > > + sun8i-v3s-licheepi-zero-dock.dtb 
> > >  dtb-$(CONFIG_MACH_SUN9I) += \ 
> > >  sun9i-a80-optimus.dtb \ 
> > >  sun9i-a80-cubieboard4.dtb 
> > > diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts 
> > > b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts 
> > > new file mode 100644 
> > > index ..956fa47fde53 
> > > --- /dev/null 
> > > +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts 
> > > @@ -0,0 +1,98 @@ 
> > > +/* 
> > > + * Copyright (C) 2016 Icenowy Zheng  
> > > + * 
> > > + * This file is dual-licensed: you can use it either under the terms 
> > > + * of the GPL or the X11 license, at your option. Note that this dual 
> > > + * licensing only applies to this file, and not this project as a 
> > > + * whole. 
> > > + * 
> > > + *  a) This file is free software; you can redistribute it and/or 
> > > + * modify it under the terms of the GNU General Public License as 
> > > + * published by the Free Software Foundation; either version 2 of 
> > > the 
> > > + * License, or (at your option) any later version. 
> > > + * 
> > > + * This file is distributed in the hope that it will be useful, 
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of 
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
> > > + * GNU General Public License for more details. 
> > > + * 
> > > + * Or, alternatively, 
> > > + * 
> > > + *  b) Permission is hereby granted, free of charge, to any person 
> > > + * obtaining a copy of this software and associated documentation 
> > > + * files (the "Software"), to deal in the Software without 
> > > + * restriction, including without limitation the rights to use, 
> > > + * copy, modify, merge, publish, distribute, sublicense, and/or 
> > > + * sell copies of the Software, and to permit persons to whom the 
> > > + * Software is furnished to do so, subject to the following 
> > > + * conditions: 
> > > + * 
> > > + * The above copyright notice and this permission notice shall be 
> > > + * included in all copies or substantial portions of the Software. 
> > > + * 
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
> > > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
> > > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 
> > > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 
> > > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 
> > > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 
> > > + * OTHER DEALINGS IN THE SOFTWARE. 
> > > + */ 
> > > + 
> > > +#include "sun8i-v3s-licheepi-zero.dts" 
> > > + 
> > > +#include  
> > > + 
> > > +/ { 
> > > + model = "Lichee Pi Zero with Dock"; 
> > > + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", 
> > > +  "allwinner,sun8i-v3s"; 
> > > +}; 
> > > + 
> > > + { 
> > > + /* The LEDs conflict with MMC1 slot */ 
> >
> > How does it conflicts? 
> 
> They both use PGx.

So they use the same bank? How is that a conflict?

> > > + { 
> > > + pinctrl-0 = <_pins>; 
> > > + pinctrl-names = "default"; 
> > > + broken-cd; 
> >
> > There's no card-detect on a GPIO? 
> 
> Yes.
> 
> All SD slots on Lichee Pi series have no card-detect.

Weird... Ok.

Maxime

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[linux-sunxi] Re: [PATCH v2 4/7] sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs

2017-03-24 Thread Maxime Ripard

On Wed, Mar 22, 2017 at 06:19:12PM +0100, Jernej Škrabec wrote:
> Hi,
> 
> Dne sreda, 22. marec 2017 ob 08:45:48 CET je Maxime Ripard napisal(a):
> > On Tue, Mar 21, 2017 at 11:26:46PM +0100, Jernej Škrabec wrote:
> > > Hi,
> > > 
> > > Dne torek, 21. marec 2017 ob 20:34:33 CET je Maxime Ripard napisal(a):
> > > > Hi,
> > > > 
> > > > On Mon, Mar 20, 2017 at 11:01:25PM +0100, Jernej Skrabec wrote:
> > > > > diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h
> > > > > index 1b7bfb6c22..146f7f4e1b 100644
> > > > > --- a/include/configs/sun50i.h
> > > > > +++ b/include/configs/sun50i.h
> > > > > @@ -21,6 +21,8 @@
> > > > > 
> > > > >  #define GICD_BASE0x1c81000
> > > > >  #define GICC_BASE0x1c82000
> > > > > 
> > > > > +#define CONFIG_SUNXI_DE2
> > > > > +
> > > > > 
> > > > >  /*
> > > > >  
> > > > >   * Include common sunxi configuration where most the settings are
> > > > >   */
> > > > > 
> > > > > diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
> > > > > index a4c3fb69e4..c42b901107 100644
> > > > > --- a/include/configs/sun8i.h
> > > > > +++ b/include/configs/sun8i.h
> > > > > @@ -25,6 +25,10 @@
> > > > > 
> > > > >   #define CONFIG_SUNXI_USB_PHYS   2
> > > > >  
> > > > >  #endif
> > > > > 
> > > > > +#ifdef CONFIG_MACH_SUNXI_H3_H5
> > > > > +#define CONFIG_SUNXI_DE2
> > > > > +#endif
> > > > > +
> > > > > 
> > > > >  /*
> > > > >  
> > > > >   * Include common sunxi configuration where most the settings are
> > > > >   */
> > > > > 
> > > > > diff --git a/scripts/config_whitelist.txt
> > > > > b/scripts/config_whitelist.txt
> > > > > index 8e5dc36fa7..ba0eb12665 100644
> > > > > --- a/scripts/config_whitelist.txt
> > > > > +++ b/scripts/config_whitelist.txt
> > > > > @@ -3102,6 +3102,7 @@ CONFIG_STV0991_HZ_CLOCK
> > > > > 
> > > > >  CONFIG_ST_SMI
> > > > >  CONFIG_SUN4
> > > > >  CONFIG_SUNXI_AHCI
> > > > > 
> > > > > +CONFIG_SUNXI_DE2
> > > > > 
> > > > >  CONFIG_SUNXI_EMAC
> > > > >  CONFIG_SUNXI_GMAC
> > > > >  CONFIG_SUNXI_GPIO
> > > > 
> > > > This should be a Kconfig option.
> > > 
> > > So hidden option in board/sunxi/Kconfig will probably be the best
> > > then?
> > 
> > Yes, I guess, but I'm not entirely sure why you need two different
> > options there?
> 
> I used define for CONFIG_SUNXI_DE2 here because SoC has or has not DE2 IP 
> block 
> and that is not a choice. Option in patch 5 is configurable and gives 
> opportunity to build video driver or skip it, whithout influencing clock 
> structure.
> 
> I could make only one option, but then it would have to be configurable, 
> which 
> doesn't really make sense from patch 4 perspective, because, as I already 
> stated before, this is property of the SoC.
> 
> Which solution do you prefer? One option, define and option (as it is now) or 
> two options?
> 
> Frankly, none of them is ideal. Best solution would be to convert clocks to 
> use driver model framework.

I guess you could make a hidden Kconfig option selected by the
relevant MACH_ options.

As a general basis, we move away from the old-style config options, so
adding any new !Kconfig options isn't really an option.

Maxime

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[linux-sunxi] Re: [PATCH v2 1/1] ARM: dts: sun8i: NanoPi NEO Air add WiFi / eMMC

2017-03-24 Thread Maxime Ripard

Hi,

On Thu, Mar 23, 2017 at 10:24:44PM +0100, Jelle van der Waa wrote:
> Enable the WiFi (AP6212) chip and eMMC support for the NanoPi NEO Air.
> 
> Signed-off-by: Jelle van der Waa 
> ---
>  arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 45 
> +++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts 
> b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> index 3ba081c1f555..457a28e56514 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> @@ -73,6 +73,13 @@
>   gpios = < 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
>   };
>   };
> +
> + wifi-pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <>;

Could you please drop that pinctrl group for that GPIO? It will help
us prevent a bug in the future in the pinctrl driver that allows two
GPIO users to claim the same pin.

Unfortunately, that will require removing all those pinctrl properties
for the GPIOs, so we'd better not introduce them in the first place :)

Thanks!
Maxime

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[linux-sunxi] [PATCH 1/2] sunxi: Display: Add some comments about unimplemented LVDS features

2017-03-24 Thread Priit Laes

Following LVDS features might be supported (according to BSP), but are
unimplemented due to lack of proper hardware:
 - dual channel LVDS
 - choosing between NS or JEIDA mode
 - cross-polarity support

Add at least some comments about them.

Signed-off-by: Priit Laes 
---
 drivers/video/sunxi_display.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index 6f8ee01..bcd33dd 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -829,8 +829,20 @@ static void sunxi_lcdc_tcon0_mode_set(const struct 
ctfb_res_modes *mode,
 #endif
 #ifdef CONFIG_VIDEO_LCD_IF_LVDS
val = (sunxi_display.depth == 18) ? 1 : 0;
+   /*
+* TODO: LVDS features (from BSP, no hardware):
+* BIT(30) - LVDS single/dual channel (single - 0, dual - 1)
+* BIT(29) - 0
+* BIT(28) - 0
+* BIT(27) - LVDS mode (NS - 0, JEIDA - 1)
+* BIT(23) - 0
+*/
writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) |
   SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, >tcon0_lvds_intf);
+   /*
+* TODO: LVDS cross-polarity support (from BSP, no hardware):
+* set bits (0x1f << 21) | (0x1f << 5) for lvds_ana1 register
+*/
 #endif
 
if (sunxi_display.depth == 18 || sunxi_display.depth == 16) {
-- 
2.9.3

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[linux-sunxi] [PATCH 2/2] sunxi: Display: Mark sunxi_rgb2yuv_coef array as const

2017-03-24 Thread Priit Laes

sunxi_rgb2yuv_coef is readonly and never modified.

Signed-off-by: Priit Laes 
---
 drivers/video/sunxi_display.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index bcd33dd..a12c4c3 100644
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -457,7 +457,7 @@ static void sunxi_composer_init(void)
setbits_le32(_be->mode, SUNXI_DE_BE_MODE_ENABLE);
 }
 
-static u32 sunxi_rgb2yuv_coef[12] = {
+static const u32 sunxi_rgb2yuv_coef[12] = {
0x0107, 0x0204, 0x0064, 0x0108,
0x3f69, 0x3ed6, 0x01c1, 0x0808,
0x01c1, 0x3e88, 0x3fb8, 0x0808
-- 
2.9.3

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[linux-sunxi] [PATCH 2/3] clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch

2017-03-24 Thread Chen-Yu Tsai

In commit 2beaa601c849 ("clk: sunxi-ng: Implement minimum for
multipliers"), the multiplier minimums in the set_rate callback
for NM and NKMP style clocks were not updated.

This patch fixes them to match their round_rate callbacks.

Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
 drivers/clk/sunxi-ng/ccu_nm.c   | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 162ff2664f64..e58c95787f94 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -138,9 +138,9 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned 
long rate,
unsigned long flags;
u32 reg;
 
-   _nkmp.min_n = 1;
+   _nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
-   _nkmp.min_k = 1;
+   _nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index f312c92f2a21..5e5e90a4a50c 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -122,7 +122,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long 
rate,
else
ccu_frac_helper_disable(>common, >frac);
 
-   _nm.min_n = 1;
+   _nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
-- 
2.11.0

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[linux-sunxi] [PATCH 1/3] clk: sunxi-ng: use 1 as fallback for minimum multiplier

2017-03-24 Thread Chen-Yu Tsai

A zero multiplier does not make sense for clocks.

Use 1 as the minimum when a multiplier minimum isn't specified.

Fixes: 2beaa601c849 ("clk: sunxi-ng: Implement minimum for multipliers")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu_nk.c   | 8 
 drivers/clk/sunxi-ng/ccu_nkm.c  | 8 
 drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
 drivers/clk/sunxi-ng/ccu_nm.c   | 2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index b9e9b8a9d1b4..2485bda87a9a 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -102,9 +102,9 @@ static long ccu_nk_round_rate(struct clk_hw *hw, unsigned 
long rate,
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nk->fixed_post_div;
 
-   _nk.min_n = nk->n.min;
+   _nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
-   _nk.min_k = nk->k.min;
+   _nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
 
ccu_nk_find_best(*parent_rate, rate, &_nk);
@@ -127,9 +127,9 @@ static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long 
rate,
if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nk->fixed_post_div;
 
-   _nk.min_n = nk->n.min;
+   _nk.min_n = nk->n.min ?: 1;
_nk.max_n = nk->n.max ?: 1 << nk->n.width;
-   _nk.min_k = nk->k.min;
+   _nk.min_k = nk->k.min ?: 1;
_nk.max_k = nk->k.max ?: 1 << nk->k.width;
 
ccu_nk_find_best(parent_rate, rate, &_nk);
diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c b/drivers/clk/sunxi-ng/ccu_nkm.c
index 71f81e95a061..cba84afe1cf1 100644
--- a/drivers/clk/sunxi-ng/ccu_nkm.c
+++ b/drivers/clk/sunxi-ng/ccu_nkm.c
@@ -109,9 +109,9 @@ static unsigned long ccu_nkm_round_rate(struct 
ccu_mux_internal *mux,
struct ccu_nkm *nkm = data;
struct _ccu_nkm _nkm;
 
-   _nkm.min_n = nkm->n.min;
+   _nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
-   _nkm.min_k = nkm->k.min;
+   _nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
@@ -138,9 +138,9 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned 
long rate,
unsigned long flags;
u32 reg;
 
-   _nkm.min_n = nkm->n.min;
+   _nkm.min_n = nkm->n.min ?: 1;
_nkm.max_n = nkm->n.max ?: 1 << nkm->n.width;
-   _nkm.min_k = nkm->k.min;
+   _nkm.min_k = nkm->k.min ?: 1;
_nkm.max_k = nkm->k.max ?: 1 << nkm->k.width;
_nkm.min_m = 1;
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index 488055ed944f..162ff2664f64 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -116,9 +116,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned 
long rate,
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
 
-   _nkmp.min_n = nkmp->n.min;
+   _nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
-   _nkmp.min_k = nkmp->k.min;
+   _nkmp.min_k = nkmp->k.min ?: 1;
_nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width;
_nkmp.min_m = 1;
_nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index af71b1909cd9..f312c92f2a21 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -99,7 +99,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned 
long rate,
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
 
-   _nm.min_n = nm->n.min;
+   _nm.min_n = nm->n.min ?: 1;
_nm.max_n = nm->n.max ?: 1 << nm->n.width;
_nm.min_m = 1;
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
-- 
2.11.0

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[linux-sunxi] [PATCH 0/3] clk: sunxi-ng: minimum multiplier and comment fixes

2017-03-24 Thread Chen-Yu Tsai

Hi Maxime,

Here's a few fixes I came up with while thinking more about how to
implement some of the tricky clocks on the A83T.

Please have a look. The first 2 might need to go in stable, but I'll
leave the decision to you.

Regards
ChenYu


Chen-Yu Tsai (3):
  clk: sunxi-ng: use 1 as fallback for minimum multiplier
  clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
  clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code

 drivers/clk/sunxi-ng/ccu-sun9i-a80.c | 3 +--
 drivers/clk/sunxi-ng/ccu_nk.c| 8 
 drivers/clk/sunxi-ng/ccu_nkm.c   | 8 
 drivers/clk/sunxi-ng/ccu_nkmp.c  | 8 
 drivers/clk/sunxi-ng/ccu_nm.c| 4 ++--
 5 files changed, 15 insertions(+), 16 deletions(-)

-- 
2.11.0

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Re: [linux-sunxi] Re: [RESEND PATCH v4 2/9] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs

2017-03-24 Thread Chen-Yu Tsai

On Fri, Mar 24, 2017 at 3:55 PM, Quentin Schulz
 wrote:
> Hi,
>
> On 23/03/2017 10:52, Chen-Yu Tsai wrote:
>> On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel  wrote:
>>> Hi,
>>>
>>> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
 P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
 Not sure if that was the intended usage of the new imply syntax though.
>>>
>>> I think adding "default MFD_AXP20X" to the sub-drivers is cleaner,
>>> as you will not end up with a long list.
>>
>> I'd still need to add imply statements for the various subsystems though,
>> like regulators, power supplies, extcon, etc..
>> But I suppose that's cleaner, and fits the original intent of the syntax.
>>
>
> Hum. I don't really understand what you are saying.. Am I supposed to
> modify something or, is it okay and we're waiting for Lee to apply on
> his tree?
>
> Thanks in advance for clearing it up,
>
> Quentin

I'm just mentioning some follow up tasks I want to do.
The patch is fine and we're waiting for Lee to take it.

ChenYu

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[linux-sunxi] Re: [RESEND PATCH v4 2/9] iio: adc: add support for X-Powers AXP20X and AXP22X PMICs ADCs

2017-03-24 Thread Quentin Schulz

Hi,

On 23/03/2017 10:52, Chen-Yu Tsai wrote:
> On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel  wrote:
>> Hi,
>>
>> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
>>> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
>>> Not sure if that was the intended usage of the new imply syntax though.
>>
>> I think adding "default MFD_AXP20X" to the sub-drivers is cleaner,
>> as you will not end up with a long list.
> 
> I'd still need to add imply statements for the various subsystems though,
> like regulators, power supplies, extcon, etc..
> But I suppose that's cleaner, and fits the original intent of the syntax.
> 

Hum. I don't really understand what you are saying.. Am I supposed to
modify something or, is it okay and we're waiting for Lee to apply on
his tree?

Thanks in advance for clearing it up,

Quentin

-- 
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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[linux-sunxi] Re: [PATCH] mmc: sunxi: change controller error info to debug level

2017-03-24 Thread Icenowy Zheng



24.03.2017, 15:46, "Ulf Hansson" :
> On 16 March 2017 at 14:29, Icenowy Zheng  wrote:
>>  The controller's errors are usually normal (for example, for MMC or SDIO
>>  cards, some errors are expected to happen; and for boards without a
>>  dedicated card detect pin the error info will even flood console and
>>  hide other normal messages) and hard to understand.
>>
>>  Change their print level to debug, thus it won't be shown to generic
>>  users.
>>
>>  Signed-off-by: Icenowy Zheng 
>
> For some reason this change didn't enter the mmc patchtracker. However
> I have picked it up for next anyway.

Thanks!

Maybe it's because of the e-mail provider chosen by AOSC (Yandex.Mail).

Sorry. I will try to ask for a migration to other e-mail provider.

>
> Thanks!
>
> Kind regards
> Uffe
>
>>  ---
>>   drivers/mmc/host/sunxi-mmc.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>  diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>  index 6ffcd2838272..0391c62cc99f 100644
>>  --- a/drivers/mmc/host/sunxi-mmc.c
>>  +++ b/drivers/mmc/host/sunxi-mmc.c
>>  @@ -489,7 +489,7 @@ static void sunxi_mmc_dump_errinfo(struct 
>> sunxi_mmc_host *host)
>>    cmd->opcode == SD_IO_RW_DIRECT))
>>  return;
>>
>>  - dev_err(mmc_dev(host->mmc),
>>  + dev_dbg(mmc_dev(host->mmc),
>>  "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
>>  host->mmc->index, cmd->opcode,
>>  data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
>>  --
>>  2.12.0

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Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Icenowy Zheng



24.03.2017, 14:56, "Chen-Yu Tsai" :
> On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng  wrote:
>>  24.03.2017, 11:05, "Chen-Yu Tsai" :
>>>  On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng  wrote:
   The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
   register offset missing.

   Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>>>
>>>  You are implying that all SoCs after A33 have PHYCTL at 0x10.
>>>
>>>  This is not true. As the A83T, which was released after the A33, has
>>>  PHYCTL at the old offset.
>>
>>  No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.
>>
>>  The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
>>  ```
>>  #if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || 
>> defined (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined 
>> (CONFIG_ARCH_SUN8IW7)
>>  #define USBPHYC_REG_o_PHYCTL 0x0410
>>  #else
>>  #define USBPHYC_REG_o_PHYCTL 0x0404
>>  #endif
>>  ```
>>
>>  In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
>>  ```
>>  #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || 
>> defined (CONFIG_ARCH_SUN8IW11)
>>  #define USBPHYC_REG_o_PHYCTL 0x0410
>>  #else
>>  #define USBPHYC_REG_o_PHYCTL 0x0404
>>  #endif
>>  ```
>>
>>  So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.
>
> Seems you are right. However I think it's best to not assume or infer
> anything. Who knows, Allwinner might re-release some old SoC under a
> different under a different name again.
>
> Just state the facts: H3 has its PHYCTL at 0x10.

OK. Thanks ;-)

>
> ChenYu
>
>>>  Just state that H3 has PHYCTL at 0x10.
>>>
>>>  ChenYu
>>>
   Signed-off-by: Icenowy Zheng 
   ---
   New patch in v4.

    drivers/phy/phy-sun4i-usb.c | 1 +
    1 file changed, 1 insertion(+)

   diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
   index 62b4d25448c6..a650f283f6ff 100644
   --- a/drivers/phy/phy-sun4i-usb.c
   +++ b/drivers/phy/phy-sun4i-usb.c
   @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = 
 {
   .num_phys = 4,
   .type = sun8i_h3_phy,
   .disc_thresh = 3,
   + .phyctl_offset = REG_PHYCTL_A33,
   .dedicated_clocks = true,
   .enable_pmu_unk1 = true,
    };
   --
   2.12.0

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>>>
>>>  --
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[linux-sunxi] Re: [PATCH] mmc: sunxi: change controller error info to debug level

2017-03-24 Thread Ulf Hansson

On 16 March 2017 at 14:29, Icenowy Zheng  wrote:
> The controller's errors are usually normal (for example, for MMC or SDIO
> cards, some errors are expected to happen; and for boards without a
> dedicated card detect pin the error info will even flood console and
> hide other normal messages) and hard to understand.
>
> Change their print level to debug, thus it won't be shown to generic
> users.
>
> Signed-off-by: Icenowy Zheng 

For some reason this change didn't enter the mmc patchtracker. However
I have picked it up for next anyway.

Thanks!

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 6ffcd2838272..0391c62cc99f 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -489,7 +489,7 @@ static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host 
> *host)
>   cmd->opcode == SD_IO_RW_DIRECT))
> return;
>
> -   dev_err(mmc_dev(host->mmc),
> +   dev_dbg(mmc_dev(host->mmc),
> "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
> host->mmc->index, cmd->opcode,
> data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
> --
> 2.12.0
>

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Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Chen-Yu Tsai

On Fri, Mar 24, 2017 at 2:27 PM, Icenowy Zheng  wrote:
>
>
> 24.03.2017, 11:05, "Chen-Yu Tsai" :
>> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng  wrote:
>>>  The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>>  register offset missing.
>>>
>>>  Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>>
>> You are implying that all SoCs after A33 have PHYCTL at 0x10.
>>
>> This is not true. As the A83T, which was released after the A33, has
>> PHYCTL at the old offset.
>
> No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.
>
> The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined 
> (CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined 
> (CONFIG_ARCH_SUN8IW7)
> #define  USBPHYC_REG_o_PHYCTL   0x0410
> #else
> #define  USBPHYC_REG_o_PHYCTL   0x0404
> #endif
> ```
>
> In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
> ```
> #if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined 
> (CONFIG_ARCH_SUN8IW11)
> #define  USBPHYC_REG_o_PHYCTL   0x0410
> #else
> #define  USBPHYC_REG_o_PHYCTL   0x0404
> #endif
> ```
>
> So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.
>

Seems you are right. However I think it's best to not assume or infer
anything. Who knows, Allwinner might re-release some old SoC under a
different under a different name again.

Just state the facts: H3 has its PHYCTL at 0x10.

ChenYu

>>
>> Just state that H3 has PHYCTL at 0x10.
>>
>> ChenYu
>>
>>>  Signed-off-by: Icenowy Zheng 
>>>  ---
>>>  New patch in v4.
>>>
>>>   drivers/phy/phy-sun4i-usb.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>>  diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>>  index 62b4d25448c6..a650f283f6ff 100644
>>>  --- a/drivers/phy/phy-sun4i-usb.c
>>>  +++ b/drivers/phy/phy-sun4i-usb.c
>>>  @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>>  .num_phys = 4,
>>>  .type = sun8i_h3_phy,
>>>  .disc_thresh = 3,
>>>  + .phyctl_offset = REG_PHYCTL_A33,
>>>  .dedicated_clocks = true,
>>>  .enable_pmu_unk1 = true,
>>>   };
>>>  --
>>>  2.12.0
>>>
>>>  --
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>>
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Re: [linux-sunxi] [PATCH v4 3/8] phy: sun4i-usb: add PHYCTL offset for H3 SoC

2017-03-24 Thread Icenowy Zheng



24.03.2017, 11:05, "Chen-Yu Tsai" :
> On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng  wrote:
>>  The config structure of H3 in phy-sun4i-usb driver have the PHYCTL
>>  register offset missing.
>>
>>  Add it. Because it's a SoC after A33, its PHYCTL offset should be 0x10.
>
> You are implying that all SoCs after A33 have PHYCTL at 0x10.
>
> This is not true. As the A83T, which was released after the A33, has
> PHYCTL at the old offset.

No, in Allwinner's BSP A83T is using also PHYCTL at 0x10.

The code in linux-3.4/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
```
#if defined (CONFIG_ARCH_SUN8IW5) || defined (CONFIG_ARCH_SUN8IW6) || defined 
(CONFIG_ARCH_SUN8IW9) || defined (CONFIG_ARCH_SUN8IW8) || defined 
(CONFIG_ARCH_SUN8IW7)
#define  USBPHYC_REG_o_PHYCTL   0x0410
#else
#define  USBPHYC_REG_o_PHYCTL   0x0404
#endif
```

In linux-3.10/drivers/usb/sunxi_usb/include/sunxi_usb_bsp.c is
```
#if defined (CONFIG_ARCH_SUN50I) || defined (CONFIG_ARCH_SUN8IW10) || defined 
(CONFIG_ARCH_SUN8IW11)
#define  USBPHYC_REG_o_PHYCTL   0x0410
#else
#define  USBPHYC_REG_o_PHYCTL   0x0404
#endif
```

So sun50i* and sun50iw5~w11 all use PHYCTL at 0x10.

>
> Just state that H3 has PHYCTL at 0x10.
>
> ChenYu
>
>>  Signed-off-by: Icenowy Zheng 
>>  ---
>>  New patch in v4.
>>
>>   drivers/phy/phy-sun4i-usb.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>>  diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
>>  index 62b4d25448c6..a650f283f6ff 100644
>>  --- a/drivers/phy/phy-sun4i-usb.c
>>  +++ b/drivers/phy/phy-sun4i-usb.c
>>  @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
>>  .num_phys = 4,
>>  .type = sun8i_h3_phy,
>>  .disc_thresh = 3,
>>  + .phyctl_offset = REG_PHYCTL_A33,
>>  .dedicated_clocks = true,
>>  .enable_pmu_unk1 = true,
>>   };
>>  --
>>  2.12.0
>>
>>  --
>>  You received this message because you are subscribed to the Google Groups 
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>
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