[linux-sunxi] Re: [PATCH 4/5] ARM: sun8i: a83t: Add dt node for the syscon control module

2017-06-05 Thread Chen-Yu Tsai 
On Tue, Jun 6, 2017 at 3:21 AM, Corentin Labbe
 wrote:
> This patch add the dt node for the syscon register present on the
> Allwinner A83T
>
> Signed-off-by: Corentin Labbe 
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
> b/arch/arm/boot/dts/sun8i-a83t.dtsi
> index 1dc4cfe81534..ae559dc42caa 100644
> --- a/arch/arm/boot/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -163,6 +163,12 @@
> #size-cells = <1>;
> ranges;
>
> +   syscon: syscon@1c0 {
> +   compatible = "syscon",
> +   "allwinner,sun8i-a83t-system-controller";

syscon is the most generic compatible string here.
It should be the last one in the list.

Otherwise,

Reviewed-by: Chen-Yu Tsai 

> +   reg = <0x01c0 0x1000>;
> +   };
> +
> dma: dma-controller@1c02000 {
> compatible = "allwinner,sun8i-a83t-dma";
> reg = <0x01c02000 0x1000>;
> --
> 2.13.0
>

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[linux-sunxi] [PATCH 1/5] ARM: sun8i: orangepi-plus: Enable dwmac-sun8i

2017-06-05 Thread Corentin Labbe 
The dwmac-sun8i hardware is present on the Orange PI plus.
It uses an external PHY rtl8211e via RGMII.

This patch create the needed regulator, emac and phy nodes.

Signed-off-by: Corentin Labbe 
---
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
index 8c40ab7bfa72..331ed683ac62 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
@@ -47,6 +47,20 @@
model = "Xunlong Orange Pi Plus / Plus 2";
compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
 
+   aliases {
+   ethernet0 = 
+   };
+
+   reg_gmac_3v3: gmac-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "gmac-3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   enable-active-high;
+   gpio = < 3 6 GPIO_ACTIVE_HIGH>;
+   };
+
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -64,6 +78,24 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii_pins>;
+   phy-supply = <_gmac_3v3>;
+   phy-handle = <_rgmii_phy>;
+   phy-mode = "rgmii";
+
+   allwinner,leds-active-low;
+   status = "okay";
+};
+
+ {
+   ext_rgmii_phy: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <0>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_8bit_pins>;
-- 
2.13.0

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[linux-sunxi] [PATCH 5/5] ARM: sun8i: a83t: add dwmac-sun8i ethernet driver

2017-06-05 Thread Corentin Labbe 
The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000 speed.
This patch enable the dwmac-sun8i on the Allwinner a83t SoC Device-tree.

Signed-off-by: Corentin Labbe 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 28 
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index ae559dc42caa..304a966c8048 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -200,6 +200,14 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
 
+   emac_rgmii_pins: emac0-pins {
+   pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+  "PD11", "PD12", "PD13", "PD14", "PD18",
+  "PD19", "PD21", "PD22", "PD23";
+   function = "gmac";
+   drive-strength = <40>;
+   };
+
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
   "PF3", "PF4", "PF5";
@@ -266,6 +274,26 @@
status = "disabled";
};
 
+   emac: ethernet@1c3 {
+   compatible = "allwinner,sun8i-a83t-emac";
+   syscon = <>;
+   reg = <0x01c3 0x104>;
+   interrupts = ;
+   interrupt-names = "macirq";
+   resets = < 13>;
+   reset-names = "stmmaceth";
+   clocks = < 27>;
+   clock-names = "stmmaceth";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+
+   mdio: mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+   };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
reg = <0x01c81000 0x1000>,
-- 
2.13.0

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[linux-sunxi] [PATCH 0/5] ARM: sunxi: Enable dwmac-sun8i on more boards

2017-06-05 Thread Corentin Labbe 
Hello

This serie enable dwmac-sun8i on more boards.
The first 3 patch enable dwmac-sun8i on some h3/h5 boards.
The last 2 add dwmac-sun8i on a83t.

Corentin Labbe (5):
  ARM: sun8i: orangepi-plus: Enable dwmac-sun8i
  ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i
  ARM: sun50i: orangepi-pc2: Enable dwmac-sun8i
  ARM: sun8i: a83t: Add dt node for the syscon control module
  ARM: sun8i: a83t: add dwmac-sun8i ethernet driver

 arch/arm/boot/dts/sun8i-a83t.dtsi  | 34 ++
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 29 ++
 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts   | 32 
 .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 27 +
 4 files changed, 122 insertions(+)

-- 
2.13.0

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[linux-sunxi] [PATCH 4/5] ARM: sun8i: a83t: Add dt node for the syscon control module

2017-06-05 Thread Corentin Labbe 
This patch add the dt node for the syscon register present on the
Allwinner A83T

Signed-off-by: Corentin Labbe 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 1dc4cfe81534..ae559dc42caa 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -163,6 +163,12 @@
#size-cells = <1>;
ranges;
 
+   syscon: syscon@1c0 {
+   compatible = "syscon",
+   "allwinner,sun8i-a83t-system-controller";
+   reg = <0x01c0 0x1000>;
+   };
+
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a83t-dma";
reg = <0x01c02000 0x1000>;
-- 
2.13.0

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[linux-sunxi] [PATCH 3/5] ARM: sun50i: orangepi-pc2: Enable dwmac-sun8i

2017-06-05 Thread Corentin Labbe 
The dwmac-sun8i hardware is present on the Orange PI PC2.
It uses an external PHY rtl8211e via RGMII.

This patch create the needed regulator, emac and phy nodes.
Signed-off-by: Corentin Labbe 
---
 .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 27 ++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts 
b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
index dfecc17dcc92..a8296feee884 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
@@ -59,6 +59,7 @@
};
 
aliases {
+   ethernet0 = 
serial0 = 
};
 
@@ -91,6 +92,16 @@
};
};
 
+   reg_gmac_3v3: gmac-3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "gmac-3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   startup-delay-us = <10>;
+   enable-active-high;
+   gpio = < 3 6 GPIO_ACTIVE_HIGH>;
+   };
+
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
@@ -126,12 +137,28 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii_pins>;
+   phy-supply = <_gmac_3v3>;
+   phy-handle = <_rgmii_phy>;
+   phy-mode = "rgmii";
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
 };
 
+ {
+   ext_rgmii_phy: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <1>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
-- 
2.13.0

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[linux-sunxi] [PATCH 2/5] ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i

2017-06-05 Thread Corentin Labbe 
The dwmac-sun8i hardware is present on the Banana Pi M2+
It uses an external PHY rtl8211e via RGMII.

This patch create the needed regulator, emac and phy nodes.

Signed-off-by: Corentin Labbe 
---
 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 29 +
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts 
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index 883072b611fa..d756ff825116 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
 
aliases {
+   ethernet0 = 
serial0 = 
serial1 = 
};
@@ -84,6 +85,16 @@
};
};
 
+   reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ startup-delay-us = <10>;
+ enable-active-high;
+ gpio = < 3 6 GPIO_ACTIVE_HIGH>;
+   };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
@@ -104,12 +115,30 @@
status = "okay";
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_rgmii_pins>;
+   phy-supply = <_gmac_3v3>;
+   phy-handle = <_rgmii_phy>;
+   phy-mode = "rgmii";
+
+   allwinner,leds-active-low;
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
 };
 
+ {
+   ext_rgmii_phy: ethernet-phy@1 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <0>;
+   };
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin>;
-- 
2.13.0

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[linux-sunxi] Re: [PATCH] net-next: stmmac: dwmac-sun8i: ensure the EPHY is properly reseted

2017-06-05 Thread David Miller 
From: Icenowy Zheng 
Date: Mon,  5 Jun 2017 01:53:23 +0800

> The EPHY may be already enabled by bootloaders which have Ethernet
> capability (e.g. current U-Boot). Thus it should be reseted properly
> before doing the enabling sequence in the dwmac-sun8i driver, otherwise
> the EMAC reset process may fail if no cable is plugged, and then fail
> the dwmac-sun8i probing.
> 
> Tested on Orange Pi PC, One and Zero. All the boards fail to have
> dwmac-sun8i probed with "EMAC reset timeout" without cable plugged
> before, and with this fix they're now all able to successfully probe the
> EMAC without cable plugged and then use the connection after a cable is
> hot-plugged in.
> 
> Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
> Signed-off-by: Icenowy Zheng 

Applied, thanks.

Re: [linux-sunxi] [PATCH] net-next: stmmac: dwmac-sun8i: ensure the EPHY is properly reseted

2017-06-05 Thread David Miller 
From: Corentin Labbe 
Date: Mon, 5 Jun 2017 13:10:19 +0200

> On Mon, Jun 05, 2017 at 01:53:23AM +0800, Icenowy Zheng wrote:
>> The EPHY may be already enabled by bootloaders which have Ethernet
>> capability (e.g. current U-Boot). Thus it should be reseted properly
>> before doing the enabling sequence in the dwmac-sun8i driver, otherwise
>> the EMAC reset process may fail if no cable is plugged, and then fail
>> the dwmac-sun8i probing.
>> 
>> Tested on Orange Pi PC, One and Zero. All the boards fail to have
>> dwmac-sun8i probed with "EMAC reset timeout" without cable plugged
>> before, and with this fix they're now all able to successfully probe the
>> EMAC without cable plugged and then use the connection after a cable is
>> hot-plugged in.
>> 
>> Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
>> Signed-off-by: Icenowy Zheng 
> 
> Thanks for the fix.
> Tested-by: Corentin Labbe 
> 
> Since I am the writter of the file, does I have the right to:
> Acked-by: Corentin Labbe 
> or
> Reviewed-by: Corentin Labbe 
> ?

Anyone whatsoever may contribute Acked-by and Reviewed-by tags to a
patch posting.

This is all documented in Documentation/process/submitting-patches.rst

[linux-sunxi] Re: [PATCH 10/19] drm/sun4i: hdmi: Rename internal DDC clock to avoid name collision

2017-06-05 Thread Maxime Ripard 
On Sat, Jun 03, 2017 at 10:33:25PM +0800, Chen-Yu Tsai wrote:
> On Sat, Jun 3, 2017 at 3:30 AM, Maxime Ripard
>  wrote:
> > On Fri, Jun 02, 2017 at 06:10:15PM +0800, Chen-Yu Tsai wrote:
> >> The DDC parent clock on the A31 SoC is also conveniently named
> >> "hdmi-ddc", which results in a name collision when the hdmi driver
> >> registers its internal DDC divider clock.
> >>
> >> Rename the internal clock to "hdmi-ddc-divider".
> >>
> >> Signed-off-by: Chen-Yu Tsai 
> >> ---
> >>  drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c 
> >> b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> >> index e1071838f487..9a6b6243e977 100644
> >> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> >> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_ddc_clk.c
> >> @@ -125,7 +125,7 @@ static int _sun4i_ddc_create(struct sun4i_hdmi *hdmi, 
> >> struct clk *parent,
> >>   if (!ddc)
> >>   return -ENOMEM;
> >>
> >> - init.name = "hdmi-ddc";
> >> + init.name = "hdmi-ddc-divider";
> >
> > Can't we rename the CCU clock instead? Having the clock called
> > hdmi-ddc being the actual clock output on the DDC bus feels more
> > natural.
> 
> Do you have any suggestions? The manual labels the conflicting one
> in the CCU as "HDMI_DDC"...

DDC as the main CCU clock, and hdmi-ddc as the one actually generated
by the HDMI controller?

Maxime

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[linux-sunxi] Re: [PATCH v2 0/2] ARM/arm64: sunxi: convert CCU raw numbers to macros

2017-06-05 Thread Maxime Ripard 
On Mon, Jun 05, 2017 at 05:00:31PM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> This is a fixed version of my "convert CCU raw numbers to macros" series.
> Please take these instead.
> 
> Changes since v1:
> 
>   - Fixed incorrect macro name for IR reset control phandle
> 
>   - Fixed header filename typo
> 
> These are some clean up patches for 4.12. They convert raw number
> references for the CCU and R_CCU nodes, from when the CCU/R_CCU stuff
> was first added, to the defined macros in the device tree header files.
> 
> These affect the A64 and H3/H5.
> 
> These are based on our sunxi/fixes-for-4.12 branch. Once these are merged,
> I think it's time to send off pull requests for our fixes branches.

Applied both, thanks!
Maxime

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[linux-sunxi] Re: [PATCH 0/3] pinctrl: sun8i: Add support for A83T R_PIO

2017-06-05 Thread Maxime Ripard 
On Sat, Jun 03, 2017 at 10:44:24PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> This series adds support for the R_PIO pin controller on the A83T.
> The pins managed this controller are mainly used for communicating
> with the PMIC and codec, and various GPIOs for enabling power switches
> for USB ports and WiFi.
> 
> Patch 1 updates the sunxi pinctrl bindings.
> 
> Patch 2 adds the pinctrl driver.
> 
> Patch 3 adds a device node for the pin controller.

Acked-by: Maxime Ripard 

Maxime

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[linux-sunxi] [PATCH v4 3/3] ASoC: sun4i-codec: Add support for V3s codec

2017-06-05 Thread Icenowy Zheng 
From: Icenowy Zheng 

The codec in the V3s is similar to the one found on the A31. One key
difference is the analog path controls are routed through the PRCM
block. This is supported by the sun8i-codec-analog driver, and tied
into this codec driver with the audio card's aux_dev.

In addition, the V3s does not have LINEIN, LINEOUT, MBIAS and MIC2,
MIC3, and the FIFO related registers are like H3.

Signed-off-by: Icenowy Zheng 
Acked-by: Rob Herring 
---
Changes in v4:
- Added Rob's ACK.
Changes in v3:
- Change regmap max register.
- Add a note for further DAP support.

 .../devicetree/bindings/sound/sun4i-codec.txt  | 11 ++--
 sound/soc/sunxi/sun4i-codec.c  | 63 ++
 2 files changed, 70 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/sun4i-codec.txt 
b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
index 3863531d1e6d..2d4e10deb6f4 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-codec.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-codec.txt
@@ -7,6 +7,7 @@ Required properties:
- "allwinner,sun7i-a20-codec"
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+   - "allwinner,sun8i-v3s-codec"
 - reg: must contain the registers location and length
 - interrupts: must contain the codec interrupt
 - dmas: DMA channels for tx and rx dma. See the DMA client binding,
@@ -25,6 +26,7 @@ Required properties for the following compatibles:
- "allwinner,sun6i-a31-codec"
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+   - "allwinner,sun8i-v3s-codec"
 - resets: phandle to the reset control for this device
 - allwinner,audio-routing: A list of the connections between audio components.
   Each entry is a pair of strings, the first being the
@@ -34,15 +36,15 @@ Required properties for the following compatibles:
   Audio pins on the SoC:
   "HP"
   "HPCOM"
-  "LINEIN"
-  "LINEOUT"(not on sun8i-a23)
+  "LINEIN" (not on sun8i-v3s)
+  "LINEOUT"(not on sun8i-a23 or sun8i-v3s)
   "MIC1"
-  "MIC2"
+  "MIC2"   (not on sun8i-v3s)
   "MIC3"   (sun6i-a31 only)
 
   Microphone biases from the SoC:
   "HBIAS"
-  "MBIAS"
+  "MBIAS"  (not on sun8i-v3s)
 
   Board connectors:
   "Headphone"
@@ -55,6 +57,7 @@ Required properties for the following compatibles:
 Required properties for the following compatibles:
- "allwinner,sun8i-a23-codec"
- "allwinner,sun8i-h3-codec"
+   - "allwinner,sun8i-v3s-codec"
 - allwinner,codec-analog-controls: A phandle to the codec analog controls
   block in the PRCM.
 
diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
index c3aab10fa085..150069987c0c 100644
--- a/sound/soc/sunxi/sun4i-codec.c
+++ b/sound/soc/sunxi/sun4i-codec.c
@@ -1339,6 +1339,44 @@ static struct snd_soc_card 
*sun8i_h3_codec_create_card(struct device *dev)
return card;
 };
 
+static struct snd_soc_card *sun8i_v3s_codec_create_card(struct device *dev)
+{
+   struct snd_soc_card *card;
+   int ret;
+
+   card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
+   if (!card)
+   return ERR_PTR(-ENOMEM);
+
+   aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
+
"allwinner,codec-analog-controls",
+0);
+   if (!aux_dev.codec_of_node) {
+   dev_err(dev, "Can't find analog controls for codec.\n");
+   return ERR_PTR(-EINVAL);
+   };
+
+   card->dai_link = sun4i_codec_create_link(dev, >num_links);
+   if (!card->dai_link)
+   return ERR_PTR(-ENOMEM);
+
+   card->dev   = dev;
+   card->name  = "V3s Audio Codec";
+   card->dapm_widgets  = sun6i_codec_card_dapm_widgets;
+   card->num_dapm_widgets  = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
+   card->dapm_routes   = sun8i_codec_card_routes;
+   card->num_dapm_routes   = ARRAY_SIZE(sun8i_codec_card_routes);
+   card->aux_dev   = _dev;
+   card->num_aux_devs  = 1;
+   card->fully_routed  = true;
+
+   ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
+   if (ret)
+   dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
+
+   return card;
+};
+

[linux-sunxi] [PATCH v4 2/3] ASoC: sun8i-codec-analog: add support for V3s SoC

2017-06-05 Thread Icenowy Zheng 
From: Icenowy Zheng 

The V3s SoC features an analog codec with headphone support but without
mic2 and linein.

Add support for it.

Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
Changes in v4:
- Added Chen-Yu's Reviewed-By.
- Added Rob's ACK.

 Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt | 1 +
 sound/soc/sunxi/sun8i-codec-analog.c   | 9 +
 2 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt 
b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
index 779b735781ba..1b6e7c4e50ab 100644
--- a/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
+++ b/Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible: must be one of the following compatibles:
- "allwinner,sun8i-a23-codec-analog"
- "allwinner,sun8i-h3-codec-analog"
+   - "allwinner,sun8i-v3s-codec-analog"
 
 Required properties if not a sub-node of the PRCM node:
 - reg: must contain the registers location and length
diff --git a/sound/soc/sunxi/sun8i-codec-analog.c 
b/sound/soc/sunxi/sun8i-codec-analog.c
index 29c446068151..485e79f292c4 100644
--- a/sound/soc/sunxi/sun8i-codec-analog.c
+++ b/sound/soc/sunxi/sun8i-codec-analog.c
@@ -810,6 +810,11 @@ static int sun8i_codec_analog_add_mixer(struct 
snd_soc_component *cmpnt,
return 0;
 }
 
+static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = {
+   .has_headphone  = true,
+   .has_hmic   = true,
+};
+
 static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
 {
struct device *dev = cmpnt->dev;
@@ -886,6 +891,10 @@ static const struct of_device_id 
sun8i_codec_analog_of_match[] = {
.compatible = "allwinner,sun8i-h3-codec-analog",
.data = _h3_quirks,
},
+   {
+   .compatible = "allwinner,sun8i-v3s-codec-analog",
+   .data = _v3s_quirks,
+   },
{}
 };
 MODULE_DEVICE_TABLE(of, sun8i_codec_analog_of_match);
-- 
2.12.2

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[linux-sunxi] [PATCH v4 0/3] Allwinner V3s audio codec support (ASoC part)

2017-06-05 Thread Icenowy Zheng 
This is the ASoC part of the Allwinner V3s audio codec support.

The audio codec is like the ones on A23/H3, but much simpler.

As it lacks two features that used to be common (MIC2 and LINEIN),
some structures are altered to exclude these features.

Icenowy Zheng (3):
  ASoC: sun8i-codec-analog: prepare a mixer control/widget/route set for
V3s
  ASoC: sun8i-codec-analog: add support for V3s SoC
  ASoC: sun4i-codec: Add support for V3s codec

 .../devicetree/bindings/sound/sun4i-codec.txt  |  11 ++-
 .../bindings/sound/sun8i-codec-analog.txt  |   1 +
 sound/soc/sunxi/sun4i-codec.c  |  63 
 sound/soc/sunxi/sun8i-codec-analog.c   | 110 -
 4 files changed, 180 insertions(+), 5 deletions(-)

-- 
2.12.2

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[linux-sunxi] [PATCH v4 1/3] ASoC: sun8i-codec-analog: prepare a mixer control/widget/route set for V3s

2017-06-05 Thread Icenowy Zheng 
Allwinner V3s has an analog codec without MIC2 and Line In, which will
need a special set of mixer controls/widgets/routes, otherwise meaningless
controls will be exported to userspace and confuse the user.

Add the special set, and use it when the SoC has no MIC2 and Line In.

Signed-off-by: Icenowy Zheng 
---
Changes in v4:
- Added TODO comment.
- Check the return value of sun8i_codec_analog_add_mixer().

 sound/soc/sunxi/sun8i-codec-analog.c | 101 ++-
 1 file changed, 100 insertions(+), 1 deletion(-)

diff --git a/sound/soc/sunxi/sun8i-codec-analog.c 
b/sound/soc/sunxi/sun8i-codec-analog.c
index edcc3eb7cd9a..29c446068151 100644
--- a/sound/soc/sunxi/sun8i-codec-analog.c
+++ b/sound/soc/sunxi/sun8i-codec-analog.c
@@ -219,6 +219,22 @@ static const struct snd_kcontrol_new 
sun8i_codec_mixer_controls[] = {
  SUN8I_ADDA_LOMIXSC_MIC2, 1, 0),
 };
 
+/* mixer controls */
+static const struct snd_kcontrol_new sun8i_v3s_codec_mixer_controls[] = {
+   SOC_DAPM_DOUBLE_R("DAC Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACL, 1, 0),
+   SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_DACR, 1, 0),
+   SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
+ SUN8I_ADDA_LOMIXSC,
+ SUN8I_ADDA_ROMIXSC,
+ SUN8I_ADDA_LOMIXSC_MIC1, 1, 0),
+};
+
 /* ADC mixer controls */
 static const struct snd_kcontrol_new sun8i_codec_adc_mixer_controls[] = {
SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
@@ -243,6 +259,22 @@ static const struct snd_kcontrol_new 
sun8i_codec_adc_mixer_controls[] = {
  SUN8I_ADDA_LADCMIXSC_MIC2, 1, 0),
 };
 
+/* ADC mixer controls */
+static const struct snd_kcontrol_new sun8i_v3s_codec_adc_mixer_controls[] = {
+   SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRL, 1, 0),
+   SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_OMIXRR, 1, 0),
+   SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
+ SUN8I_ADDA_LADCMIXSC,
+ SUN8I_ADDA_RADCMIXSC,
+ SUN8I_ADDA_LADCMIXSC_MIC1, 1, 0),
+};
+
 /* volume / mute controls */
 static const DECLARE_TLV_DB_SCALE(sun8i_codec_out_mixer_pregain_scale,
  -450, 150, 0);
@@ -292,8 +324,9 @@ static const struct snd_soc_dapm_widget 
sun8i_codec_common_widgets[] = {
/* Mic input path */
SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN8I_ADDA_MIC1G_MICBIAS_CTRL,
 SUN8I_ADDA_MIC1G_MICBIAS_CTRL_MIC1AMPEN, 0, NULL, 0),
+};
 
-   /* Mixers */
+static const struct snd_soc_dapm_widget sun8i_codec_mixer_widgets[] = {
SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
   SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
   sun8i_codec_mixer_controls,
@@ -312,10 +345,31 @@ static const struct snd_soc_dapm_widget 
sun8i_codec_common_widgets[] = {
   ARRAY_SIZE(sun8i_codec_adc_mixer_controls)),
 };
 
+static const struct snd_soc_dapm_widget sun8i_v3s_codec_mixer_widgets[] = {
+   SND_SOC_DAPM_MIXER("Left Mixer", SUN8I_ADDA_DAC_PA_SRC,
+  SUN8I_ADDA_DAC_PA_SRC_LMIXEN, 0,
+  sun8i_v3s_codec_mixer_controls,
+  ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
+   SND_SOC_DAPM_MIXER("Right Mixer", SUN8I_ADDA_DAC_PA_SRC,
+  SUN8I_ADDA_DAC_PA_SRC_RMIXEN, 0,
+  sun8i_v3s_codec_mixer_controls,
+  ARRAY_SIZE(sun8i_v3s_codec_mixer_controls)),
+   SND_SOC_DAPM_MIXER("Left ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+  SUN8I_ADDA_ADC_AP_EN_ADCLEN, 0,
+  sun8i_v3s_codec_adc_mixer_controls,
+  ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
+   SND_SOC_DAPM_MIXER("Right ADC Mixer", SUN8I_ADDA_ADC_AP_EN,
+  SUN8I_ADDA_ADC_AP_EN_ADCREN, 0,
+  sun8i_v3s_codec_adc_mixer_controls,
+  ARRAY_SIZE(sun8i_v3s_codec_adc_mixer_controls)),
+};
+
 static const struct snd_soc_dapm_route sun8i_codec_common_routes[] = {
/* Microphone Routes */
{ "Mic1 Amplifier", NULL, "MIC1"},
+};
 
+static const struct snd_soc_dapm_route sun8i_codec_mixer_routes[] = {
/* Left Mixer Routes */
{ "Left Mixer", "DAC Playback

Re: [linux-sunxi] [PATCH 1/2] dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk

2017-06-05 Thread Chen-Yu Tsai 
On Mon, Jun 5, 2017 at 8:33 PM, Icenowy Zheng  wrote:
> From: Icenowy Zheng 
>
> Originally we enable a special gate bit when the compatible indicates
> A23/33.
>
> But according to BSP sources and user manuals, more SoCs will need this
> gate bit.
>
> So make it a common quirk configured in the config struct.
>
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Chen-Yu Tsai 

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Re: [linux-sunxi] [PATCH] net-next: stmmac: dwmac-sun8i: ensure the EPHY is properly reseted

2017-06-05 Thread Andrew Lunn 
On Mon, Jun 05, 2017 at 01:10:19PM +0200, Corentin Labbe wrote:
> On Mon, Jun 05, 2017 at 01:53:23AM +0800, Icenowy Zheng wrote:
> > The EPHY may be already enabled by bootloaders which have Ethernet
> > capability (e.g. current U-Boot). Thus it should be reseted properly
> > before doing the enabling sequence in the dwmac-sun8i driver, otherwise
> > the EMAC reset process may fail if no cable is plugged, and then fail
> > the dwmac-sun8i probing.
> > 
> > Tested on Orange Pi PC, One and Zero. All the boards fail to have
> > dwmac-sun8i probed with "EMAC reset timeout" without cable plugged
> > before, and with this fix they're now all able to successfully probe the
> > EMAC without cable plugged and then use the connection after a cable is
> > hot-plugged in.
> > 
> > Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
> > Signed-off-by: Icenowy Zheng 
> 
> Thanks for the fix.
> Tested-by: Corentin Labbe 
> 
> Since I am the writter of the file, does I have the right to:
> Acked-by: Corentin Labbe 
> or
> Reviewed-by: Corentin Labbe 

Documentation/process/submitting-patches.rst says:

If a person was not directly involved in the preparation or handling of a
patch but wishes to signify and record their approval of it then they can
ask to have an Acked-by: line added to the patch's changelog.

Acked-by: is not as formal as Signed-off-by:.  It is a record that the acker
has at least reviewed the patch and has indicated acceptance.

Nothing limits who can give an Acked-by, you just need to of done the
necessary work.

Reviewed-by: is similar.

So feel free to have either.

   Andrew

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[linux-sunxi] [PATCH 2/2] dmaengine: sun6i: support V3s SoC variant

2017-06-05 Thread Icenowy Zheng 
From: Icenowy Zheng 

Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.

Add support for it.

Signed-off-by: Icenowy Zheng 
Acked-by: Chen-Yu Tsai 
Acked-by: Rob Herring 
---
Changes since the original codec patchset v3:
- Added Rob's ACK.

 Documentation/devicetree/bindings/dma/sun6i-dma.txt |  1 +
 drivers/dma/sun6i-dma.c | 13 +
 2 files changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt 
b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
index 6b267045f522..98fbe1a5c6dd 100644
--- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
+++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
@@ -9,6 +9,7 @@ Required properties:
  "allwinner,sun8i-a23-dma"
  "allwinner,sun8i-a83t-dma"
  "allwinner,sun8i-h3-dma"
+ "allwinner,sun8i-v3s-dma"
 - reg: Should contain the registers base address and length
 - interrupts:  Should contain a reference to the interrupt used by this device
 - clocks:  Should contain a reference to the parent AHB clock
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 252b59c1d1d5..bcd496edc70f 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -1040,11 +1040,24 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
.nr_max_vchans   = 34,
 };
 
+/*
+ * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
+ * and a total of 24 usable source and destination endpoints.
+ */
+
+static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
+   .nr_max_channels = 8,
+   .nr_max_requests = 23,
+   .nr_max_vchans   = 24,
+   .gate_needed = true,
+};
+
 static const struct of_device_id sun6i_dma_match[] = {
{ .compatible = "allwinner,sun6i-a31-dma", .data = _a31_dma_cfg },
{ .compatible = "allwinner,sun8i-a23-dma", .data = _a23_dma_cfg },
{ .compatible = "allwinner,sun8i-a83t-dma", .data = _a83t_dma_cfg 
},
{ .compatible = "allwinner,sun8i-h3-dma", .data = _h3_dma_cfg },
+   { .compatible = "allwinner,sun8i-v3s-dma", .data = _v3s_dma_cfg },
{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, sun6i_dma_match);
-- 
2.12.2

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[linux-sunxi] [PATCH 0/2] Allwinner V3s DMA support

2017-06-05 Thread Icenowy Zheng 
This is a dedicated patchset of Allwinner V3s DMA support, which used
to be part of the audio codec support patchset.

It's a derivation of the DMA part of v3 of the codec patchset.

Icenowy Zheng (2):
  dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk
  dmaengine: sun6i: support V3s SoC variant

 .../devicetree/bindings/dma/sun6i-dma.txt  |  1 +
 drivers/dma/sun6i-dma.c| 33 +-
 2 files changed, 27 insertions(+), 7 deletions(-)

-- 
2.12.2

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[linux-sunxi] [PATCH 1/2] dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirk

2017-06-05 Thread Icenowy Zheng 
From: Icenowy Zheng 

Originally we enable a special gate bit when the compatible indicates
A23/33.

But according to BSP sources and user manuals, more SoCs will need this
gate bit.

So make it a common quirk configured in the config struct.

Signed-off-by: Icenowy Zheng 
---
Changes since original codec patchset v3:
- Refactored comments to cover some words found in official documents.
- Removed the comments when toggling the gate bit.

 drivers/dma/sun6i-dma.c | 20 +---
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index a2358780ab2c..252b59c1d1d5 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
@@ -101,6 +101,17 @@ struct sun6i_dma_config {
u32 nr_max_channels;
u32 nr_max_requests;
u32 nr_max_vchans;
+   /*
+* In the datasheets/user manuals of newer Allwinner SoCs, a special
+* bit (bit 2 at register 0x20) is present.
+* It's named "DMA MCLK interface circuit auto gating bit" in the
+* documents, and the footnote of this register says that this bit
+* should be set up when initializing the DMA controller.
+* Allwinner A23/A33 user manuals do not have this bit documented,
+* however these SoCs really have and need this bit, as seen in the
+* BSP kernel source code.
+*/
+   bool gate_needed;
 };
 
 /*
@@ -1009,6 +1020,7 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
.nr_max_channels = 8,
.nr_max_requests = 24,
.nr_max_vchans   = 37,
+   .gate_needed = true,
 };
 
 static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
@@ -1174,13 +1186,7 @@ static int sun6i_dma_probe(struct platform_device *pdev)
goto err_dma_unregister;
}
 
-   /*
-* sun8i variant requires us to toggle a dma gating register,
-* as seen in Allwinner's SDK. This register is not documented
-* in the A23 user manual.
-*/
-   if (of_device_is_compatible(pdev->dev.of_node,
-   "allwinner,sun8i-a23-dma"))
+   if (sdc->cfg->gate_needed)
writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE);
 
return 0;
-- 
2.12.2

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Re: [linux-sunxi] [PATCH] net-next: stmmac: dwmac-sun8i: ensure the EPHY is properly reseted

2017-06-05 Thread Corentin Labbe 
On Mon, Jun 05, 2017 at 01:53:23AM +0800, Icenowy Zheng wrote:
> The EPHY may be already enabled by bootloaders which have Ethernet
> capability (e.g. current U-Boot). Thus it should be reseted properly
> before doing the enabling sequence in the dwmac-sun8i driver, otherwise
> the EMAC reset process may fail if no cable is plugged, and then fail
> the dwmac-sun8i probing.
> 
> Tested on Orange Pi PC, One and Zero. All the boards fail to have
> dwmac-sun8i probed with "EMAC reset timeout" without cable plugged
> before, and with this fix they're now all able to successfully probe the
> EMAC without cable plugged and then use the connection after a cable is
> hot-plugged in.
> 
> Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
> Signed-off-by: Icenowy Zheng 

Thanks for the fix.
Tested-by: Corentin Labbe 

Since I am the writter of the file, does I have the right to:
Acked-by: Corentin Labbe 
or
Reviewed-by: Corentin Labbe 
?

Perhaps I need to set myself as reviewer for this file in MAINTAINERS ?
Regards

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[linux-sunxi] [PATCH v2 0/2] ARM/arm64: sunxi: convert CCU raw numbers to macros

2017-06-05 Thread Chen-Yu Tsai 
Hi Maxime,

This is a fixed version of my "convert CCU raw numbers to macros" series.
Please take these instead.

Changes since v1:

  - Fixed incorrect macro name for IR reset control phandle

  - Fixed header filename typo

These are some clean up patches for 4.12. They convert raw number
references for the CCU and R_CCU nodes, from when the CCU/R_CCU stuff
was first added, to the defined macros in the device tree header files.

These affect the A64 and H3/H5.

These are based on our sunxi/fixes-for-4.12 branch. Once these are merged,
I think it's time to send off pull requests for our fixes branches.

ChenYu

Chen-Yu Tsai (2):
  ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros
  arm64: allwinner: a64: Convert CCU raw number references to macros

 arch/arm/boot/dts/sunxi-h3-h5.dtsi|  8 +++---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 ++-
 2 files changed, 23 insertions(+), 20 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v2 2/2] arm64: allwinner: a64: Convert CCU raw number references to macros

2017-06-05 Thread Chen-Yu Tsai 
The A64 device tree file has some remnants of raw number references
to the CCU node, likely from when the CCU bindings and device tree
changes were first merged.

Convert these, and the R_CCU ones, to use the proper defined macros
from their respective device tree binding header files.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 ++-
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 166c9ef884dc..23a531c80308 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,6 +43,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 
@@ -303,8 +304,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 67>;
-   resets = < 46>;
+   clocks = < CLK_BUS_UART0>;
+   resets = < RST_BUS_UART0>;
status = "disabled";
};
 
@@ -314,8 +315,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 68>;
-   resets = < 47>;
+   clocks = < CLK_BUS_UART1>;
+   resets = < RST_BUS_UART1>;
status = "disabled";
};
 
@@ -325,8 +326,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 69>;
-   resets = < 48>;
+   clocks = < CLK_BUS_UART2>;
+   resets = < RST_BUS_UART2>;
status = "disabled";
};
 
@@ -336,8 +337,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 70>;
-   resets = < 49>;
+   clocks = < CLK_BUS_UART3>;
+   resets = < RST_BUS_UART3>;
status = "disabled";
};
 
@@ -347,8 +348,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 71>;
-   resets = < 50>;
+   clocks = < CLK_BUS_UART4>;
+   resets = < RST_BUS_UART4>;
status = "disabled";
};
 
@@ -356,8 +357,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = ;
-   clocks = < 63>;
-   resets = < 42>;
+   clocks = < CLK_BUS_I2C0>;
+   resets = < RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -367,8 +368,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = ;
-   clocks = < 64>;
-   resets = < 43>;
+   clocks = < CLK_BUS_I2C1>;
+   resets = < RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -378,8 +379,8 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = ;
-   clocks = < 65>;
-   resets = < 44>;
+   clocks = < CLK_BUS_I2C2>;
+   resets = < RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -417,7 +418,7 @@
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = ;
-   clocks = <_ccu 3>, <>, <>;
+   clocks = <_ccu CLK_APB0_PIO>, <>, <>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
-- 
2.11.0

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[linux-sunxi] [PATCH v2 1/2] ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros

2017-06-05 Thread Chen-Yu Tsai 
Now that the R_CCU device tree binding headers have been merged, we
can convert the raw number references in the device trees to use the
defined macros.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d4f600dbb7eb..5a3ce6bcf895 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -41,8 +41,10 @@
  */
 
 #include 
+#include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -574,9 +576,9 @@
 
ir: ir@01f02000 {
compatible = "allwinner,sun5i-a13-ir";
-   clocks = <_ccu 4>, <_ccu 11>;
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
clock-names = "apb", "ir";
-   resets = <_ccu 0>;
+   resets = <_ccu RST_APB0_IR>;
interrupts = ;
reg = <0x01f02000 0x40>;
status = "disabled";
@@ -586,7 +588,7 @@
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
interrupts = ;
-   clocks = <_ccu 3>, <>, <>;
+   clocks = <_ccu CLK_APB0_PIO>, <>, <>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
-- 
2.11.0

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[linux-sunxi] Re: [PATCH 2/2] arm64: allwinner: a64: Convert CCU raw number references to macros

2017-06-05 Thread kbuild test robot 
Hi Chen-Yu,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.12-rc4 next-20170602]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chen-Yu-Tsai/ARM-arm64-sunxi-convert-CCU-raw-numbers-to-macros/20170605-124326
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

   In file included from 
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts:45:0,
from 
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts:43:
>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi:46:42: fatal error: 
>> dt-bindings/clock/sun8-r-ccu.h: No such file or directory
#include 
 ^
   compilation terminated.

vim +46 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

40   * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42   * OTHER DEALINGS IN THE SOFTWARE.
43   */
44  
45  #include 
  > 46  #include 
47  #include 
48  #include 
49  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

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.config.gz
Description: application/gzip

[linux-sunxi] Re: [PATCH 0/2] ARM/arm64: sunxi: convert CCU raw numbers to macros

2017-06-05 Thread Chen-Yu Tsai 
On Mon, Jun 5, 2017 at 4:14 PM, Maxime Ripard
 wrote:
> On Mon, Jun 05, 2017 at 12:32:22PM +0800, Chen-Yu Tsai wrote:
>> Hi Maxime,
>>
>> These are some clean up patches for 4.12. They convert raw number
>> references for the CCU and R_CCU nodes, from when the CCU/R_CCU stuff
>> was first added, to the defined macros in the device tree header files.
>>
>> These affect the A64 and H3/H5.
>>
>> These are based on our sunxi/fixes-for-4.12 branch. Once these are merged,
>> I think it's time to send off pull requests for our fixes branches.
>>
>> ChenYu
>
> Applied both, thanks!
> Maxime

Argh... Could you fix the build break on patch 1? It's simply

sed -i -e 's/RST_IR/RST_APB0_IR/' arch/arm/boot/dts/sunxi-h3-h5.dtsi

Thanks
ChenYu

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[linux-sunxi] Re: [PATCH 0/2] ARM/arm64: sunxi: convert CCU raw numbers to macros

2017-06-05 Thread Maxime Ripard 
On Mon, Jun 05, 2017 at 12:32:22PM +0800, Chen-Yu Tsai wrote:
> Hi Maxime,
> 
> These are some clean up patches for 4.12. They convert raw number
> references for the CCU and R_CCU nodes, from when the CCU/R_CCU stuff
> was first added, to the defined macros in the device tree header files.
> 
> These affect the A64 and H3/H5.
> 
> These are based on our sunxi/fixes-for-4.12 branch. Once these are merged,
> I think it's time to send off pull requests for our fixes branches.
> 
> ChenYu

Applied both, thanks!
Maxime

-- 
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Embedded Linux and Kernel engineering
http://free-electrons.com

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Description: PGP signature

Re: [linux-sunxi] Re: [PATCH v6 2/9] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

2017-06-05 Thread Marc Zyngier 
On 05/06/17 08:56, Icenowy Zheng wrote:
> 
> 
> 于 2017年6月5日 GMT+08:00 下午3:53:50, Marc Zyngier  写到:
>> On 05/06/17 06:57, Chen-Yu Tsai wrote:
>>> Hi Marc,
>>>
>>> On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai  wrote:
 On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng 
>> wrote:
>
>
> 于 2017年5月22日 GMT+08:00 下午5:39:22, Marc Zyngier
>>  写到:
>> On 18/05/17 08:16, Icenowy Zheng wrote:
>>> Add support for the newly imported compatible for the A64 R_INTC
>> in
>>> irq-sunxi-nmi driver.
>>>
>>> Signed-off-by: Icenowy Zheng 
>>> ---
>>> Changes in v5:
>>> - Fix A64 R_INTC compatible.
>>>
>>>  drivers/irqchip/irq-sunxi-nmi.c | 13 +
>>>  1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-sunxi-nmi.c
>> b/drivers/irqchip/irq-sunxi-nmi.c
>>> index 668730c5cb66..5559c1d593bf 100644
>>> --- a/drivers/irqchip/irq-sunxi-nmi.c
>>> +++ b/drivers/irqchip/irq-sunxi-nmi.c
>>> @@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs
>> sun9i_reg_offs
>> = {
>>>  .enable = 0x04,
>>>  };
>>>
>>> +static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
>>> +.ctrl   = 0x0c,
>>> +.pend   = 0x10,
>>> +.enable = 0x40,
>>> +};
>>> +
>>
>> Magic values? Even if no #define is provided, a pointer to the
>> corresponding documentation would be appreciated (assuming
>> documentation
>> exists).
>
> No documents is available for A64 R_INTC.

 No code either. In Allwinner's BSP, the interrupts for the PMICs go
 through the (closed source) OpenRISC firmware, so there's no driver
 for it in the kernel.

 The registers line up with the old interrupt controller from the
>> A10,
 but it seems only the NMI interrupt is wired up.
>>>
>>> Is this OK? Or do you want Icenowy to respin a version with defines?
>>
>> Ideally, I'd like to see some #defines, but given that the rest of the
>> file is already littered with hard-coded constants, you might as well
>> do
>> the whole thing in a subsequent patch that I would merge with these two
>> patches.
> 
> Personally I think the values are self-explained (the variable
> name) and used only once in this structure.
> 
> Making defines doesn't make the code more clear.

That's where you're severely misguided. There is plenty of places in the
kernel where constants are used exactly once, and yet they have a
#define. And the reason for this is consistency. We don't deal with raw
values, we deal with named constants.

For you, this code is probably "write-only". Once it works, you'll never
go back to it. On the other hand, I get to maintain it and apply tree
wide changes as necessary. So if the code looks better *to me*, then
that's the way.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

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Re: [linux-sunxi] Re: [PATCH v6 2/9] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

2017-06-05 Thread Icenowy Zheng 


于 2017年6月5日 GMT+08:00 下午3:53:50, Marc Zyngier  写到:
>On 05/06/17 06:57, Chen-Yu Tsai wrote:
>> Hi Marc,
>> 
>> On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai  wrote:
>>> On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng 
>wrote:


 于 2017年5月22日 GMT+08:00 下午5:39:22, Marc Zyngier
> 写到:
> On 18/05/17 08:16, Icenowy Zheng wrote:
>> Add support for the newly imported compatible for the A64 R_INTC
>in
>> irq-sunxi-nmi driver.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>> Changes in v5:
>> - Fix A64 R_INTC compatible.
>>
>>  drivers/irqchip/irq-sunxi-nmi.c | 13 +
>>  1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-sunxi-nmi.c
> b/drivers/irqchip/irq-sunxi-nmi.c
>> index 668730c5cb66..5559c1d593bf 100644
>> --- a/drivers/irqchip/irq-sunxi-nmi.c
>> +++ b/drivers/irqchip/irq-sunxi-nmi.c
>> @@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs
>sun9i_reg_offs
> = {
>>  .enable = 0x04,
>>  };
>>
>> +static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
>> +.ctrl   = 0x0c,
>> +.pend   = 0x10,
>> +.enable = 0x40,
>> +};
>> +
>
> Magic values? Even if no #define is provided, a pointer to the
> corresponding documentation would be appreciated (assuming
> documentation
> exists).

 No documents is available for A64 R_INTC.
>>>
>>> No code either. In Allwinner's BSP, the interrupts for the PMICs go
>>> through the (closed source) OpenRISC firmware, so there's no driver
>>> for it in the kernel.
>>>
>>> The registers line up with the old interrupt controller from the
>A10,
>>> but it seems only the NMI interrupt is wired up.
>> 
>> Is this OK? Or do you want Icenowy to respin a version with defines?
>
>Ideally, I'd like to see some #defines, but given that the rest of the
>file is already littered with hard-coded constants, you might as well
>do
>the whole thing in a subsequent patch that I would merge with these two
>patches.

Personally I think the values are self-explained (the variable
name) and used only once in this structure.

Making defines doesn't make the code more clear.

>
>
>>  static inline void sunxi_sc_nmi_write(struct irq_chip_generic
>*gc,
> u32 off,
>>u32 val)
>>  {
>> @@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct
> device_node *node,
>>  return sunxi_sc_nmi_irq_init(node, _reg_offs);
>>  }
>>  IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi",
> sun9i_nmi_irq_init);
>> +
>> +static int __init sun50i_nmi_irq_init(struct device_node *node,
>> + struct device_node *parent)
>> +{
>> +return sunxi_sc_nmi_irq_init(node, _reg_offs);
>> +}
>> +IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc",
> sun50i_nmi_irq_init);
>>
>
> Apart from the above:
>
> Acked-by: Marc Zyngier 
>
> Let me know how you want this to be merged.
>> 
>> This, and the previous dt bindings patch, can be merged through
>whatever
>> tree irqchip drivers are merged through. Is that Jason's irqchip
>tree?
>
>I'll probably start pushing a branch with all the irqchip patches I've
>collected at some point this week, for Thomas to take into 4.13.
>
>Thanks,
>
>   M.
>-- 
>Jazz is not dead. It just smells funny...
>
>___
>linux-arm-kernel mailing list
>linux-arm-ker...@lists.infradead.org
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Re: [linux-sunxi] Re: [PATCH v6 2/9] irqchip/sunxi-nmi: add support for the NMI in A64 R_INTC

2017-06-05 Thread Marc Zyngier 
On 05/06/17 06:57, Chen-Yu Tsai wrote:
> Hi Marc,
> 
> On Mon, May 22, 2017 at 10:25 PM, Chen-Yu Tsai  wrote:
>> On Mon, May 22, 2017 at 5:41 PM, Icenowy Zheng  wrote:
>>>
>>>
>>> 于 2017年5月22日 GMT+08:00 下午5:39:22, Marc Zyngier  写到:
 On 18/05/17 08:16, Icenowy Zheng wrote:
> Add support for the newly imported compatible for the A64 R_INTC in
> irq-sunxi-nmi driver.
>
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v5:
> - Fix A64 R_INTC compatible.
>
>  drivers/irqchip/irq-sunxi-nmi.c | 13 +
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/irqchip/irq-sunxi-nmi.c
 b/drivers/irqchip/irq-sunxi-nmi.c
> index 668730c5cb66..5559c1d593bf 100644
> --- a/drivers/irqchip/irq-sunxi-nmi.c
> +++ b/drivers/irqchip/irq-sunxi-nmi.c
> @@ -56,6 +56,12 @@ static struct sunxi_sc_nmi_reg_offs sun9i_reg_offs
 = {
>  .enable = 0x04,
>  };
>
> +static struct sunxi_sc_nmi_reg_offs sun50i_reg_offs = {
> +.ctrl   = 0x0c,
> +.pend   = 0x10,
> +.enable = 0x40,
> +};
> +

 Magic values? Even if no #define is provided, a pointer to the
 corresponding documentation would be appreciated (assuming
 documentation
 exists).
>>>
>>> No documents is available for A64 R_INTC.
>>
>> No code either. In Allwinner's BSP, the interrupts for the PMICs go
>> through the (closed source) OpenRISC firmware, so there's no driver
>> for it in the kernel.
>>
>> The registers line up with the old interrupt controller from the A10,
>> but it seems only the NMI interrupt is wired up.
> 
> Is this OK? Or do you want Icenowy to respin a version with defines?

Ideally, I'd like to see some #defines, but given that the rest of the
file is already littered with hard-coded constants, you might as well do
the whole thing in a subsequent patch that I would merge with these two
patches.


>  static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc,
 u32 off,
>u32 val)
>  {
> @@ -220,3 +226,10 @@ static int __init sun9i_nmi_irq_init(struct
 device_node *node,
>  return sunxi_sc_nmi_irq_init(node, _reg_offs);
>  }
>  IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi",
 sun9i_nmi_irq_init);
> +
> +static int __init sun50i_nmi_irq_init(struct device_node *node,
> + struct device_node *parent)
> +{
> +return sunxi_sc_nmi_irq_init(node, _reg_offs);
> +}
> +IRQCHIP_DECLARE(sun50i_nmi, "allwinner,sun50i-a64-r-intc",
 sun50i_nmi_irq_init);
>

 Apart from the above:

 Acked-by: Marc Zyngier 

 Let me know how you want this to be merged.
> 
> This, and the previous dt bindings patch, can be merged through whatever
> tree irqchip drivers are merged through. Is that Jason's irqchip tree?

I'll probably start pushing a branch with all the irqchip patches I've
collected at some point this week, for Thomas to take into 4.13.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

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[linux-sunxi] Re: [PATCH 1/2] ARM: sunxi: h3-h5: Convert R_CCU raw numbers to macros

2017-06-05 Thread kbuild test robot 
Hi Chen-Yu,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.12-rc4 next-20170602]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chen-Yu-Tsai/ARM-arm64-sunxi-convert-CCU-raw-numbers-to-macros/20170605-124326
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-hisi_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/sunxi-h3-h5.dtsi:580.21-22 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

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