[linux-sunxi] [PATCH v6 4/6] dt-bindings: List devicetree binding for the CCU of Allwinner A10

2017-07-14 Thread Priit Laes 
Allwinner A10 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.

Acked-by: Rob Herring 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Priit Laes 
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index 81d0fa4..429168d 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -3,6 +3,7 @@ Allwinner Clock Control Unit Binding
 
 Required properties :
 - compatible: must contain one of the following compatibles:
+   - "allwinner,sun4i-a10-ccu"
- "allwinner,sun6i-a31-ccu"
- "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
-- 
git-series 0.9.1

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[linux-sunxi] [PATCH v6 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-14 Thread Priit Laes 
Introduce a clock controller driver for sun4i A10 and sun7i A20
series SoCs.

Signed-off-by: Priit Laes 
---
 drivers/clk/sunxi-ng/Kconfig  |   13 +-
 drivers/clk/sunxi-ng/Makefile |1 +-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +++-
 include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
 include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
 7 files changed, 1851 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 7342928..1b5cea9 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -11,6 +11,19 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
 
+config SUNXI_A10_CCU
+   bool "Support for the Allwinner A10/A20 CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_MULT
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN4I
+   default MACH_SUN7I
+   depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
+
 config SUN5I_CCU
bool "Support for the Allwinner sun5i family CCM"
default MACH_SUN5I
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0c45fa5..01e958c 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -21,6 +21,7 @@ lib-$(CONFIG_SUNXI_CCU)   += ccu_mp.o
 obj-$(CONFIG_SUN50I_A64_CCU)   += ccu-sun50i-a64.o
 obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
 obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
+obj-$(CONFIG_SUNXI_A10_CCU)+= ccu-sun4i-a10.o
 obj-$(CONFIG_SUN8I_A23_CCU)+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_A83T_CCU)   += ccu-sun8i-a83t.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c 
b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
new file mode 100644
index 000..09e97d7
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -0,0 +1,1454 @@
+/*
+ * Copyright (c) 2017 Priit Laes .
+ * Copyright (c) 2017 Maxime Ripard.
+ * Copyright (c) 2017 Jonathan Liu.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun4i-a10.h"
+
+static struct ccu_nkmp pll_core_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
+   .k  = _SUNXI_CCU_MULT(4, 2),
+   .m  = _SUNXI_CCU_DIV(0, 2),
+   .p  = _SUNXI_CCU_DIV(16, 2),
+   .common = {
+   .reg= 0x000,
+   .hw.init= CLK_HW_INIT("pll-core",
+ "hosc",
+ _nkmp_ops,
+ 0),
+   },
+};
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names.
+ */
+#define SUN4I_PLL_AUDIO_REG0x008
+static struct ccu_nm pll_audio_base_clk = {
+   .enable = BIT(31),
+   .n  = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
+   .m  = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
+   .common = {
+   .reg= 0x008,
+   .hw.init= CLK_HW_INIT("pll-audio-base",
+ "hosc",
+ _nm_ops,
+ 0),
+   },
+
+};
+
+static struct ccu_mult pll_video0_clk = {
+   .enable = BIT(31),
+   .mult   = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
+   .frac   =

[linux-sunxi] [PATCH v6 1/6] clk: sunxi-ng: div: Add support for fixed post-divider

2017-07-14 Thread Priit Laes 
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.

Signed-off-by: Priit Laes 
---
 drivers/clk/sunxi-ng/ccu_div.c | 15 +--
 drivers/clk/sunxi-ng/ccu_div.h |  3 ++-
 2 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index c0e5c10..744502a 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct 
ccu_mux_internal *mux,
 {
struct ccu_div *cd = data;
 
+   if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+   rate *= cd->fixed_post_div;
+
return divider_round_rate_parent(>common.hw, parent,
 rate, parent_rate,
 cd->div.table, cd->div.width,
@@ -62,8 +65,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
parent_rate = ccu_mux_helper_apply_prediv(>common, >mux, -1,
  parent_rate);
 
-   return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
-  cd->div.flags);
+   val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
+ cd->div.flags);
+
+   if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+   val /= cd->fixed_post_div;
+
+   return val;
 }
 
 static int ccu_div_determine_rate(struct clk_hw *hw,
@@ -86,6 +94,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long 
rate,
parent_rate = ccu_mux_helper_apply_prediv(>common, >mux, -1,
  parent_rate);
 
+   if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+   rate *= cd->fixed_post_div;
+
val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
  cd->div.flags);
 
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 08d0744..f3a5028 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -86,9 +86,10 @@ struct ccu_div_internal {
 struct ccu_div {
u32 enable;
 
-   struct ccu_div_internal div;
+   struct ccu_div_internal div;
struct ccu_mux_internal mux;
struct ccu_common   common;
+   unsigned intfixed_post_div;
 };
 
 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg,   \
-- 
git-series 0.9.1

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[linux-sunxi] [PATCH v6 3/6] dt-bindings: List devicetree binding for the CCU of Allwinner A20

2017-07-14 Thread Priit Laes 
Allwinner A20 is now driven by sunxi-ng CCU driver.

Add devicetree binding for it.

Acked-by: Rob Herring 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Priit Laes 
---
 Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index df9fad5..81d0fa4 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -4,6 +4,7 @@ Allwinner Clock Control Unit Binding
 Required properties :
 - compatible: must contain one of the following compatibles:
- "allwinner,sun6i-a31-ccu"
+   - "allwinner,sun7i-a20-ccu"
- "allwinner,sun8i-a23-ccu"
- "allwinner,sun8i-a33-ccu"
- "allwinner,sun8i-a83t-ccu"
-- 
git-series 0.9.1

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[linux-sunxi] [PATCH v6 5/6] ARM: sun7i: Convert to CCU

2017-07-14 Thread Priit Laes 
Convert sun7i-a20.dtsi to new CCU driver.

Tested on Cubietruck.

Signed-off-by: Priit Laes 
---
 arch/arm/boot/dts/sun7i-a20.dtsi | 719 +++-
 1 file changed, 84 insertions(+), 635 deletions(-)

diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 96bee77..a5ca5a8 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -46,8 +46,6 @@
 
 #include 
 #include 
-
-#include 
 #include 
 
 / {
@@ -66,9 +64,10 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
-   clocks = <_gates 36>, <_gates 43>,
-<_gates 44>, <_be0_clk>,
-<_ch1_clk>, <_gates 26>;
+   clocks = < 56>, < 60>,
+< 62>, < 144>,
+< 155>, < 140>,
+< 164>;
status = "disabled";
};
 
@@ -76,9 +75,9 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
-   clocks = <_gates 36>, <_gates 44>,
-<_be0_clk>, <_ch0_clk>,
-<_gates 26>;
+   clocks = < 56>, < 62>,
+< 144>, < 149>,
+< 140>;
status = "disabled";
};
 
@@ -86,10 +85,10 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
-   clocks = <_gates 34>, <_gates 36>,
-<_gates 44>,
-<_be0_clk>, <_ch1_clk>,
-<_gates 5>, <_gates 26>;
+   clocks = < 54>, < 56>,
+< 62>,
+< 144>, < 155>,
+< 135>, < 140>;
status = "disabled";
};
};
@@ -102,7 +101,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
-   clocks = <>;
+   clocks = < 20>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHzuV */
@@ -183,21 +182,11 @@
 
osc24M: clk@01c20050 {
#clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-osc-clk";
-   reg = <0x01c20050 0x4>;
+   compatible = "fixed-clock";
clock-frequency = <2400>;
clock-output-names = "osc24M";
};
 
-   osc3M: osc3M_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-factor-clock";
-   clock-div = <8>;
-   clock-mult = <1>;
-   clocks = <>;
-   clock-output-names = "osc3M";
-   };
-
osc32k: clk@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -205,528 +194,6 @@
clock-output-names = "osc32k";
};
 
-   pll1: clk@01c2 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-pll1-clk";
-   reg = <0x01c2 0x4>;
-   clocks = <>;
-   clock-output-names = "pll1";
-   };
-
-   pll2: clk@01c20008 {
-   #clock-cells = <1>;
-   compatible = "allwinner,sun4i-a10-pll2-clk";
-   reg = <0x01c20008 0x8>;
-   clocks = <>;
-   clock-output-names = "pll2-1x", "pll2-2x",
-"pll2-4x", "pll2-8x";
-   };
-
-   pll3: clk@01c20010 {
-   #clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-pll3-clk";
-   reg = <0x01c20010 0x4>;
-   clocks = <>;
-   clock-output-names = "pll3";
-   };
-
-   pll3x2: pll3x2_clk {
-   #clock-cells = <0>;
-   compatible = "fixed-factor-clock";
-   clocks = <>;
-   clock-div = <1>;
-

[linux-sunxi] [PATCH v6 6/6] ARM: sun4i: Convert to CCU

2017-07-14 Thread Priit Laes 
Convert sun4i-a10.dtsi to new CCU driver.

Tested on Gemei G9 tablet.

Signed-off-by: Priit Laes 
---
 arch/arm/boot/dts/sun4i-a10.dtsi | 646 +++-
 1 file changed, 73 insertions(+), 573 deletions(-)

diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 41c2579..fc23c41 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -45,7 +45,6 @@
 
 #include 
 
-#include 
 #include 
 
 / {
@@ -64,9 +63,9 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
-   clocks = <_gates 36>, <_gates 43>,
-<_gates 44>, <_be0_clk>,
-<_ch1_clk>, <_gates 26>;
+   clocks = < 56>, < 60>,
+< 62>, < 144>,
+< 155>, < 140>;
status = "disabled";
};
 
@@ -74,10 +73,11 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
-   clocks = <_gates 36>, <_gates 43>,
-<_gates 44>, <_gates 46>,
-<_be0_clk>, <_fe0_clk>, <_ch1_clk>,
-<_gates 25>, <_gates 26>;
+   clocks = < 56>, < 60>,
+< 62>, < 64>,
+< 144>, < 146>,
+< 155>, < 164>,
+< 139>, < 140>;
status = "disabled";
};
 
@@ -85,9 +85,10 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0";
-   clocks = <_gates 36>, <_gates 44>, <_gates 
46>,
-<_be0_clk>, <_fe0_clk>, <_ch0_clk>,
-<_gates 25>, <_gates 26>;
+   clocks = < 56>, < 62>,
+< 64>, < 144>,
+< 146>, < 149>,
+< 139>, < 140>;
status = "disabled";
};
 
@@ -95,11 +96,11 @@
compatible = "allwinner,simple-framebuffer",
 "simple-framebuffer";
allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
-   clocks = <_gates 34>, <_gates 36>,
-<_gates 44>, <_gates 46>,
-<_be0_clk>, <_fe0_clk>,
-<_ch1_clk>, <_gates 5>,
-<_gates 25>, <_gates 26>;
+   clocks = < 54>, < 56>,
+< 62>, < 64>,
+< 144>, < 146>,
+< 155>, < 135>,
+< 139>, < 140>;
status = "disabled";
};
};
@@ -111,7 +112,7 @@
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
-   clocks = <>;
+   clocks = < 20>;
clock-latency = <244144>; /* 8 32k periods */
operating-points = <
/* kHzuV */
@@ -167,507 +168,19 @@
#size-cells = <1>;
ranges;
 
-   /*
-* This is a dummy clock, to be used as placeholder on
-* other mux clocks when a specific parent clock is not
-* yet implemented. It should be dropped when the driver
-* is complete.
-*/
-   dummy: dummy {
-   #clock-cells = <0>;
-   compatible = "fixed-clock";
-   clock-frequency = <0>;
-   };
-
osc24M: clk@01c20050 {
#clock-cells = <0>;
-   compatible = "allwinner,sun4i-a10-osc-clk";
-   reg = <0x01c20050 0x4>;
+   compatible = "fixed-clock";
clock-frequency = <2400>;
clock-output-names = "osc24M";
};
 
-   osc3M: osc3M_clk {
-   compatible = "fixed-factor-clock";
-   #clock-cells = <0>;
-   clock-div = <8>;
-   clock-mult = <1>;
-   clocks = <>;
-

[linux-sunxi] [PATCH v6 0/6] ARM: sunxi: Convert sun4i/sun7i series SoCs to sunxi-ng CCU

2017-07-14 Thread Priit Laes 
Hi,

This serie brings A10 (sun4i) and A20 (sun7i) SoCs into the
sunxi-ng world. With this patchset we now support all the clocks
in sun4i/sun7i SoCs.

As mentioned in sun5i conversion, this is pretty much standard
stuff as most of the required clocks were already implemented in
the sunxi-ng framework.

In order to make cross-tree merges bisectable, device trees are
currently using plain numbers instead of defines.

Changes from v5:
 - Added reviewed-by tags for Wens (A10/A20 dts bindings)
 - Fix hdmi clock parents (Jonathan Liu)
 - Add missing TVE0/1 reset bits (Olliver Schinagl)
 - Fix divider clock's fixed postdivider logic again (Maxime Ripard)
 - Set CLK_SET_RATE_PARENT for main hdmi and gpu clocks (Jonathan Liu)

Changes from v4:
 - Add CLK_SET_RATE_PARENT to "sata" clock.
 - Add proper postdivider support for divider clock.

Changes from v3:
 - Add support for fixed post-divider support for DIV clocks.
 - Fix wrong clk_ops for SATA. Spotted by Jonathan Liu.
 - Use numeric values for clock indices to make merging somewhat easier
 - Create separate sun7i/a20 specific header.

Changes from v2:
 - Rename driver and relevant files to sun4i-a10-ccu.
 - Drop mmc output and sample clocks for sun4i-a10.
 - Rename CSI ISP clock to SCLK as it is called on other variants.
 - Add comment on why PLL6 is used as AHB parent.
 - Fix parents for out_a/out_b clocks.
 - Stop exporting PLL_PERIPH_SATA gate. Driver takes care of gate.
 - Rework SATA clock handling.
 - Fix ahb gate parents.
 - Simplefb clock fixes (add dependencies for HDMI/LVDS clocks).
 - Fixes for pll-ve and pll-video1 clocks pointed out by Jonathan Liu.
 - Adapt to latest upstream changes from sunxi-next.

Changes from v1:
 - Drop useless comments
 - Add support for A10 / sun4i.
 - Rename driver to sunxi-a10-a20.
 - Add previously unimplemented clocks.
 - Document the audio pll hardcoded post-divider
 - Add Acked-by: Rob Herring  on patch 4

Priit Laes (6):
  clk: sunxi-ng: div: Add support for fixed post-divider
  clk: sunxi-ng: Add sun4i/sun7i CCU driver
  dt-bindings: List devicetree binding for the CCU of Allwinner A20
  dt-bindings: List devicetree binding for the CCU of Allwinner A10
  ARM: sun7i: Convert to CCU
  ARM: sun4i: Convert to CCU

 Documentation/devicetree/bindings/clock/sunxi-ccu.txt |2 +-
 arch/arm/boot/dts/sun4i-a10.dtsi  |  646 +
 arch/arm/boot/dts/sun7i-a20.dtsi  |  719 +-
 drivers/clk/sunxi-ng/Kconfig  |   13 +-
 drivers/clk/sunxi-ng/Makefile |1 +-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.c  | 1454 ++-
 drivers/clk/sunxi-ng/ccu-sun4i-a10.h  |   61 +-
 drivers/clk/sunxi-ng/ccu_div.c|   15 +-
 drivers/clk/sunxi-ng/ccu_div.h|3 +-
 include/dt-bindings/clock/sun4i-a10-ccu.h |  200 +-
 include/dt-bindings/clock/sun7i-a20-ccu.h |   53 +-
 include/dt-bindings/reset/sun4i-a10-ccu.h |   69 +-
 12 files changed, 2025 insertions(+), 1211 deletions(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun4i-a10.h
 create mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h
 create mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h
 create mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h

base-commit: 4ca6df134847a6349620b485a3e63f00fb3bfad8
-- 
git-series 0.9.1

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Re: [linux-sunxi] [PATCH v5 2/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver

2017-07-14 Thread Priit Laes 
On Thu, Jul 13, 2017 at 09:46:57PM +0200, Olliver Schinagl wrote:
> Hey Priit,
> 
> On 07/13/17 21:23, Priit Laes wrote:
> > On Mon, Jul 10, 2017 at 11:45:32AM +0200, Olliver Schinagl wrote:
> >> Hi Pleas,
> >>
> >> again, but this time with content :)
> >>
> >> On 04-07-17 22:04, Priit Laes wrote:
> >>> Introduce a clock controller driver for sun4i A10 and sun7i A20
> >>> series SoCs.
> > [ ... ]
> >
> >>> +++ b/drivers/clk/sunxi-ng/Kconfig
> >>> @@ -11,6 +11,19 @@ config SUN50I_A64_CCU
> >>>   default ARM64 && ARCH_SUNXI
> >>>   depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
> >>>
> >>> +config SUNXI_A10_CCU
> >> I understand why you say sunXi here (it's support for both sun4i and sun7i)
> >> but then why A10, as it also supports the A20.
> >>
> >> I guess the CCU is identical on the A20 and the A10, right? Thus would it
> >> not be sensible to just call it sun4i_ccu (like we do for sun5i_ccu below?
> > No, it's not identical.
> But then saying SUNXI_A10_CCU is not correct? Since it is not identical
> on the A20? So what does the A10 stand for?

There's no easy way it supports both SUN4I_A10 and SUN7I_A20, therefore
I used SUNXI_A10 where SUNXI may indicate it's not only for SUN4I and
I'm currently keeping it as is...

[ ... ]
> >>> +/* Not present on A20 */
> >>> +static SUNXI_CCU_GATE(axi_dram_clk,  "axi-dram", "ahb",
> >>> +   0x05c, BIT(31), 0);
> >> Same here I guess, two defines make this a bit more readable.
> > You mean SUN4I_CCU_GATE? and SUN7I_CCU_GATE defines?
> > I don't think it makes things more readable...
> you think 0x05c and BIT(31) are easier to read? I'll do a pop quiz in 6
> months from now and see if you remember :p

Can you give an example on how it should be written?

> >
> >>> +
> >>> +static SUNXI_CCU_GATE(ahb_otg_clk,   "ahb-otg",  "ahb",
> > ...
> >>> +   0x060, BIT(14), CLK_IS_CRITICAL);
> >> 
> >>
> >>> +static struct ccu_reset_map sun7i_a20_ccu_resets[] = {
> >>> + [RST_USB_PHY0]  = { 0x0cc, BIT(0) },
> >>> + [RST_USB_PHY1]  = { 0x0cc, BIT(1) },
> >>> + [RST_USB_PHY2]  = { 0x0cc, BIT(2) },
> >>> + [RST_GPS]   = { 0x0d0, BIT(0) },
> >>> + [RST_DE_BE0]= { 0x104, BIT(30) },
> >>> + [RST_DE_BE1]= { 0x108, BIT(30) },
> >>> + [RST_DE_FE0]= { 0x10c, BIT(30) },
> >>> + [RST_DE_FE1]= { 0x110, BIT(30) },
> >>> + [RST_DE_MP] = { 0x114, BIT(30) },
> >>> + [RST_TCON0] = { 0x118, BIT(30) },
> >>> + [RST_TCON1] = { 0x11c, BIT(30) },
> >> You are missing the TV encoder reset:
> >> +  [RST_TVE0]  = { 0x118, BIT(29) },
> >> +  [RST_TVE1]  = { 0x11c, BIT(29) },
> >>
> >> (to match your table i did not use defines :p)
> > Where did you get this information?
> > This is not present in any datasheets I have:
> >   * A10 - 1.50
> >   * A20 - 1.4
> It is actually from the A13. In the A13 all the other bits match up. We
> know from both that TCON0 is at 0x118 with its reset at BIT(30) and
> TCON1 has its reset 0x11c. From the A13 datasheet we gather that TCON(0)
> and TV(0) are at 0x118 with RST_TV on BIT(31) and thus it is only
> logical that that for the TVE1 we have the rest at 0x11c.
> 
> But this is writing from the top of my head, I think we can also find it
> in the 3.4 sources if I recall correctly.

Thanks, added the reset bits for TVE0/1.

Päikest,
Priit :)

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[linux-sunxi] Re: [PATCH 05/11] mmc: sunxi: Support controllers that can use both old and new timings

2017-07-14 Thread Ulf Hansson 
On 14 July 2017 at 11:40, Chen-Yu Tsai  wrote:
> On Fri, Jul 14, 2017 at 5:26 PM, Ulf Hansson  wrote:
>> On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
>>> On the SoCs that introduced the new timing mode for MMC controllers,
>>> both the old (where the clock delays are set in the CCU) and new
>>> (where the clock delays are set in the MMC controller) timing modes
>>> are available, and we have to support them both. However there are
>>> two bits that control which mode is active. One is in the CCU, the
>>> other is in the MMC controller. The settings on both sides must be
>>> the same, or nothing will work.
>>>
>>> The CCU's get/set_phase callbacks return -ENOTSUPP when the new
>>> timing mode is active. This provides a way to know which mode is
>>> active on that side, and we can set the bit on the MMC controller
>>> side accordingly.
>
> Argh... I forgot to update the commit log... :(
>
>>>
>>> Signed-off-by: Chen-Yu Tsai 
>>> ---
>>>  drivers/mmc/host/sunxi-mmc.c | 34 ++
>>>  1 file changed, 30 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>> index 0fb4e4c119e1..56e45c65b52d 100644
>>> --- a/drivers/mmc/host/sunxi-mmc.c
>>> +++ b/drivers/mmc/host/sunxi-mmc.c
>>> @@ -22,6 +22,7 @@
>>>  #include 
>>>
>>>  #include 
>>> +#include 
>>
>> I don't like this. This looks like an SoC specific hack.
>>
>>>  #include 
>>>  #include 
>>>  #include 
>>> @@ -259,7 +260,7 @@ struct sunxi_mmc_cfg {
>>> /* Does DATA0 needs to be masked while the clock is updated */
>>> bool mask_data0;
>>>
>>> -   bool needs_new_timings;
>>> +   bool has_new_timings;
>>>  };
>>>
>>>  struct sunxi_mmc_host {
>>> @@ -293,6 +294,9 @@ struct sunxi_mmc_host {
>>>
>>> /* vqmmc */
>>> boolvqmmc_enabled;
>>> +
>>> +   /* timings */
>>> +   booluse_new_timings;
>>>  };
>>>
>>>  static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
>>> @@ -714,7 +718,7 @@ static int sunxi_mmc_clk_set_phase(struct 
>>> sunxi_mmc_host *host,
>>>  {
>>> int index;
>>>
>>> -   if (!host->cfg->clk_delays)
>>> +   if (host->use_new_timings)
>>> return 0;
>>>
>>> /* determine delays */
>>> @@ -765,6 +769,15 @@ static int sunxi_mmc_clk_set_rate(struct 
>>> sunxi_mmc_host *host,
>>> ios->bus_width == MMC_BUS_WIDTH_8)
>>> clock <<= 1;
>>>
>>> +   if (host->use_new_timings) {
>>> +   ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
>>
>> Can't this be solved through some other generic API/interface?
>
> The old discussion is here: https://lkml.org/lkml/2017/5/5/77
>
> It is possible to piggy back on existing API, but as Maxime mentioned
> back in the discussion, it is confusing.
>
> IIRC Mike said (via Maxime) an SoC specific call was the easy way
> to handle this. I don't think there's anything generic about this.
> Even if you could have a _set_mode callback for the clks, the modes
> would be SoC specific anyway.

Right. But it would benefit that we can keep drivers generic, as they
are using generic APIs/interfaces. I prefer that.

Anyway, let me try to dig up the earlier discussion.

Kind regards
Uffe

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[linux-sunxi] Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

2017-07-14 Thread Chen-Yu Tsai 
On Fri, Jul 14, 2017 at 5:16 PM, Ulf Hansson  wrote:
> On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
>> The register for the "new timing mode" also has bit fields for setting
>> output and sample timing phases. According to comments in Allwinner's
>> BSP kernel, the default values are good enough.
>>
>> Keep the default values already in the hardware when setting new timing
>> mode, instead of overwriting the whole register.
>>
>> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>>   controllers")
>> Signed-off-by: Chen-Yu Tsai 
>
> It looks like this change doesn't depend on anything else? Do you want
> me to pick it up for fixes and adding stable tag?

Yes, please.

ChenYu

>
> Kind regards
> Uffe
>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index d6fa2214aaae..0fb4e4c119e1 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
>> *host,
>> }
>> mmc_writel(host, REG_CLKCR, rval);
>>
>> -   if (host->cfg->needs_new_timings)
>> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
>> +   if (host->cfg->needs_new_timings) {
>> +   /* Don't touch the delay bits */
>> +   rval = mmc_readl(host, REG_SD_NTSR);
>> +   rval |= SDXC_2X_TIMING_MODE;
>> +   mmc_writel(host, REG_SD_NTSR, rval);
>> +   }
>>
>> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
>> if (ret)
>> --
>> 2.13.2
>>

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[linux-sunxi] Re: [PATCH 05/11] mmc: sunxi: Support controllers that can use both old and new timings

2017-07-14 Thread Chen-Yu Tsai 
On Fri, Jul 14, 2017 at 5:26 PM, Ulf Hansson  wrote:
> On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
>> On the SoCs that introduced the new timing mode for MMC controllers,
>> both the old (where the clock delays are set in the CCU) and new
>> (where the clock delays are set in the MMC controller) timing modes
>> are available, and we have to support them both. However there are
>> two bits that control which mode is active. One is in the CCU, the
>> other is in the MMC controller. The settings on both sides must be
>> the same, or nothing will work.
>>
>> The CCU's get/set_phase callbacks return -ENOTSUPP when the new
>> timing mode is active. This provides a way to know which mode is
>> active on that side, and we can set the bit on the MMC controller
>> side accordingly.

Argh... I forgot to update the commit log... :(

>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 34 ++
>>  1 file changed, 30 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 0fb4e4c119e1..56e45c65b52d 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -22,6 +22,7 @@
>>  #include 
>>
>>  #include 
>> +#include 
>
> I don't like this. This looks like an SoC specific hack.
>
>>  #include 
>>  #include 
>>  #include 
>> @@ -259,7 +260,7 @@ struct sunxi_mmc_cfg {
>> /* Does DATA0 needs to be masked while the clock is updated */
>> bool mask_data0;
>>
>> -   bool needs_new_timings;
>> +   bool has_new_timings;
>>  };
>>
>>  struct sunxi_mmc_host {
>> @@ -293,6 +294,9 @@ struct sunxi_mmc_host {
>>
>> /* vqmmc */
>> boolvqmmc_enabled;
>> +
>> +   /* timings */
>> +   booluse_new_timings;
>>  };
>>
>>  static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
>> @@ -714,7 +718,7 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host 
>> *host,
>>  {
>> int index;
>>
>> -   if (!host->cfg->clk_delays)
>> +   if (host->use_new_timings)
>> return 0;
>>
>> /* determine delays */
>> @@ -765,6 +769,15 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
>> *host,
>> ios->bus_width == MMC_BUS_WIDTH_8)
>> clock <<= 1;
>>
>> +   if (host->use_new_timings) {
>> +   ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
>
> Can't this be solved through some other generic API/interface?

The old discussion is here: https://lkml.org/lkml/2017/5/5/77

It is possible to piggy back on existing API, but as Maxime mentioned
back in the discussion, it is confusing.

IIRC Mike said (via Maxime) an SoC specific call was the easy way
to handle this. I don't think there's anything generic about this.
Even if you could have a _set_mode callback for the clks, the modes
would be SoC specific anyway.

ChenYu

>
>> +   if (ret) {
>> +   dev_err(mmc_dev(mmc),
>> +   "error setting new timing mode\n");
>> +   return ret;
>> +   }
>> +   }
>> +
>
> [...]
>
> Kind regards
> Uffe

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[linux-sunxi] Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

2017-07-14 Thread Ulf Hansson 
On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
>
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>   controllers")
> Signed-off-by: Chen-Yu Tsai 

It looks like this change doesn't depend on anything else? Do you want
me to pick it up for fixes and adding stable tag?

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index d6fa2214aaae..0fb4e4c119e1 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> }
> mmc_writel(host, REG_CLKCR, rval);
>
> -   if (host->cfg->needs_new_timings)
> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
> +   if (host->cfg->needs_new_timings) {
> +   /* Don't touch the delay bits */
> +   rval = mmc_readl(host, REG_SD_NTSR);
> +   rval |= SDXC_2X_TIMING_MODE;
> +   mmc_writel(host, REG_SD_NTSR, rval);
> +   }
>
> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> if (ret)
> --
> 2.13.2
>

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[linux-sunxi] [PATCH 07/11] mmc: sunxi: Add support for A83T eMMC (MMC2)

2017-07-14 Thread Chen-Yu Tsai 
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly
different. It supports a wider 8-bit bus, has a dedicated controllable
reset pin for eMMC, and a "new timing mode" which is supposed to deliver
better signals and thus better performance.

Add a compatible for this one to use the new timing mode not found in the
other controllers.

Signed-off-by: Chen-Yu Tsai 
---
 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 +
 drivers/mmc/host/sunxi-mmc.c| 8 
 2 files changed, 9 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt 
b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
index 7d53a799f140..63b57e2a10fb 100644
--- a/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
@@ -12,6 +12,7 @@ Required properties:
* "allwinner,sun4i-a10-mmc"
* "allwinner,sun5i-a13-mmc"
* "allwinner,sun7i-a20-mmc"
+   * "allwinner,sun8i-a83t-emmc"
* "allwinner,sun9i-a80-mmc"
* "allwinner,sun50i-a64-emmc"
* "allwinner,sun50i-a64-mmc"
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 7b6f5f49620e..e70065dbd50e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1113,6 +1113,13 @@ static const struct sunxi_mmc_cfg sun7i_a20_cfg = {
.can_calibrate = false,
 };
 
+static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = {
+   .idma_des_size_bits = 16,
+   .clk_delays = sunxi_mmc_clk_delays,
+   .can_calibrate = false,
+   .has_new_timings = true,
+};
+
 static const struct sunxi_mmc_cfg sun9i_a80_cfg = {
.idma_des_size_bits = 16,
.clk_delays = sun9i_mmc_clk_delays,
@@ -1137,6 +1144,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = _a13_cfg },
{ .compatible = "allwinner,sun7i-a20-mmc", .data = _a20_cfg },
+   { .compatible = "allwinner,sun8i-a83t-emmc", .data = 
_a83t_emmc_cfg },
{ .compatible = "allwinner,sun9i-a80-mmc", .data = _a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = _a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data = 
_a64_emmc_cfg },
-- 
2.13.2

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[linux-sunxi] [PATCH 06/11] mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode

2017-07-14 Thread Chen-Yu Tsai 
The MMC controller can support DDR52 transfers under the new timing
mode. According to the BSP kernel, the module clock has to be double
the card clock, regardless of the bus width. The default timings in
the hardware can be used.

This also reworks the code setting the internal divider, getting rid
of a extra conditional.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/host/sunxi-mmc.c | 30 ++
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 56e45c65b52d..7b6f5f49620e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -751,7 +751,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
 {
struct mmc_host *mmc = host->mmc;
long rate;
-   u32 rval, clock = ios->clock;
+   u32 rval, clock = ios->clock, div = 1;
int ret;
 
ret = sunxi_mmc_oclk_onoff(host, 0);
@@ -764,10 +764,21 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
if (!ios->clock)
return 0;
 
-   /* 8 bit DDR requires a higher module clock */
+   /*
+* Under the old timing mode, 8 bit DDR requires the module
+* clock to be double the card clock. Under the new timing
+* mode, all DDR modes require a doubled module clock.
+*
+* We currently only support the standard MMC DDR52 mode.
+* This block should be updated once support for other DDR
+* modes is added.
+*/
if (ios->timing == MMC_TIMING_MMC_DDR52 &&
-   ios->bus_width == MMC_BUS_WIDTH_8)
+   (host->use_new_timings ||
+ios->bus_width == MMC_BUS_WIDTH_8)) {
+   div = 2;
clock <<= 1;
+   }
 
if (host->use_new_timings) {
ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
@@ -795,15 +806,10 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
return ret;
}
 
-   /* clear internal divider */
+   /* set internal divider */
rval = mmc_readl(host, REG_CLKCR);
rval &= ~0xff;
-   /* set internal divider for 8 bit eMMC DDR, so card clock is right */
-   if (ios->timing == MMC_TIMING_MMC_DDR52 &&
-   ios->bus_width == MMC_BUS_WIDTH_8) {
-   rval |= 1;
-   rate >>= 1;
-   }
+   rval |= div - 1;
mmc_writel(host, REG_CLKCR, rval);
 
if (host->use_new_timings) {
@@ -834,7 +840,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
return ret;
 
/* And we just enabled our clock back */
-   mmc->actual_clock = rate;
+   mmc->actual_clock = rate / div;
 
return 0;
 }
@@ -1300,7 +1306,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
mmc->caps  |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
-   if (host->cfg->clk_delays)
+   if (host->cfg->clk_delays || host->use_new_timings)
mmc->caps  |= MMC_CAP_1_8V_DDR;
 
ret = mmc_of_parse(mmc);
-- 
2.13.2

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[linux-sunxi] [PATCH 02/11] clk: sunxi-ng: Add interface to query or configure MMC timing modes.

2017-07-14 Thread Chen-Yu Tsai 
Starting with the A83T SoC, Allwinner introduced a new timing mode for
its MMC clocks. The new mode changes how the MMC controller sample and
output clocks are delayed to match chip and board specifics. There are
two controls for this, one on the CCU side controlling how the clocks
behave, and one in the MMC controller controlling what inputs to take
and how to route them.

In the old mode, the MMC clock had 2 child clocks providing the output
and sample clocks, which could be delayed by a number of clock cycles
measured from the MMC clock's parent.

With the new mode, the 2 delay clocks are no longer active. Instead,
the delays and associated controls are moved into the MMC controller.
The output of the MMC clock is also halved.

The difference in how things are wired between the modes means that the
clock controls and the MMC controls must match. To achieve this in a
clear, explicit way, we introduce two functions for the MMC driver to
use: one queries the hardware for the current mode set, and the other
allows the MMC driver to request a mode.

With newer SoCs such as the A64, the old mode is all but removed. Hence
we support two variations, one where the mode can be toggled, and the
other where the clock is fixed in the new mode.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/Makefile |  1 +
 drivers/clk/sunxi-ng/ccu_common.h |  2 +
 drivers/clk/sunxi-ng/ccu_mmc_timing.c | 73 +++
 include/linux/clk/sunxi-ng.h  | 20 ++
 4 files changed, 96 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu_mmc_timing.c
 create mode 100644 include/linux/clk/sunxi-ng.h

diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 0c45fa50283d..45a5910379a5 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -1,5 +1,6 @@
 # Common objects
 lib-$(CONFIG_SUNXI_CCU)+= ccu_common.o
+lib-$(CONFIG_SUNXI_CCU)+= ccu_mmc_timing.o
 lib-$(CONFIG_SUNXI_CCU)+= ccu_reset.o
 
 # Base clock types
diff --git a/drivers/clk/sunxi-ng/ccu_common.h 
b/drivers/clk/sunxi-ng/ccu_common.h
index d6fdd7a789aa..88981e7fd978 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -23,6 +23,8 @@
 #define CCU_FEATURE_FIXED_POSTDIV  BIT(3)
 #define CCU_FEATURE_ALL_PREDIV BIT(4)
 #define CCU_FEATURE_LOCK_REG   BIT(5)
+#define CCU_FEATURE_MMC_TIMING_SWITCH  BIT(6)
+#define CCU_FEATURE_MMC_ALWAYS_NEW BIT(7)
 
 struct device_node;
 
diff --git a/drivers/clk/sunxi-ng/ccu_mmc_timing.c 
b/drivers/clk/sunxi-ng/ccu_mmc_timing.c
new file mode 100644
index ..f236a56abf48
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_mmc_timing.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+
+#define CCU_MMC_NEW_TIMING_MODEBIT(30)
+
+/**
+ * sunxi_ccu_set_mmc_timing_mode: Configure the MMC clock timing mode
+ * @clk: clock to be configured
+ * @new_mode: true for new timing mode introduced in A83T and later
+ *
+ * Returns 0 on success, -ENOTSUPP if the clock does not support
+ * switching modes.
+ */
+int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
+{
+   struct clk_hw *hw = __clk_get_hw(clk);
+   struct ccu_common *cm = hw_to_ccu_common(hw);
+   unsigned long flags;
+   u32 val;
+
+   if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
+   return -ENOTSUPP;
+
+   spin_lock_irqsave(cm->lock, flags);
+
+   val = readl(cm->base + cm->reg);
+   if (new_mode)
+   val |= CCU_MMC_NEW_TIMING_MODE;
+   else
+   val &= ~CCU_MMC_NEW_TIMING_MODE;
+   writel(val, cm->base + cm->reg);
+
+   spin_unlock_irqrestore(cm->lock, flags);
+
+   return 0;
+}
+
+/**
+ * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode
+ * @clk: clock to query
+ *
+ * Returns 0 if the clock is in old timing mode, > 0 if it is in
+ * new timing mode, and -ENOTSUPP if the clock does not support
+ * this function.
+ */
+int sunxi_ccu_get_mmc_timing_mode(struct clk *clk)
+{
+   struct clk_hw *hw = __clk_get_hw(clk);
+   struct ccu_common *cm = hw_to_ccu_common(hw);
+
+   if (cm->features & CCU_FEATURE_MMC_ALWAYS_NEW)
+   return 1;
+
+   if (!(cm->features & CCU_FEATURE_MMC_TIMING_SWITCH))
+   return -ENOTSUPP;
+
+   return !!(readl(cm->base +

[linux-sunxi] [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

2017-07-14 Thread Chen-Yu Tsai 
The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
  controllers")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/host/sunxi-mmc.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d6fa2214aaae..0fb4e4c119e1 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
}
mmc_writel(host, REG_CLKCR, rval);
 
-   if (host->cfg->needs_new_timings)
-   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
+   if (host->cfg->needs_new_timings) {
+   /* Don't touch the delay bits */
+   rval = mmc_readl(host, REG_SD_NTSR);
+   rval |= SDXC_2X_TIMING_MODE;
+   mmc_writel(host, REG_SD_NTSR, rval);
+   }
 
ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret)
-- 
2.13.2

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[linux-sunxi] [PATCH 11/11] ARM: dts: sun8i: a83t: h8homlet: Enable micro-SD card and onboard eMMC

2017-07-14 Thread Chen-Yu Tsai 
The H8 homlet has a micro-SD card slot connected to mmc0,
and onboard eMMC from FORESEE, connected to mmc2.

Signed-off-by: Chen-Yu Tsai 
---
 .../boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts   | 21 +
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts 
b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index aecdeeb368ed..7afbaa4eea8d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -43,6 +43,7 @@
 
 /dts-v1/;
 #include "sun8i-a83t.dtsi"
+#include "sunxi-common-regulators.dtsi"
 
 / {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
@@ -57,6 +58,26 @@
};
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v0>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   bus-width = <4>;
+   cd-inverted;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_8bit_emmc_pins>;
+   vmmc-supply = <_vcc3v0>;
+   bus-width = <8>;
+   non-removable;
+   cap-mmc-hw-reset;
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pb_pins>;
-- 
2.13.2

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[linux-sunxi] [PATCH 05/11] mmc: sunxi: Support controllers that can use both old and new timings

2017-07-14 Thread Chen-Yu Tsai 
On the SoCs that introduced the new timing mode for MMC controllers,
both the old (where the clock delays are set in the CCU) and new
(where the clock delays are set in the MMC controller) timing modes
are available, and we have to support them both. However there are
two bits that control which mode is active. One is in the CCU, the
other is in the MMC controller. The settings on both sides must be
the same, or nothing will work.

The CCU's get/set_phase callbacks return -ENOTSUPP when the new
timing mode is active. This provides a way to know which mode is
active on that side, and we can set the bit on the MMC controller
side accordingly.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/host/sunxi-mmc.c | 34 ++
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 0fb4e4c119e1..56e45c65b52d 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -22,6 +22,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -259,7 +260,7 @@ struct sunxi_mmc_cfg {
/* Does DATA0 needs to be masked while the clock is updated */
bool mask_data0;
 
-   bool needs_new_timings;
+   bool has_new_timings;
 };
 
 struct sunxi_mmc_host {
@@ -293,6 +294,9 @@ struct sunxi_mmc_host {
 
/* vqmmc */
boolvqmmc_enabled;
+
+   /* timings */
+   booluse_new_timings;
 };
 
 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host)
@@ -714,7 +718,7 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host 
*host,
 {
int index;
 
-   if (!host->cfg->clk_delays)
+   if (host->use_new_timings)
return 0;
 
/* determine delays */
@@ -765,6 +769,15 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
ios->bus_width == MMC_BUS_WIDTH_8)
clock <<= 1;
 
+   if (host->use_new_timings) {
+   ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
+   if (ret) {
+   dev_err(mmc_dev(mmc),
+   "error setting new timing mode\n");
+   return ret;
+   }
+   }
+
rate = clk_round_rate(host->clk_mmc, clock);
if (rate < 0) {
dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n",
@@ -793,7 +806,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
}
mmc_writel(host, REG_CLKCR, rval);
 
-   if (host->cfg->needs_new_timings) {
+   if (host->use_new_timings) {
/* Don't touch the delay bits */
rval = mmc_readl(host, REG_SD_NTSR);
rval |= SDXC_2X_TIMING_MODE;
@@ -1105,7 +1118,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
.clk_delays = NULL,
.can_calibrate = true,
.mask_data0 = true,
-   .needs_new_timings = true,
+   .has_new_timings = true,
 };
 
 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
@@ -1262,6 +1275,19 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
goto error_free_host;
}
 
+   if (host->cfg->clk_delays && host->cfg->has_new_timings) {
+   /*
+* Supports both old and new timing modes.
+* Try setting the clk to new timing mode.
+*/
+   ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
+   if (!ret)
+   host->use_new_timings = true;
+   } else if (host->cfg->has_new_timings) {
+   /* Supports new timing mode only */
+   host->use_new_timings = true;
+   }
+
mmc->ops= _mmc_ops;
mmc->max_blk_count  = 8192;
mmc->max_blk_size   = 4096;
-- 
2.13.2

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[linux-sunxi] [PATCH 01/11] ARM: dts: sun8i: a83t: Switch to CCU device tree binding macros

2017-07-14 Thread Chen-Yu Tsai 
Now that the CCU device tree binding headers have been merged, we can
use the properly named macros in the device tree, instead of raw
numbers.

Signed-off-by: Chen-Yu Tsai 
---

This patch is included as it is a pre-requisite to the other device
tree changes in this series. It is however independent, and should
be applied as a fix for 4.13-rc, not for -next, and preferably sooner
than later.

---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 21439d0aa55d..beed05e10a3b 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -44,7 +44,9 @@
 
 #include 
 
+#include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -175,8 +177,8 @@
compatible = "allwinner,sun8i-a83t-dma";
reg = <0x01c02000 0x1000>;
interrupts = ;
-   clocks = < 21>;
-   resets = < 7>;
+   clocks = < CLK_BUS_DMA>;
+   resets = < RST_BUS_DMA>;
#dma-cells = <1>;
};
 
@@ -195,7 +197,7 @@
 ,
 ;
reg = <0x01c20800 0x400>;
-   clocks = < 45>, <>, <>;
+   clocks = < CLK_BUS_PIO>, <>, <>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@@ -247,8 +249,8 @@
 "allwinner,sun8i-h3-spdif";
reg = <0x01c21000 0x400>;
interrupts = ;
-   clocks = < 44>, < 76>;
-   resets = < 32>;
+   clocks = < CLK_BUS_SPDIF>, < CLK_SPDIF>;
+   resets = < RST_BUS_SPDIF>;
clock-names = "apb", "spdif";
dmas = < 2>;
dma-names = "tx";
@@ -263,8 +265,8 @@
interrupts = ;
reg-shift = <2>;
reg-io-width = <4>;
-   clocks = < 53>;
-   resets = < 40>;
+   clocks = < CLK_BUS_UART0>;
+   resets = < RST_BUS_UART0>;
status = "disabled";
};
 
-- 
2.13.2

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[linux-sunxi] [PATCH 03/11] clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock

2017-07-14 Thread Chen-Yu Tsai 
The MMC2 clock supports a new timing mode. When the new mode is active,
the output clock rate is halved.

This patch sets the feature flag for the new timing mode, and adds
a pre-divider based on the mode bit.

Signed-off-by: Chen-Yu Tsai 
---
 drivers/clk/sunxi-ng/ccu-sun8i-a83t.c | 38 +++
 1 file changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 947f9f6e05d2..ee6688e9b361 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -418,14 +418,36 @@ static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", 
"mmc1",
 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
   0x08c, 8, 3, 0);
 
-/* TODO Support MMC2 clock's new timing mode. */
-static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
- 0x090,
- 0, 4, /* M */
- 16, 2,/* P */
- 24, 2,/* mux */
- BIT(31),  /* gate */
- 0);
+/*
+ * MMC2 supports both old and new timing modes. When the new timing
+ * mode is active, the output clock rate is halved by two. Here we
+ * treat it as a variable pre-divider. Note that the pre-divider is
+ * _not_ included in the possible factors during a set clock rate
+ * operation. It is only read out.
+ */
+static const struct ccu_mux_var_prediv mmc2_new_timing_predivs[] = {
+   { .index = 0, .shift = 30, .width = 1 },
+   { .index = 1, .shift = 30, .width = 1 },
+};
+static struct ccu_mp mmc2_clk = {
+   .enable = BIT(31),
+   .m  = _SUNXI_CCU_DIV(0, 4),
+   .p  = _SUNXI_CCU_DIV(16, 2),
+   .mux= {
+   .shift  = 24,
+   .width  = 2,
+   .var_predivs= mmc2_new_timing_predivs,
+   .n_var_predivs  = ARRAY_SIZE(mmc2_new_timing_predivs),
+   },
+   .common = {
+   .reg= 0x090,
+   .features   = CCU_FEATURE_MMC_TIMING_SWITCH,
+   .hw.init= CLK_HW_INIT_PARENTS("mmc2",
+ mod0_default_parents,
+ _mp_ops,
+ CLK_GET_RATE_NOCACHE),
+   },
+};
 
 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
   0x090, 20, 3, 0);
-- 
2.13.2

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[linux-sunxi] [PATCH 10/11] ARM: dts: sun8i: a83t: cubietruck-plus: Enable micro-SD card and eMMC

2017-07-14 Thread Chen-Yu Tsai 
Now that we support the MMC controllers on the A83T SoC, we can enable
them on some boards.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts | 27 
 1 file changed, 27 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts 
b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index cff33454fc24..163ddf8868b5 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -83,6 +83,13 @@
};
};
 
+   reg_vcc3v3: vcc3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
@@ -102,6 +109,26 @@
};
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <4>;
+   cd-gpios = < 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+   cd-inverted;
+   status = "okay";
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_8bit_emmc_pins>;
+   vmmc-supply = <_vcc3v3>;
+   bus-width = <8>;
+   non-removable;
+   cap-mmc-hw-reset;
+   status = "okay";
+};
+
  {
status = "okay";
 };
-- 
2.13.2

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[linux-sunxi] [PATCH 08/11] ARM: dts: sun8i: a83t: Add MMC controller device nodes

2017-07-14 Thread Chen-Yu Tsai 
The A83T has 3 MMC controllers. The third one is a bit special, as it
supports a wider 8-bit bus, and a "new timing mode".

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 57 +++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index beed05e10a3b..085312d0c521 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -182,6 +182,63 @@
#dma-cells = <1>;
};
 
+   mmc0: mmc@1c0f000 {
+   compatible = "allwinner,sun7i-a20-mmc";
+   reg = <0x01c0f000 0x1000>;
+   clocks = < CLK_BUS_MMC0>,
+< CLK_MMC0>,
+< CLK_MMC0_OUTPUT>,
+< CLK_MMC0_SAMPLE>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = < RST_BUS_MMC0>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc1: mmc@1c1 {
+   compatible = "allwinner,sun7i-a20-mmc";
+   reg = <0x01c1 0x1000>;
+   clocks = < CLK_BUS_MMC1>,
+< CLK_MMC1>,
+< CLK_MMC1_OUTPUT>,
+< CLK_MMC1_SAMPLE>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = < RST_BUS_MMC1>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
+   mmc2: mmc@1c11000 {
+   compatible = "allwinner,sun8i-a83t-emmc";
+   reg = <0x01c11000 0x1000>;
+   clocks = < CLK_BUS_MMC2>,
+< CLK_MMC2>,
+< CLK_MMC2_OUTPUT>,
+< CLK_MMC2_SAMPLE>;
+   clock-names = "ahb",
+ "mmc",
+ "output",
+ "sample";
+   resets = < RST_BUS_MMC2>;
+   reset-names = "ahb";
+   interrupts = ;
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
ccu: clock@1c2 {
compatible = "allwinner,sun8i-a83t-ccu";
reg = <0x01c2 0x400>;
-- 
2.13.2

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[linux-sunxi] [PATCH 09/11] ARM: dts: sun8i: a83t: Add pingroup for 8-bit eMMC on mmc2

2017-07-14 Thread Chen-Yu Tsai 
mmc2 can support 8-bit eMMC chips, with a dedicated reset line.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 085312d0c521..b1198d80873e 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -269,6 +269,15 @@
bias-pull-up;
};
 
+   mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
+   pins = "PC5", "PC6", "PC8", "PC9",
+  "PC10", "PC11", "PC12", "PC13",
+  "PC14", "PC15", "PC16";
+   function = "mmc2";
+   drive-strength = <30>;
+   bias-pull-up;
+   };
+
spdif_tx_pin: spdif-tx-pin {
pins = "PE18";
function = "spdif";
-- 
2.13.2

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