[linux-sunxi] [PATCH 1/2] dt-bindings: add compatible string for Allwinner V3s SoC

2017-08-19 Thread Icenowy Zheng 
The compatible string for Allwinner V3s SoC used to be missing.

Add it to the binding document.

Fixes: b074fede01c0 ("arm: sunxi: add support for V3s SoC")
Signed-off-by: Icenowy Zheng 
---
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index d2c46449b4eb..f35c6ada5a65 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
+  allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
   nextthing,gr8
-- 
2.13.0

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[linux-sunxi] [PATCH 2/2] ARM: sunxi: add support for R40 SoC

2017-08-19 Thread Icenowy Zheng 
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
 Documentation/arm/sunxi/README  | 6 ++
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c | 1 +
 3 files changed, 8 insertions(+)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index d7b1f016bd62..4fa836782e46 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -75,6 +75,12 @@ SunXi family
 + Datasheet
   http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
 
+  - Allwinner R40 (sun8i)
++ Datasheet
+  https://github.com/tinalinux/docs/raw/r40-v1.y/R40_Datasheet_V1.0.pdf
++ User Manual
+  
https://github.com/tinalinux/docs/raw/r40-v1.y/Allwinner_R40_User_Manual_V1.0.pdf
+
 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
   - Allwinner A80
 + Datasheet
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt 
b/Documentation/devicetree/bindings/arm/sunxi.txt
index f35c6ada5a65..e4beec3d9ad3 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -14,6 +14,7 @@ using one of the following compatible strings:
   allwinner,sun8i-a83t
   allwinner,sun8i-h2-plus
   allwinner,sun8i-h3
+  allwinner-sun8i-r40
   allwinner,sun8i-v3s
   allwinner,sun9i-a80
   allwinner,sun50i-a64
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 7ab353fb25f2..311e6c4fc4f4 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -66,6 +66,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
"allwinner,sun8i-v3s",
+   "allwinner,sun8i-r40",
NULL,
 };
 
-- 
2.13.0

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[linux-sunxi] Re: [PATCH] ARM: sun8i: a83t: Add device tree for Sinovoip Bananapi BPI-M3

2017-08-19 Thread kbuild test robot 
Hi Chen-Yu,

[auto build test ERROR on robh/for-next]
[also build test ERROR on v4.13-rc5 next-20170817]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chen-Yu-Tsai/ARM-sun8i-a83t-Add-device-tree-for-Sinovoip-Bananapi-BPI-M3/20170820-055904
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts:64.1-7 Label or path 
>> ehci0 not found
>> Error: arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts:71.1-6 Label or path 
>> mmc0 not found
>> Error: arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts:81.1-6 Label or path 
>> mmc2 not found
>> Error: arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts:91.1-7 Label or path 
>> r_rsb not found
>> Error: arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts:145.1-8 Label or path 
>> usbphy not found
   FATAL ERROR: Syntax error parsing input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation

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.config.gz
Description: application/gzip

Re: [linux-sunxi] [PATCH v5 5/8] ASoC: sun4i-i2s: Add regmap field to set DAI format

2017-08-19 Thread Chen-Yu Tsai 
On Sat, Aug 19, 2017 at 8:48 PM,   wrote:
> From: Marcus Cooper 
>
> On the newer SoCs the bits to configure the operational mode are
> located in a different register. Add a regmap field so that this
> location can be configured.
>
> Signed-off-by: Marcus Cooper 

Reviewed-by: Chen-Yu Tsai 

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Re: [linux-sunxi] [PATCH v5 4/8] ASoC: sun4i-i2s: Add mclk enable regmap field

2017-08-19 Thread Chen-Yu Tsai 
On Sat, Aug 19, 2017 at 8:48 PM,   wrote:
> From: Marcus Cooper 
>
> The location of the mclk output enable bit is different on newer
> SoCs. Use a regmap field to enable it.
>
> Signed-off-by: Marcus Cooper 

Reviewed-by: Chen-Yu Tsai 

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Re: [linux-sunxi] [PATCH v5 1/8] ASoC: sun4i-i2s: Add regmap fields for channels

2017-08-19 Thread Chen-Yu Tsai 
On Sat, Aug 19, 2017 at 8:48 PM,   wrote:
> From: Marcus Cooper 
>
> On the original i2s block the channel mapping and selection were
> configured for stereo audio by default: This is not the case with
> the newer SoCs and they are also located at different offsets.
>
> To support the newer SoC then regmap fields have been added to the
> quirks and these are initialised to their correct settings during
> probing.
>
> Signed-off-by: Marcus Cooper 
> Reviewed-by: Chen-Yu Tsai 

Reviewed-by still stands.

> ---
>  sound/soc/sunxi/sun4i-i2s.c | 77 
> -
>  1 file changed, 69 insertions(+), 8 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c

[...]

> +static int sun4i_i2s_init_regmap_fields(struct device *dev,
> +   struct sun4i_i2s *i2s)
> +{
> +   i2s->field_txchanmap =
> +   devm_regmap_field_alloc(dev, i2s->regmap,
> +   
> i2s->variant->field_txchanmap);
> +   if (IS_ERR(i2s->field_txchanmap))
> +   return PTR_ERR(i2s->field_txchanmap);
> +
> +   i2s->field_rxchanmap =
> +   devm_regmap_field_alloc(dev, i2s->regmap,
> +   
> i2s->variant->field_rxchanmap);
> +   if (IS_ERR(i2s->field_rxchanmap))
> +   return PTR_ERR(i2s->field_rxchanmap);
> +
> +   i2s->field_txchansel =
> +   devm_regmap_field_alloc(dev, i2s->regmap,
> +   
> i2s->variant->field_txchansel);
> +   if (IS_ERR(i2s->field_txchansel))
> +   return PTR_ERR(i2s->field_txchansel);
> +
> +   i2s->field_rxchansel =
> +   devm_regmap_field_alloc(dev, i2s->regmap,
> +   
> i2s->variant->field_rxchansel);
> +   return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
> +}
> +

That's much better. Thanks!

ChenYu

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Re: [linux-sunxi] [PATCH v5 3/8] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

2017-08-19 Thread Chen-Yu Tsai 
On Sat, Aug 19, 2017 at 8:48 PM,   wrote:
> From: Marcus Cooper 
>
> On newer SoCs the bit fields for the blck and lrclk polarity are in
> a different locations. Use regmap fields to set the polarity bits
> as intended.
>
> Signed-off-by: Marcus Cooper 

Reviewed-by: Chen-Yu Tsai 

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[linux-sunxi] [PATCH v5 5/8] ASoC: sun4i-i2s: Add regmap field to set DAI format

2017-08-19 Thread codekipper 
From: Marcus Cooper 

On the newer SoCs the bits to configure the operational mode are
located in a different register. Add a regmap field so that this
location can be configured.

Signed-off-by: Marcus Cooper 
---
 sound/soc/sunxi/sun4i-i2s.c | 15 ---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 761b7c0f6a32..d9910f6617ad 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -106,6 +106,7 @@
  * @field_fmt_sr: regmap field to set sample resolution.
  * @field_fmt_bclk: regmap field to set clk polarity.
  * @field_fmt_lrclk: regmap field to set frame polarity.
+ * @field_fmt_mode: regmap field to set the operational mode.
  * @field_txchanmap: location of the tx channel mapping register.
  * @field_rxchanmap: location of the rx channel mapping register.
  * @field_txchansel: location of the tx channel select bit fields.
@@ -125,6 +126,7 @@ struct sun4i_i2s_quirks {
struct reg_fieldfield_fmt_sr;
struct reg_fieldfield_fmt_bclk;
struct reg_fieldfield_fmt_lrclk;
+   struct reg_fieldfield_fmt_mode;
struct reg_fieldfield_txchanmap;
struct reg_fieldfield_rxchanmap;
struct reg_fieldfield_txchansel;
@@ -148,6 +150,7 @@ struct sun4i_i2s {
struct regmap_field *field_fmt_sr;
struct regmap_field *field_fmt_bclk;
struct regmap_field *field_fmt_lrclk;
+   struct regmap_field *field_fmt_mode;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -365,9 +368,7 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, 
unsigned int fmt)
return -EINVAL;
}
 
-   regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
-  SUN4I_I2S_FMT0_FMT_MASK,
-  val);
+   regmap_field_write(i2s->field_fmt_mode, val);
 
/* DAI clock polarity */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
@@ -722,6 +723,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = 
{
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk= REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+   .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -737,6 +739,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = 
{
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk= REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+   .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -776,6 +779,12 @@ static int sun4i_i2s_init_regmap_fields(struct device *dev,
if (IS_ERR(i2s->field_fmt_lrclk))
return PTR_ERR(i2s->field_fmt_lrclk);
 
+   i2s->field_fmt_mode =
+   devm_regmap_field_alloc(dev, i2s->regmap,
+   i2s->variant->field_fmt_mode);
+   if (IS_ERR(i2s->field_fmt_mode))
+   return PTR_ERR(i2s->field_fmt_mode);
+
i2s->field_txchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_txchanmap);
-- 
2.14.1

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[linux-sunxi] [PATCH v5 4/8] ASoC: sun4i-i2s: Add mclk enable regmap field

2017-08-19 Thread codekipper 
From: Marcus Cooper 

The location of the mclk output enable bit is different on newer
SoCs. Use a regmap field to enable it.

Signed-off-by: Marcus Cooper 
---
 sound/soc/sunxi/sun4i-i2s.c | 16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 8c7ad5bfe821..761b7c0f6a32 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -101,6 +101,7 @@
  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
  * @fmt_offset: Value by which wss and sr needs to be adjusted.
+ * @field_clkdiv_mclk_en: regmap field to enable mclk output.
  * @field_fmt_wss: regmap field to set word select size.
  * @field_fmt_sr: regmap field to set sample resolution.
  * @field_fmt_bclk: regmap field to set clk polarity.
@@ -119,6 +120,7 @@ struct sun4i_i2s_quirks {
unsigned intfmt_offset;
 
/* Register fields for i2s */
+   struct reg_fieldfield_clkdiv_mclk_en;
struct reg_fieldfield_fmt_wss;
struct reg_fieldfield_fmt_sr;
struct reg_fieldfield_fmt_bclk;
@@ -141,6 +143,7 @@ struct sun4i_i2s {
struct snd_dmaengine_dai_dma_data   playback_dma_data;
 
/* Register fields for i2s */
+   struct regmap_field *field_clkdiv_mclk_en;
struct regmap_field *field_fmt_wss;
struct regmap_field *field_fmt_sr;
struct regmap_field *field_fmt_bclk;
@@ -283,8 +286,9 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
 
regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
-SUN4I_I2S_CLK_DIV_MCLK(mclk_div) |
-SUN4I_I2S_CLK_DIV_MCLK_EN);
+SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
+
+   regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 
return 0;
 }
@@ -713,6 +717,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = 
{
.has_reset  = false,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss  = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
@@ -727,6 +732,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = 
{
.has_reset  = true,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
.field_fmt_wss  = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
@@ -740,6 +746,12 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks 
= {
 static int sun4i_i2s_init_regmap_fields(struct device *dev,
struct sun4i_i2s *i2s)
 {
+   i2s->field_clkdiv_mclk_en =
+   devm_regmap_field_alloc(dev, i2s->regmap,
+   i2s->variant->field_clkdiv_mclk_en);
+   if (IS_ERR(i2s->field_clkdiv_mclk_en))
+   return PTR_ERR(i2s->field_clkdiv_mclk_en);
+
i2s->field_fmt_wss =
devm_regmap_field_alloc(dev, i2s->regmap,
i2s->variant->field_fmt_wss);
-- 
2.14.1

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[linux-sunxi] [PATCH v5 6/8] ASoC: sun4i-i2s: Check for slave select bit

2017-08-19 Thread codekipper 
From: Marcus Cooper 

The newer SoCs do not have this setting. Instead they set the pin
direction. Add a check to see if the bit is valid and if so set
it accordingly.

Signed-off-by: Marcus Cooper 
Reviewed-by: Chen-Yu Tsai 
---
 sound/soc/sunxi/sun4i-i2s.c | 37 +
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index d9910f6617ad..573acca24a2c 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -96,6 +96,7 @@
  * struct sun4i_i2s_quirks - Differences between SoC variants.
  *
  * @has_reset: SoC needs reset deasserted.
+ * @has_slave_select_bit: SoC has a bit to enable slave mode.
  * @reg_offset_txdata: offset of the tx fifo.
  * @sun4i_i2s_regmap: regmap config to use.
  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
@@ -114,6 +115,7 @@
  */
 struct sun4i_i2s_quirks {
boolhas_reset;
+   boolhas_slave_select_bit;
unsigned intreg_offset_txdata;  /* TX FIFO */
const struct regmap_config  *sun4i_i2s_regmap;
unsigned intmclk_offset;
@@ -394,24 +396,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, 
unsigned int fmt)
regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 
-   /* DAI clock master masks */
-   switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
-   case SND_SOC_DAIFMT_CBS_CFS:
-   /* BCLK and LRCLK master */
-   val = SUN4I_I2S_CTRL_MODE_MASTER;
-   break;
-   case SND_SOC_DAIFMT_CBM_CFM:
-   /* BCLK and LRCLK slave */
-   val = SUN4I_I2S_CTRL_MODE_SLAVE;
-   break;
-   default:
-   return -EINVAL;
+   if (i2s->variant->has_slave_select_bit) {
+   /* DAI clock master masks */
+   switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+   case SND_SOC_DAIFMT_CBS_CFS:
+   /* BCLK and LRCLK master */
+   val = SUN4I_I2S_CTRL_MODE_MASTER;
+   break;
+   case SND_SOC_DAIFMT_CBM_CFM:
+   /* BCLK and LRCLK slave */
+   val = SUN4I_I2S_CTRL_MODE_SLAVE;
+   break;
+   default:
+   return -EINVAL;
+   }
+   regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+  SUN4I_I2S_CTRL_MODE_MASK,
+  val);
}
 
-   regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
-  SUN4I_I2S_CTRL_MODE_MASK,
-  val);
-
/* Set significant bits in our FIFOs */
regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
   SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
@@ -723,6 +726,7 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = 
{
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk= REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+   .has_slave_select_bit   = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
@@ -739,6 +743,7 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = 
{
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
.field_fmt_lrclk= REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
+   .has_slave_select_bit   = true,
.field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
-- 
2.14.1

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[linux-sunxi] [PATCH v5 3/8] ASoC: sun4i-i2s: bclk and lrclk polarity tidyup

2017-08-19 Thread codekipper 
From: Marcus Cooper 

On newer SoCs the bit fields for the blck and lrclk polarity are in
a different locations. Use regmap fields to set the polarity bits
as intended.

Signed-off-by: Marcus Cooper 
---
 sound/soc/sunxi/sun4i-i2s.c | 45 -
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 563de785d639..8c7ad5bfe821 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -50,6 +50,8 @@
 #define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
 #define SUN4I_I2S_FMT0_FMT_LEFT_J  (1 << 0)
 #define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
+#define SUN4I_I2S_FMT0_POLARITY_INVERTED   (1)
+#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
 
 #define SUN4I_I2S_FMT1_REG 0x08
 #define SUN4I_I2S_FIFO_TX_REG  0x0c
@@ -101,6 +103,8 @@
  * @fmt_offset: Value by which wss and sr needs to be adjusted.
  * @field_fmt_wss: regmap field to set word select size.
  * @field_fmt_sr: regmap field to set sample resolution.
+ * @field_fmt_bclk: regmap field to set clk polarity.
+ * @field_fmt_lrclk: regmap field to set frame polarity.
  * @field_txchanmap: location of the tx channel mapping register.
  * @field_rxchanmap: location of the rx channel mapping register.
  * @field_txchansel: location of the tx channel select bit fields.
@@ -117,6 +121,8 @@ struct sun4i_i2s_quirks {
/* Register fields for i2s */
struct reg_fieldfield_fmt_wss;
struct reg_fieldfield_fmt_sr;
+   struct reg_fieldfield_fmt_bclk;
+   struct reg_fieldfield_fmt_lrclk;
struct reg_fieldfield_txchanmap;
struct reg_fieldfield_rxchanmap;
struct reg_fieldfield_txchansel;
@@ -137,6 +143,8 @@ struct sun4i_i2s {
/* Register fields for i2s */
struct regmap_field *field_fmt_wss;
struct regmap_field *field_fmt_sr;
+   struct regmap_field *field_fmt_bclk;
+   struct regmap_field *field_fmt_lrclk;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -335,6 +343,8 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, 
unsigned int fmt)
 {
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
u32 val;
+   u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
+   u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 
/* DAI Mode */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -359,32 +369,25 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, 
unsigned int fmt)
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_IB_IF:
/* Invert both clocks */
-   val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
-   SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED;
+   bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
+   lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_IB_NF:
/* Invert bit clock */
-   val = SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED |
-   SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
+   bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_IF:
/* Invert frame clock */
-   val = SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED |
-   SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL;
+   lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
break;
case SND_SOC_DAIFMT_NB_NF:
-   /* Nothing to do for both normal cases */
-   val = SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL |
-   SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL;
break;
default:
return -EINVAL;
}
 
-   regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
-  SUN4I_I2S_FMT0_BCLK_POLARITY_MASK |
-  SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK,
-  val);
+   regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
+   regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 
/* DAI clock master masks */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
@@ -712,6 +715,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = 
{
.sun4i_i2s_regmap   = _i2s_regmap_config,
.field_fmt_wss  = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
.field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
+   .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
+   .field_fmt_lrclk=

[linux-sunxi] [PATCH v5 7/8] ASoC: sun4i-i2s: Update global enable with bitmask

2017-08-19 Thread codekipper 
From: Marcus Cooper 

The default value of the config register is different on newer
SoCs and therefore enabling/disabling with a register write
will clear bits used to set the direction of the clock and frame
pins.

Signed-off-by: Marcus Cooper 
Reviewed-by: Chen-Yu Tsai 
---
 sound/soc/sunxi/sun4i-i2s.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 573acca24a2c..19d50ca10d1f 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -529,8 +529,8 @@ static int sun4i_i2s_startup(struct snd_pcm_substream 
*substream,
struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 
/* Enable the whole hardware block */
-   regmap_write(i2s->regmap, SUN4I_I2S_CTRL_REG,
-SUN4I_I2S_CTRL_GL_EN);
+   regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+  SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 
/* Enable the first output line */
regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
@@ -553,7 +553,8 @@ static void sun4i_i2s_shutdown(struct snd_pcm_substream 
*substream,
   SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 
/* Disable the whole hardware block */
-   regmap_write(i2s->regmap, SUN4I_I2S_CTRL_REG, 0);
+   regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
+  SUN4I_I2S_CTRL_GL_EN, 0);
 }
 
 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
-- 
2.14.1

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[linux-sunxi] [PATCH v5 2/8] ASoC: sun4i-i2s: Add regfields for word size select and sample resolution

2017-08-19 Thread codekipper 
From: Marcus Cooper 

On newer SoCs the location of the slot width select and sample
resolution are different and also there is a bigger range of
support.

For the current supported rates then an offset is required.

Signed-off-by: Marcus Cooper 
Reviewed-by: Chen-Yu Tsai 
---
 sound/soc/sunxi/sun4i-i2s.c | 31 ---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 87feb5a14cff..563de785d639 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -98,6 +98,9 @@
  * @sun4i_i2s_regmap: regmap config to use.
  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
+ * @fmt_offset: Value by which wss and sr needs to be adjusted.
+ * @field_fmt_wss: regmap field to set word select size.
+ * @field_fmt_sr: regmap field to set sample resolution.
  * @field_txchanmap: location of the tx channel mapping register.
  * @field_rxchanmap: location of the rx channel mapping register.
  * @field_txchansel: location of the tx channel select bit fields.
@@ -109,8 +112,11 @@ struct sun4i_i2s_quirks {
const struct regmap_config  *sun4i_i2s_regmap;
unsigned intmclk_offset;
unsigned intbclk_offset;
+   unsigned intfmt_offset;
 
/* Register fields for i2s */
+   struct reg_fieldfield_fmt_wss;
+   struct reg_fieldfield_fmt_sr;
struct reg_fieldfield_txchanmap;
struct reg_fieldfield_rxchanmap;
struct reg_fieldfield_txchansel;
@@ -129,6 +135,8 @@ struct sun4i_i2s {
struct snd_dmaengine_dai_dma_data   playback_dma_data;
 
/* Register fields for i2s */
+   struct regmap_field *field_fmt_wss;
+   struct regmap_field *field_fmt_sr;
struct regmap_field *field_txchanmap;
struct regmap_field *field_rxchanmap;
struct regmap_field *field_txchansel;
@@ -314,9 +322,10 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream 
*substream,
return -EINVAL;
}
 
-   regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
-  SUN4I_I2S_FMT0_WSS_MASK | SUN4I_I2S_FMT0_SR_MASK,
-  SUN4I_I2S_FMT0_WSS(wss) | SUN4I_I2S_FMT0_SR(sr));
+   regmap_field_write(i2s->field_fmt_wss,
+  wss + i2s->variant->fmt_offset);
+   regmap_field_write(i2s->field_fmt_sr,
+  sr + i2s->variant->fmt_offset);
 
return sun4i_i2s_set_clk_rate(i2s, params_rate(params),
  params_width(params));
@@ -701,6 +710,8 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = 
{
.has_reset  = false,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_fmt_wss  = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+   .field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -711,6 +722,8 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = 
{
.has_reset  = true,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_fmt_wss  = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
+   .field_fmt_sr   = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
.field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
.field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
.field_txchansel= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
@@ -720,6 +733,18 @@ static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks 
= {
 static int sun4i_i2s_init_regmap_fields(struct device *dev,
struct sun4i_i2s *i2s)
 {
+   i2s->field_fmt_wss =
+   devm_regmap_field_alloc(dev, i2s->regmap,
+   i2s->variant->field_fmt_wss);
+   if (IS_ERR(i2s->field_fmt_wss))
+   return PTR_ERR(i2s->field_fmt_wss);
+
+   i2s->field_fmt_sr =
+   devm_regmap_field_alloc(dev, i2s->regmap,
+   i2s->variant->field_fmt_sr);
+   if (IS_ERR(i2s->field_fmt_sr))
+   return PTR_ERR(i2s->field_fmt_sr);
+
i2s->field_txchanmap =
devm_regmap_field_alloc(dev, i2s->regmap,

[linux-sunxi] [PATCH v5 8/8] ASoC: sun4i-i2s: Add support for H3

2017-08-19 Thread codekipper 
From: Marcus Cooper 

The sun8i-h3 introduces a lot of changes to the i2s block such
as different register locations, extended clock division and
more operational modes. As we have to consider the earlier
implementation then these changes need to be isolated.

None of the new functionality has been implemented yet, the
driver has just been expanded to allow it work on the H3 SoC.

Signed-off-by: Marcus Cooper 
Reviewed-by: Chen-Yu Tsai 
---
 .../devicetree/bindings/sound/sun4i-i2s.txt|   2 +
 sound/soc/sunxi/sun4i-i2s.c| 176 -
 2 files changed, 176 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt 
b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
index ee21da865771..fc5da6080759 100644
--- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
@@ -8,6 +8,7 @@ Required properties:
 - compatible: should be one of the following:
- "allwinner,sun4i-a10-i2s"
- "allwinner,sun6i-a31-i2s"
+   - "allwinner,sun8i-h3-i2s"
 - reg: physical base address of the controller and length of memory mapped
   region.
 - interrupts: should contain the I2S interrupt.
@@ -22,6 +23,7 @@ Required properties:
 
 Required properties for the following compatibles:
- "allwinner,sun6i-a31-i2s"
+   - "allwinner,sun8i-h3-i2s"
 - resets: phandle to the reset line for this codec
 
 Example:
diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index 19d50ca10d1f..04f92583a969 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -92,11 +92,41 @@
 #define SUN4I_I2S_RX_CHAN_SEL_REG  0x38
 #define SUN4I_I2S_RX_CHAN_MAP_REG  0x3c
 
+/* Defines required for sun8i-h3 support */
+#define SUN8I_I2S_CTRL_BCLK_OUTBIT(18)
+#define SUN8I_I2S_CTRL_LRCK_OUTBIT(17)
+
+#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASKGENMASK(17, 8)
+#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
+
+#define SUN8I_I2S_INT_STA_REG  0x0c
+#define SUN8I_I2S_FIFO_TX_REG  0x20
+
+#define SUN8I_I2S_CHAN_CFG_REG 0x30
+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASKGENMASK(6, 4)
+#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)   (chan - 1)
+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASKGENMASK(2, 0)
+#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)   (chan - 1)
+
+#define SUN8I_I2S_TX_CHAN_MAP_REG  0x44
+#define SUN8I_I2S_TX_CHAN_SEL_REG  0x34
+#define SUN8I_I2S_TX_CHAN_OFFSET_MASK  GENMASK(13, 11)
+#define SUN8I_I2S_TX_CHAN_OFFSET(offset)   (offset << 12)
+#define SUN8I_I2S_TX_CHAN_EN_MASK  GENMASK(11, 4)
+#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
+
+#define SUN8I_I2S_RX_CHAN_SEL_REG  0x54
+#define SUN8I_I2S_RX_CHAN_MAP_REG  0x58
+
 /**
  * struct sun4i_i2s_quirks - Differences between SoC variants.
  *
  * @has_reset: SoC needs reset deasserted.
  * @has_slave_select_bit: SoC has a bit to enable slave mode.
+ * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
+ * @has_chcfg: tx and rx slot number need to be set.
+ * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
+ * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
  * @reg_offset_txdata: offset of the tx fifo.
  * @sun4i_i2s_regmap: regmap config to use.
  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
@@ -116,6 +146,10 @@
 struct sun4i_i2s_quirks {
boolhas_reset;
boolhas_slave_select_bit;
+   boolhas_fmt_set_lrck_period;
+   boolhas_chcfg;
+   boolhas_chsel_tx_chen;
+   boolhas_chsel_offset;
unsigned intreg_offset_txdata;  /* TX FIFO */
const struct regmap_config  *sun4i_i2s_regmap;
unsigned intmclk_offset;
@@ -173,6 +207,7 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] 
= {
{ .div = 8, .val = 3 },
{ .div = 12, .val = 4 },
{ .div = 16, .val = 5 },
+   /* TODO - extend divide ratio supported by newer SoCs */
 };
 
 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
@@ -184,6 +219,7 @@ static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] 
= {
{ .div = 12, .val = 5 },
{ .div = 16, .val = 6 },
{ .div = 24, .val = 7 },
+   /* TODO - extend divide ratio supported by newer SoCs */
 };
 
 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
@@ -295,6 +331,12 @@ static int sun4i_i2s_set_clk_rate(struct sun4i_i2s *i2s,
 
regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 
+   /* Set sync period */
+   if (i2s->variant->has_fmt_set_lrck_period)

[linux-sunxi] [PATCH v5 0/8] ASoC: Add I2S support for Allwinner H3 SoCs

2017-08-19 Thread codekipper 
From: Marcus Cooper 

Hi All,
please find attached a series of patches to bring i2s support to the
Allwinner H3 SoC. This has been tested with the following setups:

A20 Olimex EVB connected to a pcm5102
Orange Pi 2 connected to a uda1380
Orange Pi 2 hdmi audio playback
Pine 64 connected to the audio DAC board

To get i2s working some additional patches are required which will be
delivered later. For now they have been pushed here

https://github.com/codekipper/linux-sunxi/commits/sunxi-audio-h3

I don't own a A33 device which uses the i2s block for the audio codec
so if someone could test against that it would be much appreciated.

I'm also wondering if there is a preferred way of setting the lrclk
size in the dts?..currently it is set to the sample width but for example
the pcm5102a wants it to be 32 bits whatever the sample rate.

Thanks in advance,
CK

---

v5 changes compared to v4 are:
- fixed bad logic in fmt0 set LRCK period define.
- fixed PTR_ERR checks in init of regmap fields
- added reviewed-by to commit messages
- removed delivered patches

v4 changes compared to v3 are:
- moved clkdiv variant adjustment out of function
- used PTR_ERR_OR_ZERO for checks
- tidy up of extra lines and lines over 80 chars.
- reduced names of polarity, wss and sr reg fields.
- added reviewed-by to commit messages
- added comments for functionality that hasn't been implemented yet.
- removed delivered patches

v3 changes compared to v2 are:
- initial changes to prepare driver for newer SoCs has been broken down
  into smaller patches
- reduce use of regmap fields to where just needed.
- clkdiv expansion will be delivered later.
- defines for H3 variant segregated.
- fixed regmap config issue with SUN8I_I2S_FIFO_TX_REG.

v2 changes compared to v1 are:
 - massive refactoring to remove duplicate code making use of regmap_fields.
 - extending the clock divisors.
 - removed code that should be delivered when we support 20/24bits

---

Marcus Cooper (8):
  ASoC: sun4i-i2s: Add regmap fields for channels
  ASoC: sun4i-i2s: Add regfields for word size select and sample
resolution
  ASoC: sun4i-i2s: bclk and lrclk polarity tidyup
  ASoC: sun4i-i2s: Add mclk enable regmap field
  ASoC: sun4i-i2s: Add regmap field to set DAI format
  ASoC: sun4i-i2s: Check for slave select bit
  ASoC: sun4i-i2s: Update global enable with bitmask
  ASoC: sun4i-i2s: Add support for H3

 .../devicetree/bindings/sound/sun4i-i2s.txt|   2 +
 sound/soc/sunxi/sun4i-i2s.c| 406 ++---
 2 files changed, 357 insertions(+), 51 deletions(-)

-- 
2.14.1

-- 
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[linux-sunxi] [PATCH v5 1/8] ASoC: sun4i-i2s: Add regmap fields for channels

2017-08-19 Thread codekipper 
From: Marcus Cooper 

On the original i2s block the channel mapping and selection were
configured for stereo audio by default: This is not the case with
the newer SoCs and they are also located at different offsets.

To support the newer SoC then regmap fields have been added to the
quirks and these are initialised to their correct settings during
probing.

Signed-off-by: Marcus Cooper 
Reviewed-by: Chen-Yu Tsai 
---
 sound/soc/sunxi/sun4i-i2s.c | 77 -
 1 file changed, 69 insertions(+), 8 deletions(-)

diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
index dfb79492..87feb5a14cff 100644
--- a/sound/soc/sunxi/sun4i-i2s.c
+++ b/sound/soc/sunxi/sun4i-i2s.c
@@ -82,7 +82,7 @@
 #define SUN4I_I2S_TX_CNT_REG   0x2c
 
 #define SUN4I_I2S_TX_CHAN_SEL_REG  0x30
-#define SUN4I_I2S_TX_CHAN_SEL(num_chan)(((num_chan) - 1) << 0)
+#define SUN4I_I2S_CHAN_SEL(num_chan)   (((num_chan) - 1) << 0)
 
 #define SUN4I_I2S_TX_CHAN_MAP_REG  0x34
 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)((sample) << (chan << 2))
@@ -98,6 +98,10 @@
  * @sun4i_i2s_regmap: regmap config to use.
  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
+ * @field_txchanmap: location of the tx channel mapping register.
+ * @field_rxchanmap: location of the rx channel mapping register.
+ * @field_txchansel: location of the tx channel select bit fields.
+ * @field_rxchansel: location of the rx channel select bit fields.
  */
 struct sun4i_i2s_quirks {
boolhas_reset;
@@ -105,6 +109,12 @@ struct sun4i_i2s_quirks {
const struct regmap_config  *sun4i_i2s_regmap;
unsigned intmclk_offset;
unsigned intbclk_offset;
+
+   /* Register fields for i2s */
+   struct reg_fieldfield_txchanmap;
+   struct reg_fieldfield_rxchanmap;
+   struct reg_fieldfield_txchansel;
+   struct reg_fieldfield_rxchansel;
 };
 
 struct sun4i_i2s {
@@ -118,6 +128,12 @@ struct sun4i_i2s {
struct snd_dmaengine_dai_dma_data   capture_dma_data;
struct snd_dmaengine_dai_dma_data   playback_dma_data;
 
+   /* Register fields for i2s */
+   struct regmap_field *field_txchanmap;
+   struct regmap_field *field_rxchanmap;
+   struct regmap_field *field_txchansel;
+   struct regmap_field *field_rxchansel;
+
const struct sun4i_i2s_quirks   *variant;
 };
 
@@ -268,6 +284,17 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream 
*substream,
if (params_channels(params) != 2)
return -EINVAL;
 
+   /* Map the channels for playback and capture */
+   regmap_field_write(i2s->field_txchanmap, 0x76543210);
+   regmap_field_write(i2s->field_rxchanmap, 0x3210);
+
+   /* Configure the channels */
+   regmap_field_write(i2s->field_txchansel,
+  SUN4I_I2S_CHAN_SEL(params_channels(params)));
+
+   regmap_field_write(i2s->field_rxchansel,
+  SUN4I_I2S_CHAN_SEL(params_channels(params)));
+
switch (params_physical_width(params)) {
case 16:
width = DMA_SLAVE_BUSWIDTH_2_BYTES;
@@ -490,13 +517,6 @@ static int sun4i_i2s_startup(struct snd_pcm_substream 
*substream,
   SUN4I_I2S_CTRL_SDO_EN_MASK,
   SUN4I_I2S_CTRL_SDO_EN(0));
 
-   /* Enable the first two channels */
-   regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_SEL_REG,
-SUN4I_I2S_TX_CHAN_SEL(2));
-
-   /* Map them to the two first samples coming in */
-   regmap_write(i2s->regmap, SUN4I_I2S_TX_CHAN_MAP_REG,
-SUN4I_I2S_TX_CHAN_MAP(0, 0) | SUN4I_I2S_TX_CHAN_MAP(1, 1));
 
return clk_prepare_enable(i2s->mod_clk);
 }
@@ -681,14 +701,49 @@ static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks 
= {
.has_reset  = false,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
+   .field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
+   .field_txchansel= REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
+   .field_rxchansel= REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 };
 
 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
.has_reset  = true,
.reg_offset_txdata  = SUN4I_I2S_FIFO_TX_REG,
.sun4i_i2s_regmap   = _i2s_regmap_config,
+   .field_txchanmap= REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
+   .field_rxchanmap= REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
+

Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread icenowy 

在 2017-08-19 17:11，Chen-Yu Tsai 写道：

On Tue, Aug 15, 2017 at 4:52 PM,   wrote:

在 2017-08-15 13:55，Icenowy Zheng 写道：


Allwinner R40 SoC have a clock controller module in the style of the
SoCs beyond sun6i, however, it's more rich and complex.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
Changes in v5:
- Added TODO's for PLL constraints.
- Forced OHCI12M mux to 0.
- Changed "adda" clock to "codec" to be consistent with "bus-codec".
- Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
- Added PLL_CPU gate notifier.
Changes in v4:
- Removed usb-ohci-12M mux clocks.
- Removed unused (and not in user manual) adda-4x clock.
- Implemented proper SATA PLL system.
- Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
- Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
- Added missing RST_DRAM.
- Several clock post/pre-dividers and constraints fixes.
Changes in v3:
- Rebased on current linux-next.
Changes in v2:
- Fixes according to the SoC's user manual.

 drivers/clk/sunxi-ng/Kconfig  |5 +
 drivers/clk/sunxi-ng/Makefile |1 +
 drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
+
 drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
 include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
 include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
 6 files changed, 1682 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
 create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h

[...]

+static void __init sun8i_r40_ccu_setup(struct device_node *node)
+{
+   void __iomem *reg;
+   u32 val;
+
+   reg = of_io_request_and_map(node, 0, 
of_node_full_name(node));

+   if (IS_ERR(reg)) {
+   pr_err("%s: Could not map the clock registers\n",
+  of_node_full_name(node));
+   return;
+   }
+
+   /* Force the PLL-Audio-1x divider to 4 */
+   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
+   val &= ~GENMASK(19, 16);
+   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
+
+   /* Force PLL-MIPI to MIPI mode */
+   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
+   val &= ~BIT(16);
+   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
+
+   /* Force OHCI 12M parent to 0 */


Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M


+   val = readl(reg + SUN8I_R40_USB_CLK_REG);
+   val &= ~GENMASK(20, 6);



Sorry but I think this line should be:

val &= ~GENMASK(25, 20);

I didn't understand GENMASK well...


Fixed and applied. Thanks!


Thanks!



ChenYu


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Re: [linux-sunxi] Re: [PATCH v5] clk: sunxi-ng: support R40 SoC

2017-08-19 Thread Chen-Yu Tsai 
On Tue, Aug 15, 2017 at 4:52 PM,   wrote:
> 在 2017-08-15 13:55，Icenowy Zheng 写道：
>>
>> Allwinner R40 SoC have a clock controller module in the style of the
>> SoCs beyond sun6i, however, it's more rich and complex.
>>
>> Add support for it.
>>
>> Signed-off-by: Icenowy Zheng 
>> ---
>> Changes in v5:
>> - Added TODO's for PLL constraints.
>> - Forced OHCI12M mux to 0.
>> - Changed "adda" clock to "codec" to be consistent with "bus-codec".
>> - Added several CLK_SET_RATE_{UNGATE,PARENT} flags.
>> - Added PLL_CPU gate notifier.
>> Changes in v4:
>> - Removed usb-ohci-12M mux clocks.
>> - Removed unused (and not in user manual) adda-4x clock.
>> - Implemented proper SATA PLL system.
>> - Renamed MP (Mixed Processor) clock names to drop the extra "DE_".
>> - Renamed TCONs' clock names to "tcon-lcdX" or "tcon-tvX".
>> - Added missing RST_DRAM.
>> - Several clock post/pre-dividers and constraints fixes.
>> Changes in v3:
>> - Rebased on current linux-next.
>> Changes in v2:
>> - Fixes according to the SoC's user manual.
>>
>>  drivers/clk/sunxi-ng/Kconfig  |5 +
>>  drivers/clk/sunxi-ng/Makefile |1 +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.c  | 1290
>> +
>>  drivers/clk/sunxi-ng/ccu-sun8i-r40.h  |   69 ++
>>  include/dt-bindings/clock/sun8i-r40-ccu.h |  187 +
>>  include/dt-bindings/reset/sun8i-r40-ccu.h |  130 +++
>>  6 files changed, 1682 insertions(+)
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c
>>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h
>>  create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h
>>  create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h
>>
>> [...]
>>
>> +static void __init sun8i_r40_ccu_setup(struct device_node *node)
>> +{
>> +   void __iomem *reg;
>> +   u32 val;
>> +
>> +   reg = of_io_request_and_map(node, 0, of_node_full_name(node));
>> +   if (IS_ERR(reg)) {
>> +   pr_err("%s: Could not map the clock registers\n",
>> +  of_node_full_name(node));
>> +   return;
>> +   }
>> +
>> +   /* Force the PLL-Audio-1x divider to 4 */
>> +   val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
>> +   val &= ~GENMASK(19, 16);
>> +   writel(val | (3 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
>> +
>> +   /* Force PLL-MIPI to MIPI mode */
>> +   val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
>> +   val &= ~BIT(16);
>> +   writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
>> +
>> +   /* Force OHCI 12M parent to 0 */

Clarified the comment as

Force OHCI 12M parent to 12M divided from 48M

>> +   val = readl(reg + SUN8I_R40_USB_CLK_REG);
>> +   val &= ~GENMASK(20, 6);
>
>
> Sorry but I think this line should be:
>
> val &= ~GENMASK(25, 20);
>
> I didn't understand GENMASK well...

Fixed and applied. Thanks!

ChenYu

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