Re: [linux-sunxi] Allwinner A13 (Olimex A13SOM) DRM support
On Sat, Dec 12, 2020 at 3:33 AM Sergio Sota wrote: > > Hi Clement, > > yes, tve0 is only for VGA/CVBS video output (which we don't use right now) > But just in case we have enabled this controller and the result is the same. > > You're probably right about the I2C port (as the binding suggest) The thing is > we are using the olimex olinuxino tft lcd 10.1" panel, and as the binding file > states there should be an I2C bus connection (besides the RGB, hsync, vsync, > de, clk, backlight, etc) This I2C bus should connect to an internal eeprom > that > contains the timing requirements (then the driver knows what kind of panel is > attached and selects between 4.3/7/10.1 inches olimex panels) But then on > the physical boards there is no I2C bus connecting the panel... (check the > schematics) besides in the future we intend to use other tft lcd 10.1" panels. > > Olimex A13SOM board schematic: > https://github.com/OLIMEX/SOM/blob/master/A13/A13-SOM/A13-SOM512_Rev_G.pdf > > Olimex Olinuxino-micro board schematic (with an A13 similar as A13SOM) > https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A13-OLinuXino-MICRO/1.%20Latest%20hardware%20revision/A13-OLinuXino-MICRO%20hardware%20revision%20B1/A13-OLinuXino-MICRO_Rev_B1.pdf > > Olimex Olinuxino 10.1" tft lcd board schematic > https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/LCDs/LCD-OLinuXino-10TS/Hardware%20revision%20C1/LCD-OLINUXINO-10''TS_Rev_C.pdf > > that's why we set the timing in the device tree. So, may be what we should do > is remove the panel from the compatible line and use it only as a generic one: > > +compatible = "simple-panel"; > -compatible = "olimex,lcd-olinuxino", "simple-panel"; > > Anyway, we will check both posibilities (defining the panel on a I2C bus and > in the root but only as a generic panel) Thanks again for your invaluable > help :-D If you want to specify display timings in the device tree, you should be using the "panel-dpi" compatible, as specified in the panel-dpi binding: Documentation/devicetree/bindings/display/panel/panel-dpi.yaml Also, when asking for help, please always include full kernel logs. Others do not know what is happening on your system and can only guess if you do not provide logs. ChenYu > Best Regards, > Sergio Sota > > El viernes, 11 de diciembre de 2020 a las 19:56:16 UTC+1, peron...@gmail.com > escribió: >> >> Hi Sergio, >> >> Sorry looks like the tve0 is only required for composite / VGA output. >> >> Which LCD Panel do you use ? >> >> Looks like the bindings you are using should be declared on a I2C bus. >> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml >> >> So the drivers will read the configuration from the I2C eeprom >> Also check that CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is enabled. >> >> Regards, >> Clement >> >> On Fri, 11 Dec 2020 at 17:37, Clément Péron wrote: >> > >> > Hi Sergio, >> > >> > Maybe you missed enabling tve0 ? >> > >> > https://elixir.bootlin.com/linux/v5.9.13/source/arch/arm/boot/dts/sun5i.dtsi#L244 >> > >> > Also could you send the bootlog is this doesn't fix your issue. >> > >> > Clement >> > >> > On Fri, 11 Dec 2020 at 17:13, Sergio Sota wrote: >> > > >> > > Hi Clement, >> > > >> > > this week we have had no luck with Allwinner A13 video decoding, here you >> > > can find my device tree. We have added panel description (before we used >> > > an uboot configuration) front-end, back-end and tcon. Also on linux >> > > mainline >> > > kernel (5.9.11) we have selected DRM_SUN4I and DRM_SUN4I_BACKEND, >> > > but seems to be no DRM plane support on our system (no sun4i-drm kernel >> > > messages and no /dev/dri/card0 device) >> > > >> > > Also with VLC player we have selected in the menu the configuration >> > > options: >> > > VA-API video decoder and X11 video output (XCB) but no video decoding. >> > > With MPV player instead we can see some video frames, but it seems to be >> > > trying to decode via software, so it is almost like static pictures. >> > > >> > > Best Regards, >> > > Sergio Sota >> > > >> > > This device tree is based on mainline kernel >> > > sun5i-a13-olinuxino-micro.dts >> > > >> > > ### >> > > ## DEVICE TREE START # >> > > ### >> > > >> > > >> > > /* >> > > * Copyright 2012 Maxime Ripard >> > > * Copyright 2013 Hans de Goede >> > > * >> > > * This file is dual-licensed: you can use it either under the terms >> > > * of the GPL or the X11 license, at your option. Note that this dual >> > > * licensing only applies to this file, and not this project as a >> > > * whole. >> > > * >> > > * a) This file is free software; you can redistribute it and/or >> > > * modify it under the terms of the GNU General Public License as >> > > * published by the Free Software Foundation; either version 2 of the >> > > * License, or (at
Re: [linux-sunxi] Allwinner A13 (Olimex A13SOM) DRM support
Hi *Clement*, yes, *tve0* is only for *VGA/CVBS* video output (which we don't use right now) But just in case *we have enabled this controller and the result is the same*. You're probably right about the *I2C* port (as the binding suggest) The thing is we are using the *olimex olinuxino tft lcd 10.1"* panel, and as the binding file states there should be an *I2C* bus connection (besides the RGB, hsync, vsync, de, clk, backlight, etc) This *I2C* bus should connect to an internal eeprom that contains the timing requirements (then the driver knows what kind of panel is attached and selects between 4.3/7/10.1 inches olimex panels) But then on the physical boards* there is no I2C bus connecting the panel*... (check the schematics) besides in the future we intend to *use other tft lcd 10.1" panels*. *Olimex A13SOM board schematic*: *https://github.com/OLIMEX/SOM/blob/master/A13/A13-SOM/A13-SOM512_Rev_G.pdf* *Olimex Olinuxino-micro board schematic (with an A13 similar as A13SOM)* *https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A13-OLinuXino-MICRO/1.%20Latest%20hardware%20revision/A13-OLinuXino-MICRO%20hardware%20revision%20B1/A13-OLinuXino-MICRO_Rev_B1.pdf* *Olimex Olinuxino 10.1" tft lcd board schematic* *https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/LCDs/LCD-OLinuXino-10TS/Hardware%20revision%20C1/LCD-OLINUXINO-10''TS_Rev_C.pdf* that's why we set the timing in the device tree. So, may be what we should do is remove the panel from the compatible line and use it only as a generic one: *+compatible = "simple-panel"; * * -compatible = "olimex,lcd-olinuxino", "simple-panel"; * Anyway, *we will check both posibilities* (defining the panel on a I2C bus and in the root but only as a generic panel)* Thanks again for your invaluable help :-D* Best Regards, *Sergio Sota* El viernes, 11 de diciembre de 2020 a las 19:56:16 UTC+1, peron...@gmail.com escribió: > Hi Sergio, > > Sorry looks like the tve0 is only required for composite / VGA output. > > Which LCD Panel do you use ? > > Looks like the bindings you are using should be declared on a I2C bus. > > https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml > > So the drivers will read the configuration from the I2C eeprom > Also check that CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is enabled. > > Regards, > Clement > > On Fri, 11 Dec 2020 at 17:37, Clément Péron wrote: > > > > Hi Sergio, > > > > Maybe you missed enabling tve0 ? > > > > > https://elixir.bootlin.com/linux/v5.9.13/source/arch/arm/boot/dts/sun5i.dtsi#L244 > > > > Also could you send the bootlog is this doesn't fix your issue. > > > > Clement > > > > On Fri, 11 Dec 2020 at 17:13, Sergio Sota wrote: > > > > > > Hi Clement, > > > > > > this week we have had no luck with Allwinner A13 video decoding, here > you > > > can find my device tree. We have added panel description (before we > used > > > an uboot configuration) front-end, back-end and tcon. Also on linux > mainline > > > kernel (5.9.11) we have selected DRM_SUN4I and DRM_SUN4I_BACKEND, > > > but seems to be no DRM plane support on our system (no sun4i-drm kernel > > > messages and no /dev/dri/card0 device) > > > > > > Also with VLC player we have selected in the menu the configuration > options: > > > VA-API video decoder and X11 video output (XCB) but no video decoding. > > > With MPV player instead we can see some video frames, but it seems to > be > > > trying to decode via software, so it is almost like static pictures. > > > > > > Best Regards, > > > Sergio Sota > > > > > > This device tree is based on mainline kernel > sun5i-a13-olinuxino-micro.dts > > > > > > ### > > > ## DEVICE TREE START # > > > ### > > > > > > > > > /* > > > * Copyright 2012 Maxime Ripard > > > * Copyright 2013 Hans de Goede > > > * > > > * This file is dual-licensed: you can use it either under the terms > > > * of the GPL or the X11 license, at your option. Note that this dual > > > * licensing only applies to this file, and not this project as a > > > * whole. > > > * > > > * a) This file is free software; you can redistribute it and/or > > > * modify it under the terms of the GNU General Public License as > > > * published by the Free Software Foundation; either version 2 of the > > > * License, or (at your option) any later version. > > > * > > > * This file is distributed in the hope that it will be useful, > > > * but WITHOUT ANY WARRANTY; without even the implied warranty of > > > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > > * GNU General Public License for more details. > > > * > > > * Or, alternatively, > > > * > > > * b) Permission is hereby granted, free of charge, to any person > > > * obtaining a copy of this software and associated documentation > > > * files (the "Software"), to deal
Re: [linux-sunxi] Allwinner A13 (Olimex A13SOM) DRM support
Hi Sergio,
Sorry looks like the tve0 is only required for composite / VGA output.
Which LCD Panel do you use ?
Looks like the bindings you are using should be declared on a I2C bus.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/display/panel/olimex,lcd-olinuxino.yaml
So the drivers will read the configuration from the I2C eeprom
Also check that CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is enabled.
Regards,
Clement
On Fri, 11 Dec 2020 at 17:37, Clément Péron wrote:
>
> Hi Sergio,
>
> Maybe you missed enabling tve0 ?
>
> https://elixir.bootlin.com/linux/v5.9.13/source/arch/arm/boot/dts/sun5i.dtsi#L244
>
> Also could you send the bootlog is this doesn't fix your issue.
>
> Clement
>
> On Fri, 11 Dec 2020 at 17:13, Sergio Sota wrote:
> >
> > Hi Clement,
> >
> > this week we have had no luck with Allwinner A13 video decoding, here you
> > can find my device tree. We have added panel description (before we used
> > an uboot configuration) front-end, back-end and tcon. Also on linux mainline
> > kernel (5.9.11) we have selected DRM_SUN4I and DRM_SUN4I_BACKEND,
> > but seems to be no DRM plane support on our system (no sun4i-drm kernel
> > messages and no /dev/dri/card0 device)
> >
> > Also with VLC player we have selected in the menu the configuration options:
> > VA-API video decoder and X11 video output (XCB) but no video decoding.
> > With MPV player instead we can see some video frames, but it seems to be
> > trying to decode via software, so it is almost like static pictures.
> >
> > Best Regards,
> > Sergio Sota
> >
> > This device tree is based on mainline kernel sun5i-a13-olinuxino-micro.dts
> >
> > ###
> > ## DEVICE TREE START #
> > ###
> >
> >
> > /*
> > * Copyright 2012 Maxime Ripard
> > * Copyright 2013 Hans de Goede
> > *
> > * This file is dual-licensed: you can use it either under the terms
> > * of the GPL or the X11 license, at your option. Note that this dual
> > * licensing only applies to this file, and not this project as a
> > * whole.
> > *
> > * a) This file is free software; you can redistribute it and/or
> > * modify it under the terms of the GNU General Public License as
> > * published by the Free Software Foundation; either version 2 of the
> > * License, or (at your option) any later version.
> > *
> > * This file is distributed in the hope that it will be useful,
> > * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > * GNU General Public License for more details.
> > *
> > * Or, alternatively,
> > *
> > * b) Permission is hereby granted, free of charge, to any person
> > * obtaining a copy of this software and associated documentation
> > * files (the "Software"), to deal in the Software without
> > * restriction, including without limitation the rights to use,
> > * copy, modify, merge, publish, distribute, sublicense, and/or
> > * sell copies of the Software, and to permit persons to whom the
> > * Software is furnished to do so, subject to the following
> > * conditions:
> > *
> > * The above copyright notice and this permission notice shall be
> > * included in all copies or substantial portions of the Software.
> > *
> > * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > * OTHER DEALINGS IN THE SOFTWARE.
> > */
> >
> > /dts-v1/;
> > #include "sun5i-a13.dtsi"
> > #include "sunxi-common-regulators.dtsi"
> > #include
> > #include
> > #include
> >
> > / {
> > model = "Olimex A13-Olinuxino Micro";
> > compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
> >
> > aliases {
> > serial0 =
> > };
> >
> > chosen {
> > stdout-path = "serial0:115200n8";
> > };
> >
> > leds {
> > compatible = "gpio-leds";
> > pinctrl-names = "default";
> > pinctrl-0 = <_pins_olinuxinom>;
> >
> > power {
> > label = "a13-olinuxino-micro:green:power";
> > gpios = < 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
> > default-state = "on";
> > };
> > };
> >
> > /*
> > * clock spi0 mcp2515 (spi can controller)
> >
> > */
> >
Re: [linux-sunxi] Allwinner A13 (Olimex A13SOM) DRM support
Hi Sergio,
Maybe you missed enabling tve0 ?
https://elixir.bootlin.com/linux/v5.9.13/source/arch/arm/boot/dts/sun5i.dtsi#L244
Also could you send the bootlog is this doesn't fix your issue.
Clement
On Fri, 11 Dec 2020 at 17:13, Sergio Sota wrote:
>
> Hi Clement,
>
> this week we have had no luck with Allwinner A13 video decoding, here you
> can find my device tree. We have added panel description (before we used
> an uboot configuration) front-end, back-end and tcon. Also on linux mainline
> kernel (5.9.11) we have selected DRM_SUN4I and DRM_SUN4I_BACKEND,
> but seems to be no DRM plane support on our system (no sun4i-drm kernel
> messages and no /dev/dri/card0 device)
>
> Also with VLC player we have selected in the menu the configuration options:
> VA-API video decoder and X11 video output (XCB) but no video decoding.
> With MPV player instead we can see some video frames, but it seems to be
> trying to decode via software, so it is almost like static pictures.
>
> Best Regards,
> Sergio Sota
>
> This device tree is based on mainline kernel sun5i-a13-olinuxino-micro.dts
>
> ###
> ## DEVICE TREE START #
> ###
>
>
> /*
> * Copyright 2012 Maxime Ripard
> * Copyright 2013 Hans de Goede
> *
> * This file is dual-licensed: you can use it either under the terms
> * of the GPL or the X11 license, at your option. Note that this dual
> * licensing only applies to this file, and not this project as a
> * whole.
> *
> * a) This file is free software; you can redistribute it and/or
> * modify it under the terms of the GNU General Public License as
> * published by the Free Software Foundation; either version 2 of the
> * License, or (at your option) any later version.
> *
> * This file is distributed in the hope that it will be useful,
> * but WITHOUT ANY WARRANTY; without even the implied warranty of
> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> * GNU General Public License for more details.
> *
> * Or, alternatively,
> *
> * b) Permission is hereby granted, free of charge, to any person
> * obtaining a copy of this software and associated documentation
> * files (the "Software"), to deal in the Software without
> * restriction, including without limitation the rights to use,
> * copy, modify, merge, publish, distribute, sublicense, and/or
> * sell copies of the Software, and to permit persons to whom the
> * Software is furnished to do so, subject to the following
> * conditions:
> *
> * The above copyright notice and this permission notice shall be
> * included in all copies or substantial portions of the Software.
> *
> * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> /dts-v1/;
> #include "sun5i-a13.dtsi"
> #include "sunxi-common-regulators.dtsi"
> #include
> #include
> #include
>
> / {
> model = "Olimex A13-Olinuxino Micro";
> compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
>
> aliases {
> serial0 =
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
>
> leds {
> compatible = "gpio-leds";
> pinctrl-names = "default";
> pinctrl-0 = <_pins_olinuxinom>;
>
> power {
> label = "a13-olinuxino-micro:green:power";
> gpios = < 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
> default-state = "on";
> };
> };
>
> /*
> * clock spi0 mcp2515 (spi can controller)
>
> */
> clocks {
> #address-cells = <1>;
> #size-cells = <1>;
> can0_osc_fixed: can0_osc_fixed {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <1000>;
> };
> };
>
> /*
> * panel backlight
>
> */
> backlight: backlight {
> compatible = "pwm-backlight";
> pwms = < 0 5 PWM_POLARITY_INVERTED>;
> brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> default-brightness-level = <8>;
> };
>
>
Re: [linux-sunxi] Allwinner A13 (Olimex A13SOM) DRM support
Hi* Clement,*
this week we have had no luck with *Allwinner A13* *video decoding*, here
you
can find my *device tree*. We have added *panel description* (before we used
an uboot configuration) *front-end*, *back-end* and *tcon*. Also on linux
mainline
kernel (5.9.11) we have selected *DRM_SUN4I* and *DRM_SUN4I_BACKEND*,
but seems to be *no DRM plane support* on our system (no *sun4i-drm* kernel
messages and no */dev/dri/card0* device)
Also with *VLC player *we have selected in the menu the configuration
options:
*VA-API video decoder* and *X11 video output (XCB)* but no video decoding.
With *MPV player* instead we can see some video frames, but it seems to be
trying to decode via software, so it is almost like static pictures.
Best Regards,
*Sergio Sota*
This device tree is based on mainline kernel *sun5i-a13-olinuxino-micro.dts*
###
## DEVICE TREE START #
###
/*
* Copyright 2012 Maxime Ripard
* Copyright 2013 Hans de Goede
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "sun5i-a13.dtsi"
#include "sunxi-common-regulators.dtsi"
#include
#include
#include
/ {
model = "Olimex A13-Olinuxino Micro";
compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
aliases {
serial0 =
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <_pins_olinuxinom>;
power {
label = "a13-olinuxino-micro:green:power";
gpios = < 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
default-state = "on";
};
};
/*
* clock spi0 mcp2515 (spi can controller)
*/
clocks {
#address-cells = <1>;
#size-cells = <1>;
can0_osc_fixed: can0_osc_fixed {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000>;
};
};
/*
* panel backlight
*/
backlight: backlight {
compatible = "pwm-backlight";
pwms = < 0 5 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
};
/*
* panel tft lcd 10.1" (rgb interface)
*/
panel {
compatible = "olimex,lcd-olinuxino", "simple-panel";
power-supply = <_vcc3v3>;
enable-gpios = < 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
backlight = <>;
status = "okay";
display-timings {
timing0 {
[linux-sunxi] [PATCH v3 15/15] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-16-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 14/15] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..d6d55c12b995 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1066,6 +1066,32 @@ csi_in: port {
};
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_MIPI_CSI>,
+< CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
--
2.29.2
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[linux-sunxi] [PATCH v3 13/15] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering
both the protocol logic and the D-PHY implementation. This controller
seems to be found on the A83T only and probably was abandoned since.
This implementation splits the protocol and D-PHY registers and
uses the PHY framework internally. The D-PHY is not registered as a
standalone PHY driver since it cannot be used with any other
controller.
There are a few notable points about the controller:
- The initialisation sequence involes writing specific magic init
values that do not seem to make any particular sense given the
concerned register fields;
- Interrupts appear to be hitting regardless of the interrupt mask
registers, which can cause a serious flood when transmission errors
occur.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
This work is based on the first version of the driver submitted by
Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP.
This version integrates MIPI CSI-2 support as a standalone V4L2 subdev
instead of merging it in the sun6i-csi driver.
It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane
configuration.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 2 +-
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 +
.../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 +
.../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++
.../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++
.../sun8i_a83t_mipi_csi2.c| 657 ++
.../sun8i_a83t_mipi_csi2.h| 197 ++
9 files changed, 1003 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index b437eaeb91e9..bebe843a069b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -151,7 +151,7 @@ port@1 {
csi_in_mipi_csi2: endpoint {
remote-endpoint = <_csi2_out_csi>;
- }
+ };
};
};
};
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 9684e07454ad..db4c07be7e4c 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -3,3 +3,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
+source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index 887a7cae8fca..9aa01cb01883 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -3,5 +3,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
obj-y += sun6i-mipi-csi2/
+obj-y += sun8i-a83t-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
new file mode 100644
index ..60e7a9c41065
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN8I_A83T_MIPI_CSI2
+ tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY.
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
new file mode 100644
index ..1427d15a879a
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o
+
[linux-sunxi] [PATCH v3 12/15] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..e607fae7d85e
--- /dev/null
+++
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: MIPI-specific Clock
+ - description: Misc CSI Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+ - const: mipi
+ - const: misc
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ clock-lanes:
+maxItems: 1
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI_SCLK>,
+ < CLK_MIPI_CSI>,
+ < CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = < RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v3 11/15] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-12-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 10/15] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 67
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..b7f2bcd25c86 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
+ csi0: camera@1cb {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint =
<_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -552,5 +577,47 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint =
<_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = < CLK_BUS_CSI>,
+< CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
};
};
--
2.29.2
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[linux-sunxi] [PATCH v3 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
6 files changed, 725 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
+obj-y += sun6i-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..47f1bb0779a8
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+ tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select PHY_SUN6I_MIPI_DPHY
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..87307beda4cf
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+ MEDIA_BUS_FMT_SBGGR8_1X8,
+ MEDIA_BUS_FMT_SGBRG8_1X8,
+ MEDIA_BUS_FMT_SGRBG8_1X8,
+ MEDIA_BUS_FMT_SRGGB8_1X8,
+ MEDIA_BUS_FMT_SBGGR10_1X10,
+ MEDIA_BUS_FMT_SGBRG10_1X10,
+ MEDIA_BUS_FMT_SGRBG10_1X10,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+ struct sun6i_mipi_csi2_video *video =
+ sun6i_mipi_csi2_subdev_video(subdev);
+ struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+ struct v4l2_subdev *remote_subdev = video->remote_subdev;
+ struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+ >endpoint.bus.mipi_csi2;
+ union phy_configure_opts dphy_opts = { 0 };
+ struct phy_configure_opts_mipi_dphy *dphy_cfg = _opts.mipi_dphy;
+ struct regmap *regmap = cdev->regmap;
+ struct v4l2_ctrl *ctrl;
+ unsigned int lanes_count;
+ unsigned int bpp;
+ unsigned long
[linux-sunxi] [PATCH v3 08/15] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
1 file changed, 149 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..4d0bab541da1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+oneOf:
+ - const: allwinner,sun6i-a31-mipi-csi2
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-csi2
+ - const: allwinner,sun6i-a31-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+
+ phys:
+items:
+ - description: MIPI D-PHY
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = < RST_BUS_CSI>;
+
+phys = <>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v3 07/15] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
interface and are no longer immutable so that userspace can select
which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
active.
In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
(internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
DMA engine.
Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 123 ++
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 3 -
.../platform/sunxi/sun6i-csi/sun6i_video.c| 53
.../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +-
4 files changed, 135 insertions(+), 51 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index f1150de94e98..481181038e1e 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -52,15 +52,16 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
u32 pixformat, u32 mbus_code)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
/*
* Some video receivers have the ability to be compatible with
* 8bit and 16bit bus width.
* Identify the media bus format from device tree.
*/
- if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ if ((endpoint->bus_type == V4L2_MBUS_PARALLEL
+|| endpoint->bus_type == V4L2_MBUS_BT656)
+&& endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct
sun6i_csi_dev *sdev,
static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
{
- struct v4l2_fwnode_endpoint *endpoint = >csi.v4l2_ep;
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = >csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+ case V4L2_MBUS_CSI2_DPHY:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool
enable)
* Media Controller and V4L2
*/
static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
{
struct media_entity *sink;
- struct media_pad *sink_pad;
int src_pad_index;
int ret;
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
sink = >video.vdev.entity;
- sink_pad = >video.pad;
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
sink_pad->index,
- MEDIA_LNK_FL_ENABLED |
- MEDIA_LNK_FL_IMMUTABLE);
+ enabled ? MEDIA_LNK_FL_ENABLED : 0);
if (ret < 0) {
[linux-sunxi] [PATCH v3 06/15] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.
Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.
Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.
This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0.
Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-csi.yaml| 88 ---
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..77ded77505e9 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -67,6 +67,62 @@ properties:
additionalProperties: false
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+required:
+ - bus-width
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -95,19 +151,25 @@ examples:
"ram";
resets = < RST_BUS_CSI>;
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>; /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>; /* Rising */
+};
};
};
};
--
2.29.2
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[linux-sunxi] [PATCH v3 05/15] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 531a4cccd14a..f1150de94e98 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+ bool input_parallel = false;
bool input_interlaced = false;
+ if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+ endpoint->bus_type == V4L2_MBUS_BT656)
+ input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
CSI_IF_CFG_SRC_TYPE_MASK);
+ if (input_parallel) {
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ case 16: /* No need to configure DATA_WIDTH for 16bit */
+ break;
+ default:
+ dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+ break;
+ }
+ }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
- switch (bus_width) {
- case 8:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
- break;
- case 10:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
- break;
- case 12:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
- break;
- case 16: /* No need to configure DATA_WIDTH for 16bit */
- break;
- default:
- dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
- break;
- }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
}
--
2.29.2
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[linux-sunxi] [PATCH v3 04/15] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++
1 file changed, 20 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..092445f04c60 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -86,53 +86,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
dma_addr_t addr);
*/
void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
static inline int sun6i_csi_get_bpp(unsigned int pixformat)
{
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ int bpp = 0;
+
+ /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
- case V4L2_PIX_FMT_SBGGR8:
- case V4L2_PIX_FMT_SGBRG8:
- case V4L2_PIX_FMT_SGRBG8:
- case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
- case V4L2_PIX_FMT_SBGGR10:
- case V4L2_PIX_FMT_SGBRG10:
- case V4L2_PIX_FMT_SGRBG10:
- case V4L2_PIX_FMT_SRGGB10:
- return 10;
- case V4L2_PIX_FMT_SBGGR12:
- case V4L2_PIX_FMT_SGBRG12:
- case V4L2_PIX_FMT_SGRBG12:
- case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
- case V4L2_PIX_FMT_NV12:
- case V4L2_PIX_FMT_NV21:
- case V4L2_PIX_FMT_YUV420:
- case V4L2_PIX_FMT_YVU420:
return 12;
- case V4L2_PIX_FMT_YUYV:
- case V4L2_PIX_FMT_YVYU:
- case V4L2_PIX_FMT_UYVY:
- case V4L2_PIX_FMT_VYUY:
- case V4L2_PIX_FMT_NV16:
- case V4L2_PIX_FMT_NV61:
- case V4L2_PIX_FMT_YUV422P:
- case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
- case V4L2_PIX_FMT_RGB24:
- case V4L2_PIX_FMT_BGR24:
- return 24;
- case V4L2_PIX_FMT_RGB32:
- case V4L2_PIX_FMT_BGR32:
- return 32;
- default:
+ }
+
+ info = v4l2_format_info(pixformat);
+ if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
- break;
+ return 0;
+ }
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ /* We return bits per pixel while V4L2 format info is bytes. */
+ bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
- return 0;
+ return bpp;
}
#endif /* __SUN6I_CSI_H__ */
--
2.29.2
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[linux-sunxi] [PATCH v3 03/15] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..0389b6b670d6 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
#define SUN6I_DPHY_TX_CTL_REG 0x04
#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
+#define SUN6I_DPHY_RX_CTL_REG 0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
+
#define SUN6I_DPHY_TX_TIME0_REG0x10
#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
+
#define SUN6I_DPHY_ANA0_REG0x4c
#define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
#define SUN6I_DPHY_ANA1_REG0x50
#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
struct phy *phy;
struct phy_configure_opts_mipi_dphy config;
+
+ int submode;
};
static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_MIPI_DPHY)
+ return -EINVAL;
+
+ dphy->submode = submode;
+
+ return 0;
+}
+
static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
*opts)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
phy_configure_opts *opts)
return 0;
}
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
- struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
}
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+ /* Physical clock rate is actually half of symbol rate with DDR. */
+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+ unsigned long dphy_clk_rate;
+ unsigned int rx_dly;
+ unsigned int lprst_dly;
+ u32 value;
+
+ dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+ if (!dphy_clk_rate)
+ return -EINVAL;
+
+ /* Hardcoded timing parameters from the Allwinner BSP. */
+ regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I_DPHY_RX_TIME0_LP_RX(255));
+
+ /*
+* Formula from the Allwinner BSP, with hardcoded coefficients
+* (probably internal divider/multiplier).
+*/
+
[linux-sunxi] [PATCH v3 02/15] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c
b/drivers/staging/media/rkisp1/rkisp1-isp.c
index a9715b0b7264..f1167995688a 100644
--- a/drivers/staging/media/rkisp1/rkisp1-isp.c
+++ b/drivers/staging/media/rkisp1/rkisp1-isp.c
@@ -914,7 +914,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
sensor->lanes, cfg);
- phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, );
phy_power_on(sensor->dphy);
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
#ifndef __PHY_MIPI_DPHY_H_
#define __PHY_MIPI_DPHY_H_
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+ PHY_MIPI_DPHY_SUBMODE_TX = 0,
+ PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
/**
* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
*
--
2.29.2
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[linux-sunxi] [PATCH v3 01/15] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski Reviewed-by: Maxime Ripard --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-2-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 00/15] Allwinner MIPI CSI-2 support for A31/V3s/A83T
This series introduces support for MIPI CSI-2, with the A31 controller that is found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific controller. While the former uses the same MIPI D-PHY that is already supported for DSI, the latter embeds its own D-PHY. In order to distinguish the use of the D-PHY between Rx mode (for MIPI CSI-2) and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY API. This allows adding Rx support in the A31 D-PHY driver. A few changes and fixes are applied to the A31 CSI controller driver, in order to support the MIPI CSI-2 use-case. Changes since v2: - added Kconfig depend on PM since it's not optional; - removed phy-names for A31 MIPI CSI-2 controller; - removed v3s compatible in the A31 MIPI CSI-2 controller driver; - removed A31 CSI controller single-port binding deprecation; - removed empty dt port definitions; - fixed minor checkpatch warnings; - added collected tags; - added media-ctl output in cover letter. Changes since v1: - reworked fwnode and media graph on the CSI controller end to have one port per interface, which solves the bus type representation issue; - removed unused IRQ handlers in the MIPI CSI-2 bridges; - avoided the use of devm_regmap_init_mmio_clk; - deasserted reset before enabling clocks; - fixed reported return code issues (ret |=, missing checks); - applied requested cosmetic changes (backward goto, etc); - switched over to runtime PM for the mipi csi-2 bridge drivers; - selected PHY_SUN6I_MIPI_DPHY in Kconfig for sun6i-mipi-csi2; - registered nodes with mipi csi-2 bridge subdevs; - used V4L2 format info instead of switch/case for sun6i-csi bpp; - fixed device-tree bindings as requested (useless properties, license); - fixed mipi bridge dt instances names; - added PHY API documentation about mode/power on order requirement; - fixed clock error return code in d-phy code; - fixed D-PHY mode check in d-phy code; - added MAINTAINERS entries for the new drivers; - added V4L2 compliance results; - added various comments and rework commit mesages as requested. Media ctl outputs for the testing setups are available below: # sun6i-csi + sun6i-mipi-csi2 + ov5648 Media device information driver sun6i-csi model Allwinner Video Capture Device serial bus infoplatform:1cb.camera hw revision 0x0 driver version 5.10.0 Device topology - entity 1: sun6i-csi (2 pads, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 pad0: Sink pad1: Sink <- "sun6i-mipi-csi2":1 [ENABLED] - entity 6: sun6i-mipi-csi2 (2 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Sink [fmt:unknown/0x0] <- "ov5648 0-0036":0 [ENABLED,IMMUTABLE] pad1: Source [fmt:unknown/0x0] -> "sun6i-csi":1 [ENABLED] - entity 9: ov5648 0-0036 (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 device node name /dev/v4l-subdev1 pad0: Source [fmt:SBGGR8_1X8/2592x1944@1/15 field:none colorspace:raw xfer:none ycbcr:601 quantization:full-range] -> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE] # sun6i-csi + sun8i-a83t-mipi-csi2 + ov8865 Media device information driver sun6i-csi model Allwinner Video Capture Device serial bus infoplatform:1cb.camera hw revision 0x0 driver version 5.10.0 Device topology - entity 1: sun6i-csi (2 pads, 1 link) type Node subtype V4L flags 0 device node name /dev/video0 pad0: Sink pad1: Sink <- "sun8i-a83t-mipi-csi2":1 [ENABLED] - entity 6: sun8i-a83t-mipi-csi2 (2 pads, 2 links) type V4L2 subdev subtype Unknown flags 0 device node name /dev/v4l-subdev0 pad0: Sink [fmt:unknown/0x0] <- "ov8865 1-0036":0 [ENABLED,IMMUTABLE] pad1: Source [fmt:unknown/0x0] -> "sun6i-csi":1 [ENABLED] - entity 9: ov8865 1-0036 (1 pad, 1 link) type V4L2 subdev subtype Sensor flags 0 device node name /dev/v4l-subdev1 pad0: Source [fmt:SBGGR10_1X10/3264x2448@1/30 field:none colorspace:raw xfer:none ycbcr:601 quantization:full-range] -> "sun8i-a83t-mipi-csi2":0 [ENABLED,IMMUTABLE] V4L2 compliance runs are available below: # sun6i-csi + sun6i-mipi-csi2 + ov5648 v4l2-compliance SHA: not available, 32 bits Compliance test for sun6i-video device /dev/video0: Driver Info: Driver name : sun6i-video Card type: sun6i-csi Bus info : platform:camera Driver version : 5.10.0 Capabilities : 0x8421 Video Capture Streaming
