[linux-sunxi] Re: [PATCH v6 02/17] mfd: axp20x: Allow AXP 806 chips without interrupt lines
On Wed, 19 May 2021, Andre Przywara wrote: > Currently the AXP chip requires to have its IRQ line connected to some > interrupt controller, and will fail probing when this is not the case. > > On a new Allwinner SoC (H616) there is no NMI pin anymore, and at > least one board does not connect the AXP's IRQ pin to anything else, > so the interrupt functionality of the AXP chip is simply not available. > > Check whether the interrupt line number returned by the platform code is > valid, before trying to register the irqchip. If not, we skip this > registration, to avoid the driver to bail out completely. > Also we need to skip the power key functionality, as this relies on > a valid IRQ as well. > > Signed-off-by: Andre Przywara > --- > drivers/mfd/axp20x.c | 24 +--- > 1 file changed, 17 insertions(+), 7 deletions(-) Applied, thanks. -- Lee Jones [李琼斯] Senior Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519150138.GK2549456%40dell.
[linux-sunxi] [PATCH v6 17/17] arm64: dts: allwinner: h616: Add X96 Mate TV box support
The X96 Mate is an Allwinner H616 based TV box, featuring:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 2GiB/4GiB RAM (fully usable!)
- 16/32/64GiB eMMC
- 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
- Unsupported Allwinner WiFi chip
- 2 x USB 2.0 host ports
- HDMI port
- IR receiver
- 5V/2A DC power supply via barrel plug
For more information see: https://linux-sunxi.org/X96_Mate
Add a basic devicetree for it, with SD card, eMMC and USB working, as
well as serial and the essential peripherals, like the AXP PMIC.
This DT is somewhat minimal, and should work on many other similar TV
boxes with the Allwinner H616 chip.
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../dts/allwinner/sun50i-h616-x96-mate.dts| 201 ++
2 files changed, 202 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 9ba4b5d92657..370d24ebaacf 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -37,3 +37,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
new file mode 100644
index ..b960bb310289
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2021 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+
+/ {
+ model = "X96 Mate";
+ compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ vqmmc-supply = <_bldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-sys";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3-ext";
+ status = "disabled";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo3: aldo3 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3-ext2";
+ status = "disabled";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt
[linux-sunxi] [PATCH v6 15/17] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding
Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ac750025a2eb..1ca550062a85 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -937,4 +937,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 +items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-16-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 14/17] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
And while there is still the extra sunxi interrupt controller, the
package lacks the corresponding NMI pin, so no interrupts for the PMIC.
USB is a bit tricky: host controller 0, 1 and 3 depend on some help from
controller and PHY 2, so we need to include one reset line and one
clock gate from HCI 2 into every other HCI node, plus need some nasty
quirk.
The reserved memory node is actually handled by Trusted Firmware now,
but U-Boot fails to propagate this to a separately loaded DTB, so we
keep it in here for now, until U-Boot learns to do this properly.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 747 ++
1 file changed, 747 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index ..30195e4779de
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,747 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@4000 {
+ reg = <0x0 0x4000 0x0 0x8>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ syscon: syscon@300 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x0300 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x3>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = <0x03001000
[linux-sunxi] [PATCH v6 16/17] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
The OrangePi Zero 2 is a development board with the new H616 SoC. It
comes with the following features:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 512MiB/1GiB DDR3 DRAM
- AXP305 PMIC
- Raspberry-Pi-1 compatible GPIO header
- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
- 1 USB 2.0 host port
- 1 USB 2.0 type C port (power supply + OTG)
- MicroSD slot
- on-board 2MiB bootable SPI NOR flash
- 1Gbps Ethernet port (via RTL8211F PHY)
- micro-HDMI port
- unsupported Allwinner WiFi/BT chip
For more details see: https://linux-sunxi.org/Orange_Pi_Zero_2
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 245 ++
2 files changed, 246 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680e5f8d..9ba4b5d92657 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index ..a26201288872
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = < 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = < 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_vcc5v>;
+ enable-active-high;
+ gpio = < 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ status = "okay";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <_rgmii_phy>;
+ phy-supply = <_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+ {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+
[linux-sunxi] [PATCH v6 13/17] phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index ed7b9cc5a424..a55765ad7bad 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -994,6 +994,17 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
+ .needs_phy2_siddq = true,
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = _a13_cfg },
@@ -1008,6 +1019,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[]
= {
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = _h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data =
_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.17.5
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[linux-sunxi] [PATCH v6 12/17] phy: sun4i-usb: Introduce port2 SIDDQ quirk
At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask
Instead of disguising this as some generic feature, do exactly that
in our PHY init:
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We can pull in the
other required clocks via the DT.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++
1 file changed, 29 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 126ef74d013c..ed7b9cc5a424 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -120,6 +120,7 @@ struct sun4i_usb_phy_cfg {
u8 phyctl_offset;
bool dedicated_clocks;
bool phy0_dual_route;
+ bool needs_phy2_siddq;
int missing_phys;
};
@@ -331,6 +332,27 @@ static int sun4i_usb_phy_init(struct phy *_phy)
queue_delayed_work(system_wq, >detect, 0);
}
+ /* Some PHYs on some SoCs need the help of PHY2 to work. */
+ if (data->cfg->needs_phy2_siddq && phy->index != 2) {
+ struct sun4i_usb_phy *phy2 = >phys[2];
+
+ /*
+* This extra clock is just needed to access the
+* REG_HCI_PHY_CTL PMU register for PHY2.
+*/
+ ret = clk_prepare_enable(phy2->clk2);
+ if (ret)
+ return ret;
+
+ if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
+ val = readl(phy2->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_clear;
+ writel(val, phy2->pmu + REG_HCI_PHY_CTL);
+ }
+
+ clk_disable_unprepare(phy->clk2);
+ }
+
return 0;
}
@@ -785,6 +807,13 @@ static int sun4i_usb_phy_probe(struct platform_device
*pdev)
dev_err(dev, "failed to get clock %s\n", name);
return PTR_ERR(phy->clk2);
}
+ } else {
+ snprintf(name, sizeof(name), "pmu%d_clk", i);
+ phy->clk2 = devm_clk_get_optional(dev, name);
+ if (IS_ERR(phy->clk2)) {
+ dev_err(dev, "failed to get clock %s\n", name);
+ return PTR_ERR(phy->clk2);
+ }
}
snprintf(name, sizeof(name), "usb%d_reset", i);
--
2.17.5
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[linux-sunxi] [PATCH v6 11/17] phy: sun4i-usb: Allow reset line to be shared
The USB HCIs (and PHYs?) in Allwinner's newer generation SoCs (H616)
rely on the reset line of USB PHY 2 to be de-asserted, even when only
one of the other PHYs is actually in use.
To make those ports work, we include this reset line in the HCIs' resets
property, which requires this line to be shareable.
Change the call to allocate the reset line to mark it as shared, to
enable the other ports on those SoCs.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 142f4cafdc78..126ef74d013c 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -788,7 +788,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
}
snprintf(name, sizeof(name), "usb%d_reset", i);
- phy->reset = devm_reset_control_get(dev, name);
+ phy->reset = devm_reset_control_get_shared(dev, name);
if (IS_ERR(phy->reset)) {
dev_err(dev, "failed to get reset %s\n", name);
return PTR_ERR(phy->reset);
--
2.17.5
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[linux-sunxi] [PATCH v6 10/17] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 30 ---
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..142f4cafdc78 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -43,7 +43,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_OTGCTL 0x20
-#define REG_PMU_UNK1 0x10
+#define REG_HCI_PHY_CTL0x10
#define PHYCTL_DATABIT(7)
@@ -82,6 +82,7 @@
/* A83T specific control bits for PHY0 */
#define PHY_CTL_VBUSVLDEXT BIT(5)
#define PHY_CTL_SIDDQ BIT(3)
+#define PHY_CTL_H3_SIDDQ BIT(1)
/* A83T specific control bits for PHY2 HSIC */
#define SUNXI_EHCI_HS_FORCEBIT(20)
@@ -115,9 +116,9 @@ struct sun4i_usb_phy_cfg {
int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
+ u32 hci_phy_ctl_clear;
u8 phyctl_offset;
bool dedicated_clocks;
- bool enable_pmu_unk1;
bool phy0_dual_route;
int missing_phys;
};
@@ -288,6 +289,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
+ val = readl(phy->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_clear;
+ writel(val, phy->pmu + REG_HCI_PHY_CTL);
+ }
+
if (data->cfg->type == sun8i_a83t_phy ||
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) {
@@ -297,11 +304,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, data->base + data->cfg->phyctl_offset);
}
} else {
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
-
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -863,7 +865,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -872,7 +873,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -881,7 +881,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -890,7 +889,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -899,7 +897,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -908,7 +905,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -925,7 +921,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
.phy0_dual_route = true,
};
@@ -935,7 +931,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
.phy0_dual_route = true,
};
@@ -945,7 +941,7
[linux-sunxi] [PATCH v6 09/17] dt-bindings: usb: sunxi-musb: Add H616 compatible string
The H616 MUSB peripheral is compatible to the H3 one (8 endpoints). Signed-off-by: Andre Przywara Acked-by: Maxime Ripard --- .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index 0f520f17735e..933fa356d2ce 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -22,6 +22,9 @@ properties: - allwinner,sun8i-a83t-musb - allwinner,sun50i-h6-musb - const: allwinner,sun8i-a33-musb + - items: + - const: allwinner,sun50i-h616-musb + - const: allwinner,sun8i-h3-musb reg: maxItems: 1 -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-10-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 08/17] dt-bindings: usb: Add H616 compatible string
The H616 has four PHYs as the H3, along with their respective clock gates and resets, so the property description is identical. However the PHYs itself need some special bits, so we need a new compatible string for it. Signed-off-by: Andre Przywara --- .../devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index f80431060803..e288450e0844 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -15,7 +15,9 @@ properties: const: 1 compatible: -const: allwinner,sun8i-h3-usb-phy +enum: + - allwinner,sun8i-h3-usb-phy + - allwinner,sun50i-h616-usb-phy reg: items: -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-9-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 07/17] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 4422baeed3d8..5f3fefd9a74e 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1147,11 +1147,13 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
struct stmmac_resources stmmac_res;
struct sunxi_priv_data *gmac;
struct device *dev = >dev;
+ struct reg_field syscon_field;
phy_interface_t interface;
int ret;
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, _res);
if (ret)
@@ -1209,8 +1211,12 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-
*gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1330,6 +1336,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = _variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = _variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = _variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
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[linux-sunxi] [PATCH v6 06/17] dt-bindings: net: sun8i-emac: Add H616 compatible string
Add the obvious compatible name to the existing EMAC binding, and pair it with the existing A64 fallback compatible string, as the devices are compatible. On the way use enums to group the compatible devices together. Signed-off-by: Andre Przywara --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 7f2578d48e3f..0ccdab103f59 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -19,7 +19,9 @@ properties: - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac - items: - - const: allwinner,sun50i-h6-emac + - enum: + - allwinner,sun50i-h6-emac + - allwinner,sun50i-h616-emac - const: allwinner,sun50i-a64-emac reg: -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-7-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 05/17] rtc: sun6i: Add Allwinner H616 support
The H616 RTC changes its day storage to the newly introduced linear day
scheme, so pair the new compatible string with this feature flag.
So far the clock parts seem to be the same as the H6, so combine the
compatible string with the existing H6 support bits.
Signed-off-by: Andre Przywara
---
drivers/rtc/rtc-sun6i.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index 0228e9dfd969..ec0cd0ee539a 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -382,6 +382,8 @@ static void __init sun50i_h6_rtc_clk_init(struct
device_node *node)
}
CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
sun50i_h6_rtc_clk_init);
+CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_clk, "allwinner,sun50i-h616-rtc",
+ sun50i_h6_rtc_clk_init);
/*
* The R40 user manual is self-conflicting on whether the prescaler is
@@ -773,6 +775,8 @@ static const struct of_device_id sun6i_rtc_dt_ids[] = {
{ .compatible = "allwinner,sun8i-v3-rtc" },
{ .compatible = "allwinner,sun50i-h5-rtc" },
{ .compatible = "allwinner,sun50i-h6-rtc" },
+ { .compatible = "allwinner,sun50i-h616-rtc",
+ .data = (void *)RTC_LINEAR_DAY },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
--
2.17.5
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[linux-sunxi] [PATCH v6 04/17] rtc: sun6i: Add support for linear day storage
Newer versions of the Allwinner RTC, as for instance found in the H616
SoC, no longer store a broken-down day/month/year representation in the
RTC_DAY_REG, but just a linear day number.
The user manual does not give any indication about the expected epoch
time of this day count, but the BSP kernel uses the UNIX epoch, which
allows easy support due to existing conversion functions in the kernel.
Allow tagging a compatible string with a flag, and use that to mark
those new RTCs. Then convert between a UNIX day number (converted into
seconds) and the broken-down day representation using mktime64() and
time64_to_tm() in the set_time/get_time functions.
That enables support for the RTC in those new chips.
Reviewed-by: Andre Przywara
---
drivers/rtc/rtc-sun6i.c | 58 +
1 file changed, 41 insertions(+), 17 deletions(-)
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
index adec1b14a8de..0228e9dfd969 100644
--- a/drivers/rtc/rtc-sun6i.c
+++ b/drivers/rtc/rtc-sun6i.c
@@ -133,12 +133,15 @@ struct sun6i_rtc_clk_data {
unsigned int has_auto_swt : 1;
};
+#define RTC_LINEAR_DAY BIT(0)
+
struct sun6i_rtc_dev {
struct rtc_device *rtc;
const struct sun6i_rtc_clk_data *data;
void __iomem *base;
int irq;
unsigned long alarm;
+ unsigned long flags;
struct clk_hw hw;
struct clk_hw *int_osc;
@@ -471,17 +474,30 @@ static int sun6i_rtc_gettime(struct device *dev, struct
rtc_time *rtc_tm)
rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
- rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
- rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
- rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
-
- rtc_tm->tm_mon -= 1;
-
- /*
-* switch from (data_year->min)-relative offset to
-* a (1900)-relative one
-*/
- rtc_tm->tm_year += SUN6I_YEAR_OFF;
+ if (chip->flags & RTC_LINEAR_DAY) {
+ struct tm tm;
+
+ /*
+* Newer chips store a linear day number, the manual
+* does not mandate any epoch base. The BSP driver uses
+* the UNIX epoch, let's just copy that, as it's the
+* easiest anyway.
+*/
+ time64_to_tm((date & 0x) * 3600ULL * 24, 0, );
+ rtc_tm->tm_mday = tm.tm_mday;
+ rtc_tm->tm_mon = tm.tm_mon;
+ rtc_tm->tm_year = tm.tm_year;
+ } else {
+ rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
+ rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date) - 1;
+ rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
+
+ /*
+* switch from (data_year->min)-relative offset to
+* a (1900)-relative one
+*/
+ rtc_tm->tm_year += SUN6I_YEAR_OFF;
+ }
return 0;
}
@@ -571,15 +587,21 @@ static int sun6i_rtc_settime(struct device *dev, struct
rtc_time *rtc_tm)
u32 date = 0;
u32 time = 0;
- rtc_tm->tm_year -= SUN6I_YEAR_OFF;
rtc_tm->tm_mon += 1;
- date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
- SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
- SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
+ if (chip->flags & RTC_LINEAR_DAY) {
+ date = mktime64(rtc_tm->tm_year + 1900, rtc_tm->tm_mon,
+ rtc_tm->tm_mday, 0, 0, 0) / (3600ULL * 24);
+ } else {
+ rtc_tm->tm_year -= SUN6I_YEAR_OFF;
+
+ date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
+ SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
+ SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
- if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
- date |= SUN6I_LEAP_SET_VALUE(1);
+ if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
+ date |= SUN6I_LEAP_SET_VALUE(1);
+ }
time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
@@ -678,6 +700,8 @@ static int sun6i_rtc_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, chip);
+ chip->flags = (unsigned long)of_device_get_match_data(>dev);
+
chip->irq = platform_get_irq(pdev, 0);
if (chip->irq < 0)
return chip->irq;
--
2.17.5
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[linux-sunxi] [PATCH v6 03/17] dt-bindings: rtc: sun6i: Add H616 compatible string
Add the obvious compatible name to the existing RTC binding. The actual RTC part of the device uses a different day/month/year storage scheme, so it's not compatible with the previous devices. Signed-off-by: Andre Przywara --- .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index b1b0ee769b71..178c955f88bf 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,7 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - const: allwinner,sun50i-h616-rtc reg: maxItems: 1 @@ -97,7 +98,9 @@ allOf: properties: compatible: contains: -const: allwinner,sun50i-h6-rtc +enum: + - allwinner,sun50i-h6-rtc + - allwinner,sun50i-h616-rtc then: properties: -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-4-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 02/17] mfd: axp20x: Allow AXP 806 chips without interrupt lines
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, and at
least one board does not connect the AXP's IRQ pin to anything else,
so the interrupt functionality of the AXP chip is simply not available.
Check whether the interrupt line number returned by the platform code is
valid, before trying to register the irqchip. If not, we skip this
registration, to avoid the driver to bail out completely.
Also we need to skip the power key functionality, as this relies on
a valid IRQ as well.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3eae04e24ac8..4145a38b3890 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -884,8 +884,13 @@ int axp20x_match_device(struct axp20x_dev *axp20x)
axp20x->regmap_irq_chip = _regmap_irq_chip;
break;
case AXP806_ID:
+ /*
+* Don't register the power key part if in slave mode or
+* if there is no interrupt line.
+*/
if (of_property_read_bool(axp20x->dev->of_node,
- "x-powers,self-working-mode")) {
+ "x-powers,self-working-mode") &&
+ axp20x->irq > 0) {
axp20x->nr_cells =
ARRAY_SIZE(axp806_self_working_cells);
axp20x->cells = axp806_self_working_cells;
} else {
@@ -959,12 +964,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
- ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
- IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
- -1, axp20x->regmap_irq_chip, >regmap_irqc);
- if (ret) {
- dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
- return ret;
+ /* Only if there is an interrupt line connected towards the CPU. */
+ if (axp20x->irq > 0) {
+ ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
+ IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
+ -1, axp20x->regmap_irq_chip,
+ >regmap_irqc);
+ if (ret) {
+ dev_err(axp20x->dev, "failed to add irq chip: %d\n",
+ ret);
+ return ret;
+ }
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
--
2.17.5
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[linux-sunxi] [PATCH v6 01/17] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ)
The AXP305 PMIC used in AXP805 seems to be fully compatible to the AXP805 PMIC, so add the proper chain of compatible strings. Also at least on one board (Orangepi Zero2) there is no interrupt line connected to the CPU, so make the "interrupts" property optional. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 4991a6415796..4fd748101e3c 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -26,10 +26,10 @@ Required properties: * "x-powers,axp803" * "x-powers,axp806" * "x-powers,axp805", "x-powers,axp806" +* "x-powers,axp803", "x-powers,axp805", "x-powers,axp806" * "x-powers,axp809" * "x-powers,axp813" - reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 @@ -43,6 +43,7 @@ more information: AXP20x/LDO3: software-based implementation Optional properties: +- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz AXP152/20X: range: 750-1875, Default: 1.5 MHz AXP22X/8XX: range: 1800-4050, Default: 3 MHz -- 2.17.5 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210519104152.21119-2-andre.przywara%40arm.com.
[linux-sunxi] [PATCH v6 00/17] arm64: sunxi: Initial Allwinner H616 SoC support
Hi,
after some pause those are the "remaining" patches to get the new
Allwinner H616 SoC supported.
Compared to v5 from January there are quite some changes: For a start
the clock, pinctrl and MMC bits made it into v5.12 already, so this series
starts right after that. The missing interrupt facility of the AXP is now
hopefully solved properly (patch 02).
The RTC turned out to be incompatible, the date is stored in a different
way. Patch 04 addresses this now. And finally the USB support got some
major overhaul: For a start it now seems to work - but I claimed that
before, so don't hold your breath, but test, please! There are now two
new patches to the Allwinner USB PHY driver to make this happen (11 and 12),
plus we need some seemingly random extra list of clocks and reset added to
each EHCI and OHCI node. Not pretty, but this looks like a nasty hardware
problem, so probably justifies some quirk. Meh.
Changelog below. Based on 5.13-rc1.
U-Boot support is part of the v2021.04 release, and Trusted Firmware
support is also mainline and part of the just released v2.5 version.
As an added bonus I got myself the "X96 Mate" TV box [2] with this SoC, so
the final patch contains a DT for this box as well. Probably the first
supported Allwinner machine with 4GB of DRAM actually usable.
The whole series can also be found here:
https://github.com/apritzel/linux/commits/h616-v6
Thanks!
Andre
==
This series gathers patches to support the Allwinner H616 SoC. This is
a rather uninspired SoC (Quad-A53 with the usual peripherals), but
allows for some cheap development boards and TV boxes, and supports
up to 4GB of DRAM.
Various DT binding patches are sprinkled throughout the series, to add
the new compatible names right before they are used.
Patch 2 teaches the AXP MFD driver to get along without having an
interrupt, as the missing NMI pin on the H616 leads to some boards not
having the AXP IRQ line connected.
Patch 4 and 5 add support for the new RTC: the date is now stored as a
linear number, not broken down into day-month-year. The benefit is that
this lifts the limit of the old date counter, which would have rolled
over around 2032.
Patch 7 adds a tweak to the EMAC driver, to deal with the second EMAC
clock used for the second Ethernet controller.
This is somewhat optional for the current .dts, as this doesn't use
the second EMAC (yet).
Patches 10-13 add the USB support, there are several small changes needed
to the Allwinner PHY driver to make this work. Some hardware changes look
like accidents ;-)
Eventually we get the .dtsi for the SoC in patch 14, and the .dts for
the OrangePi Zero2 board[1] in the penultimate patch, followed by
the .dts for the X96 Mate TV box[2] in the final commit.
U-Boot and Trusted Firmware support is now merged in released versions,
it allows booting via FEL or SD card, also you can TFTP kernels in on
the OrangePi Zero 2 board.
Many thanks to Jernej for his tremendous help on this, also for the
awesome input and help from the #linux-sunxi Freenode channel.
Happy reviewing!
Cheers,
Andre
[1] https://linux-sunxi.org/Orange_Pi_Zero_2
[2] https://linux-sunxi.org/X96_Mate
Changelog v5 .. v6:
- Drop already merged clock, pinctrl and MMC support from this series
- Properly fix AXP support by skipping power key initialisation
- Add patch to support new RTC date storage encoding
- Re-add USB HCI PHY refactoring
- Add patch to allow USB reset line sharing
- Add patch to introduce quirk for PHY2 SIDDQ clearing
- Re-add USB nodes to the .dtsi
- Enable USB gadget support
- Add DT for X96 Mate TV box
Changelog v4 .. v5:
- Fix CCU binding to pass dtbs_check
- Add RSB compatible string to binding doc
- Rename IR pin name to pass dtbs_check
- Add EMAC compatible string to binding doc
- Drop USB PHY support and binding doc patches
- Drop USB nodes from .dtsi and .dts
- Drop second EMAC node from .dtsi
Changelog v3 .. v4:
- Drop MMC and pinctrl matches (already in some -next trees)
- Add Maxime's Acks
- Add patch to update the AXP MFD DT bindings
- Add new patch (05/21) to fix axp20x-pek driver
- Change AXP IRQ fix to check for invalid IRQ line number
- Split joint DT bindings patch (v3 18/21) into subsystems
- move dwmac variable to keep christmas tree
- Use enums for USB PHY compatible strings in DT binding
- Enable watchdog (briefly verified to work)
- Add PHY2 to HCI1&3, this fixes USB
- limit r-ccu register frame length to not collide with NMI controller
- add interrupt-controller property to AXP DT node
Changelog v2 .. v3:
- Add Rob's Acks
- Drop redundant maxItems from pinctrl DT binding
- Rename h_i2s* to just i2s* in pinctrl names
- Use more declarative i2s0_d{in,out}{0,1} names
- Add RSB pins to pinctrl
- Include RSB clocks (sharing with newly added H6 versions)
- Fix CEC clock (add 2nd enable bit, also fix predivider flag)
- Rename PMU_UNK1 register in USB PHY
- Add USB and MUSB DT binding patches
- Add MMC/SD speed modes to .dtsi
Changelog v1 .. v2:
- pinctrl:
