Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Wed, Feb 06, 2019 at 10:16:08AM +0100, Maxime Ripard wrote: > On Tue, Feb 05, 2019 at 09:49:17AM -0800, Vasily Khoruzhick wrote: > > On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard > > wrote: > > > > > > On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote: > > > > On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote: > > > > > >> IIRC, from the previous discussion, HDMI had a tolerancy > > > > > >> requirement > > > > > >> in the standard. Do you know if there's such a thing for eDP? That > > > > > >> would solve the issue for all the eDP displays at once. > > > > > > > > > > > >I don't have access to eDP standard - vesa.org says it's available to > > > > > >members only. > > > > > > > > > > Try out to grab an old version? > > > > > > > > > > I remember 1.0 is open. > > > > > > > > I can't find anything regarding dot clock tolerance in DisplayPort > > > > specification. > > > > > > I guess since the DP is a VESA spec, it's probably .5%, just like on > > > the EDID (well, CVT). > > > > Unfortunately that's not enough for Pinebook. It needs 1% for 768p > > panel. > > And that mode is stored in the EDID as a standard (or established) > timing, or a detailed timing? > > If the latter, then it should also provide the tolerancies as part of > the panel timing description. The simple-panel driver can, in addition to a struct drm_display_mode take a struct display_timings to specify the modes. These allow to define triplets for each parameter, which are usually found in panel datasheets. Of course that's not going to help you much if all you have is EDID and if that doesn't provide tolerances. Thierry > If the former, then what would be the advertised pixel clock and the > one we can compute? Maybe we have a bug somewhere. > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Tue, Feb 05, 2019 at 09:49:17AM -0800, Vasily Khoruzhick wrote: > On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard > wrote: > > > > On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote: > > > On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote: > > > > >> IIRC, from the previous discussion, HDMI had a tolerancy requirement > > > > >> in the standard. Do you know if there's such a thing for eDP? That > > > > >> would solve the issue for all the eDP displays at once. > > > > > > > > > >I don't have access to eDP standard - vesa.org says it's available to > > > > >members only. > > > > > > > > Try out to grab an old version? > > > > > > > > I remember 1.0 is open. > > > > > > I can't find anything regarding dot clock tolerance in DisplayPort > > > specification. > > > > I guess since the DP is a VESA spec, it's probably .5%, just like on > > the EDID (well, CVT). > > Unfortunately that's not enough for Pinebook. It needs 1% for 768p > panel. And that mode is stored in the EDID as a standard (or established) timing, or a detailed timing? If the latter, then it should also provide the tolerancies as part of the panel timing description. If the former, then what would be the advertised pixel clock and the one we can compute? Maybe we have a bug somewhere. Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Tue, Feb 5, 2019 at 7:42 AM Maxime Ripard wrote: > > On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote: > > On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote: > > > >> IIRC, from the previous discussion, HDMI had a tolerancy requirement > > > >> in the standard. Do you know if there's such a thing for eDP? That > > > >> would solve the issue for all the eDP displays at once. > > > > > > > >I don't have access to eDP standard - vesa.org says it's available to > > > >members only. > > > > > > Try out to grab an old version? > > > > > > I remember 1.0 is open. > > > > I can't find anything regarding dot clock tolerance in DisplayPort > > specification. > > I guess since the DP is a VESA spec, it's probably .5%, just like on > the EDID (well, CVT). Unfortunately that's not enough for Pinebook. It needs 1% for 768p panel. > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Mon, Feb 04, 2019 at 10:50:17AM -0800, Vasily Khoruzhick wrote: > On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote: > > >> IIRC, from the previous discussion, HDMI had a tolerancy requirement > > >> in the standard. Do you know if there's such a thing for eDP? That > > >> would solve the issue for all the eDP displays at once. > > > > > >I don't have access to eDP standard - vesa.org says it's available to > > >members only. > > > > Try out to grab an old version? > > > > I remember 1.0 is open. > > I can't find anything regarding dot clock tolerance in DisplayPort > specification. I guess since the DP is a VESA spec, it's probably .5%, just like on the EDID (well, CVT). Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. signature.asc Description: PGP signature
Re: [linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Mon, Feb 4, 2019 at 8:29 AM Icenowy Zheng wrote: > >> IIRC, from the previous discussion, HDMI had a tolerancy requirement > >> in the standard. Do you know if there's such a thing for eDP? That > >> would solve the issue for all the eDP displays at once. > > > >I don't have access to eDP standard - vesa.org says it's available to > >members only. > > Try out to grab an old version? > > I remember 1.0 is open. I can't find anything regarding dot clock tolerance in DisplayPort specification. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
On Mon, Feb 4, 2019 at 6:20 AM Maxime Ripard wrote:
>
> Hi,
>
> On Sun, Feb 03, 2019 at 10:54:55AM -0800, Vasily Khoruzhick wrote:
> > Clock rate check that was added in commit bb43d40d7c83 ("drm/sun4i: rgb:
> > Validate the clock rate") prevents some panel and bridges from working with
> > sun4i driver.
> >
> > Unfortunately, dotclock frequency for some modes are not achievable on
> > sunxi hardware, and there's a slight deviation in rate returned by
> > clk_round_rate(), so they fail this check.
> >
> > Experiments show that panels and bridges work fine with this slight
> > deviation, e.g. Pinebook that uses ANX6345 bridge with 768p eDP panel
> > requests 73 MHz, gets 72.296MHz instead (0.96% difference) and works just
> > fine.
> >
> > This patch adds a 1% tolerence to the dot clock check when bridge is
> > connected.
> >
> > Signed-off-by: Vasily Khoruzhick
>
> I'm not sure we want to make exceptions for all the hardware
> combination we face, but we should go for something more generic (and
> easier to maintain instead).
>
> IIRC, from the previous discussion, HDMI had a tolerancy requirement
> in the standard. Do you know if there's such a thing for eDP? That
> would solve the issue for all the eDP displays at once.
I don't have access to eDP standard - vesa.org says it's available to
members only.
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
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[linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
于 2019年2月5日 GMT+08:00 上午12:26:43, Vasily Khoruzhick 写到:
>On Mon, Feb 4, 2019 at 6:20 AM Maxime Ripard
> wrote:
>>
>> Hi,
>>
>> On Sun, Feb 03, 2019 at 10:54:55AM -0800, Vasily Khoruzhick wrote:
>> > Clock rate check that was added in commit bb43d40d7c83 ("drm/sun4i:
>rgb:
>> > Validate the clock rate") prevents some panel and bridges from
>working with
>> > sun4i driver.
>> >
>> > Unfortunately, dotclock frequency for some modes are not achievable
>on
>> > sunxi hardware, and there's a slight deviation in rate returned by
>> > clk_round_rate(), so they fail this check.
>> >
>> > Experiments show that panels and bridges work fine with this slight
>> > deviation, e.g. Pinebook that uses ANX6345 bridge with 768p eDP
>panel
>> > requests 73 MHz, gets 72.296MHz instead (0.96% difference) and
>works just
>> > fine.
>> >
>> > This patch adds a 1% tolerence to the dot clock check when bridge
>is
>> > connected.
>> >
>> > Signed-off-by: Vasily Khoruzhick
>>
>> I'm not sure we want to make exceptions for all the hardware
>> combination we face, but we should go for something more generic (and
>> easier to maintain instead).
>>
>> IIRC, from the previous discussion, HDMI had a tolerancy requirement
>> in the standard. Do you know if there's such a thing for eDP? That
>> would solve the issue for all the eDP displays at once.
>
>I don't have access to eDP standard - vesa.org says it's available to
>members only.
Try out to grab an old version?
I remember 1.0 is open.
>
>> Maxime
>>
>> --
>> Maxime Ripard, Bootlin
>> Embedded Linux and Kernel engineering
>> https://bootlin.com
>
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[linux-sunxi] Re: [PATCH RESEND v2 06/12] drm/sun4i: rgb: Add 1% tolerance to dclk frequency check when bridge is connected
Hi,
On Sun, Feb 03, 2019 at 10:54:55AM -0800, Vasily Khoruzhick wrote:
> Clock rate check that was added in commit bb43d40d7c83 ("drm/sun4i: rgb:
> Validate the clock rate") prevents some panel and bridges from working with
> sun4i driver.
>
> Unfortunately, dotclock frequency for some modes are not achievable on
> sunxi hardware, and there's a slight deviation in rate returned by
> clk_round_rate(), so they fail this check.
>
> Experiments show that panels and bridges work fine with this slight
> deviation, e.g. Pinebook that uses ANX6345 bridge with 768p eDP panel
> requests 73 MHz, gets 72.296MHz instead (0.96% difference) and works just
> fine.
>
> This patch adds a 1% tolerence to the dot clock check when bridge is
> connected.
>
> Signed-off-by: Vasily Khoruzhick
I'm not sure we want to make exceptions for all the hardware
combination we face, but we should go for something more generic (and
easier to maintain instead).
IIRC, from the previous discussion, HDMI had a tolerancy requirement
in the standard. Do you know if there's such a thing for eDP? That
would solve the issue for all the eDP displays at once.
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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