[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Maxime Ripard]

On Fri, Dec 04, 2015 at 10:24:42PM +0100, Jens Kuske wrote:
> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
> 
> Signed-off-by: Jens Kuske 

Applied, thanks!
Maxime

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[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Maxime Ripard]

On Tue, Dec 08, 2015 at 09:06:58AM +0100, Jean-Francois Moine wrote:
> On Mon, 7 Dec 2015 19:44:30 +0100
> Jens Kuske  wrote:
> 
> > >> + "bus_lcd0", "bus_lcd1", 
> > >> "bus_deint",
> > 
> > >   "bus_tcon0", "bus_tcon1", "bus_deint",
> > > 
> > > (the tcon1 clock is used by both lcd0 and lcd1, while
> > >  the tcon0 clock is used for TV output from lcd1)
> > 
> > Hi,
> > 
> > These are only the ahb bus gates, not the module clocks.
> > Naming them lcd might be a bit confusing, but it follows the naming we
> > used since sun4i. And the tcon modules are still called lcd0 and lcd1
> > module in the manual too.
> 
> There is no reference to TCON0 in the LCDs registers (H3 V1.1 pages 428
> and 435), only TCON1.
> 
> > Interestingly there is only a tcon0 module clock in the manual and no
> > tcon1, but that is not part of this patch.
> 
> Well, I looked again in the 3.4 kernel and, for the LCD0/HDMI, there is
> no clock setting for TCON1: it just receives the AHB1 clock.
> 
> This means that its gate ("bus_lcd1" or "ahb1_tcon1") must be enabled
> when streaming on LCD0 or LCD1.
> 
> The role of tcon0 is not yet clear to me, but it seems that its clock
> is the streaming clock for LCD1/TV, as the HDMI clock is for LCD0/HDMI.

If the H3 display block is done the same way than the A10 (and later)
one on this aspect, then the TCON has two channels with two different
streaming (or functional, you pick the name) clocks. The channel 0 is
usually used for RGB, the channel 1 for HDMI, composite and VGA.

Maybe they just added different bus gates for those two different
channels, and moved HDMI to the channel 0.

Anyway, that can always be changed later on if we have more clue on
what's going on.

Maxime

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Embedded Linux, Kernel and Android engineering
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[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jean-Francois Moine]

On Mon, 7 Dec 2015 19:44:30 +0100
Jens Kuske  wrote:

> >> +   "bus_lcd0", "bus_lcd1", 
> >> "bus_deint",
> 
> > "bus_tcon0", "bus_tcon1", "bus_deint",
> > 
> > (the tcon1 clock is used by both lcd0 and lcd1, while
> >  the tcon0 clock is used for TV output from lcd1)
> 
> Hi,
> 
> These are only the ahb bus gates, not the module clocks.
> Naming them lcd might be a bit confusing, but it follows the naming we
> used since sun4i. And the tcon modules are still called lcd0 and lcd1
> module in the manual too.

There is no reference to TCON0 in the LCDs registers (H3 V1.1 pages 428
and 435), only TCON1.

> Interestingly there is only a tcon0 module clock in the manual and no
> tcon1, but that is not part of this patch.

Well, I looked again in the 3.4 kernel and, for the LCD0/HDMI, there is
no clock setting for TCON1: it just receives the AHB1 clock.

This means that its gate ("bus_lcd1" or "ahb1_tcon1") must be enabled
when streaming on LCD0 or LCD1.

The role of tcon0 is not yet clear to me, but it seems that its clock
is the streaming clock for LCD1/TV, as the HDMI clock is for LCD0/HDMI.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jean-Francois Moine]

On Tue, 8 Dec 2015 09:32:24 +0100
Maxime Ripard  wrote:

> If the H3 display block is done the same way than the A10 (and later)
> one on this aspect, then the TCON has two channels with two different
> streaming (or functional, you pick the name) clocks. The channel 0 is
> usually used for RGB, the channel 1 for HDMI, composite and VGA.
> 
> Maybe they just added different bus gates for those two different
> channels, and moved HDMI to the channel 0.
> 
> Anyway, that can always be changed later on if we have more clue on
> what's going on.

I don't know about the other Allwinner chips, and your DRM driver for
these ones cannot be reused for the H3 because its display engine
(DE.2) is completely different.

The DE2 runs at 432MHz and treats both LCDs. The TCON1 runs at a fixed
rate, 200MHz, and the streaming rates are defined by the HDMI (LCD0) and
TCON0 (LCD1) clocks.

BTW, I hope to submit a H3 DRM driver before new year.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jean-Francois Moine]

On Fri,  4 Dec 2015 22:24:42 +0100
Jens Kuske  wrote:

> The Allwinner H3 is a home entertainment system oriented SoC with
> four Cortex-A7 cores and a Mali-400MP2 GPU.
> 
> Signed-off-by: Jens Kuske 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 497 
> 
>  1 file changed, 497 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> new file mode 100644
> index 000..1524130e
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -0,0 +1,497 @@
[snip]
> + bus_gates: clk@01c20060 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun8i-h3-bus-gates-clk";
> + reg = <0x01c20060 0x14>;
> + clocks = <>, <>, <>, <>;
> + clock-names = "ahb1", "ahb2", "apb1", "apb2";
> + clock-indices = <5>, <6>, <8>,
> + <9>, <10>, <13>,
> + <14>, <17>, <18>,
> + <19>, <20>,
> + <21>, <23>,
> + <24>, <25>,
> + <26>, <27>,
> + <28>, <29>,
> + <30>, <31>, <32>,
> + <35>, <36>, <37>,
> + <40>, <41>, <43>,
> + <44>, <52>, <53>,
> + <54>, <64>,
> + <65>, <69>, <72>,
> + <76>, <77>, <78>,
> + <96>, <97>, <98>,
> + <112>, <113>,
> + <114>, <115>,
> + <116>, <128>, <135>;
> + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
> +  "bus_mmc1", "bus_mmc2", "bus_nand",
> +  "bus_sdram", "bus_gmac", "bus_ts",
> +  "bus_hstimer", "bus_spi0",
> +  "bus_spi1", "bus_otg",
> +  "bus_otg_ehci0", "bus_ehci1",
> +  "bus_ehci2", "bus_ehci3",
> +  "bus_otg_ohci0", "bus_ohci1",
> +  "bus_ohci2", "bus_ohci3", "bus_ve",
> +  "bus_lcd0", "bus_lcd1", 
> "bus_deint",

The tcon1 clock is used by both lcd0 and lcd1, while the tcon0 clock is used 
for TV output from lcd1, so, this should be:

"bus_tcon0", "bus_tcon1", "bus_deint",

(the tcon1 clock is used by both lcd0 and lcd1, while
 the tcon0 clock is used for TV output from lcd1)

> +  "bus_csi", "bus_tve", "bus_hdmi",
> +  "bus_de", "bus_gpu", "bus_msgbox",
> +  "bus_spinlock", "bus_codec",
> +  "bus_spdif", "bus_pio", "bus_ths",
> +  "bus_i2s0", "bus_i2s1", "bus_i2s2",
> +  "bus_i2c0", "bus_i2c1", "bus_i2c2",
> +  "bus_uart0", "bus_uart1",
> +  "bus_uart2", "bus_uart3",
> +  "bus_scr", "bus_ephy", "bus_dbg";
> + };
[snip]

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

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[linux-sunxi] Re: [PATCH v5 3/4] ARM: dts: sunxi: Add Allwinner H3 DTSI

[Jens Kuske]

On 07/12/15 09:12, Jean-Francois Moine wrote:
> On Fri,  4 Dec 2015 22:24:42 +0100
> Jens Kuske  wrote:
> 
>> The Allwinner H3 is a home entertainment system oriented SoC with
>> four Cortex-A7 cores and a Mali-400MP2 GPU.
>>
>> Signed-off-by: Jens Kuske 
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 497 
>> 
>>  1 file changed, 497 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
>> b/arch/arm/boot/dts/sun8i-h3.dtsi
>> new file mode 100644
>> index 000..1524130e
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -0,0 +1,497 @@
>   [snip]
>> +bus_gates: clk@01c20060 {
>> +#clock-cells = <1>;
>> +compatible = "allwinner,sun8i-h3-bus-gates-clk";
>> +reg = <0x01c20060 0x14>;
>> +clocks = <>, <>, <>, <>;
>> +clock-names = "ahb1", "ahb2", "apb1", "apb2";
>> +clock-indices = <5>, <6>, <8>,
>> +<9>, <10>, <13>,
>> +<14>, <17>, <18>,
>> +<19>, <20>,
>> +<21>, <23>,
>> +<24>, <25>,
>> +<26>, <27>,
>> +<28>, <29>,
>> +<30>, <31>, <32>,
>> +<35>, <36>, <37>,
>> +<40>, <41>, <43>,
>> +<44>, <52>, <53>,
>> +<54>, <64>,
>> +<65>, <69>, <72>,
>> +<76>, <77>, <78>,
>> +<96>, <97>, <98>,
>> +<112>, <113>,
>> +<114>, <115>,
>> +<116>, <128>, <135>;
>> +clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
>> + "bus_mmc1", "bus_mmc2", "bus_nand",
>> + "bus_sdram", "bus_gmac", "bus_ts",
>> + "bus_hstimer", "bus_spi0",
>> + "bus_spi1", "bus_otg",
>> + "bus_otg_ehci0", "bus_ehci1",
>> + "bus_ehci2", "bus_ehci3",
>> + "bus_otg_ohci0", "bus_ohci1",
>> + "bus_ohci2", "bus_ohci3", "bus_ve",
>> + "bus_lcd0", "bus_lcd1", 
>> "bus_deint",
> 
> The tcon1 clock is used by both lcd0 and lcd1, while the tcon0 clock is used 
> for TV output from lcd1, so, this should be:
> 
>   "bus_tcon0", "bus_tcon1", "bus_deint",
> 
> (the tcon1 clock is used by both lcd0 and lcd1, while
>  the tcon0 clock is used for TV output from lcd1)

Hi,

These are only the ahb bus gates, not the module clocks.
Naming them lcd might be a bit confusing, but it follows the naming we
used since sun4i. And the tcon modules are still called lcd0 and lcd1
module in the manual too.

Interestingly there is only a tcon0 module clock in the manual and no
tcon1, but that is not part of this patch.

Jens


> 
>> + "bus_csi", "bus_tve", "bus_hdmi",
>> + "bus_de", "bus_gpu", "bus_msgbox",
>> + "bus_spinlock", "bus_codec",
>> + "bus_spdif", "bus_pio", "bus_ths",
>> + "bus_i2s0", "bus_i2s1", "bus_i2s2",
>> + "bus_i2c0", "bus_i2c1", "bus_i2c2",
>> + "bus_uart0", "bus_uart1",
>> + "bus_uart2", "bus_uart3",
>> + "bus_scr", "bus_ephy", "bus_dbg";
>> +};
>   [snip]
> 

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