Re: [HELP] USB 3.0 PCI Endpoint problem

2016-02-29 Thread Joao Pinto 
Hi Felipe,

On 2/22/2016 8:39 AM, Felipe Balbi wrote:
> 
> Could this be a bug in your emulation environment ? Have you tested any
> other PCIe endpoints ?
> 

We tried with a SATA endpoint and experienced the same problem, so there's some
problem that must be solved in our virtualization environment.
Thanks.

Joao
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Re: [HELP] USB 3.0 PCI Endpoint problem

2016-02-22 Thread Felipe Balbi 

Hi,

Joao Pinto  writes:
> Hi to all!
> I am testing a PCIe Root Complex prototyping setup in which I have a USB 3.0
> host as a PCI Endpoint.
> Running in an ARC CPU platform it works well, but when running in an emulated
> ARM64 (this is done by a Synopsys virtualization tool) the endpoint
> initialization fails as can be seen in the following log:
>
> xhci_hcd :01:00.0: xHCI Host Controller
> xhci_hcd :01:00.0: new USB bus registered, assigned bus number 1
> xhci_hcd :01:00.0: xHCI capability registers at ff80002c4000:
> xhci_hcd :01:00.0: CAPLENGTH AND HCIVERSION 0x960020:
> xhci_hcd :01:00.0: CAPLENGTH: 0x20
> xhci_hcd :01:00.0: HCIVERSION: 0x96
> xhci_hcd :01:00.0: HCSPARAMS 1: 0x4000820
> xhci_hcd :01:00.0:   Max device slots: 32
> xhci_hcd :01:00.0:   Max interrupters: 8
> xhci_hcd :01:00.0:   Max ports: 4
> xhci_hcd :01:00.0: HCSPARAMS 2: 0x11
> xhci_hcd :01:00.0:   Isoc scheduling threshold: 1
> xhci_hcd :01:00.0:   Maximum allowed segments in event ring: 1
> xhci_hcd :01:00.0: HCSPARAMS 3 0x0:
> xhci_hcd :01:00.0:   Worst case U1 device exit latency: 0
> xhci_hcd :01:00.0:   Worst case U2 device exit latency: 0
> xhci_hcd :01:00.0: HCC PARAMS 0x14042cb:
> xhci_hcd :01:00.0:   HC generates 64 bit addresses
> xhci_hcd :01:00.0:   FIXME: more HCCPARAMS debugging
> xhci_hcd :01:00.0: RTSOFF 0x600:
> xhci_hcd :01:00.0: xHCI operational registers at ff80002c4020:
> xhci_hcd :01:00.0: USBCMD 0x0:
> xhci_hcd :01:00.0:   HC is being stopped
> xhci_hcd :01:00.0:   HC has finished hard reset
> xhci_hcd :01:00.0:   Event Interrupts disabled
> xhci_hcd :01:00.0:   Host System Error Interrupts disabled
> xhci_hcd :01:00.0:   HC has finished light reset
> xhci_hcd :01:00.0: USBSTS 0x9:
> xhci_hcd :01:00.0:   Event ring is not empty
> xhci_hcd :01:00.0:   No Host System Error
> xhci_hcd :01:00.0:   HC is halted
> xhci_hcd :01:00.0: ff80002c4420 port status reg = 0x2a0
> xhci_hcd :01:00.0: ff80002c4424 port power reg = 0x0
> xhci_hcd :01:00.0: ff80002c4428 port link reg = 0x0
> xhci_hcd :01:00.0: ff80002c442c port reserved reg = 0x0
> xhci_hcd :01:00.0: ff80002c4430 port status reg = 0x2a0
> xhci_hcd :01:00.0: ff80002c4434 port power reg = 0x0
> xhci_hcd :01:00.0: ff80002c4438 port link reg = 0x0
> xhci_hcd :01:00.0: ff80002c443c port reserved reg = 0x0
> xhci_hcd :01:00.0: ff80002c4440 port status reg = 0x2a0
> xhci_hcd :01:00.0: ff80002c port power reg = 0x0
> xhci_hcd :01:00.0: ff80002c4448 port link reg = 0x0
> xhci_hcd :01:00.0: ff80002c444c port reserved reg = 0x0
> xhci_hcd :01:00.0: ff80002c4450 port status reg = 0x2a0
> xhci_hcd :01:00.0: ff80002c4454 port power reg = 0x0
> xhci_hcd :01:00.0: ff80002c4458 port link reg = 0x0
> xhci_hcd :01:00.0: ff80002c445c port reserved reg = 0x0
> xhci_hcd :01:00.0: // Halt the HC
> xhci_hcd :01:00.0: Resetting HCD
> xhci_hcd :01:00.0: // Reset the HC
> xhci_hcd :01:00.0: Wait for controller to be ready for doorbell rings
> xhci_hcd :01:00.0: Reset complete
> xhci_hcd :01:00.0: Enabling 64-bit DMA addresses.
> xhci_hcd :01:00.0: Calling HCD init
> xhci_hcd :01:00.0: xhci_init
> xhci_hcd :01:00.0: xHCI doesn't need link TRB QUIRK
> xhci_hcd :01:00.0: Supported page size register = 0x1
> xhci_hcd :01:00.0: Supported page size of 4K
> xhci_hcd :01:00.0: HCD page size set to 4K
> xhci_hcd :01:00.0: // xHC can handle at most 32 device slots.
> xhci_hcd :01:00.0: // Setting Max device slots reg = 0x20.
> xhci_hcd :01:00.0: // Device context base array address = 0xfcafb000 
> (DMA),
> ff80002c7000 (virt)
> xhci_hcd :01:00.0: Allocated command ring at ffc07db28cc0
> xhci_hcd :01:00.0: First segment DMA is 0xfc42c000
> xhci_hcd :01:00.0: // Setting command ring address to 0x20
> xhci_hcd :01:00.0: // xHC command ring deq ptr low bits + flags = 
> @
> xhci_hcd :01:00.0: // xHC command ring deq ptr high bits = @
> xhci_hcd :01:00.0: // Doorbell array is located at offset 0x800 from cap
> regs base addr
> xhci_hcd :01:00.0: // xHCI capability registers at ff80002c4000:
> xhci_hcd :01:00.0: // @ff80002c4000 = 0x960020 (CAPLENGTH AND 
> HCIVERSION)
> xhci_hcd :01:00.0: //   CAPLENGTH: 0x20
> xhci_hcd :01:00.0: // xHCI operational registers at ff80002c4020:
> xhci_hcd :01:00.0: // @ff80002c4018 = 0x600 RTSOFF
> xhci_hcd :01:00.0: // xHCI runtime registers at ff80002c4600:
> xhci_hcd :01:00.0: // @ff80002c4014 = 0x800 DBOFF
> xhci_hcd :01:00.0: // Doorbell array at ff80002c4800:
> xhci_hcd :01:00.0: xHCI runtime registers at ff80002c4600:
> xhci_hcd :01:00.0:   ff80002c4600: Microframe index = 0x0
> xhci_hcd

[HELP] USB 3.0 PCI Endpoint problem

2016-02-19 Thread Joao Pinto 
Hi to all!
I am testing a PCIe Root Complex prototyping setup in which I have a USB 3.0
host as a PCI Endpoint.
Running in an ARC CPU platform it works well, but when running in an emulated
ARM64 (this is done by a Synopsys virtualization tool) the endpoint
initialization fails as can be seen in the following log:

xhci_hcd :01:00.0: xHCI Host Controller
xhci_hcd :01:00.0: new USB bus registered, assigned bus number 1
xhci_hcd :01:00.0: xHCI capability registers at ff80002c4000:
xhci_hcd :01:00.0: CAPLENGTH AND HCIVERSION 0x960020:
xhci_hcd :01:00.0: CAPLENGTH: 0x20
xhci_hcd :01:00.0: HCIVERSION: 0x96
xhci_hcd :01:00.0: HCSPARAMS 1: 0x4000820
xhci_hcd :01:00.0:   Max device slots: 32
xhci_hcd :01:00.0:   Max interrupters: 8
xhci_hcd :01:00.0:   Max ports: 4
xhci_hcd :01:00.0: HCSPARAMS 2: 0x11
xhci_hcd :01:00.0:   Isoc scheduling threshold: 1
xhci_hcd :01:00.0:   Maximum allowed segments in event ring: 1
xhci_hcd :01:00.0: HCSPARAMS 3 0x0:
xhci_hcd :01:00.0:   Worst case U1 device exit latency: 0
xhci_hcd :01:00.0:   Worst case U2 device exit latency: 0
xhci_hcd :01:00.0: HCC PARAMS 0x14042cb:
xhci_hcd :01:00.0:   HC generates 64 bit addresses
xhci_hcd :01:00.0:   FIXME: more HCCPARAMS debugging
xhci_hcd :01:00.0: RTSOFF 0x600:
xhci_hcd :01:00.0: xHCI operational registers at ff80002c4020:
xhci_hcd :01:00.0: USBCMD 0x0:
xhci_hcd :01:00.0:   HC is being stopped
xhci_hcd :01:00.0:   HC has finished hard reset
xhci_hcd :01:00.0:   Event Interrupts disabled
xhci_hcd :01:00.0:   Host System Error Interrupts disabled
xhci_hcd :01:00.0:   HC has finished light reset
xhci_hcd :01:00.0: USBSTS 0x9:
xhci_hcd :01:00.0:   Event ring is not empty
xhci_hcd :01:00.0:   No Host System Error
xhci_hcd :01:00.0:   HC is halted
xhci_hcd :01:00.0: ff80002c4420 port status reg = 0x2a0
xhci_hcd :01:00.0: ff80002c4424 port power reg = 0x0
xhci_hcd :01:00.0: ff80002c4428 port link reg = 0x0
xhci_hcd :01:00.0: ff80002c442c port reserved reg = 0x0
xhci_hcd :01:00.0: ff80002c4430 port status reg = 0x2a0
xhci_hcd :01:00.0: ff80002c4434 port power reg = 0x0
xhci_hcd :01:00.0: ff80002c4438 port link reg = 0x0
xhci_hcd :01:00.0: ff80002c443c port reserved reg = 0x0
xhci_hcd :01:00.0: ff80002c4440 port status reg = 0x2a0
xhci_hcd :01:00.0: ff80002c port power reg = 0x0
xhci_hcd :01:00.0: ff80002c4448 port link reg = 0x0
xhci_hcd :01:00.0: ff80002c444c port reserved reg = 0x0
xhci_hcd :01:00.0: ff80002c4450 port status reg = 0x2a0
xhci_hcd :01:00.0: ff80002c4454 port power reg = 0x0
xhci_hcd :01:00.0: ff80002c4458 port link reg = 0x0
xhci_hcd :01:00.0: ff80002c445c port reserved reg = 0x0
xhci_hcd :01:00.0: // Halt the HC
xhci_hcd :01:00.0: Resetting HCD
xhci_hcd :01:00.0: // Reset the HC
xhci_hcd :01:00.0: Wait for controller to be ready for doorbell rings
xhci_hcd :01:00.0: Reset complete
xhci_hcd :01:00.0: Enabling 64-bit DMA addresses.
xhci_hcd :01:00.0: Calling HCD init
xhci_hcd :01:00.0: xhci_init
xhci_hcd :01:00.0: xHCI doesn't need link TRB QUIRK
xhci_hcd :01:00.0: Supported page size register = 0x1
xhci_hcd :01:00.0: Supported page size of 4K
xhci_hcd :01:00.0: HCD page size set to 4K
xhci_hcd :01:00.0: // xHC can handle at most 32 device slots.
xhci_hcd :01:00.0: // Setting Max device slots reg = 0x20.
xhci_hcd :01:00.0: // Device context base array address = 0xfcafb000 (DMA),
ff80002c7000 (virt)
xhci_hcd :01:00.0: Allocated command ring at ffc07db28cc0
xhci_hcd :01:00.0: First segment DMA is 0xfc42c000
xhci_hcd :01:00.0: // Setting command ring address to 0x20
xhci_hcd :01:00.0: // xHC command ring deq ptr low bits + flags = @
xhci_hcd :01:00.0: // xHC command ring deq ptr high bits = @
xhci_hcd :01:00.0: // Doorbell array is located at offset 0x800 from cap
regs base addr
xhci_hcd :01:00.0: // xHCI capability registers at ff80002c4000:
xhci_hcd :01:00.0: // @ff80002c4000 = 0x960020 (CAPLENGTH AND 
HCIVERSION)
xhci_hcd :01:00.0: //   CAPLENGTH: 0x20
xhci_hcd :01:00.0: // xHCI operational registers at ff80002c4020:
xhci_hcd :01:00.0: // @ff80002c4018 = 0x600 RTSOFF
xhci_hcd :01:00.0: // xHCI runtime registers at ff80002c4600:
xhci_hcd :01:00.0: // @ff80002c4014 = 0x800 DBOFF
xhci_hcd :01:00.0: // Doorbell array at ff80002c4800:
xhci_hcd :01:00.0: xHCI runtime registers at ff80002c4600:
xhci_hcd :01:00.0:   ff80002c4600: Microframe index = 0x0
xhci_hcd :01:00.0: // Allocating event ring
xhci_hcd :01:00.0: TRB math tests passed.
xhci_hcd :01:00.0: // Allocated event ring segment table at 0xfc42e000
xhci_hcd :01:00.0: Set ERST to 0; private num segs = 1, virt addr =