From: Meng Li <meng...@windriver.com>
Based on FPGA ghrd(golden hardware reference design) hw design
that includes gpio feature, add corresponding dts file to enable
FPGA sw3, FPGA buttion and FPGA led.
Signed-off-by: Meng Li <meng...@windriver.com>
---
arch/arm64/boot/dts/altera/Makefile | 2 +-
.../altera/socfpga_stratix10_socdk_ghrd.dts | 78 +++++++++++++++++++
2 files changed, 79 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
diff --git a/arch/arm64/boot/dts/altera/Makefile
b/arch/arm64/boot/dts/altera/Makefile
index 43f4f47d3ea0..170f1811c4b5 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
socfpga_stratix10_fpga_update.dtb socfpga_stratix10_socdk_pcie.dtb \
- socfpga_stratix10_socdk_sgmii.dtb
socfpga_stratix10_socdk_nand.dtb
+ socfpga_stratix10_socdk_sgmii.dtb
socfpga_stratix10_socdk_ghrd.dtb socfpga_stratix10_socdk_nand.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
new file mode 100644
index 000000000000..a05fd640b2e5
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_ghrd.dts
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright Altera Corporation (C) 2021. All rights reserved.
+ */
+
+#include "socfpga_stratix10_socdk.dts"
+
+/{
+ soc {
+
+ led_pio: gpio@1080 {
+ compatible = "altr,pio-1.0";
+ reg = <0xf9001080 0x8>;
+ altr,gpio-bank-width = <4>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ resetvalue = <0>;
+ };
+
+ button_pio: gpio@1060 {
+ compatible = "altr,pio-1.0";
+ reg = <0xf9001060 0x10>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 18 4>;
+ altr,gpio-bank-width = <4>;
+ altr,interrupt-type = <2>;
+ altr,interrupt_type = <2>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ dipsw_pio: gpio@1070 {
+ compatible = "altr,pio-1.0";
+ reg = <0xf9001070 0x10>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 17 4>;
+ altr,gpio-bank-width = <4>;
+ altr,interrupt-type = <3>;
+ altr,interrupt_type = <3>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ trigger_pio: gpio@1040 {
+ compatible = "altr,pio-1.0";
+ reg = <0xf9001040 0x20>;
+ altr,gpio-bank-width = <4>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ resetvalue = <0>;
+ };
+
+ soc_leds: leds {
+ compatible = "gpio-leds";
+
+ led_fpga0: fpga0 {
+ label = "fpga_led0";
+ gpios = <&led_pio 0 0>;
+ }; //end fpga0 (led_fpga0)
+
+ led_fpga1: fpga1 {
+ label = "fpga_led1";
+ gpios = <&led_pio 1 0>;
+ }; //end fpga1 (led_fpga1)
+
+ led_fpga2: fpga2 {
+ label = "fpga_led2";
+ gpios = <&led_pio 2 0>;
+ }; //end fpga2 (led_fpga2)
+
+ led_fpga3: fpga3 {
+ label = "fpga_led3";
+ gpios = <&led_pio 3 0>;
+ }; //end fpga3 (led_fpga3)
+ };
+
+ };
+};
--
2.17.1
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