From: Paul Butler <paul.but...@windriver.com>
BASE_ADDR1 register
Updated PCIe driver to set PCIe BASE_ADDR1 register to 0x0 without
which PCIe inbound access wasn't working and we were seeing several
suprious PEI interrupts including BAR mismatch interrupt.
Signed-off-by: SangeethaRao <sangeetha....@lsi.com>
Signed-off-by: Paul Butler <paul.but...@windriver.com>
---
arch/arm/mach-axxia/pci.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-axxia/pci.c b/arch/arm/mach-axxia/pci.c
index 2600892..49565e8 100644
--- a/arch/arm/mach-axxia/pci.c
+++ b/arch/arm/mach-axxia/pci.c
@@ -667,20 +667,23 @@ static int axxia_pcie_setup(int portno, struct
pci_sys_data *sys)
/* Configure the inbound window size */
inbound_size = (u32) resource_size(&port->inbound);
- writel(inbound_size, port->regs + PCIE_RC_BAR0_SIZE);
+ writel(~(inbound_size-1), port->regs + PCIE_RC_BAR0_SIZE);
/* Verify BAR0 size */
{
u32 bar0_size;
writel(~0, port->regs + PCI_BASE_ADDRESS_0);
bar0_size = readl(port->regs + PCI_BASE_ADDRESS_0);
- if ((bar0_size & ~0xf) != inbound_size)
+ if ((bar0_size & ~0xf) != ~(inbound_size-1))
pr_err("PCIE%d: Config BAR0 failed\n", port->index);
}
/* Set the BASE0 address to start of PCIe base */
writel(port->pci_bar, port->regs + PCI_BASE_ADDRESS_0);
+ /* Set the BASE1 address to 0x0 */
+ writel(0x0, port->regs + PCI_BASE_ADDRESS_1);
+
/* Setup TPAGE registers for inbound mapping
*
* We set the MSB of each TPAGE to select 128-bit AXI access. For the
--
1.7.9.5
--
_______________________________________________
linux-yocto mailing list
linux-yocto@yoctoproject.org
https://lists.yoctoproject.org/listinfo/linux-yocto
