Driver for the Microchip MRF24J40 802.15.4 WPAN module.
Changes in v4
Remove unnecessary #includes.
Fix comment style.
Fix hard-coded magic FIFO size
Fix C99 comment style.
Fix BUG_ON() for TX buffer length.
Added blank lines for readability.
use print_hex_dump() instead of printk().
Remove magic number 192us.
remove sizeof(*devrec) in call to iee802154_alloc_device().
rename mutex to buffer_mutex
Remove extra read of interrupt status register.
---
drivers/ieee802154/Kconfig| 11 +
drivers/ieee802154/Makefile |1 +
drivers/ieee802154/mrf24j40.c | 780 +
3 files changed, 792 insertions(+), 0 deletions(-)
create mode 100644 drivers/ieee802154/mrf24j40.c
diff --git a/drivers/ieee802154/Kconfig b/drivers/ieee802154/Kconfig
index b1f0ce8..7c8fde7 100644
--- a/drivers/ieee802154/Kconfig
+++ b/drivers/ieee802154/Kconfig
@@ -49,3 +49,14 @@ config IEEE802154_ADF7242
tristate ADF7242 transceiver driver
depends on IEEE802154_DRIVERS MAC802154
depends on SPI
+
+config IEEE802154_MRF24J40
+ tristate Microchip MRF24J40 transceiver driver
+ depends on IEEE802154_DRIVERS MAC802154
+ depends on SPI
+ ---help---
+ Say Y here to enable the MRF24J20 SPI 802.15.4 wireless
+ controller.
+
+ This driver can also be built as a module. To do so, say M here.
+ the module will be called 'mrf24j40'.
diff --git a/drivers/ieee802154/Makefile b/drivers/ieee802154/Makefile
index 54efc02..f060d51 100644
--- a/drivers/ieee802154/Makefile
+++ b/drivers/ieee802154/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_IEEE802154_SERIAL) += serial.o
obj-$(CONFIG_IEEE802154_AT86RF230) += at86rf230.o
obj-$(CONFIG_IEEE802154_CC2420) += cc2420.o
obj-$(CONFIG_IEEE802154_ADF7242) += adf7242.o
+obj-$(CONFIG_IEEE802154_MRF24J40) += mrf24j40.o
diff --git a/drivers/ieee802154/mrf24j40.c b/drivers/ieee802154/mrf24j40.c
new file mode 100644
index 000..c3e63fb
--- /dev/null
+++ b/drivers/ieee802154/mrf24j40.c
@@ -0,0 +1,780 @@
+/*
+ * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
+ *
+ * Copyright (C) 2012 Alan Ott a...@signal11.us
+ *Signal 11 Software
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include linux/spi/spi.h
+#include linux/interrupt.h
+#include linux/module.h
+#include net/wpan-phy.h
+#include net/mac802154.h
+
+/* MRF24J40 Short Address Registers */
+#define REG_RXMCR0x00 /* Receive MAC control */
+#define REG_PANIDL 0x01 /* PAN ID (low) */
+#define REG_PANIDH 0x02 /* PAN ID (high) */
+#define REG_SADRL0x03 /* Short address (low) */
+#define REG_SADRH0x04 /* Short address (high) */
+#define REG_EADR00x05 /* Long address (low) (high is EADR7) */
+#define REG_TXMCR0x11 /* Transmit MAC control */
+#define REG_PACON0 0x16 /* Power Amplifier Control */
+#define REG_PACON1 0x17 /* Power Amplifier Control */
+#define REG_PACON2 0x18 /* Power Amplifier Control */
+#define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */
+#define REG_TXSTAT 0x24 /* TX MAC Status Register */
+#define REG_SOFTRST 0x2A /* Soft Reset */
+#define REG_TXSTBL 0x2E /* TX Stabilization */
+#define REG_INTSTAT 0x31 /* Interrupt Status */
+#define REG_INTCON 0x32 /* Interrupt Control */
+#define REG_RFCTL0x36 /* RF Control Mode Register */
+#define REG_BBREG1 0x39 /* Baseband Registers */
+#define REG_BBREG2 0x3A /* */
+#define REG_BBREG6 0x3E /* */
+#define REG_CCAEDTH 0x3F /* Energy Detection Threshold */
+
+/* MRF24J40 Long Address Registers */
+#define REG_RFCON0 0x200 /* RF Control Registers */
+#define REG_RFCON1 0x201
+#define REG_RFCON2 0x202
+#define REG_RFCON3 0x203
+#define REG_RFCON5 0x205
+#define REG_RFCON6 0x206
+#define REG_RFCON7 0x207
+#define REG_RFCON8 0x208
+#define REG_RSSI 0x210
+#define REG_SLPCON00x211 /* Sleep Clock Control Registers */
+#define REG_SLPCON10x220
+#define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
+#define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
+#define REG_RX_FIFO0x300 /* Receive FIFO */
+
+/* Device configuration: Only channels 11-26 on page 0 are supported. */
+#define MRF24J40_CHAN_MIN 11
+#define
