Re: [PATCH 0/5] Relocatable 64-bit kernel using linker PIE support
David Woodhouse writes: Is this mature enough for us to consider putting it in Fedora? We'd _love_ to stop building a separate kdump kernel for ppc64... Almost, but not quite. We'll need some modifications to yaboot (it refuses to accept an ET_DYN image, for instance), plus I'm currently seeing a puzzling crash inside OF on POWER5 when the image is loaded from yaboot but not when it's been loaded by netbooting the wrapper (having hacked the ELF header of vmlinux to make it an ET_EXEC so yaboot would touch it). The main remaining substantial technical issue is how we detect very early on that we are a kdump kernel. I think the policy should be that the kernel copies itself down to 0 if it's not a kdump kernel and runs wherever it was loaded if it's a kdump kernel. The only way to tell whether we're a kdump kernel seems to be to look at the kernel command line, which is a little tricky to do in head_64.S when the command line is buried inside the DTB. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/5] Relocatable 64-bit kernel using linker PIE support
Kumar Gala writes: Also, can we get this on ppc32 (head_32.S)? Probably. I'll give it a go. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 0/5] Relocatable 64-bit kernel using linker PIE support
From: Paul Mackerras [EMAIL PROTECTED] Date: Fri, 29 Aug 2008 15:40:36 +1000 The main remaining substantial technical issue is how we detect very early on that we are a kdump kernel. I think the policy should be that the kernel copies itself down to 0 if it's not a kdump kernel and runs wherever it was loaded if it's a kdump kernel. The only way to tell whether we're a kdump kernel seems to be to look at the kernel command line, which is a little tricky to do in head_64.S when the command line is buried inside the DTB. Why not put a key at a fixed location in the .text section or similar? Then you can access it using PC relative addressing, and whatever loads the kdump kernel can put an appropriate value there. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Thu, 2008-08-28 at 17:04 +0200, Arnd Bergmann wrote:
On Thursday 28 August 2008, Li Yang wrote:
Some of Freescale SoC chips have a QE or CPM co-processor which
supports full speed USB. The driver adds device mode support
of both QE and CPM USB controller to Linux USB gadget. The
driver is tested with MPC8360 and MPC8272, and should work with
other models having QE/CPM given minor tweaks.
Looks pretty good, just a few comments on the driver:
+config USB_GADGET_FSL_QE
+ boolean Freescale QE/CPM USB Device Controller
+ depends on FSL_SOC (QUICC_ENGINE || CPM)
+ help
+ Some of Freescale PowerPC processors have a Full Speed
+ QE/CPM2 USB controller, which support device mode with 4
+ programmable endpoints. This driver supports the
+ controller in the MPC8360 and MPC8272, and should work with
+ controllers having QE or CPM2, given minor tweaks.
+
+ Say y to link the driver statically, or m to build a
+ dynamically linked module called fsl_qe_udc and force all
+ gadget drivers to also be dynamically linked.
+
+config USB_FSL_QE
+ tristate
+ depends on USB_GADGET_FSL_QE
+ default USB_GADGET
+ select USB_GADGET_SELECTED
Why do you need the two config options, not just one?
This is common for udc drivers. I guess this measure is used to make
the selection of udc drivers a choice list while still make it possible
to compiled as module.
+#ifdef CONFIG_CPM2
+#include asm/cpm.h
+
+#define qe_muram_addr cpm_muram_addr
+#define qe_muram_offset cpm_muram_offset
+#define qe_muram_alloc cpm_muram_alloc
+#define qe_muram_free cpm_muram_free
+#endif
...
+static int qe_ep_cmd_restarttx(struct qe_ep *ep)
+{
+ u8 ep_num;
+#ifdef CONFIG_CPM2
+ u32 command;
+ u8 opcode;
+
+ ep_num = ep-epnum CPM_USB_EP_SHIFT;
+ command = CPM_USB_RESTART_TX | (u32)ep_num;
+ opcode = CPM_USB_RESTART_TX_OPCODE;
+ cpm_command(command, opcode);
+#else
+ ep_num = ep-epnum;
+ qe_issue_cmd(QE_USB_RESTART_TX, QE_CR_SUBBLOCK_USB, ep_num, 0);
+#endif
+ return 0;
+}
This part doesn't look good, you should try to avoid hardcoding
the specific type of chip (QE or CPM2) here. AFAICT, you can build
a multiplatform kernel that supports both QE and CPM2, but your code
here would be broken in that case if you try to run it on QE.
Ok.
+static void setup_received_handle(struct qe_udc *udc,
+ struct usb_ctrlrequest *setup);
+static int qe_ep_rxframe_handle(struct qe_ep *ep);
+static void ep0_req_complete(struct qe_udc *udc, struct qe_req *req);
Better try to avoid static forward declarations by reordering your
functions in call order. That is the common coding style and makes
drivers easier to read when you're used to it.
+
+ tasklet_schedule(udc-rx_tasklet);
Not a problem, but an observation: Most new code uses work queues instead
of tasklets these days, which gives you more predictable real time
latencies.
If you don't have a specific reason to prefer a tasklet, just use
a workqueue here.
Is this truly a trend? Work queue is more flexible but it has higher
latency. Why are work queues preferred?
- Leo
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: RFC: Could cpm2_clk_setup and cpm2_set_pin be exported ?
Hi Scott, On Thursday 28 August 2008, Scott Wood wrote: Laurent Pinchart wrote: On Thursday 28 August 2008, Scott Wood wrote: On Thu, Aug 28, 2008 at 05:57:13PM +0200, Laurent Pinchart wrote: I'm facing a situation where I need to call cpm2_clk_setup and cpm2_set_pin from a device driver compiled as a module. Before submitting a patch to export both functions, I'd like to make sure there isn't a cleaner way to implement the desired functionality without calling functions that are supposed to be used by board setup code. Have you looked at using the GPIO API? Yes, but the GPIO API doesn't support dedicated pin usage. Basically all I can do is configure a pin as a general purpose input or output, and set its level when configured as an output. The GPIO API doesn't provide any way to access the PAR and SOR registers. OK, wasn't sure what it was that you needed to set at runtime. Are you actually switching between dedicated functions dynamically? Why do you need to do this? Beside, the GPIO API won't help configuring clock routing. Why does the clock routing need to change dynamically? The Infineon SHDSL chip uses separate clocks for transmit and receives. The receive clock is always derived from the analog line and is routed from the SHDSL chip to a clock input on the MPC8248. The transmit clock is a bit trickier to handle, as it depends on which mode the SHDSL channel is configured in. When in Central Office mode, the transmit clock is generated by the MPC8248 using one of its BRG and output on an I/O pin. Clock routing on the MPC8248 routes CLKx to the SCC RX clock and BRGx to the SCC transmit clock. The CLKx and BRGx I/O pins must be configured accordingly. When in Remote Terminal mode, the receive clock must be looped to the transmit clock. This is achieved using a tristate buffer. The transmit clock signal is thus driven by the buffer instead of being driven by the MPC8248 BRGx pin. To avoid electrical conflicts I have to switch the BRGx I/O pin to an input. Clock routing must be reconfigured to route CLKx to both the SCC RX and TX clocks. If it turns out this really does need to happen, we can add some locks and export the functions, but I'd like to hear more about the use case first. GPIO configuration might be worked around by extending the GPIO API or providing CPM2-specific extensions. Clock routing configuration is in my opinion required at runtime and I can't see any easy work around this. Feel free to prove me wrong :-) Best regards, -- Laurent Pinchart CSE Semaphore Belgium Chaussee de Bruxelles, 732A B-1410 Waterloo Belgium T +32 (2) 387 42 59 F +32 (2) 387 42 75 signature.asc Description: This is a digitally signed message part. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Friday 29 August 2008, Li Yang wrote: Not a problem, but an observation: Most new code uses work queues instead of tasklets these days, which gives you more predictable real time latencies. If you don't have a specific reason to prefer a tasklet, just use a workqueue here. Is this truly a trend? Work queue is more flexible but it has higher latency. Why are work queues preferred? Most drivers don't need the low irq to bottom half latency. As I said, not a problem at all, just my observation. In 2.6.27, we have around three times more new workqueue usages than new tasklet usages. My feeling from doing reviews was that it would be closer to a factor of ten, but I guess I was wrong in that. Arnd ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Advice : console
Hello, I am trying to port linux for my ppc board. There is no keybord and no scree. There is only UART. I would like to have a console/terminal using UART. What is the best way ? to write a serial driver using struct uart_driver or using tty_driver or to write a driver from scratch. Maybe there is other way. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Advice : console
On Aug 29, 2008, at 4:40 AM, Sébastien Chrétien wrote: Hello, I am trying to port linux for my ppc board. There is no keybord and no scree. There is only UART. I would like to have a console/terminal using UART. What is the best way ? to write a serial driver using struct uart_driver or using tty_driver or to write a driver from scratch. Maybe there is other way. What powerpc chip is this? Most of the current SoC based chips 4xx/ 8xx/8xxx should have UART drivers in existence already. If this is something custom you are probably better of asking on the linux-kernel list this question since its not specific to PPC but just writing a driver. (and I'm guessing the answer is uart_driver, but I haven't looked at what Alan Cox has been up to w/tty vs uart lately). - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Efficient memcpy()/memmove() for G2/G3 cores...
On Wednesday 27 August 2008 23:04:39 Steven Munroe wrote: On Tue, 2008-08-26 at 08:28 +1000, Benjamin Herrenschmidt wrote: On Mon, 2008-08-25 at 15:06 +0200, David Jander wrote: Hi Matt, On Monday 25 August 2008 13:00:10 Matt Sealey wrote: The focus has definitely been on VMX but that's not to say lower power processors were forgotten :) lower-power (pun intended) is coming strong these days, as energy-efficiency is getteing more important every day. And the MPC5121 is a brand-new embedded processor, that will pop-up in quite a lot devices around you most probably ;-) It would be useful of somebody interested in getting things things into glibc did the necessary FSF copyright assignment stuff and worked toward integrating them. Ben makes a very good point! Sounds reasonable... but I am still wondering about what you mean with things? AFAICS there is almost nothing there (besides the memcpy() routine from Gunnar von Boehn, which is apparently still far from optimal). And I was asking for someone to correct me here ;-) There is also a framework for adding and maintaining optimizations of this type: http://penguinppc.org/dev/glibc/glibc-powerpc-cpu-addon.html I had already stumbled across this one, but it seems to focus on G3 or newer processors (power4). There is no optimal memcpy() for G2/PPC603/e300. [...] So it does no good to complain here. If you have core you want to contribute, Get your FSF CR assignment and join #glibc on freenode IRC. I am not complaining. I was only wondering if it is just me or there really is very little that has been done (for either uClibc, glibc, or whatever for powerpc) to improve performance of (linux-) applications on lower-power platforms (G2 core), AFAICS there is a LOT that can be gained by simple tweaks. And we will help you. Thanks, now that I know which is the correct way to contribute, I only need to come up with a good set of optimization, worthy of inclusion in glibc. OTOH, maybe it is easier and simpler to start with a collection of functions in a shared-library, that may be suited for preloading via LD_PRELOAD or /etc/ld_preload... Maybe once this collection is more stable (in terms of that heavy tweaking has stopped) one could try the pilgrimage towards glibc inclusion The problem is: I have very little experience with powerpc assembly and only very limited time to dedicate to this and I am looking for others who have Greetings, -- David Jander ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v3 1/2] powerpc: Board support for GE Fanuc SBC610
On Aug 26, 2008, at 8:13 AM, Martyn Welch wrote:
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0; // From uboot
+ clock-frequency = 0;// From uboot
you can remove these since u-boot will set them.
+ };
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0x0001;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0; // From uboot
+ clock-frequency = 0;// From uboot
you can remove these since u-boot will set them.
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x4000;// set by u-boot
if the comment is zero just set it to 0 0;
+ };
+
what u-boot version are you using/shipping with these boards?
Wondering if other props (like cache info, is set by u-boot for you).
- k
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [82xx] powerpc: Add support for mpc8247 based board MGCOGE from keymile.
On Jun 18, 2008, at 3:38 AM, Heiko Schocher wrote: Hello, changes since the last patch: update the Portpin initialization. [powerpc] Added support for the MPC8247 based board MGCOGE from Keymile. Signed-off-by: Heiko Schocher [EMAIL PROTECTED] --- arch/powerpc/boot/dts/mgcoge.dts | 174 +++ arch/powerpc/configs/mgcoge_defconfig | 900 + arch/powerpc/platforms/82xx/Kconfig |8 + arch/powerpc/platforms/82xx/Makefile |1 + arch/powerpc/platforms/82xx/mgcoge.c | 129 + 5 files changed, 1212 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mgcoge.dts create mode 100644 arch/powerpc/configs/mgcoge_defconfig create mode 100644 arch/powerpc/platforms/82xx/mgcoge.c applied to powerpc-next. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [8xx] powerpc: Add support for the MPC852 based mgsuvd board from keymile.
On Jun 14, 2008, at 2:02 PM, Heiko Schocher wrote: here the updated patch for the mgsuvd board. [powerpc] add support for the MPC852 based mgsuvd board from keymile to arch/powerpc. Supported SMC1 (serial console), SCC3 Ethernet (10Mbps hdx). Signed-off-by: Heiko Schocher [EMAIL PROTECTED] --- arch/powerpc/boot/dts/mgsuvd.dts | 163 ++ arch/powerpc/configs/mgsuvd_defconfig | 872 + arch/powerpc/platforms/8xx/Kconfig|6 + arch/powerpc/platforms/8xx/Makefile |1 + arch/powerpc/platforms/8xx/mgsuvd.c | 92 5 files changed, 1134 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mgsuvd.dts create mode 100644 arch/powerpc/configs/mgsuvd_defconfig create mode 100644 arch/powerpc/platforms/8xx/mgsuvd.c applied to powerpc-next. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc: Fix determining TI_CPU in power_save_ppc32_restore()
On Aug 25, 2008, at 11:39 PM, Benjamin Herrenschmidt wrote: On Mon, 2008-08-25 at 21:08 -0500, Kumar Gala wrote: The calculation to get TI_CPU based off of SPRG3 was just plain wrong. Just offset off the stack pointer (to get to thread_info) like all the other references to TI_CPU do. This was pointed out by Chen Gong [EMAIL PROTECTED] Signed-off-by: Kumar Gala [EMAIL PROTECTED] Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED] Paul, you picking this up for 2.6.27? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] cpm1: Fix race condition in CPM1 GPIO library.
On Aug 27, 2008, at 5:32 AM, Jochen Friedrich wrote: The CPM1 GPIO library code uses the non thread-safe clrbits32/ setbits32 macros. This patch protects them with a spinlock. Based on the CPM2 patch from Laurent Pinchart [EMAIL PROTECTED] , commit 639d64456e20cbfc866b18dc03cf9f9babc9c7cd. Signed-off-by: Jochen Friedrich [EMAIL PROTECTED] --- arch/powerpc/sysdev/cpm1.c | 74 ++ +- 1 files changed, 52 insertions(+), 22 deletions(-) applied. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2] powerpc: Only make kernel text pages of linear mapping executable
Commit bc033b63bbfeb6c4b4eb0a1d083c650e4a0d2af8 (powerpc/mm: Fix
attribute confusion with htab_bolt_mapping()) moved the check for
whether we should make pages of the linear mapping executable from
htab_bolt_mapping into its callers, including htab_initialize.
A side-effect of this is that the decision is now made once for
each contiguous section in the LMB array rather than for each page
individually. This can often mean that the whole of the linear
mapping ends up being executable.
This reverts to the previous behaviour, where individual pages are
checked for being part of the kernel text or not, by moving the check
back down into htab_bolt_mapping.
Signed-off-by: Paul Mackerras [EMAIL PROTECTED]
---
Previous version left all pages non-executable. Oops.
diff a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -191,12 +191,17 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long
vend,
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, ssize);
unsigned long va = hpt_va(vaddr, vsid, ssize);
+ unsigned long tprot = prot;
+
+ /* Make kernel text executable */
+ if (overlaps_kernel_text(vaddr, vaddr + step))
+ tprot = ~HPTE_R_N;
hash = hpt_hash(va, shift, ssize);
hpteg = ((hash htab_hash_mask) * HPTES_PER_GROUP);
BUG_ON(!ppc_md.hpte_insert);
- ret = ppc_md.hpte_insert(hpteg, va, paddr, prot,
+ ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
HPTE_V_BOLTED, psize, ssize);
if (ret 0)
@@ -584,7 +589,7 @@ void __init htab_initialize(void)
{
unsigned long table;
unsigned long pteg_count;
- unsigned long prot, tprot;
+ unsigned long prot;
unsigned long base = 0, size = 0, limit;
int i;
@@ -660,10 +665,9 @@ void __init htab_initialize(void)
for (i=0; i lmb.memory.cnt; i++) {
base = (unsigned long)__va(lmb.memory.region[i].base);
size = lmb.memory.region[i].size;
- tprot = prot | (in_kernel_text(base) ? _PAGE_EXEC : 0);
DBG(creating mapping for region: %lx..%lx (prot: %x)\n,
- base, size, tprot);
+ base, size, prot);
#ifdef CONFIG_U3_DART
/* Do not map the DART space. Fortunately, it will be aligned
@@ -680,21 +684,21 @@ void __init htab_initialize(void)
unsigned long dart_table_end = dart_tablebase + 16 * MB;
if (base != dart_tablebase)
BUG_ON(htab_bolt_mapping(base, dart_tablebase,
- __pa(base), tprot,
+ __pa(base), prot,
mmu_linear_psize,
mmu_kernel_ssize));
if ((base + size) dart_table_end)
BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
base + size,
__pa(dart_table_end),
-tprot,
+prot,
mmu_linear_psize,
mmu_kernel_ssize));
continue;
}
#endif /* CONFIG_U3_DART */
BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
- tprot, mmu_linear_psize, mmu_kernel_ssize));
+ prot, mmu_linear_psize, mmu_kernel_ssize));
}
/*
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Efficient memcpy()/memmove() for G2/G3 cores...
On Fri, 2008-08-29 at 13:48 +0200, David Jander wrote: On Wednesday 27 August 2008 23:04:39 Steven Munroe wrote: On Tue, 2008-08-26 at 08:28 +1000, Benjamin Herrenschmidt wrote: On Mon, 2008-08-25 at 15:06 +0200, David Jander wrote: Hi Matt, [SNIP] I am not complaining. I was only wondering if it is just me or there really is very little that has been done (for either uClibc, glibc, or whatever for powerpc) to improve performance of (linux-) applications on lower-power platforms (G2 core), AFAICS there is a LOT that can be gained by simple tweaks. [SNIP] The problem is: I have very little experience with powerpc assembly and only very limited time to dedicate to this and I am looking for others who have I improved the PowerPC memcpy and friends in uClibc a while ago. It does basically the same a the kernel memcpy but without any cache instructions. It is written in C, but in such a way that optimal assembly is generated. Jocke ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][USB] powerpc: Workaround for the PPC440EPX USBH_23 errata
Alan Stern wrote: On Thu, 28 Aug 2008, Steven A. Falco wrote: Alan Stern wrote: Your original post mentioned that the 440EPx has only one USB 2.0 host port. Then how can you use a keyboard and memory stick at the same time? You'd have to plug them into a hub -- in which case only one controller would be needed, the one driving the hub. The patch would be unnecessary. I have one of these processors on a Sequoia board. What happens is that if you build the kernel with both EHCI and OHCI support, then plug in a modern USB memory stick, it initially tries EHCI, the driver fails, and the whole thing falls back to OHCI. So you wind up running at 12 Mbps. The only way to make high speed work is to turn off the OHCI driver, and then you cannot support slow devices with that kernel. So, hile you cannot plug two devices in at one time, you can plug in different speed devices at different times, and my understanding is that this patch will let that work seamlessly. Is there some reason why it doesn't work already? All the patch does is suspend the OHCI root hub when you plug in the memory stick -- but the root hub should already be suspended. Unless the memory stick is already plugged in when the kernel boots. In which case the root hub won't be suspended -- it won't suspend until 1 second after ohci-hcd initializes the controller. Is that the scenario you're worried about? Not sure about other users, but in my case, yes. I was using a USB stick as the root filesystem. When the kernel first came up, it would try the EHCI driver, which would fail. Then the drive would be recognized by the OHCI driver, but would only run at full (12 Mbps) speed rather than high speed. I've since gone to a directly attached CF card on the processor external bus, and I'm not using USB anymore. But I think the patch is still desirable to work around the processor bug. Steve Alan Stern ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] [82xx] powerpc: Add support for mpc8247 based board MGCOGE from keymile.
Kumar Gala wrote: arch/powerpc/boot/dts/mgcoge.dts | 174 +++ arch/powerpc/configs/mgcoge_defconfig | 900 + arch/powerpc/platforms/82xx/Kconfig |8 + arch/powerpc/platforms/82xx/Makefile |1 + arch/powerpc/platforms/82xx/mgcoge.c | 129 + 5 files changed, 1212 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mgcoge.dts create mode 100644 arch/powerpc/configs/mgcoge_defconfig create mode 100644 arch/powerpc/platforms/82xx/mgcoge.c applied to powerpc-next. - k This is a bit ambiguous. Do you mean your galak next branch? Or the Ben/Paul powerpc next branch? Thanks, jdl ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:
_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)
On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.
The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.
On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/reg_booke.h |7
arch/powerpc/include/asm/tlbflush.h | 13 +---
arch/powerpc/kernel/misc_32.S| 52 ++
arch/powerpc/kernel/ppc_ksyms.c |3 ++
4 files changed, 70 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index be980f4..6745376 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -109,6 +109,7 @@
#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
#define SPRN_L1CSR00x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
@@ -410,6 +411,12 @@
#define L2CSR0_L2LOA 0x0080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO0x0020 /* L2 Cache Lock Overflow */
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI 0x0002 /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI 0x0004 /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI 0x0040 /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI 0x0020 /* TLB3 Flash invalidate */
+
/* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/include/asm/tlbflush.h
b/arch/powerpc/include/asm/tlbflush.h
index 361cd5c..38ec1e7 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -29,6 +29,9 @@
#include linux/mm.h
extern void _tlbie(unsigned long address, unsigned int pid);
+extern void _tlbil_all(void);
+extern void _tlbil_pid(unsigned int pid);
+extern void _tlbil_va(unsigned long address, unsigned int pid);
#if defined(CONFIG_40x) || defined(CONFIG_8xx)
#define _tlbia() asm volatile (tlbia; sync : : : memory)
@@ -38,31 +41,31 @@ extern void _tlbia(void);
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- _tlbia();
+ _tlbil_all();
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ _tlbil_va(vmaddr, vma ? vma-vm_mm-context.id : 0);
}
static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ flush_tlb_page(vma, vmaddr);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
#elif defined(CONFIG_PPC32)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..4923ae4 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -274,6 +274,9 @@ _GLOBAL(real_writeb)
/*
* Flush MMU TLB
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_all)
+#endif
_GLOBAL(_tlbia)
#if defined(CONFIG_40x)
sync/* Flush to memory before changing mapping */
@@ -344,6 +347,9 @@ _GLOBAL(_tlbia)
/*
* Flush MMU TLB for a particular address
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_va)
+#endif
_GLOBAL(_tlbie)
#if defined(CONFIG_40x)
/* We run the search with interrupts disabled because we have to change
@@ -436,6 +442,52 @@ _GLOBAL(_tlbie)
#endif /* ! CONFIG_40x */
blr
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * Flush MMU TLB, but only on the local processor (no broadcast)
+ */
+_GLOBAL(_tlbil_all)
+#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
+MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
+ li
[PATCH v2 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..db2e7bd 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm,addr,ptep)do { pte_update(ptep, ~0, 0); } while
(0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +612,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -658,8 +655,17 @@ static inline void set_pte_at(struct mm_struct *mm,
unsigned long addr,
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
#else
+#if defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
+#else
*ptep = pte;
#endif
+#endif
}
/*
--
1.5.5.1
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/kernel/head_fsl_booke.S | 24 1 files changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3cb52fa..fa39cce 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -579,13 +579,19 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ - bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) +#ifdef CONFIG_SMP + subfr10, r11, r12 /* create false data dep */ + lwzxr13, r11, r10 /* Get upper pte bits */ +#else + lwz r13, 0(r12) /* Get upper pte bits */ #endif +#endif + + bne 2f /* Bail if permission/valid mismach */ -/* Jump to common tlb load */ + /* Jump to common tlb load */ b finish_tlb_load 2: /* The bailout. Restore registers to pre-exception conditions @@ -640,6 +646,16 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ + +#ifdef CONFIG_PTE_64BIT +#ifdef CONFIG_SMP + subfr10, r11, r12 /* create false data dep */ + lwzxr13, r11, r10 /* Get upper pte bits */ +#else + lwz r13, 0(r12) /* Get upper pte bits */ +#endif +#endif + bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT @@ -702,7 +718,7 @@ interrupt_base: /* * Both the instruction and data TLB miss get to this * point to load the TLB. - * r10 - EA of fault + * r10 - available to use * r11 - TLB (info from Linux PTE) * r12 - available to use * r13 - upper bits of PTE (if PTE_64BIT) or available to use -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 4/4] powerpc/mm: Implement _PAGE_SPECIAL pte_special() for 32-bit
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().
We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 15 +--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index db2e7bd..82bf914 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;
#define _PAGE_HWEXEC 0x0004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x0008 /* S: Page referenced */
#define _PAGE_DIRTY0x0010 /* S: Page dirty */
+#define _PAGE_SPECIAL 0x0020 /* S: Special page */
#define _PAGE_USER 0x0040 /* S: User page */
#define _PAGE_ENDIAN 0x0080 /* H: E bit */
#define _PAGE_GUARDED 0x0100 /* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xULL
+#define __HAVE_ARCH_PTE_SPECIAL
#elif defined(CONFIG_FSL_BOOKE)
/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;
#define _PAGE_COHERENT 0x00100 /* H: M bit */
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
#define _PAGE_WRITETHRU0x00400 /* H: W bit */
+#define _PAGE_SPECIAL 0x00800 /* S: Special page */
#ifdef CONFIG_PTE_64BIT
/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+#define __HAVE_ARCH_PTE_SPECIAL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
#define _PAGE_RW 0x400 /* software: user write access allowed */
+#define _PAGE_SPECIAL 0x800 /* software: Special page */
#define _PTE_NONE_MASK _PAGE_HASHPTE
@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;
/* Hash table based platforms need atomic updates of the linux PTE */
#define PTE_ATOMIC_UPDATES 1
+#define __HAVE_ARCH_PTE_SPECIAL
+
#endif
/*
@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU0
#endif
+#ifndef _PAGE_SPECIAL
+#define _PAGE_SPECIAL 0
+#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK _PMD_PRESENT
#endif
@@ -533,7 +544,7 @@ static inline int pte_write(pte_t pte) {
return pte_val(pte) _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte)
_PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte)
_PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte_val(pte)
_PAGE_FILE; }
-static inline int pte_special(pte_t pte) { return 0; }
+static inline int pte_special(pte_t pte) { return pte_val(pte)
_PAGE_SPECIAL; }
static inline void pte_uncache(pte_t pte) { pte_val(pte) |=
_PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte) { pte_val(pte) =
~_PAGE_NO_CACHE; }
@@ -552,7 +563,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {
static inline pte_t pte_mkyoung(pte_t pte) {
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- return pte; }
+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline unsigned long pte_pgprot(pte_t pte)
{
return __pgprot(pte_val(pte)) PAGE_PROT_BITS;
--
1.5.5.1
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
RAMDISK driver initialized
Hello, I am using Linux 2.6.26. When I boot my board, I don't see the message : RAMDISK driver initialized:... Is it right ? ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH][V3] powerpc: add support for dynamic reconfiguration memory in kexec/kdump kernels
kdump kernel needs to use only those memory regions that it is allowed to use
(crashkernel, rtas, tce ..etc ). Each of these regions have their own sizes
and are currently added under 'linux,usable-memory' property under each
memory@ node of the device tree. ibm,dynamic-memory property of
ibm,dynamic-reconfiguration-memory node (on power6) now stores in it the
representation for most of the logical memory blocks with the size of each
memory block being a constant (lmb_size). If one or more or part of the above
mentioned regions lie under one of the lmb from ibm,dynamic-memory property,
there is a need to identify those regions within the given lmb. Following
patch recognizes a new property 'linux,drconf-usable-memory' property added by
kexec-tools. Each entry in this property is of the form 'a counter' followed
by those many (base, size) duple for the above mentioned regions.
Signed-off-by: Chandru Siddalingappa [EMAIL PROTECTED]
---
Patch was tested on a power6 box. Could you pls add this patch to powerpc git
tree ? . Thanks,
arch/powerpc/kernel/prom.c | 40 +++--
arch/powerpc/mm/numa.c | 79 +++
2 files changed, 96 insertions(+), 23 deletions(-)
diff -Naurp powerpc-orig/arch/powerpc/kernel/prom.c
powerpc/arch/powerpc/kernel/prom.c
--- powerpc-orig/arch/powerpc/kernel/prom.c 2008-08-14 08:23:25.0
+0530
+++ powerpc/arch/powerpc/kernel/prom.c 2008-08-14 14:35:24.0 +0530
@@ -888,9 +888,10 @@ static u64 __init dt_mem_next_cell(int s
*/
static int __init early_init_dt_scan_drconf_memory(unsigned long node)
{
- cell_t *dm, *ls;
+ cell_t *dm, *ls, *usm;
unsigned long l, n, flags;
u64 base, size, lmb_size;
+ unsigned int is_kexec_kdump = 0, rngs;
ls = (cell_t *)of_get_flat_dt_prop(node, ibm,lmb-size, l);
if (ls == NULL || l dt_root_size_cells * sizeof(cell_t))
@@ -905,6 +906,12 @@ static int __init early_init_dt_scan_drc
if (l (n * (dt_root_addr_cells + 4) + 1) * sizeof(cell_t))
return 0;
+ /* check if this is a kexec/kdump kernel. */
+ usm = (cell_t *)of_get_flat_dt_prop(node, linux,drconf-usable-memory,
+l);
+ if (usm != NULL)
+ is_kexec_kdump = 1;
+
for (; n != 0; --n) {
base = dt_mem_next_cell(dt_root_addr_cells, dm);
flags = dm[3];
@@ -915,13 +922,34 @@ static int __init early_init_dt_scan_drc
if ((flags 0x80) || !(flags 0x8))
continue;
size = lmb_size;
- if (iommu_is_off) {
- if (base = 0x8000ul)
+ rngs = 1;
+ if (is_kexec_kdump) {
+ /*
+* For each lmb in ibm,dynamic-memory, a corresponding
+* entry in linux,drconf-usable-memory property contains
+* a counter 'p' followed by 'p' (base, size) duple.
+* Now read the counter from
+* linux,drconf-usable-memory property
+*/
+ rngs = dt_mem_next_cell(dt_root_size_cells, usm);
+ if (!rngs) /* there are no (base, size) duple */
continue;
- if ((base + size) 0x8000ul)
- size = 0x8000ul - base;
}
- lmb_add(base, size);
+ do {
+ if (is_kexec_kdump) {
+ base = dt_mem_next_cell(dt_root_addr_cells,
+usm);
+ size = dt_mem_next_cell(dt_root_size_cells,
+usm);
+ }
+ if (iommu_is_off) {
+ if (base = 0x8000ul)
+ continue;
+ if ((base + size) 0x8000ul)
+ size = 0x8000ul - base;
+ }
+ lmb_add(base, size);
+ } while (--rngs);
}
lmb_dump_all();
return 0;
diff -Naurp powerpc-orig/arch/powerpc/mm/numa.c powerpc/arch/powerpc/mm/numa.c
--- powerpc-orig/arch/powerpc/mm/numa.c 2008-08-14 08:23:25.0 +0530
+++ powerpc/arch/powerpc/mm/numa.c 2008-08-14 14:35:42.0 +0530
@@ -150,6 +150,21 @@ static const int *of_get_associativity(s
return of_get_property(dev, ibm,associativity, NULL);
}
+/*
+ * Returns the property linux,drconf-usable-memory if
+ * it exists (the property exists only in kexec/kdump kernels,
+ * added by kexec-tools)
+ */
+static const u32 *of_get_usable_memory(struct device_node *memory)
+{
+ const u32 *prop;
+
Re: [PATCH] [82xx] powerpc: Add support for mpc8247 based board MGCOGE from keymile.
On Aug 29, 2008, at 8:51 AM, Jon Loeliger wrote: Kumar Gala wrote: arch/powerpc/boot/dts/mgcoge.dts | 174 +++ arch/powerpc/configs/mgcoge_defconfig | 900 ++ +++ arch/powerpc/platforms/82xx/Kconfig |8 + arch/powerpc/platforms/82xx/Makefile |1 + arch/powerpc/platforms/82xx/mgcoge.c | 129 + 5 files changed, 1212 insertions(+), 0 deletions(-) create mode 100644 arch/powerpc/boot/dts/mgcoge.dts create mode 100644 arch/powerpc/configs/mgcoge_defconfig create mode 100644 arch/powerpc/platforms/82xx/mgcoge.c applied to powerpc-next. - k This is a bit ambiguous. Do you mean your galak next branch? Or the Ben/Paul powerpc next branch? seeing as the email is from me, it means its applied to my powerpc- next branch. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][USB] powerpc: Workaround for the PPC440EPX USBH_23 errata
On Fri, 29 Aug 2008, Benjamin Herrenschmidt wrote: I suppose some embedded platforms don't use CONFIG_PM, is this still a requirement for autosuspend ? Or do that happen always on an empty port nowadays ? ohci-hcd doesn't automatically suspend the root hub if CONFIG_PM isn't set. However it isn't necessary to set CONFIG_SLEEP, CONFIG_HIBERNATION, or CONFIG_USB_SUSPEND. Alan Stern ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
On Aug 29, 2008, at 8:56 AM, Kumar Gala wrote:
There are some minor issues with support 64-bit PTEs on a 32-bit
processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/
include/asm/pgtable-ppc32.h
index 6fe39e3..db2e7bd 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,7 @@ extern unsigned long
bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte)(pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr),
(ptep), __pte(0)); } while (0)
+#define pte_clear(mm,addr,ptep) do { pte_update(ptep, ~0, 0); }
while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#define pmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +612,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move
set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -658,8 +655,17 @@ static inline void set_pte_at(struct mm_struct
*mm, unsigned long addr,
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
#else
+#if defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
I know it's a nit, but can you put the clobber on a new line? I
totally missed it the first time I read this, and got all worked up
about it :)
Cheers,
B
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Fri, 29 Aug 2008, Arnd Bergmann wrote: Does building a kernel image that can run on different hardware without rebuilding also violate the relevant standards? No. That isn't what Arnd was concerned about. He noted that even if you did build multiple modules, only one of them could be loaded at any time. Well, actually it was exactly what I was concerned about ;-) The way I understand the code, it is layered into the hardware specific part and the protocol specific part, which are connected through the interfaces I pointed out. That's right. The standard requires that there can only be one protocol handler per physical interface, which is a reasonable limitation. No, you've got it exactly backward. There can be multiple protocol handlers per physical interface, but there must be only one physical interface per device. However, what the Linux implementation actually enforces is that there can only be one hardware specific driver built or loaded into the kernel, which just looks like an arbitrary restriction that does not actually help. Not at all -- it is an implementation of the constraint that there be only one physical interface. If the gadget hardware drivers were registering the device with a gadget_bus_type, you could still enforce the only one protocol rule by binding every protocol to every device in that bus type. There is no such rule. Alan Stern ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
On Aug 29, 2008, at 8:56 AM, Kumar Gala wrote: Introduced a new set of low level tlb invalidate functions that do not broadcast invalidates on the bus: _tlbil_all - invalidate all _tlbil_pid - invalidate based on process id (or mm context) _tlbil_va - invalidate based on virtual address (ea + pid) On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and _tlbil_va should be functionally equivalent to _tlbie. The intent of this change is to handle SMP based invalidates via IPIs instead of broadcasts as the mechanism scales better for larger number of cores. On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls and tlbsx/tlbwe for invalidate virtual address. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/include/asm/reg_booke.h |7 arch/powerpc/include/asm/tlbflush.h | 13 +--- arch/powerpc/kernel/misc_32.S| 52 + + arch/powerpc/kernel/ppc_ksyms.c |3 ++ 4 files changed, 70 insertions(+), 5 deletions(-) ...snip #elif defined(CONFIG_PPC32) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/ misc_32.S index 7a6dfbc..4923ae4 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -274,6 +274,9 @@ _GLOBAL(real_writeb) /* * Flush MMU TLB */ +#ifndef CONFIG_FSL_BOOKE +_GLOBAL(_tlbil_all) +#endif _GLOBAL(_tlbia) #if defined(CONFIG_40x) sync/* Flush to memory before changing mapping */ @@ -344,6 +347,9 @@ _GLOBAL(_tlbia) /* * Flush MMU TLB for a particular address */ +#ifndef CONFIG_FSL_BOOKE +_GLOBAL(_tlbil_va) +#endif _GLOBAL(_tlbie) #if defined(CONFIG_40x) /* We run the search with interrupts disabled because we have to change @@ -436,6 +442,52 @@ _GLOBAL(_tlbie) #endif /* ! CONFIG_40x */ blr +#if defined(CONFIG_FSL_BOOKE) +/* + * Flush MMU TLB, but only on the local processor (no broadcast) + */ +_GLOBAL(_tlbil_all) +#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ +MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) + li r3,(MMUCSR0_TLBFI)@l + mtspr SPRN_MMUCSR0, r3 +1: + mfspr r3,SPRN_MMUCSR0 + andi. r3,r3,[EMAIL PROTECTED] + bne 1b + blr + +/* + * Flush MMU TLB for a particular process id, but only on the local processor + * (no broadcast) + */ +_GLOBAL(_tlbil_pid) + li r3,(MMUCSR0_TLBFI)@l + mtspr SPRN_MMUCSR0, r3 +1: + mfspr r3,SPRN_MMUCSR0 + andi. r1,r2,[EMAIL PROTECTED] + bne 1b + blr + Not sure how much it actually matters, but I think mtspr of MMUCSR0 on E500 requires CSI. Otherwise, LGTM. -B ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Friday 29 August 2008, Alan Stern wrote:
The standard requires that there can only be one protocol handler
per physical interface, which is a reasonable limitation.
No, you've got it exactly backward. There can be multiple protocol
handlers per physical interface, but there must be only one physical
interface per device.
Maybe I am using wrong terminology, but I still don't see how that
fits together. Let me try to explain what I have understood so far:
The physical device is identified by a struct usb_gadget is defined
statically in the driver that exports the
usb_gadget_{un,}register_driver() functions. Obviously there can only
be one physical interface per physical device, I was not arguing
against that.
The protocol handler is identified by a usb_gadget_driver and defined
in a driver that calls usb_gadget_register_driver().
You say that there can be multiple protocol handlers, which I don't
understand because the protocol handlers all call set_gadget_data,
which overwrites the previous driver_data field in struct usb_gadget,
making it impossible to load more than one simultaneously.
However, what the Linux implementation actually enforces is
that there can only be one hardware specific driver built or loaded
into the kernel, which just looks like an arbitrary restriction
that does not actually help.
Not at all -- it is an implementation of the constraint that there be
only one physical interface.
How that? Taking drivers/usb/gadget/fsl_usb2_udc.c as an example, it will
create a new fsl_udc structure for each matching platform_device it finds
(though it will leak every one except the last one), so the interface
does not limit the number of physical interfaces at all to this point,
the implementation of the every gadget hardware driver does this.
The real problem is that you cannot build a kernel that has both
fsl_usb2_udc.c and fsl_qe_udc.c built in. Having both drivers loaded
would not violate the one-interface rule, because only one of them
would find hardware to bind to on a given system, just like you can
load both the uhci and ohci drivers without them interfering.
Arnd
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH V3] POWERPC: Allow 32-bit hashed pgtable code to support 36-bit physical
This rearranges a bit of code, and adds support for
36-bit physical addressing for configs that use a
hashed page table. The 36b physical support is not
enabled by default on any config - it must be
explicitly enabled via the config system.
This patch *only* expands the page table code to accomodate
large physical addresses on 32-bit systems and enables the
PHYS_64BIT config option for 6xx. It does *not*
allow you to boot a board with more than about 3.5GB of
RAM - for that, SWIOTLB support is also required (and
coming soon).
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
Incorporated comments from the peanut gallery - restricted the Kconfig
option to PPC_86xx for now, as it breaks old 603x parts with DTLB/ITLB
software miss handling. Also changed hash_page and add_hash_page to not
worry about ordering when !SMP.
I have not optimized set_pte_at for !SMP at this point - I think Ben
and I need to mull this over a bit more first, and it will change
the non-large PTE version of the code as well, so we can handle
that in a followon patch.
This patch depends on Kumar's recent series
[PATCH v2 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
as some changes were made to the page table code there that this
patch depends on.
Cheers,
B
arch/powerpc/include/asm/io.h|2 +-
arch/powerpc/include/asm/page_32.h | 10 +++-
arch/powerpc/include/asm/pgtable-ppc32.h | 30 ++-
arch/powerpc/kernel/head_32.S|4 +-
arch/powerpc/kernel/head_fsl_booke.S |2 -
arch/powerpc/mm/hash_low_32.S| 86 --
arch/powerpc/mm/pgtable_32.c |4 +-
arch/powerpc/platforms/Kconfig.cputype | 17 ---
8 files changed, 123 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 77c7fa0..08266d2 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -711,7 +711,7 @@ static inline void * phys_to_virt(unsigned long address)
/*
* Change struct page to physical address.
*/
-#define page_to_phys(page) (page_to_pfn(page) PAGE_SHIFT)
+#define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) PAGE_SHIFT)
/* We do NOT want virtual merging, it would put too much pressure on
* our iommu allocator. Instead, we want drivers to be smart enough
diff --git a/arch/powerpc/include/asm/page_32.h
b/arch/powerpc/include/asm/page_32.h
index ebfae53..0b253f6 100644
--- a/arch/powerpc/include/asm/page_32.h
+++ b/arch/powerpc/include/asm/page_32.h
@@ -13,10 +13,18 @@
#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#endif
+#ifdef CONFIG_PTE_64BIT
+#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */
+#define LNX_PTE_SIZE 8 /* size of a linux PTE, in bytes */
+#else
+#define PTE_FLAGS_OFFSET 0
+#define LNX_PTE_SIZE 4
+#endif
+
#ifndef __ASSEMBLY__
/*
* The basic type of a PTE - 64 bits for those CPUs with 32 bit
- * physical addressing. For now this just the IBM PPC440.
+ * physical addressing.
*/
#ifdef CONFIG_PTE_64BIT
typedef unsigned long long pte_basic_t;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 82bf914..77e6d99 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -369,7 +369,12 @@ extern int icache_44x_need_flush;
#define _PAGE_RW 0x400 /* software: user write access allowed */
#define _PAGE_SPECIAL 0x800 /* software: Special page */
+#ifdef CONFIG_PTE_64BIT
+/* We never clear the high word of the pte */
+#define _PTE_NONE_MASK (0xULL | _PAGE_HASHPTE)
+#else
#define _PTE_NONE_MASK _PAGE_HASHPTE
+#endif
#define _PMD_PRESENT 0
#define _PMD_PRESENT_MASK (PAGE_MASK)
@@ -528,7 +533,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { pte_update(ptep, ~0, 0); } while
(0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -664,8 +670,30 @@ static inline void set_pte_at(struct mm_struct *mm,
unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
+#ifndef CONFIG_PTE_64BIT
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
#else
+ /*
+* We have to do the write of the 64b pte as 2 stores. This
+* code assumes that the entry we're storing to is currently
+* not valid and that all callers have the page table lock.
+* Having the entry be not valid protects readers who might read
+* between the first and second stores.
+*/
+ unsigned int tmp;
+
[PATCH V4] POWERPC: Allow 32-bit hashed pgtable code to support 36-bit physical
This rearranges a bit of code, and adds support for
36-bit physical addressing for configs that use a
hashed page table. The 36b physical support is not
enabled by default on any config - it must be
explicitly enabled via the config system.
This patch *only* expands the page table code to accomodate
large physical addresses on 32-bit systems and enables the
PHYS_64BIT config option for 86xx. It does *not*
allow you to boot a board with more than about 3.5GB of
RAM - for that, SWIOTLB support is also required (and
coming soon).
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
Updated commit commentary to indicate 86xx, not 6xx.
Incorporated comments from the peanut gallery - restricted the Kconfig
option to PPC_86xx for now, as it breaks old 603x parts with DTLB/ITLB
software miss handling. Also changed hash_page and add_hash_page to not
worry about ordering when !SMP.
I have not optimized set_pte_at for !SMP at this point - I think Ben
and I need to mull this over a bit more first, and it will change
the non-large PTE version of the code as well, so we can handle
that in a followon patch.
This patch depends on Kumar's recent series
[PATCH v2 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
as some changes were made to the page table code there that this
patch depends on.
Cheers,
B
arch/powerpc/include/asm/io.h|2 +-
arch/powerpc/include/asm/page_32.h | 10 +++-
arch/powerpc/include/asm/pgtable-ppc32.h | 30 ++-
arch/powerpc/kernel/head_32.S|4 +-
arch/powerpc/kernel/head_fsl_booke.S |2 -
arch/powerpc/mm/hash_low_32.S| 86 --
arch/powerpc/mm/pgtable_32.c |4 +-
arch/powerpc/platforms/Kconfig.cputype | 17 ---
8 files changed, 123 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 77c7fa0..08266d2 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -711,7 +711,7 @@ static inline void * phys_to_virt(unsigned long address)
/*
* Change struct page to physical address.
*/
-#define page_to_phys(page) (page_to_pfn(page) PAGE_SHIFT)
+#define page_to_phys(page) ((phys_addr_t)page_to_pfn(page) PAGE_SHIFT)
/* We do NOT want virtual merging, it would put too much pressure on
* our iommu allocator. Instead, we want drivers to be smart enough
diff --git a/arch/powerpc/include/asm/page_32.h
b/arch/powerpc/include/asm/page_32.h
index ebfae53..0b253f6 100644
--- a/arch/powerpc/include/asm/page_32.h
+++ b/arch/powerpc/include/asm/page_32.h
@@ -13,10 +13,18 @@
#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#endif
+#ifdef CONFIG_PTE_64BIT
+#define PTE_FLAGS_OFFSET 4 /* offset of PTE flags, in bytes */
+#define LNX_PTE_SIZE 8 /* size of a linux PTE, in bytes */
+#else
+#define PTE_FLAGS_OFFSET 0
+#define LNX_PTE_SIZE 4
+#endif
+
#ifndef __ASSEMBLY__
/*
* The basic type of a PTE - 64 bits for those CPUs with 32 bit
- * physical addressing. For now this just the IBM PPC440.
+ * physical addressing.
*/
#ifdef CONFIG_PTE_64BIT
typedef unsigned long long pte_basic_t;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 82bf914..77e6d99 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -369,7 +369,12 @@ extern int icache_44x_need_flush;
#define _PAGE_RW 0x400 /* software: user write access allowed */
#define _PAGE_SPECIAL 0x800 /* software: Special page */
+#ifdef CONFIG_PTE_64BIT
+/* We never clear the high word of the pte */
+#define _PTE_NONE_MASK (0xULL | _PAGE_HASHPTE)
+#else
#define _PTE_NONE_MASK _PAGE_HASHPTE
+#endif
#define _PMD_PRESENT 0
#define _PMD_PRESENT_MASK (PAGE_MASK)
@@ -528,7 +533,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { pte_update(ptep, ~0, 0); } while
(0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -664,8 +670,30 @@ static inline void set_pte_at(struct mm_struct *mm,
unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
+#ifndef CONFIG_PTE_64BIT
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
#else
+ /*
+* We have to do the write of the 64b pte as 2 stores. This
+* code assumes that the entry we're storing to is currently
+* not valid and that all callers have the page table lock.
+* Having the entry be not valid protects readers who might read
+* between the first and
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Friday 29 August 2008, Alan Stern wrote:
I thought you _were_ arguing against that. Unless I misunderstood,
your original complaint was that since each peripheral controller
driver defines usb_gadget_{un}register_driver, there can be only one
controller driver loaded at a time.
That's probably where the misunderstanding came from: I did not expect
more than one driver to actually be useful on a given system, but that
should IMHO not prevent you from loading the drivers using modprobe, or
building them all into the kernel.
Arnd
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][USB] powerpc: Workaround for the PPC440EPX USBH_23 errata
Hi, please see my comment below. It might be helpful for some of you. On Thursday 28 August 2008 23:11:51 Steven A. Falco wrote: Alan Stern wrote: Your original post mentioned that the 440EPx has only one USB 2.0 host port. Then how can you use a keyboard and memory stick at the same time? You'd have to plug them into a hub -- in which case only one controller would be needed, the one driving the hub. The patch would be unnecessary. I have one of these processors on a Sequoia board. What happens is that if you build the kernel with both EHCI and OHCI support, then plug in a modern USB memory stick, it initially tries EHCI, the driver fails, and the whole thing falls back to OHCI. So you wind up running at 12 Mbps. The only way to make high speed work is to turn off the OHCI driver, and then you cannot support slow devices with that kernel. There is a simple trick to get all types (full, low ang high speed) of devices work: use a USB hub with transaction translators. We are doing so on a custom design based on the 440EPx. So we only build the kernel with EHCI support and there was no need for this ugly hack. So, hile you cannot plug two devices in at one time, you can plug in different speed devices at different times, and my understanding is that this patch will let that work seamlessly. That's true. Matthias ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][USB] powerpc: Workaround for the PPC440EPX USBH_23 errata
В Fri, 29 Aug 2008 11:26:07 -0400 (EDT) Alan Stern [EMAIL PROTECTED] пишет: On Fri, 29 Aug 2008, Benjamin Herrenschmidt wrote: I suppose some embedded platforms don't use CONFIG_PM, is this still a requirement for autosuspend ? Or do that happen always on an empty port nowadays ? ohci-hcd doesn't automatically suspend the root hub if CONFIG_PM isn't set. However it isn't necessary to set CONFIG_SLEEP, CONFIG_HIBERNATION, or CONFIG_USB_SUSPEND. That is good to know. But even assuming PM set, common use-case of embedded systems to have stuff on USB bus that is never plugged off; and in case of compiled-in ehci and ohci there is just Initializing USB Mass Storage driver... usb 1-1: new high speed USB device using ppc-of-ehci and address 2 usb 1-1: device descriptor read/all, error -110 hub 1-0:1.0: unable to enumerate USB device on port 1 (not touching PM here to be clear) even 1-second delay would be enough for root hub to be hosed... So, is the patch (with all the issues addressed) acceptable for mainline? Thanks, -Vitaly ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Efficient memcpy()/memmove() for G2/G3 cores...
On Fri, 2008-08-29 at 13:48 +0200, David Jander wrote: On Wednesday 27 August 2008 23:04:39 Steven Munroe wrote: On Tue, 2008-08-26 at 08:28 +1000, Benjamin Herrenschmidt wrote: On Mon, 2008-08-25 at 15:06 +0200, David Jander wrote: Hi Matt, On Monday 25 August 2008 13:00:10 Matt Sealey wrote: The focus has definitely been on VMX but that's not to say lower power processors were forgotten :) [SNIP] It would be useful of somebody interested in getting things things into glibc did the necessary FSF copyright assignment stuff and worked toward integrating them. Ben makes a very good point! Sounds reasonable... but I am still wondering about what you mean with things? AFAICS there is almost nothing there (besides the memcpy() routine from Gunnar von Boehn, which is apparently still far from optimal). And I was asking for someone to correct me here ;-) There is also a framework for adding and maintaining optimizations of this type: http://penguinppc.org/dev/glibc/glibc-powerpc-cpu-addon.html I had already stumbled across this one, but it seems to focus on G3 or newer processors (power4). There is no optimal memcpy() for G2/PPC603/e300. Well folks volunteer to work on code for the hardware they have, use, and care about. I don't have any of that hardware... this framework can be used to add optimizations for any valid gcc -mcpu=cpu-type target. [...] So it does no good to complain here. If you have core you want to contribute, Get your FSF CR assignment and join #glibc on freenode IRC. I am not complaining. I was only wondering if it is just me or there really is very little that has been done (for either uClibc, glibc, or whatever for powerpc) to improve performance of (linux-) applications on lower-power platforms (G2 core), AFAICS there is a LOT that can be gained by simple tweaks. This is a self help group (free as in freedom) We help each other. And you can help yourself. There is no free lunch. And we will help you. [SNIP] The problem is: I have very little experience with powerpc assembly and only very limited time to dedicate to this and I am looking for others who have Well this will be a good learning experience for you. We will try to answer questions. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] usb: add Freescale QE/CPM USB peripheral controller driver
On Fri, 29 Aug 2008, Arnd Bergmann wrote:
On Friday 29 August 2008, Alan Stern wrote:
I thought you _were_ arguing against that. Unless I misunderstood,
your original complaint was that since each peripheral controller
driver defines usb_gadget_{un}register_driver, there can be only one
controller driver loaded at a time.
That's probably where the misunderstanding came from: I did not expect
more than one driver to actually be useful on a given system, but that
should IMHO not prevent you from loading the drivers using modprobe, or
building them all into the kernel.
All right, then we're in agreement. :-)
Alan Stern
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][USB] powerpc: Workaround for the PPC440EPX USBH_23 errata
On Fri, 29 Aug 2008, Vitaly Bordug wrote: But even assuming PM set, common use-case of embedded systems to have stuff on USB bus that is never plugged off; and in case of compiled-in ehci and ohci there is just Initializing USB Mass Storage driver... usb 1-1: new high speed USB device using ppc-of-ehci and address 2 usb 1-1: device descriptor read/all, error -110 hub 1-0:1.0: unable to enumerate USB device on port 1 (not touching PM here to be clear) even 1-second delay would be enough for root hub to be hosed... So, is the patch (with all the issues addressed) acceptable for mainline? Try doing this instead. First, make sure CONFIG_PM is set! :-) Then replace your patch with something that adds a 2-second delay to the end of ehci_start() when running on a 440EPx system. That should give the OHCI controller time to suspend before the EHCI root hub is registered. A little more tweaking will be needed to handle system sleeps. But this should be a good start. What to do when CONFIG_PM is off is a separate matter. Let's not worry about it for now -- especially since, as Matthias suggested, you can use a USB 2.0 hub. Alan Stern ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v3] powerpc: Only make kernel text pages of linear mapping executable
Commit bc033b63bbfeb6c4b4eb0a1d083c650e4a0d2af8 (powerpc/mm: Fix
attribute confusion with htab_bolt_mapping()) moved the check for
whether we should make pages of the linear mapping executable from
htab_bolt_mapping into its callers, including htab_initialize.
A side-effect of this is that the decision is now made once for
each contiguous section in the LMB array rather than for each page
individually. This can often mean that the whole of the linear
mapping ends up being executable.
This reverts to the previous behaviour, where individual pages are
checked for being part of the kernel text or not, by moving the check
back down into htab_bolt_mapping.
Signed-off-by: Paul Mackerras [EMAIL PROTECTED]
---
Previous version used overlaps_kernel_text(), which doesn't exist
until my PIE patches go in.
diff a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -191,12 +191,17 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long
vend,
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, ssize);
unsigned long va = hpt_va(vaddr, vsid, ssize);
+ unsigned long tprot = prot;
+
+ /* Make kernel text executable */
+ if (in_kernel_text(vaddr))
+ tprot = ~HPTE_R_N;
hash = hpt_hash(va, shift, ssize);
hpteg = ((hash htab_hash_mask) * HPTES_PER_GROUP);
BUG_ON(!ppc_md.hpte_insert);
- ret = ppc_md.hpte_insert(hpteg, va, paddr, prot,
+ ret = ppc_md.hpte_insert(hpteg, va, paddr, tprot,
HPTE_V_BOLTED, psize, ssize);
if (ret 0)
@@ -584,7 +589,7 @@ void __init htab_initialize(void)
{
unsigned long table;
unsigned long pteg_count;
- unsigned long prot, tprot;
+ unsigned long prot;
unsigned long base = 0, size = 0, limit;
int i;
@@ -660,10 +665,9 @@ void __init htab_initialize(void)
for (i=0; i lmb.memory.cnt; i++) {
base = (unsigned long)__va(lmb.memory.region[i].base);
size = lmb.memory.region[i].size;
- tprot = prot | (in_kernel_text(base) ? _PAGE_EXEC : 0);
DBG(creating mapping for region: %lx..%lx (prot: %x)\n,
- base, size, tprot);
+ base, size, prot);
#ifdef CONFIG_U3_DART
/* Do not map the DART space. Fortunately, it will be aligned
@@ -680,21 +684,21 @@ void __init htab_initialize(void)
unsigned long dart_table_end = dart_tablebase + 16 * MB;
if (base != dart_tablebase)
BUG_ON(htab_bolt_mapping(base, dart_tablebase,
- __pa(base), tprot,
+ __pa(base), prot,
mmu_linear_psize,
mmu_kernel_ssize));
if ((base + size) dart_table_end)
BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
base + size,
__pa(dart_table_end),
-tprot,
+prot,
mmu_linear_psize,
mmu_kernel_ssize));
continue;
}
#endif /* CONFIG_U3_DART */
BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
- tprot, mmu_linear_psize, mmu_kernel_ssize));
+ prot, mmu_linear_psize, mmu_kernel_ssize));
}
/*
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 5/5] powerpc: Run relocatable kernel where it's loaded
This demonstrates that the relocatable kernel doesn't have to run at real address 0. It only copies the interrupt vectors down and leaves the rest of the kernel where it was loaded, and runs it there. Signed-off-by: Paul Mackerras [EMAIL PROTECTED] --- diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index c0bba84..07a6d24 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -1384,6 +1384,7 @@ _STATIC(__after_prom_start) /* process relocations for the final address of the kernel */ lis r25,[EMAIL PROTECTED] /* compute virtual base of kernel */ sldir25,r25,32 + add r25,r25,r26 mr r3,r25 bl .relocate #endif @@ -1398,10 +1399,13 @@ _STATIC(__after_prom_start) li r3,0/* target addr */ mr. r4,r26 /* In some cases the loader may */ beq 9f /* have already put us at zero */ - lis r5,(copy_to_here - _stext)@ha - addir5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ li r6,0x100/* Start offset, the first 0x100 */ /* bytes were copied earlier.*/ +#ifdef CONFIG_RELOCATABLE + li r5,__end_interrupts - _stext/* just copy interrupts */ +#else + lis r5,(copy_to_here - _stext)@ha + addir5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */ bl .copy_and_flush /* copy the first n bytes*/ /* this includes the code being */ @@ -1411,15 +1415,16 @@ _STATIC(__after_prom_start) mtctr r8 bctr +p_end: .llong _end - _stext + 4: /* Now copy the rest of the kernel up to _end */ addis r5,r26,(p_end - _stext)@ha ld r5,(p_end - _stext)@l(r5) /* get _end */ +#endif bl .copy_and_flush /* copy the rest */ 9: b .start_here_multiplatform -p_end: .llong _end - _stext - /* * Copy routine used to copy the kernel to start at physical address 0 * and flush and invalidate the caches as needed. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/5] powerpc: Rearrange head_64.S to move interrupt handler code to the beginning
This rearranges head_64.S so that we have all the first-level exception prologs together starting at 0x100, followed by all the second-level handlers that are invoked from the first-level prologs, followed by other code. This doesn't make any functional change but will make following changes for relocatable kernel support easier. Signed-off-by: Paul Mackerras [EMAIL PROTECTED] --- diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index cc8fb47..27935d1 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -325,16 +325,32 @@ do_stab_bolted_pSeries: mfspr r12,SPRN_SPRG2 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) +#ifdef CONFIG_PPC_PSERIES +/* + * Vectors for the FWNMI option. Share common code. + */ + .globl system_reset_fwnmi + .align 7 +system_reset_fwnmi: + HMT_MEDIUM + mtspr SPRN_SPRG1,r13 /* save r13 */ + EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) + + .globl machine_check_fwnmi + .align 7 +machine_check_fwnmi: + HMT_MEDIUM + mtspr SPRN_SPRG1,r13 /* save r13 */ + EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) + +#endif /* CONFIG_PPC_PSERIES */ + +#ifdef __DISABLED__ /* - * We have some room here we use that to put - * the peries slb miss user trampoline code so it's reasonably - * away from slb_miss_user_common to avoid problems with rfid - * * This is used for when the SLB miss handler has to go virtual, * which doesn't happen for now anymore but will once we re-implement * dynamic VSIDs for shared page tables */ -#ifdef __DISABLED__ slb_miss_user_pseries: std r10,PACA_EXGEN+EX_R10(r13) std r11,PACA_EXGEN+EX_R11(r13) @@ -357,25 +373,14 @@ slb_miss_user_pseries: b . /* prevent spec. execution */ #endif /* __DISABLED__ */ -#ifdef CONFIG_PPC_PSERIES + .align 7 + .globl __end_interrupts +__end_interrupts: + /* - * Vectors for the FWNMI option. Share common code. + * Code from here down to __end_handlers is invoked from the + * exception prologs above. */ - .globl system_reset_fwnmi - .align 7 -system_reset_fwnmi: - HMT_MEDIUM - mtspr SPRN_SPRG1,r13 /* save r13 */ - EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common) - - .globl machine_check_fwnmi - .align 7 -machine_check_fwnmi: - HMT_MEDIUM - mtspr SPRN_SPRG1,r13 /* save r13 */ - EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common) - -#endif /* CONFIG_PPC_PSERIES */ /*** Common interrupt handlers ***/ @@ -457,65 +462,6 @@ bad_stack: b 1b /* - * Return from an exception with minimal checks. - * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. - * If interrupts have been enabled, or anything has been - * done that might have changed the scheduling status of - * any task or sent any task a signal, you should use - * ret_from_except or ret_from_except_lite instead of this. - */ -fast_exc_return_irq: /* restores irq state too */ - ld r3,SOFTE(r1) - TRACE_AND_RESTORE_IRQ(r3); - ld r12,_MSR(r1) - rldicl r4,r12,49,63/* get MSR_EE to LSB */ - stb r4,PACAHARDIRQEN(r13) /* restore paca-hard_enabled */ - b 1f - - .globl fast_exception_return -fast_exception_return: - ld r12,_MSR(r1) -1: ld r11,_NIP(r1) - andi. r3,r12,MSR_RI /* check if RI is set */ - beq-unrecov_fer - -#ifdef CONFIG_VIRT_CPU_ACCOUNTING - andi. r3,r12,MSR_PR - beq 2f - ACCOUNT_CPU_USER_EXIT(r3, r4) -2: -#endif - - ld r3,_CCR(r1) - ld r4,_LINK(r1) - ld r5,_CTR(r1) - ld r6,_XER(r1) - mtcrr3 - mtlrr4 - mtctr r5 - mtxer r6 - REST_GPR(0, r1) - REST_8GPRS(2, r1) - - mfmsr r10 - rldicl r10,r10,48,1/* clear EE */ - rldicr r10,r10,16,61 /* clear RI (LE is 0 already) */ - mtmsrd r10,1 - - mtspr SPRN_SRR1,r12 - mtspr SPRN_SRR0,r11 - REST_4GPRS(10, r1) - ld r1,GPR1(r1) - rfid - b . /* prevent speculative execution */ - -unrecov_fer: - bl .save_nvgprs -1: addir3,r1,STACK_FRAME_OVERHEAD - bl .unrecoverable_exception - b 1b - -/* * Here r13 points to the paca, r9 contains the saved CR, * SRR0 and SRR1 are saved in r11 and r12, * r9 - r13 are saved in paca-exgen. @@ -766,6 +712,85 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) bl .altivec_unavailable_exception b .ret_from_except + .align 7 + .globl vsx_unavailable_common +vsx_unavailable_common: + EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) +#ifdef CONFIG_VSX +BEGIN_FTR_SECTION +
[PATCH 4/5] powerpc: Make the 64-bit kernel as a position-independent executable
This implements CONFIG_RELOCATABLE for 64-bit by making the kernel as
a position-independent executable (PIE) when it is set. This involves
processing the dynamic relocations in the image in the early stages of
booting, even if the kernel is being run at the address it is linked at,
since the linker does not necessarily fill in words in the image for
which there are dynamic relocations. (In fact the linker does fill in
such words for 64-bit executables, though not for 32-bit executables,
so in principle we could avoid calling relocate() entirely when we're
running a 64-bit kernel at the linked address.)
The dynamic relocations are processed by a new function relocate(addr),
where the addr parameter is the virtual address where the image will be
run. In fact we call it twice; once before calling prom_init, and again
when starting the main kernel. This means that reloc_offset() returns
0 in prom_init (since it has been relocated to the address it is running
at), which necessitated a few adjustments.
This also changes __va and __pa to use an equivalent definition that is
simpler. With the relocatable kernel, PAGE_OFFSET and MEMORY_START are
constants (for 64-bit) whereas PHYSICAL_START is a variable (and
KERNELBASE ideally should be too, but isn't yet).
With this, relocatable kernels still copy themselves down to physical
address 0 and run there.
Signed-off-by: Paul Mackerras [EMAIL PROTECTED]
---
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 587da5e..17c988b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -806,6 +806,19 @@ config PIN_TLB
endmenu
if PPC64
+config RELOCATABLE
+ bool Build a relocatable kernel
+ help
+ This builds a kernel image that is capable of running anywhere
+ in the RMA (real memory area) at any 16k-aligned base address.
+ The kernel is linked as a position-independent executable (PIE)
+ and contains dynamic relocations which are processed early
+ in the bootup process.
+
+ One use is for the kexec on panic case where the recovery kernel
+ must live at a different physical address than the primary
+ kernel.
+
config PAGE_OFFSET
hex
default 0xc000
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 9155c93..14c86fe 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -63,7 +63,9 @@ override CC += -m$(CONFIG_WORD_SIZE)
override AR:= GNUTARGET=elf$(CONFIG_WORD_SIZE)-powerpc $(AR)
endif
-LDFLAGS_vmlinux:= -Bstatic
+LDFLAGS_vmlinux-yy := -Bstatic
+LDFLAGS_vmlinux-$(CONFIG_PPC64)$(CONFIG_RELOCATABLE) := -pie
+LDFLAGS_vmlinux:= $(LDFLAGS_vmlinux-yy)
CFLAGS-$(CONFIG_PPC64) := -mminimal-toc -mtraceback=none -mcall-aixdesc
CFLAGS-$(CONFIG_PPC32) := -ffixed-r2 -mmultiple
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 14174aa..9109e1f 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -310,8 +310,11 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits) $(obj)/%.dtb
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $ -o $@
+# The iseries hypervisor won't take an ET_DYN executable, so this
+# changes the type (byte 17) in the file to ET_EXEC (2).
$(obj)/zImage.iseries: vmlinux
$(STRIP) -s -R .comment $ -o $@
+ printf \x02 | dd of=$@ conv=notrunc bs=1 seek=17
$(obj)/uImage: vmlinux $(wrapperbits)
$(call if_changed,wrap,uboot)
diff --git a/arch/powerpc/boot/elf_util.c b/arch/powerpc/boot/elf_util.c
index 7454aa4..1567a0c 100644
--- a/arch/powerpc/boot/elf_util.c
+++ b/arch/powerpc/boot/elf_util.c
@@ -27,7 +27,8 @@ int parse_elf64(void *hdr, struct elf_info *info)
elf64-e_ident[EI_MAG3] == ELFMAG3
elf64-e_ident[EI_CLASS] == ELFCLASS64
elf64-e_ident[EI_DATA] == ELFDATA2MSB
- elf64-e_type== ET_EXEC
+ (elf64-e_type== ET_EXEC ||
+ elf64-e_type== ET_DYN)
elf64-e_machine == EM_PPC64))
return 0;
@@ -58,7 +59,8 @@ int parse_elf32(void *hdr, struct elf_info *info)
elf32-e_ident[EI_MAG3] == ELFMAG3
elf32-e_ident[EI_CLASS] == ELFCLASS32
elf32-e_ident[EI_DATA] == ELFDATA2MSB
- elf32-e_type== ET_EXEC
+ (elf32-e_type== ET_EXEC ||
+ elf32-e_type== ET_DYN)
elf32-e_machine == EM_PPC))
return 0;
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index c2df53c..5a44174 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -437,7 +437,7 @@ typedef struct {
})
#endif /* 1 */
-/* This is only valid for addresses = KERNELBASE */
+/* This is only valid for addresses = PAGE_OFFSET */
[PATCH 2/5] powerpc: Make it possible to move the interrupt handlers away from the kernel
This changes the way that the exception prologs transfer control to the handlers in 64-bit kernels with the aim of making it possible to have the prologs separate from the main body of the kernel. Now, instead of computing the address of the handler by taking the top 32 bits of the paca address (to get the 0xc000 part) and ORing in something in the bottom 16 bits, we get the base address of the kernel by doing a load from the paca and add an offset. This also replaces an mfmsr and an ori to compute the MSR value for the handler with a load from the paca. That makes it unnecessary to have a separate version of EXCEPTION_PROLOG_PSERIES that forces 64-bit mode. We can no longer use a direct branches in the exception prolog code, which means that the SLB miss handlers can't branch directly to .slb_miss_realmode any more. Instead we have to compute the address and do an indirect branch. This is conditional on CONFIG_RELOCATABLE; for non-relocatable kernels we use a direct branch as before. (A later change will allow CONFIG_RELOCATABLE to be set on 64-bit powerpc.) Since the secondary CPUs on pSeries start execution in the first 0x100 bytes of real memory and then have to get to wherever the kernel is, we can't use a direct branch to get there. Instead this changes __secondary_hold_spinloop from a flag to a function pointer. When it is set to a non-NULL value, the secondary CPUs jump to the function pointed to by that value. Finally this eliminates one code difference between 32-bit and 64-bit by making __secondary_hold be the text address of the secondary CPU spinloop rather than a function descriptor for it. Signed-off-by: Paul Mackerras [EMAIL PROTECTED] --- diff --git a/arch/powerpc/include/asm/exception.h b/arch/powerpc/include/asm/exception.h index 329148b..d3d4534 100644 --- a/arch/powerpc/include/asm/exception.h +++ b/arch/powerpc/include/asm/exception.h @@ -53,14 +53,8 @@ * low halfword of the address, but for Kdump we need the whole low * word. */ -#ifdef CONFIG_CRASH_DUMP #define LOAD_HANDLER(reg, label) \ - orisreg,reg,(label)@h; /* virt addr of handler ... */ \ - ori reg,reg,(label)@l; /* .. and the rest */ -#else -#define LOAD_HANDLER(reg, label) \ - ori reg,reg,(label)@l; /* virt addr of handler ... */ -#endif + addireg,reg,(label)-_stext; /* virt addr of handler ... */ #define EXCEPTION_PROLOG_1(area) \ mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ @@ -72,37 +66,12 @@ std r9,area+EX_R13(r13);\ mfcrr9 -/* - * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode. - * The firmware calls the registered system_reset_fwnmi and - * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run - * a 32bit application at the time of the event. - * This firmware bug is present on POWER4 and JS20. - */ -#define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label) \ - EXCEPTION_PROLOG_1(area); \ - clrrdi r12,r13,32; /* get high part of label */ \ - mfmsr r10;\ - /* force 64bit mode */ \ - li r11,5; /* MSR_SF_LG|MSR_ISF_LG */ \ - rldimi r10,r11,61,0; /* insert into top 3 bits */\ - /* done 64bit mode */ \ - mfspr r11,SPRN_SRR0; /* save SRR0 */ \ - LOAD_HANDLER(r12,label) \ - ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ - mtspr SPRN_SRR0,r12; \ - mfspr r12,SPRN_SRR1; /* and SRR1 */ \ - mtspr SPRN_SRR1,r10; \ - rfid; \ - b . /* prevent speculative execution */ - #define EXCEPTION_PROLOG_PSERIES(area, label) \ EXCEPTION_PROLOG_1(area); \ - clrrdi r12,r13,32; /* get high part of label */ \ - mfmsr r10;\ + ld r12,PACAKBASE(r13); /* get high part of label */ \ + ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ mfspr r11,SPRN_SRR0; /* save SRR0 */ \ LOAD_HANDLER(r12,label) \ - ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ mtspr SPRN_SRR0,r12; \ mfspr
[PATCH 3/5] powerpc: Use LOAD_REG_IMMEDIATE only for constants on 64-bit
Using LOAD_REG_IMMEDIATE to get the address of kernel symbols generates 5 instructions where LOAD_REG_ADDR can do it in one, and will generate R_PPC64_ADDR16_* relocations in the output when we get to making the kernel as a position-independent executable, which we'd rather not have to handle. This changes various bits of assembly code to use LOAD_REG_ADDR when we need to get the address of a symbol, or to use suitable position-independent code for cases where we can't access the TOC for various reasons, or if we're not running at the address we were linked at. It also cleans up a few minor things; there's no reason to save and restore SRR0/1 around RTAS calls, __mmu_off can get the return address from LR more conveniently than the caller can supply it in R4 (and we already assume elsewhere that EA == RA if the MMU is on in early boot), and enable_64b_mode was using 5 instructions where 2 would do. Signed-off-by: Paul Mackerras [EMAIL PROTECTED] --- diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 0966899..c4a029c 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h @@ -268,7 +268,7 @@ n: * Loads the value of the constant expression 'expr' into register 'rn' * using immediate instructions only. Use this when it's important not * to reference other data (i.e. on ppc64 when the TOC pointer is not - * valid). + * valid) and when 'expr' is a constant or absolute address. * * LOAD_REG_ADDR(rn, name) * Loads the address of label 'name' into register 'rn'. Use this when diff --git a/arch/powerpc/kernel/cpu_setup_ppc970.S b/arch/powerpc/kernel/cpu_setup_ppc970.S index bf118c3..27f2507 100644 --- a/arch/powerpc/kernel/cpu_setup_ppc970.S +++ b/arch/powerpc/kernel/cpu_setup_ppc970.S @@ -110,7 +110,7 @@ load_hids: isync /* Save away cpu state */ - LOAD_REG_IMMEDIATE(r5,cpu_state_storage) + LOAD_REG_ADDR(r5,cpu_state_storage) /* Save HID0,1,4 and 5 */ mfspr r3,SPRN_HID0 @@ -134,7 +134,7 @@ _GLOBAL(__restore_cpu_ppc970) rldicl. r0,r0,4,63 beqlr - LOAD_REG_IMMEDIATE(r5,cpu_state_storage) + LOAD_REG_ADDR(r5,cpu_state_storage) /* Before accessing memory, we make sure rm_ci is clear */ li r0,0 mfspr r3,SPRN_HID4 diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S index 2d802e9..5a8619f 100644 --- a/arch/powerpc/kernel/entry_64.S +++ b/arch/powerpc/kernel/entry_64.S @@ -685,10 +685,6 @@ _GLOBAL(enter_rtas) std r7,_DAR(r1) mfdsisr r8 std r8,_DSISR(r1) - mfsrr0 r9 - std r9,_SRR0(r1) - mfsrr1 r10 - std r10,_SRR1(r1) /* Temporary workaround to clear CR until RTAS can be modified to * ignore all bits. @@ -749,6 +745,10 @@ _STATIC(rtas_return_loc) mfspr r4,SPRN_SPRG3 /* Get PACA */ clrldi r4,r4,2 /* convert to realmode address */ + bcl 20,31,$+4 +0: mflrr3 + ld r3,(1f-0b)(r3) /* get .rtas_restore_regs */ + mfmsr r6 li r0,MSR_RI andcr6,r6,r0 @@ -756,7 +756,6 @@ _STATIC(rtas_return_loc) mtmsrd r6 ld r1,PACAR1(r4) /* Restore our SP */ - LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs) ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ mtspr SPRN_SRR0,r3 @@ -764,6 +763,8 @@ _STATIC(rtas_return_loc) rfid b . /* prevent speculative execution */ +1: .llong .rtas_restore_regs + _STATIC(rtas_restore_regs) /* relocation is on at this point */ REST_GPR(2, r1) /* Restore the TOC */ @@ -783,10 +784,6 @@ _STATIC(rtas_restore_regs) mtdar r7 ld r8,_DSISR(r1) mtdsisr r8 - ld r9,_SRR0(r1) - mtsrr0 r9 - ld r10,_SRR1(r1) - mtsrr1 r10 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ ld r0,16(r1) /* get return address */ diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index 97bb6e6..df678ee 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -128,11 +128,11 @@ __secondary_hold: /* Tell the master cpu we're here */ /* Relocation is off we are located at an address less */ /* than 0x100, so only need to grab low order offset.*/ - std r24,[EMAIL PROTECTED](0) + std r24,__secondary_hold_acknowledge-_stext(0) sync /* All secondary cpus wait here until told to start. */ -100: ld r4,[EMAIL PROTECTED](0) +100: ld r4,__secondary_hold_spinloop-_stext(0) cmpdi 0,r4,0 beq 100b @@ -1223,11 +1223,14 @@ _GLOBAL(generic_secondary_smp_init) /* turn on 64-bit mode */ bl .enable_64b_mode + /* get the
