IRQ : IRQ_HOST_MAP_LEGACY
Hello I am seeing irq source. What is the use of : IRQ_HOST_MAP_LEGACY http://tomoyo.sourceforge.jp/cgi-bin/lxr/ident?i=IRQ_HOST_MAP_LEGACY ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 2/4] POWERPC: Move iommu dma ops from dma.c to dma-iommu.c
On Sep 8, 2008, at 4:57 PM, Christoph Hellwig wrote:
On Mon, Sep 08, 2008 at 02:09:53PM -0500, Becky Bruce wrote:
+/* We support DMA to/from any memory page via the iommu */
+static int dma_iommu_dma_supported(struct device *dev, u64 mask)
+{
+ struct iommu_table *tbl = dev-archdata.dma_data;
+
+ if (!tbl || tbl-it_offset mask) {
+ printk(KERN_INFO
+ Warning: IOMMU offset too big for device mask\n);
+ if (tbl)
+ printk(KERN_INFO
+ mask: 0x%08lx, table offset: 0x%08lx\n,
+ mask, tbl-it_offset);
+ else
+ printk(KERN_INFO mask: 0x%08lx, table unavailable\n,
+ mask);
+ return 0;
+ } else
+ return 1;
+}
Small nitpick, but wouldn't a
if (tbl tbl-it_offset = mask)
return 1;
the rest
be much easier to read?
Seems cleaner to me. but I want this patch, which is a move of the
iommu code, to be *just* a move. So I'm going to leave this as-is for
now.
Thanks!
-Becky
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[PATCH V2] Pass actual dev ptr to dma_* in ucc and cpm_uart serial
We're currently passing NULL, and really shouldn't be.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
drivers/serial/cpm_uart/cpm_uart_core.c |3 +++
drivers/serial/cpm_uart/cpm_uart_cpm1.c |6 +++---
drivers/serial/cpm_uart/cpm_uart_cpm2.c |6 +++---
drivers/serial/ucc_uart.c |4 ++--
4 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c
b/drivers/serial/cpm_uart/cpm_uart_core.c
index 25efca5..a6c4d74 100644
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/serial/cpm_uart/cpm_uart_core.c
@@ -1333,6 +1333,9 @@ static int __devinit cpm_uart_probe(struct of_device
*ofdev,
if (ret)
return ret;
+ /* initialize the device pointer for the port */
+ pinfo-port.dev = ofdev-dev;
+
return uart_add_one_port(cpm_reg, pinfo-port);
}
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm1.c
b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
index 0f0aff0..1b94c56 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm1.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
@@ -100,7 +100,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned
int is_con)
mem_addr = (u8 *) cpm_dpram_addr(cpm_dpalloc(memsz, 8));
dma_addr = (u32)cpm_dpram_phys(mem_addr);
} else
- mem_addr = dma_alloc_coherent(NULL, memsz, dma_addr,
+ mem_addr = dma_alloc_coherent(pinfo-port.dev, memsz, dma_addr,
GFP_KERNEL);
if (mem_addr == NULL) {
@@ -127,8 +127,8 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned
int is_con)
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
- dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo-rx_nrfifos *
- pinfo-rx_fifosize) +
+ dma_free_coherent(pinfo-port.dev, L1_CACHE_ALIGN(pinfo-rx_nrfifos *
+ pinfo-rx_fifosize) +
L1_CACHE_ALIGN(pinfo-tx_nrfifos *
pinfo-tx_fifosize), pinfo-mem_addr,
pinfo-dma_addr);
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm2.c
b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
index b8db4d3..141c0a3 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm2.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
@@ -136,7 +136,7 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned
int is_con)
dma_addr = virt_to_bus(mem_addr);
}
else
- mem_addr = dma_alloc_coherent(NULL, memsz, dma_addr,
+ mem_addr = dma_alloc_coherent(pinfo-port.dev, memsz, dma_addr,
GFP_KERNEL);
if (mem_addr == NULL) {
@@ -163,8 +163,8 @@ int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned
int is_con)
void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
{
- dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo-rx_nrfifos *
- pinfo-rx_fifosize) +
+ dma_free_coherent(pinfo-port.dev, L1_CACHE_ALIGN(pinfo-rx_nrfifos *
+ pinfo-rx_fifosize) +
L1_CACHE_ALIGN(pinfo-tx_nrfifos *
pinfo-tx_fifosize), (void __force
*)pinfo-mem_addr,
pinfo-dma_addr);
diff --git a/drivers/serial/ucc_uart.c b/drivers/serial/ucc_uart.c
index 5c5d18d..539c933 100644
--- a/drivers/serial/ucc_uart.c
+++ b/drivers/serial/ucc_uart.c
@@ -1009,7 +1009,7 @@ static int qe_uart_request_port(struct uart_port *port)
rx_size = L1_CACHE_ALIGN(qe_port-rx_nrfifos * qe_port-rx_fifosize);
tx_size = L1_CACHE_ALIGN(qe_port-tx_nrfifos * qe_port-tx_fifosize);
- bd_virt = dma_alloc_coherent(NULL, rx_size + tx_size, bd_dma_addr,
+ bd_virt = dma_alloc_coherent(port-dev, rx_size + tx_size, bd_dma_addr,
GFP_KERNEL);
if (!bd_virt) {
dev_err(port-dev, could not allocate buffer descriptors\n);
@@ -1051,7 +1051,7 @@ static void qe_uart_release_port(struct uart_port *port)
container_of(port, struct uart_qe_port, port);
struct ucc_slow_private *uccs = qe_port-us_private;
- dma_free_coherent(NULL, qe_port-bd_size, qe_port-bd_virt,
+ dma_free_coherent(port-dev, qe_port-bd_size, qe_port-bd_virt,
qe_port-bd_dma_addr);
ucc_slow_free(uccs);
--
1.5.5.1
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Re: [PATCH V2] Pass actual dev ptr to dma_* in ucc and cpm_uart serial
On Fri, Sep 12, 2008 at 10:42 AM, Becky Bruce [EMAIL PROTECTED] wrote: Signed-off-by: Becky Bruce [EMAIL PROTECTED] Acked-By: Timur Tabi [EMAIL PROTECTED] The changelog could be a little beefier, though. I'm not a fan of having the changelog be an extension of the patch title. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH V2] Pass actual dev ptr to dma_* in ucc and cpm_uart serial
On Fri, Sep 12, 2008 at 10:51:24AM -0500, Timur Tabi wrote: On Fri, Sep 12, 2008 at 10:42 AM, Becky Bruce [EMAIL PROTECTED] wrote: Signed-off-by: Becky Bruce [EMAIL PROTECTED] Acked-By: Timur Tabi [EMAIL PROTECTED] ACK The changelog could be a little beefier, though. I'm not a fan of having the changelog be an extension of the patch title. Bah, that's how git works. Otherwise, you get a silly duplicated line in git log. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: TDM driver
Surendra, I've worked on TDM drivers on MPC8360 for a custom board. You could send the patches for verification. - Srivatsan 2008/9/11 [EMAIL PROTECTED] Hi, I am working on Custom MPC8360 Target board. I have four devices connected through the TDM interface. Does any one has written TDM driver for this Processor. I have seen some patches for MPC8323. Is this TDM driver is included in any latest versions of kernel. Regards Surendra ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev -- - Srivatsan ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 4/4] Add kernel doc for the completion, fix kernel-doc-nano-HOWTO.txt
On Tue, 26 Aug 2008 10:32:02 +0200 Ingo Molnar wrote: * Kevin Diggs [EMAIL PROTECTED] wrote: This patch adds kernel doc for the completion feature. It is in kernel/sched.c and include/linux/completion.h. An error in the split-man.pl PERL snippet in kernel-doc-nano-HOWTO.txt is also fixed. applied to tip/sched/devel - thanks Kevin! Ack and thanks, but next time, please describe the error that is being fixed. --- ~Randy Linux Plumbers Conference, 17-19 September 2008, Portland, Oregon USA http://linuxplumbersconf.org/ ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH V2 4/4] POWERPC: Merge 32 and 64-bit dma code
We essentially adopt the 64-bit dma code, with some changes to support
32-bit systems, including HIGHMEM. dma functions on 32-bit are now
invoked via accessor functions which call the correct op for a device based
on archdata dma_ops. If there is no archdata dma_ops, this defaults
to dma_direct_ops.
In addition, the dma_map/unmap_page functions are added to dma_ops
because we can't just fall back on map/unmap_single when HIGHMEM is
enabled. In the case of dma_direct_*, we stop using map/unmap_single
and just use the page version - this saves a lot of ugly
ifdeffing. We leave map/unmap_single in the dma_ops definition,
though, because they are needed by the iommu code, which does not
implement map/unmap_page. Ideally, going forward, we will completely
eliminate map/unmap_single and just have map/unmap_page, if it's
workable for 64-bit.
Signed-off-by: Becky Bruce [EMAIL PROTECTED]
---
Added comments to the effect that we would like devices to properly
set up the dev and archdata in the future so we can remove the the
fallback behavior on 32-bit.
arch/powerpc/include/asm/dma-mapping.h | 187 +++-
arch/powerpc/include/asm/machdep.h |5 +-
arch/powerpc/include/asm/pci.h | 14 ++-
arch/powerpc/kernel/Makefile |4 +-
arch/powerpc/kernel/dma.c | 69
arch/powerpc/kernel/pci-common.c | 48
arch/powerpc/kernel/pci_32.c |7 ++
arch/powerpc/kernel/pci_64.c | 46
8 files changed, 175 insertions(+), 205 deletions(-)
diff --git a/arch/powerpc/include/asm/dma-mapping.h
b/arch/powerpc/include/asm/dma-mapping.h
index c7ca45f..fddb229 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -44,8 +44,6 @@ extern void __dma_sync_page(struct page *page, unsigned long
offset,
#endif /* ! CONFIG_NOT_COHERENT_CACHE */
-#ifdef CONFIG_PPC64
-
static inline unsigned long device_to_mask(struct device *dev)
{
if (dev-dma_mask *dev-dma_mask)
@@ -76,8 +74,24 @@ struct dma_mapping_ops {
struct dma_attrs *attrs);
int (*dma_supported)(struct device *dev, u64 mask);
int (*set_dma_mask)(struct device *dev, u64 dma_mask);
+ dma_addr_t (*map_page)(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction,
+ struct dma_attrs *attrs);
+ void(*unmap_page)(struct device *dev,
+ dma_addr_t dma_address, size_t size,
+ enum dma_data_direction direction,
+ struct dma_attrs *attrs);
};
+/*
+ * Available generic sets of operations
+ */
+#ifdef CONFIG_PPC64
+extern struct dma_mapping_ops dma_iommu_ops;
+#endif
+extern struct dma_mapping_ops dma_direct_ops;
+
static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
{
/* We don't handle the NULL dev case for ISA for now. We could
@@ -85,8 +99,19 @@ static inline struct dma_mapping_ops *get_dma_ops(struct
device *dev)
* only ISA DMA device we support is the floppy and we have a hack
* in the floppy driver directly to get a device for us.
*/
- if (unlikely(dev == NULL || dev-archdata.dma_ops == NULL))
+
+ if (unlikely(dev == NULL) || dev-archdata.dma_ops == NULL) {
+#ifdef CONFIG_PPC64
return NULL;
+#else
+ /* Use default on 32-bit if dma_ops is not set up */
+ /* TODO: Long term, we should fix drivers so that dev and
+* archdata dma_ops are set up for all buses.
+*/
+ return dma_direct_ops;
+#endif
+ }
+
return dev-archdata.dma_ops;
}
@@ -123,6 +148,12 @@ static inline int dma_set_mask(struct device *dev, u64
dma_mask)
return 0;
}
+/*
+ * TODO: map_/unmap_single will ideally go away, to be completely
+ * replaced by map/unmap_page. Until then, we allow dma_ops to have
+ * one or the other, or both by checking to see if the specific
+ * function requested exists; and if not, falling back on the other set.
+ */
static inline dma_addr_t dma_map_single_attrs(struct device *dev,
void *cpu_addr,
size_t size,
@@ -132,7 +163,14 @@ static inline dma_addr_t dma_map_single_attrs(struct
device *dev,
struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
BUG_ON(!dma_ops);
- return dma_ops-map_single(dev, cpu_addr, size, direction, attrs);
+
+ if (dma_ops-map_single)
+ return dma_ops-map_single(dev, cpu_addr, size, direction,
+ attrs);
+
+ return dma_ops-map_page(dev, virt_to_page(cpu_addr),
+
Device treee syntax for expanding mpc5200 gpios
I need to implement some more of the mpc5200's gpio capabilities. Right now we have: gpios = gpio_wkup 0 0; first cell is index into the bank, and second is unused. What do we need to fully describe a mpc5200 gpio? 1) open drain: 1 enable 2) interrupt: 0 no int, 1 simple, 2 wakeup, 3 both 3) interrupt type: 0 any transition, 1 rising, 2 falling, 3 pulse A gpio pin would then have four cells? Or should all of this be encoded into a single cell so that the existing two cell syntax can be preserved? -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc: fix interrupt values for DMA2 in MPC8610 HPCD device tree
On Sep 9, 2008, at 2:43 PM, Timur Tabi wrote: For Freescale 8xxx devices that use an MPIC, the interrupt numbers in the device tree must be 16 greater than the values documented in the reference manual. In these chips, the MPIC is wired to use the first 16 numbers for external interrupts, but the documentation numbers internal interrupts from 0. In the MPC8610 HPCD device tree, the interrupt properties for the DMA channels for DMA2 were not the adjusted values. This patch fixes that. Signed-off-by: Timur Tabi [EMAIL PROTECTED] --- I have no idea how this was missed for so long, but this patch is a must-fix for 2.6.27. (changes for v2: improve changelog text) arch/powerpc/boot/dts/mpc8610_hpcd.dts |8 1 files changed, 4 insertions(+), 4 deletions(-) applied. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Please pull from 'for-2.6.27'
Please pull from 'for-2.6.27' branch of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git for-2.6.27 to receive the following updates: arch/powerpc/boot/dts/mpc8610_hpcd.dts |8 +-- arch/powerpc/sysdev/cpm1.c | 74 +++-- 2 files changed, 56 insertions(+), 26 deletions(-) Jochen Friedrich (1): powerpc/cpm1: Fix race condition in CPM1 GPIO library. Timur Tabi (1): powerpc: fix interrupt values for DMA2 in MPC8610 HPCD device tree ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] POWERPC: Make dma_addr_t a u64 if CONFIG_PHYS_64BIT is set
Signed-off-by: Becky Bruce [EMAIL PROTECTED] --- arch/powerpc/include/asm/types.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h index d3374bc..a9a9262 100644 --- a/arch/powerpc/include/asm/types.h +++ b/arch/powerpc/include/asm/types.h @@ -55,7 +55,7 @@ typedef u64 phys_addr_t; typedef u32 phys_addr_t; #endif -#ifdef __powerpc64__ +#if defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT) typedef u64 dma_addr_t; #else typedef u32 dma_addr_t; -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v4 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:
_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)
On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.
The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.
On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/reg_booke.h |7
arch/powerpc/include/asm/tlbflush.h | 13 +---
arch/powerpc/kernel/misc_32.S| 52 ++
arch/powerpc/kernel/ppc_ksyms.c |3 ++
4 files changed, 70 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index be980f4..6745376 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -109,6 +109,7 @@
#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
#define SPRN_L1CSR00x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
@@ -410,6 +411,12 @@
#define L2CSR0_L2LOA 0x0080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO0x0020 /* L2 Cache Lock Overflow */
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI 0x0002 /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI 0x0004 /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI 0x0040 /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI 0x0020 /* TLB3 Flash invalidate */
+
/* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/include/asm/tlbflush.h
b/arch/powerpc/include/asm/tlbflush.h
index 361cd5c..2639559 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -29,6 +29,9 @@
#include linux/mm.h
extern void _tlbie(unsigned long address, unsigned int pid);
+extern void _tlbil_all(void);
+extern void _tlbil_pid(unsigned int pid);
+extern void _tlbil_va(unsigned long address, unsigned int pid);
#if defined(CONFIG_40x) || defined(CONFIG_8xx)
#define _tlbia() asm volatile (tlbia; sync : : : memory)
@@ -38,31 +41,31 @@ extern void _tlbia(void);
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- _tlbia();
+ _tlbil_pid(mm-context.id);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ _tlbil_va(vmaddr, vma ? vma-vm_mm-context.id : 0);
}
static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ flush_tlb_page(vma, vmaddr);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
#elif defined(CONFIG_PPC32)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..430bbce 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -274,6 +274,9 @@ _GLOBAL(real_writeb)
/*
* Flush MMU TLB
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_all)
+#endif
_GLOBAL(_tlbia)
#if defined(CONFIG_40x)
sync/* Flush to memory before changing mapping */
@@ -344,6 +347,9 @@ _GLOBAL(_tlbia)
/*
* Flush MMU TLB for a particular address
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_va)
+#endif
_GLOBAL(_tlbie)
#if defined(CONFIG_40x)
/* We run the search with interrupts disabled because we have to change
@@ -436,6 +442,52 @@ _GLOBAL(_tlbie)
#endif /* ! CONFIG_40x */
blr
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * Flush MMU TLB, but only on the local processor (no broadcast)
+ */
+_GLOBAL(_tlbil_all)
+#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
+MMUCSR0_TLB2FI |
[PATCH v4 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a WARN_ON to set_pte_at to ensure the pte isn't present for
the 64-bit pte/SMP case (to ensure our assumption of this fact).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
split out set_pte_at per Ben's desire to have a WARN_ON...
- k
arch/powerpc/include/asm/highmem.h |2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 25 -
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/highmem.h
b/arch/powerpc/include/asm/highmem.h
index 5d99b64..91c5895 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum
km_type type, pgpro
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(kmap_pte-idx)));
#endif
- set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+ __set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..1b11955 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -652,16 +650,33 @@ static inline unsigned long long pte_update(pte_t *p,
* On machines which use an MMU hash table we avoid changing the
* _PAGE_HASHPTE bit.
*/
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
+#elif defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
#else
*ptep = pte;
#endif
}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ WARN_ON(pte_present(*ptep));
+#endif
+ __set_pte_at(mm, addr, ptep, pte);
+}
+
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
* for our hash-based implementation, we fix that up here.
--
1.5.5.1
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[PATCH v4 4/4] powerpc/mm: Implement _PAGE_SPECIAL pte_special() for 32-bit
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().
We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 15 +--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 1b11955..c2e58b4 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;
#define _PAGE_HWEXEC 0x0004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x0008 /* S: Page referenced */
#define _PAGE_DIRTY0x0010 /* S: Page dirty */
+#define _PAGE_SPECIAL 0x0020 /* S: Special page */
#define _PAGE_USER 0x0040 /* S: User page */
#define _PAGE_ENDIAN 0x0080 /* H: E bit */
#define _PAGE_GUARDED 0x0100 /* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xULL
+#define __HAVE_ARCH_PTE_SPECIAL
#elif defined(CONFIG_FSL_BOOKE)
/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;
#define _PAGE_COHERENT 0x00100 /* H: M bit */
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
#define _PAGE_WRITETHRU0x00400 /* H: W bit */
+#define _PAGE_SPECIAL 0x00800 /* S: Special page */
#ifdef CONFIG_PTE_64BIT
/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+#define __HAVE_ARCH_PTE_SPECIAL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
#define _PAGE_RW 0x400 /* software: user write access allowed */
+#define _PAGE_SPECIAL 0x800 /* software: Special page */
#define _PTE_NONE_MASK _PAGE_HASHPTE
@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;
/* Hash table based platforms need atomic updates of the linux PTE */
#define PTE_ATOMIC_UPDATES 1
+#define __HAVE_ARCH_PTE_SPECIAL
+
#endif
/*
@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU0
#endif
+#ifndef _PAGE_SPECIAL
+#define _PAGE_SPECIAL 0
+#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK _PMD_PRESENT
#endif
@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte) {
return pte_val(pte) _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte)
_PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte)
_PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte_val(pte)
_PAGE_FILE; }
-static inline int pte_special(pte_t pte) { return 0; }
+static inline int pte_special(pte_t pte) { return pte_val(pte)
_PAGE_SPECIAL; }
static inline void pte_uncache(pte_t pte) { pte_val(pte) |=
_PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte) { pte_val(pte) =
~_PAGE_NO_CACHE; }
@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {
static inline pte_t pte_mkyoung(pte_t pte) {
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- return pte; }
+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline unsigned long pte_pgprot(pte_t pte)
{
return __pgprot(pte_val(pte)) PAGE_PROT_BITS;
--
1.5.5.1
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[PATCH v4 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/kernel/head_fsl_booke.S | 26 +- 1 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3cb52fa..377e0c1 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -579,13 +579,19 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ - bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif #endif -/* Jump to common tlb load */ + bne 2f /* Bail if permission/valid mismach */ + + /* Jump to common tlb load */ b finish_tlb_load 2: /* The bailout. Restore registers to pre-exception conditions @@ -640,10 +646,20 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ + +#ifdef CONFIG_PTE_64BIT +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif +#endif + bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) + lwz r13,0(r12) #endif /* Jump to common TLB load point */ @@ -702,7 +718,7 @@ interrupt_base: /* * Both the instruction and data TLB miss get to this * point to load the TLB. - * r10 - EA of fault + * r10 - available to use * r11 - TLB (info from Linux PTE) * r12 - available to use * r13 - upper bits of PTE (if PTE_64BIT) or available to use -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: TDM driver
Hi Srivatsan, I have got these patches in google. i have not yet used these for MPV8360. If you have already workded on TDM drivers for MPC8360. Can you please send me the driver code . Regards Surendra Surendra, I've worked on TDM drivers on MPC8360 for a custom board. You could send the patches for verification. - Srivatsan 2008/9/11 [EMAIL PROTECTED] Hi, I am working on Custom MPC8360 Target board. I have four devices connected through the TDM interface. Does any one has written TDM driver for this Processor. I have seen some patches for MPC8323. Is this TDM driver is included in any latest versions of kernel. Regards Surendra ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev -- - Srivatsan ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
