[PATCH 2/3] kvmppc: add hypercall infrastructure - guest part v3
From: Christian Ehrhardt [EMAIL PROTECTED]
This adds the guest portion of the hypercall infrastructure.
Version 3 now follows the beat ABI, but proposes a new implementation style as
static inline asm functions instead of pure assembler code. That should allow
the compiler to be more flexible and therefore a better optimization.
If people agree on that new implementation style we might merge this code.
The current implementation of beat style hypercalls can be found in
arch/powerpc/platforms/cell/beat_hvCall.S
Signed-off-by: Christian Ehrhardt [EMAIL PROTECTED]
---
[diffstat]
epapr_hcalls.h | 59 +
1 file changed, 59 insertions(+)
[diff]
diff --git a/include/asm-powerpc/epapr_hcalls.h
b/include/asm-powerpc/epapr_hcalls.h
new file mode 100644
--- /dev/null
+++ b/include/asm-powerpc/epapr_hcalls.h
@@ -0,0 +1,59 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * Authors:
+ * Christian Ehrhardt [EMAIL PROTECTED]
+ */
+
+#ifndef __POWERPC_EPAPR_HCALLS_H__
+#define __POWERPC_EPAPR_HCALLS_H__
+
+#ifdef __KERNEL__
+
+/* Hypercalls use the beat ABI */
+#define KVM_HYPERCALL_BIN 0x4422
+
+static inline long epapr_hypercall_1in_1out(unsigned int nr, unsigned long p1)
+{
+ register unsigned long hcall asm (r11) = nr;
+ register unsigned long arg1_ret asm (r3) = p1;
+
+ asm volatile(.long %1
+ : +r(arg1_ret)
+ : i(KVM_HYPERCALL_BIN), r(hcall)
+ : r4, r5, r6, r7, r8,
+ r9, r10, r12, cc);
+ return arg1_ret;
+}
+
+static inline long epapr_hypercall_2in_1out(unsigned int nr,
+ unsigned long p1, unsigned long p2)
+{
+ register unsigned long hcall asm (r11) = nr;
+ register unsigned long arg1_ret asm (r3) = p1;
+ register unsigned long arg2 asm (r4) = p2;
+
+ asm volatile(.long %1
+ : +r(arg1_ret)
+ : i(KVM_HYPERCALL_BIN), r(hcall), r(arg2)
+ : r5, r6, r7, r8,
+ r9, r10, r12, cc);
+ return arg1_ret;
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* __POWERPC_EPAPR_HCALLS_H__ */
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[PATCH 0/3][RFC] kvmppc: paravirtualization interface - guest part v3
From: Christian Ehrhardt [EMAIL PROTECTED] Version 3 updates: - guest hypercall infrastructure is now generic (in epapr_hcalls.h) while the kvm specific functions stay in kvm_para.h - the hypercalls now use beat style ABI - dropped the guest coop patch changing wrteei to wrtee (now mfmsr is rewritten avoiding side effects and a lot of corner cases. Additionally this does not need any guest cooperation to be effective) This patch series implements a paravirtualization interface using: - the device tree mechanism to pass hypervisor informations to the guest - hypercalls for guest-host calls - an example exploiter of that interface (magic page) The device tree format used here (=base for the discussions on embedded-hypervisor) is the following. - A node hypervisor to show the general availability of some hypervisor data - flags for features like the example feature,pv-magicpage setting 1 = available, everything else = unavailable - Some features might need to pass more data and can use an entry in the device tree like the example of data,pv-magicpage-size The host side of these patches can be found on [EMAIL PROTECTED] I hope that eventually this guest patch series (that is modifying the ppc boot process and adding e.g. new ppc fixmaps could go upstream (when discussed and agreed somewhen) via linuxppc-dev, while the kvm host part will go via kvm (Avi Kivity). [patches in series] [PATCH 1/3] kvmppc: read device tree hypervisor node infrastructure [PATCH 2/3] kvmppc: add hypercall infrastructure - guest part [PATCH 3/3] kvmppc: magic page paravirtualization - guest part --- [diffstat] arch/powerpc/kernel/kvm.c| 53 +++ b/arch/powerpc/kernel/Makefile |2 + b/arch/powerpc/kernel/kvm.c | 30 + b/arch/powerpc/kernel/setup_32.c |3 + b/arch/powerpc/platforms/44x/Kconfig |7 b/include/asm-powerpc/epapr_hcalls.h | 59 +++ b/include/asm-powerpc/fixmap.h | 10 + b/include/asm-powerpc/kvm_para.h | 43 +++-- include/asm-powerpc/kvm_para.h | 26 +++ 9 files changed, 229 insertions(+), 4 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/3] kvmppc: read device tree hypervisor node infrastructure
From: Christian Ehrhardt [EMAIL PROTECTED]
This patch adds the guest portion of the device tree based host-guest
communication. Using the device tree infrastructure this patch implements
kvm_para_available and kvm_arch_para_features (in this patch just the
infrastructure, no specific feature registered).
Signed-off-by: Christian Ehrhardt [EMAIL PROTECTED]
---
[diffstat]
arch/powerpc/kernel/Makefile |2 +
arch/powerpc/kernel/kvm.c | 30 +
arch/powerpc/kernel/setup_32.c |3 ++
arch/powerpc/platforms/44x/Kconfig |7 ++
include/asm-powerpc/kvm_para.h | 43 ++---
5 files changed, 82 insertions(+), 3 deletions(-)
[diff]
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -80,6 +80,8 @@
obj-$(CONFIG_8XX_MINIMAL_FPEMU) += softemu8xx.o
+obj-$(CONFIG_KVM_GUEST)+= kvm.o
+
ifneq ($(CONFIG_PPC_INDIRECT_IO),y)
obj-y += iomap.o
endif
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
new file mode 100644
--- /dev/null
+++ b/arch/powerpc/kernel/kvm.c
@@ -0,0 +1,30 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ * Copyright IBM Corp. 2008
+ *
+ * Authors:
+ * Hollis Blanchard [EMAIL PROTECTED]
+ * Christian Ehrhardt [EMAIL PROTECTED]
+ */
+
+#include linux/percpu.h
+#include linux/mm.h
+#include linux/kvm_para.h
+
+void __init kvm_guest_init(void)
+{
+ if (!kvm_para_available())
+ return;
+}
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -17,6 +17,7 @@
#include linux/cpu.h
#include linux/console.h
#include linux/lmb.h
+#include linux/kvm_para.h
#include asm/io.h
#include asm/prom.h
@@ -319,5 +320,7 @@
ppc_md.setup_arch();
if ( ppc_md.progress ) ppc_md.progress(arch: exit, 0x3eab);
+ kvm_guest_init();
+
paging_init();
}
diff --git a/arch/powerpc/platforms/44x/Kconfig
b/arch/powerpc/platforms/44x/Kconfig
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -152,3 +152,10 @@
# 44x errata/workaround config symbols, selected by the CPU models above
config IBM440EP_ERR42
bool
+
+config KVM_GUEST
+ bool KVM Guest support
+ depends on EXPERIMENTAL
+ help
+ This option enables various optimizations for running under the KVM
+ hypervisor.
diff --git a/include/asm-powerpc/kvm_para.h b/include/asm-powerpc/kvm_para.h
--- a/include/asm-powerpc/kvm_para.h
+++ b/include/asm-powerpc/kvm_para.h
@@ -14,7 +14,9 @@
*
* Copyright IBM Corp. 2008
*
- * Authors: Hollis Blanchard [EMAIL PROTECTED]
+ * Authors:
+ * Hollis Blanchard [EMAIL PROTECTED]
+ * Christian Ehrhardt [EMAIL PROTECTED]
*/
#ifndef __POWERPC_KVM_PARA_H__
@@ -22,15 +24,50 @@
#ifdef __KERNEL__
+#include linux/of.h
+
+static struct kvmppc_para_features {
+ char *dtcell;
+ int feature;
+} para_features[] = {
+};
+
static inline int kvm_para_available(void)
{
- return 0;
+ struct device_node *dn;
+ int ret;
+
+ dn = of_find_node_by_path(/hypervisor);
+ ret = !!dn;
+
+ of_node_put(dn);
+
+ return ret;
}
static inline unsigned int kvm_arch_para_features(void)
{
- return 0;
+ struct device_node *dn;
+ const int *dtval;
+ unsigned int features = 0;
+ int i;
+
+ dn = of_find_node_by_path(/hypervisor);
+ if (!dn)
+ return 0;
+
+ for (i = 0; i ARRAY_SIZE(para_features); i++) {
+ dtval = of_get_property(dn, para_features[i].dtcell, NULL);
+ if (dtval *dtval == 1)
+ features |= (1 para_features[i].feature);
+ }
+
+ of_node_put(dn);
+
+ return features;
}
+
+void kvm_guest_init(void);
#endif /* __KERNEL__ */
___
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Re: [PATCH 2/2] ehea: fix mutex and spinlock use
On Mon, 15 Sep 2008 17:18:27 +0200 Thomas Klein [EMAIL PROTECTED] wrote:
NACK!
I regret but this patch is wrong. It is not sufficient to only lock
the replacement of an old list with a new list. Building up those
lists is a 3-step process:
1. Count the number of entries a list will contain and allocate mem
2. Fill the list
3. Replace old list with updated list
It's obvious that the contents of the list may not change during this
procedure. That means that not only the list build-up procedure must
be locked. It must be assured that no function that modifies the list's
content can be called while another list update is in progress.
Jeff, please revert this patch.
OK, your call, you know the code better than I do.
But the locking could at least be pushed into ehea_update_firmware_handles()
and ehea_update_bcmc_registrations() instead of being at each call site.
Thanks,
Sebastien.
Thanks
Thomas
Sebastien Dugue wrote:
Looks like to me that the ehea_fw_handles.lock mutex and the
ehea_bcmc_regs.lock spinlock are taken much longer than necessary and could
as well be pushed inside the functions that need them
(ehea_update_firmware_handles() and ehea_update_bcmc_registrations())
rather than at each callsite.
Signed-off-by: Sebastien Dugue [EMAIL PROTECTED]
---
drivers/net/ehea/ehea_main.c | 26 --
1 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index b70c531..c765ec6 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -219,9 +219,11 @@ static void ehea_update_firmware_handles(void)
}
out_update:
+ mutex_lock(ehea_fw_handles.lock);
kfree(ehea_fw_handles.arr);
ehea_fw_handles.arr = arr;
ehea_fw_handles.num_entries = i;
+ mutex_unlock(ehea_fw_handles.lock);
}
static void ehea_update_bcmc_registrations(void)
@@ -293,9 +295,11 @@ static void ehea_update_bcmc_registrations(void)
}
out_update:
+ spin_lock(ehea_bcmc_regs.lock);
kfree(ehea_bcmc_regs.arr);
ehea_bcmc_regs.arr = arr;
ehea_bcmc_regs.num_entries = i;
+ spin_unlock(ehea_bcmc_regs.lock);
}
static struct net_device_stats *ehea_get_stats(struct net_device *dev)
@@ -1770,8 +1774,6 @@ static int ehea_set_mac_addr(struct net_device *dev,
void *sa)
memcpy(dev-dev_addr, mac_addr-sa_data, dev-addr_len);
- spin_lock(ehea_bcmc_regs.lock);
-
/* Deregister old MAC in pHYP */
if (port-state == EHEA_PORT_UP) {
ret = ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -1792,7 +1794,6 @@ static int ehea_set_mac_addr(struct net_device *dev,
void *sa)
out_upregs:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
out_free:
kfree(cb0);
out:
@@ -1954,8 +1955,6 @@ static void ehea_set_multicast_list(struct net_device
*dev)
}
ehea_promiscuous(dev, 0);
- spin_lock(ehea_bcmc_regs.lock);
-
if (dev-flags IFF_ALLMULTI) {
ehea_allmulti(dev, 1);
goto out;
@@ -1985,7 +1984,6 @@ static void ehea_set_multicast_list(struct net_device
*dev)
}
out:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
return;
}
@@ -2466,8 +2464,6 @@ static int ehea_up(struct net_device *dev)
if (port-state == EHEA_PORT_UP)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
ret = ehea_port_res_setup(port, port-num_def_qps,
port-num_add_tx_qps);
if (ret) {
@@ -2504,8 +2500,6 @@ static int ehea_up(struct net_device *dev)
}
}
- spin_lock(ehea_bcmc_regs.lock);
-
ret = ehea_broadcast_reg_helper(port, H_REG_BCMC);
if (ret) {
ret = -EIO;
@@ -2527,10 +2521,8 @@ out:
ehea_info(Failed starting %s. ret=%i, dev-name, ret);
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
ehea_update_firmware_handles();
- mutex_unlock(ehea_fw_handles.lock);
return ret;
}
@@ -2580,9 +2572,6 @@ static int ehea_down(struct net_device *dev)
if (port-state == EHEA_PORT_DOWN)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
- spin_lock(ehea_bcmc_regs.lock);
ehea_drop_multicast_list(dev);
ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -2591,7 +2580,6 @@ static int ehea_down(struct net_device *dev)
port-state = EHEA_PORT_DOWN;
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
ret = ehea_clean_all_portres(port);
if (ret)
@@ -2599,7 +2587,6 @@ static int ehea_down(struct net_device *dev)
dev-name, ret);
ehea_update_firmware_handles();
- mutex_unlock(ehea_fw_handles.lock);
dts file for ep8548A board
Hi all, I am working on ep8548A embedded planet board. I am using mpc8548cds dtb file (mpc8548cds.dts file in arch/powerpc/boot/dts directory of the kernel source) as my device tree file. I am tracing the kernel initilization path through BDI. The BDI tracing is hanging in early_init_devtree ( in machine_init function) if the r3 register (physical pointer to device tree block) is not set to dtb file loaded location in RAM. Once I set the r3 register manually in BDI (rm r3 dtb file location) the kernel is passing machine_init function (passing early_init_devtree( ) ). I tried to statically set r3 register in head_fsl_booke.S file by using ori instruction but I was not able to set the r3 value to dtb file RAM location. Are any changes necessary in mps8548cds.dts for ep8548A board? How do we and where should we set the r3 register value in head_fsl_booke.S file for device tree initilization? Thanks, Poornima ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 2/2] ehea: fix mutex and spinlock use
Sebastien Dugue wrote:
On Mon, 15 Sep 2008 17:18:27 +0200 Thomas Klein [EMAIL PROTECTED] wrote:
NACK!
I regret but this patch is wrong. It is not sufficient to only lock
the replacement of an old list with a new list. Building up those
lists is a 3-step process:
1. Count the number of entries a list will contain and allocate mem
2. Fill the list
3. Replace old list with updated list
It's obvious that the contents of the list may not change during this
procedure. That means that not only the list build-up procedure must
be locked. It must be assured that no function that modifies the list's
content can be called while another list update is in progress.
Jeff, please revert this patch.
OK, your call, you know the code better than I do.
But the locking could at least be pushed into ehea_update_firmware_handles()
and ehea_update_bcmc_registrations() instead of being at each call site.
Thanks,
Sebastien.
It unfortunately can't. As I already mentioned it must be assured that no
function that modifies the list's content can be called while another list
update is in progress. This means that for example ehea_broadcast_reg_helper()
may not run during a list update. That's why the locks surround these function
calls as well.
Thomas
Thanks
Thomas
Sebastien Dugue wrote:
Looks like to me that the ehea_fw_handles.lock mutex and the
ehea_bcmc_regs.lock spinlock are taken much longer than necessary and could
as well be pushed inside the functions that need them
(ehea_update_firmware_handles() and ehea_update_bcmc_registrations())
rather than at each callsite.
Signed-off-by: Sebastien Dugue [EMAIL PROTECTED]
---
drivers/net/ehea/ehea_main.c | 26 --
1 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index b70c531..c765ec6 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -219,9 +219,11 @@ static void ehea_update_firmware_handles(void)
}
out_update:
+ mutex_lock(ehea_fw_handles.lock);
kfree(ehea_fw_handles.arr);
ehea_fw_handles.arr = arr;
ehea_fw_handles.num_entries = i;
+ mutex_unlock(ehea_fw_handles.lock);
}
static void ehea_update_bcmc_registrations(void)
@@ -293,9 +295,11 @@ static void ehea_update_bcmc_registrations(void)
}
out_update:
+ spin_lock(ehea_bcmc_regs.lock);
kfree(ehea_bcmc_regs.arr);
ehea_bcmc_regs.arr = arr;
ehea_bcmc_regs.num_entries = i;
+ spin_unlock(ehea_bcmc_regs.lock);
}
static struct net_device_stats *ehea_get_stats(struct net_device *dev)
@@ -1770,8 +1774,6 @@ static int ehea_set_mac_addr(struct net_device *dev, void
*sa)
memcpy(dev-dev_addr, mac_addr-sa_data, dev-addr_len);
- spin_lock(ehea_bcmc_regs.lock);
-
/* Deregister old MAC in pHYP */
if (port-state == EHEA_PORT_UP) {
ret = ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -1792,7 +1794,6 @@ static int ehea_set_mac_addr(struct net_device *dev, void
*sa)
out_upregs:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
out_free:
kfree(cb0);
out:
@@ -1954,8 +1955,6 @@ static void ehea_set_multicast_list(struct net_device
*dev)
}
ehea_promiscuous(dev, 0);
- spin_lock(ehea_bcmc_regs.lock);
-
if (dev-flags IFF_ALLMULTI) {
ehea_allmulti(dev, 1);
goto out;
@@ -1985,7 +1984,6 @@ static void ehea_set_multicast_list(struct net_device
*dev)
}
out:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
return;
}
@@ -2466,8 +2464,6 @@ static int ehea_up(struct net_device *dev)
if (port-state == EHEA_PORT_UP)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
ret = ehea_port_res_setup(port, port-num_def_qps,
port-num_add_tx_qps);
if (ret) {
@@ -2504,8 +2500,6 @@ static int ehea_up(struct net_device *dev)
}
}
- spin_lock(ehea_bcmc_regs.lock);
-
ret = ehea_broadcast_reg_helper(port, H_REG_BCMC);
if (ret) {
ret = -EIO;
@@ -2527,10 +2521,8 @@ out:
ehea_info(Failed starting %s. ret=%i, dev-name, ret);
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
ehea_update_firmware_handles();
- mutex_unlock(ehea_fw_handles.lock);
return ret;
}
@@ -2580,9 +2572,6 @@ static int ehea_down(struct net_device *dev)
if (port-state == EHEA_PORT_DOWN)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
- spin_lock(ehea_bcmc_regs.lock);
ehea_drop_multicast_list(dev);
ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -2591,7 +2580,6 @@ static int ehea_down(struct net_device *dev)
port-state = EHEA_PORT_DOWN;
ehea_update_bcmc_registrations();
-
[PATCH] powerpc: Kill outdated Documentation/powerpc/smp.txt
From: Geert Uytterhoeven [EMAIL PROTECTED] Documentation/powerpc/smp.txt is so outdated that it makes sense to just remove it. Signed-off-by: Geert Uytterhoeven [EMAIL PROTECTED] --- Documentation/powerpc/00-INDEX |2 -- Documentation/powerpc/smp.txt | 34 -- 2 files changed, 36 deletions(-) --- a/Documentation/powerpc/00-INDEX +++ b/Documentation/powerpc/00-INDEX @@ -18,8 +18,6 @@ mpc52xx.txt - Linux 2.6.x on MPC52xx family mpc52xx-device-tree-bindings.txt - MPC5200 Device Tree Bindings -smp.txt - - use and state info about Linux/PPC on MP machines sound.txt - info on sound support under Linux/PPC zImage_layout.txt --- a/Documentation/powerpc/smp.txt +++ /dev/null @@ -1,34 +0,0 @@ - Information about Linux/PPC SMP mode -= - -This document and the related code was written by me -(Cort Dougan, [EMAIL PROTECTED]) please email me if you have questions, -comments or corrections. - -Last Change: 3.31.99 - -If you want to help by writing code or testing different hardware please -email me! - -1. State of Supported Hardware - - PowerSurge Architecture - tested on UMAX s900, Apple 9600 -The second processor on this machine boots up just fine and -enters its idle loop. Hopefully a completely working SMP kernel -on this machine will be done shortly. - -The code makes the assumption of only two processors. The changes -necessary to work with any number would not be overly difficult but -I don't have any machines with 2 processors so it's not high on my -list of priorities. If anyone else would like do to the work email -me and I can point out the places that need changed. If you have 2 -processors and don't want to add support yourself let me know and I -can take a look into it. - - BeBox -BeBox support hasn't been added to the 2.1.X kernels from 2.0.X -but work is being done and SMP support for BeBox is in the works. - - CHRP -CHRP SMP works and is fairly solid. It's been tested on the IBM F50 -with 4 processors for quite some time now. With kind regards, Geert Uytterhoeven Software Architect Sony Techsoft Centre Europe The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium Phone:+32 (0)2 700 8453 Fax: +32 (0)2 700 8622 E-mail: [EMAIL PROTECTED] Internet: http://www.sony-europe.com/ A division of Sony Europe (Belgium) N.V. VAT BE 0413.825.160 · RPR Brussels Fortis · BIC GEBABEBB · IBAN BE41293037680010___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] powerpc: Kill /proc/ppc_htab remainings
commit 14cf11af6cf608eb8c23e989ddb17a715ddce109 (powerpc: Merge enough to start building in arch/powerpc.) unwired /proc/ppc_htab, and commit 917f0af9e5a9ceecf9e72537fabb501254ba321d (powerpc: Remove arch/ppc and include/asm-ppc) removed the rest of the /proc/ppc_htab support, but there are still a few references left. Kill them for good. Signed-off-by: Geert Uytterhoeven [EMAIL PROTECTED] --- Documentation/powerpc/00-INDEX |2 Documentation/powerpc/ppc_htab.txt | 118 - include/linux/proc_fs.h|1 3 files changed, 121 deletions(-) --- a/Documentation/powerpc/00-INDEX +++ b/Documentation/powerpc/00-INDEX @@ -18,8 +18,6 @@ mpc52xx.txt - Linux 2.6.x on MPC52xx family mpc52xx-device-tree-bindings.txt - MPC5200 Device Tree Bindings -ppc_htab.txt - - info about the Linux/PPC /proc/ppc_htab entry smp.txt - use and state info about Linux/PPC on MP machines sound.txt --- a/Documentation/powerpc/ppc_htab.txt +++ /dev/null @@ -1,118 +0,0 @@ - Information about /proc/ppc_htab -= - -This document and the related code was written by me (Cort Dougan), please -email me ([EMAIL PROTECTED]) if you have questions, comments or corrections. - -Last Change: 2.16.98 - -This entry in the proc directory is readable by all users but only -writable by root. - -The ppc_htab interface is a user level way of accessing the -performance monitoring registers as well as providing information -about the PTE hash table. - -1. Reading - - Reading this file will give you information about the memory management - hash table that serves as an extended tlb for page translation on the - powerpc. It will also give you information about performance measurement - specific to the cpu that you are using. - - Explanation of the 604 Performance Monitoring Fields: -MMCR0 - the current value of the MMCR0 register -PMC1 -PMC2 - the value of the performance counters and a - description of what events they are counting - which are based on MMCR0 bit settings. - Explanation of the PTE Hash Table fields: - -Size - hash table size in Kb. -Buckets - number of buckets in the table. -Address - the virtual kernel address of the hash table base. -Entries - the number of ptes that can be stored in the hash table. -User/Kernel - how many pte's are in use by the kernel or user at that time. -Overflows - How many of the entries are in their secondary hash location. -Percent full - ratio of free pte entries to in use entries. -Reloads - Count of how many hash table misses have occurred - that were fixed with a reload from the linux tables. - Should always be 0 on 603 based machines. -Non-error Misses - Count of how many hash table misses have occurred - that were completed with the creation of a pte in the linux - tables with a call to do_page_fault(). -Error Misses - Number of misses due to errors such as bad address - and permission violations. This includes kernel access of - bad user addresses that are fixed up by the trap handler. - - Note that calculation of the data displayed from /proc/ppc_htab takes - a long time and spends a great deal of time in the kernel. It would - be quite hard on performance to read this file constantly. In time - there may be a counter in the kernel that allows successive reads from - this file only after a given amount of time has passed to reduce the - possibility of a user slowing the system by reading this file. - -2. Writing - - Writing to the ppc_htab allows you to change the characteristics of - the powerpc PTE hash table and setup performance monitoring. - - Resizing the PTE hash table is not enabled right now due to many - complications with moving the hash table, rehashing the entries - and many many SMP issues that would have to be dealt with. - - Write options to ppc_htab: - - - To set the size of the hash table to 64Kb: - - echo 'size 64' /proc/ppc_htab - - The size must be a multiple of 64 and must be greater than or equal to - 64. - - - To turn off performance monitoring: - - echo 'off' /proc/ppc_htab - - - To reset the counters without changing what they're counting: - - echo 'reset' /proc/ppc_htab - - Note that counting will continue after the reset if it is enabled. - - - To count only events in user mode or only in kernel mode: - - echo 'user' /proc/ppc_htab - ...or... - echo 'kernel' /proc/ppc_htab - - Note that these two options are exclusive of one another and the - lack of either of these options counts user and kernel. - Using 'reset' and 'off' reset these flags. - - - The 604 has 2 performance counters which can each count events from - a specific set of events. These sets are disjoint so
Re: dts file for ep8548A board
Don't know if this helps but .. The EP boards I've used have an old version of u-boot which don't support passing the device tree address so I've had to build a cuImage. Cheers. poornima r wrote: Hi all, I am working on ep8548A embedded planet board. I am using mpc8548cds dtb file (mpc8548cds.dts file in arch/powerpc/boot/dts directory of the kernel source) as my device tree file. I am tracing the kernel initilization path through BDI. The BDI tracing is hanging in early_init_devtree ( in machine_init function) if the r3 register (physical pointer to device tree block) is not set to dtb file loaded location in RAM. Once I set the r3 register manually in BDI (rm r3 dtb file location) the kernel is passing machine_init function (passing early_init_devtree( ) ). I tried to statically set r3 register in head_fsl_booke.S file by using ori instruction but I was not able to set the r3 value to dtb file RAM location. Are any changes necessary in mps8548cds.dts for ep8548A board? How do we and where should we set the r3 register value in head_fsl_booke.S file for device tree initilization? Thanks, Poornima ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev -- John Traill Systems Engineer Network and Computing Systems Group Freescale Semiconductor UK LTD Colvilles Road East Kilbride Glasgow G75 0TG, Scotland Tel: +44 (0) 1355 355494 Fax: +44 (0) 1355 261790 E-mail: [EMAIL PROTECTED] Registration Number: SC262720 VAT Number: GB831329053 [ ] General Business Use [ ] Freescale Internal Use Only [ ] Freescale Confidential Proprietary ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v5 0/2] powerpc: Board support for GE Fanuc SBC610
The following series implements basic board support for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. This series provides basic functionality: - The board can boot with a serial console. - Ethernet works, though the phys are polled. - The PCI bus is scanned and sata functions. Signed-off-by: Martyn Welch [EMAIL PROTECTED] --- arch/powerpc/boot/dts/gef_sbc610.dts | 260 ++ arch/powerpc/platforms/86xx/Kconfig |9 + arch/powerpc/platforms/86xx/Makefile |1 arch/powerpc/platforms/86xx/gef_sbc610.c | 149 + 4 files changed, 418 insertions(+), 1 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v5 2/2] powerpc: Default configuration for GE Fanuc SBC610
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch [EMAIL PROTECTED] --- arch/powerpc/configs/86xx/gef_sbc610_defconfig | 1654 1 files changed, 1654 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig new file mode 100644 index 000..f589489 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig @@ -0,0 +1,1654 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.26-rc5 +# Wed Jun 11 12:06:53 2008 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +CONFIG_PPC_MERGE=y +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_DMA_ATTRS is not set +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +CONFIG_CLASSIC_RCU=y + +# +# Platform support +# +# CONFIG_PPC_MULTIPLATFORM is not set +# CONFIG_PPC_82xx is not set +# CONFIG_PPC_83xx is not set +CONFIG_PPC_86xx=y +# CONFIG_PPC_MPC512x is not set +# CONFIG_PPC_MPC5121 is not set +# CONFIG_PPC_CELL is not set +# CONFIG_PPC_CELL_NATIVE is not set +# CONFIG_PQ2ADS is not set +# CONFIG_MPC8641_HPCN is not set +# CONFIG_SBC8641D is not set +# CONFIG_MPC8610_HPCD is not set +CONFIG_GEF_SBC610=y +CONFIG_MPC8641=y +# CONFIG_IPIC is not set +CONFIG_MPIC=y +# CONFIG_MPIC_WEIRD is not set +# CONFIG_PPC_I8259 is not set +# CONFIG_PPC_RTAS is not set +# CONFIG_MMIO_NVRAM is not set +# CONFIG_PPC_MPC106 is not set +#
[PATCH v5 1/2] powerpc: Board support for GE Fanuc SBC610
Support for the SBC610 VPX Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's SBC610, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/gef_sbc610.dts | 260 ++
arch/powerpc/platforms/86xx/Kconfig |9 +
arch/powerpc/platforms/86xx/Makefile |1
arch/powerpc/platforms/86xx/gef_sbc610.c | 149 +
4 files changed, 418 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts
b/arch/powerpc/boot/dts/gef_sbc610.dts
new file mode 100644
index 000..b80c581
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -0,0 +1,260 @@
+/*
+ * GE Fanuc SBC610 Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_SBC610;
+ compatible = gef,sbc610;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,[EMAIL PROTECTED] {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ #interrupt-cells = 2;
+ device_type = soc;
+ compatible = simple-bus;
+ ranges = 0x0 0xfef0 0x0010;
+ reg = 0xfef0 0x10;// CCSRBAR 1M
+ bus-frequency = 0;
+
+ i2c1: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl-i2c;
+ reg = 0x3000 0x100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+
+ [EMAIL PROTECTED] {
+ compatible = dallas,ds1682;
+ reg = 0x6b;
+ };
+ };
+
+ i2c2: [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl-i2c;
+ reg = 0x3100 0x100;
+ interrupts = 0x2b 0x2;
+ interrupt-parent = mpic;
+ dfsrr;
+ };
+
+ [EMAIL PROTECTED] {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-dma, fsl,eloplus-dma;
+ reg = 0x21300 0x4;
+ ranges = 0x0 0x21100 0x200;
+ cell-index = 0;
+ [EMAIL PROTECTED] {
+ compatible = fsl,mpc8641-dma-channel,
+ fsl,eloplus-dma-channel;
+
Re: [PATCH 2/2] ehea: fix mutex and spinlock use
On Tue, 16 Sep 2008 11:13:13 +0200 Thomas Klein [EMAIL PROTECTED] wrote:
Sebastien Dugue wrote:
On Mon, 15 Sep 2008 17:18:27 +0200 Thomas Klein [EMAIL PROTECTED] wrote:
NACK!
I regret but this patch is wrong. It is not sufficient to only lock
the replacement of an old list with a new list. Building up those
lists is a 3-step process:
1. Count the number of entries a list will contain and allocate mem
2. Fill the list
3. Replace old list with updated list
It's obvious that the contents of the list may not change during this
procedure. That means that not only the list build-up procedure must
be locked. It must be assured that no function that modifies the list's
content can be called while another list update is in progress.
Jeff, please revert this patch.
OK, your call, you know the code better than I do.
But the locking could at least be pushed into
ehea_update_firmware_handles()
and ehea_update_bcmc_registrations() instead of being at each call site.
Thanks,
Sebastien.
It unfortunately can't. As I already mentioned it must be assured that no
function that modifies the list's content can be called while another list
update is in progress. This means that for example
ehea_broadcast_reg_helper()
may not run during a list update. That's why the locks surround these function
calls as well.
OK, I see.
Thanks,
Sebastien.
Thomas
Thanks
Thomas
Sebastien Dugue wrote:
Looks like to me that the ehea_fw_handles.lock mutex and the
ehea_bcmc_regs.lock spinlock are taken much longer than necessary and
could
as well be pushed inside the functions that need them
(ehea_update_firmware_handles() and ehea_update_bcmc_registrations())
rather than at each callsite.
Signed-off-by: Sebastien Dugue [EMAIL PROTECTED]
---
drivers/net/ehea/ehea_main.c | 26 --
1 files changed, 4 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index b70c531..c765ec6 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -219,9 +219,11 @@ static void ehea_update_firmware_handles(void)
}
out_update:
+ mutex_lock(ehea_fw_handles.lock);
kfree(ehea_fw_handles.arr);
ehea_fw_handles.arr = arr;
ehea_fw_handles.num_entries = i;
+ mutex_unlock(ehea_fw_handles.lock);
}
static void ehea_update_bcmc_registrations(void)
@@ -293,9 +295,11 @@ static void ehea_update_bcmc_registrations(void)
}
out_update:
+ spin_lock(ehea_bcmc_regs.lock);
kfree(ehea_bcmc_regs.arr);
ehea_bcmc_regs.arr = arr;
ehea_bcmc_regs.num_entries = i;
+ spin_unlock(ehea_bcmc_regs.lock);
}
static struct net_device_stats *ehea_get_stats(struct net_device *dev)
@@ -1770,8 +1774,6 @@ static int ehea_set_mac_addr(struct net_device
*dev, void *sa)
memcpy(dev-dev_addr, mac_addr-sa_data, dev-addr_len);
- spin_lock(ehea_bcmc_regs.lock);
-
/* Deregister old MAC in pHYP */
if (port-state == EHEA_PORT_UP) {
ret = ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -1792,7 +1794,6 @@ static int ehea_set_mac_addr(struct net_device
*dev, void *sa)
out_upregs:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
out_free:
kfree(cb0);
out:
@@ -1954,8 +1955,6 @@ static void ehea_set_multicast_list(struct
net_device *dev)
}
ehea_promiscuous(dev, 0);
- spin_lock(ehea_bcmc_regs.lock);
-
if (dev-flags IFF_ALLMULTI) {
ehea_allmulti(dev, 1);
goto out;
@@ -1985,7 +1984,6 @@ static void ehea_set_multicast_list(struct
net_device *dev)
}
out:
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
return;
}
@@ -2466,8 +2464,6 @@ static int ehea_up(struct net_device *dev)
if (port-state == EHEA_PORT_UP)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
ret = ehea_port_res_setup(port, port-num_def_qps,
port-num_add_tx_qps);
if (ret) {
@@ -2504,8 +2500,6 @@ static int ehea_up(struct net_device *dev)
}
}
- spin_lock(ehea_bcmc_regs.lock);
-
ret = ehea_broadcast_reg_helper(port, H_REG_BCMC);
if (ret) {
ret = -EIO;
@@ -2527,10 +2521,8 @@ out:
ehea_info(Failed starting %s. ret=%i, dev-name, ret);
ehea_update_bcmc_registrations();
- spin_unlock(ehea_bcmc_regs.lock);
ehea_update_firmware_handles();
- mutex_unlock(ehea_fw_handles.lock);
return ret;
}
@@ -2580,9 +2572,6 @@ static int ehea_down(struct net_device *dev)
if (port-state == EHEA_PORT_DOWN)
return 0;
- mutex_lock(ehea_fw_handles.lock);
-
- spin_lock(ehea_bcmc_regs.lock);
ehea_drop_multicast_list(dev);
ehea_broadcast_reg_helper(port, H_DEREG_BCMC);
@@ -2591,7 +2580,6 @@ static int
Re: [PATCH HACK] powerpc: quick hack to get a functional eHEA with hardirq preemption
On Mon, Sep 15, 2008 at 03:13:32PM +0200, Sebastien Dugue wrote: [...] we are a bit worried about putting this into the mainstream part of non real time linux. Heck, I sure do not want this to be applied mainstream nor into any tree. The sole purpose of this patch was to trigger some reaction from the people who know the hardware and try to understand where the problem lies. There interrupts work perfectly fine, and it was a bit of a challenge to get there for all cases / configurations / machines. Agreed, but the fact that it fails with hardirq preemption leads me to believe (without any more knowledge about the harware) that there might be something amiss with this driver (or the code concerning the XICS) nevertheless. Could you try to enable these changes only for RT-Linux via a real-time kconfig switch? Nope, this is just a quick hack that allows me to have a functional eHEA under the rt kernel. I want to understand what the problem is: - Is the eHEA really delivering level interrupts to the XICS? - Is the XICS loosing interrupts when they are masked? There is a known bug in the -rt kernels, the bug causes handlers to lose edge interrupts. See this patch: http://lkml.org/lkml/2008/6/30/372 - ...? -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
Hi Jon,
On Sun, Sep 14, 2008 at 11:06:23PM -0400, Jon Smirl wrote:
I have demultiplexing the GPIO interrupts working well enough to make
my hardware work. But now I've discovered that these interrupts can't
do what I need.
Anton, Grant - are either of you interested in this code? It's not
finished but the main ideas are in place.
I think there is a small issue that ruins the whole approach.. :-/
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,17 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: [PATCH HACK] powerpc: quick hack to get a functional eHEA with hardirq preemption
Hi Anton, On Tue, 16 Sep 2008 15:59:47 +0400 Anton Vorontsov [EMAIL PROTECTED] wrote: On Mon, Sep 15, 2008 at 03:13:32PM +0200, Sebastien Dugue wrote: [...] we are a bit worried about putting this into the mainstream part of non real time linux. Heck, I sure do not want this to be applied mainstream nor into any tree. The sole purpose of this patch was to trigger some reaction from the people who know the hardware and try to understand where the problem lies. There interrupts work perfectly fine, and it was a bit of a challenge to get there for all cases / configurations / machines. Agreed, but the fact that it fails with hardirq preemption leads me to believe (without any more knowledge about the harware) that there might be something amiss with this driver (or the code concerning the XICS) nevertheless. Could you try to enable these changes only for RT-Linux via a real-time kconfig switch? Nope, this is just a quick hack that allows me to have a functional eHEA under the rt kernel. I want to understand what the problem is: - Is the eHEA really delivering level interrupts to the XICS? - Is the XICS loosing interrupts when they are masked? There is a known bug in the -rt kernels, the bug causes handlers to lose edge interrupts. See this patch: http://lkml.org/lkml/2008/6/30/372 Yes, I've been following that thread back then and my hack is based on your patch. So yes, it seems to be the same problem and it lies in the way -rt handles the fasteoi flow. But looking at the comments from the XICS code, it seems that its wired for level only interrupts. Therefore without any more specs, it's still not clear to me that there's not a bug with the way the xics handles eHEA interrupts. Are the eHEA interrupts really level interrupts? If so why do they get lost when masked? I just found that not masking that particular interrupt in the fasteoi path makes the thing work! Thanks, Sebastien. - ...? -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 -- To unsubscribe from this list: send the line unsubscribe linux-rt-users in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 8:17 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
Hi Jon,
On Sun, Sep 14, 2008 at 11:06:23PM -0400, Jon Smirl wrote:
I have demultiplexing the GPIO interrupts working well enough to make
my hardware work. But now I've discovered that these interrupts can't
do what I need.
Anton, Grant - are either of you interested in this code? It's not
finished but the main ideas are in place.
I think there is a small issue that ruins the whole approach.. :-/
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,17 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
--
Jon Smirl
[EMAIL PROTECTED]
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 08:37:55AM -0400, Jon Smirl wrote:
On Tue, Sep 16, 2008 at 8:17 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
Hi Jon,
On Sun, Sep 14, 2008 at 11:06:23PM -0400, Jon Smirl wrote:
I have demultiplexing the GPIO interrupts working well enough to make
my hardware work. But now I've discovered that these interrupts can't
do what I need.
Anton, Grant - are either of you interested in this code? It's not
finished but the main ideas are in place.
I think there is a small issue that ruins the whole approach.. :-/
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,17 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
Well, I didn't say that it will not work, what I'm trying to say
is that I don't quite like the idea of 1:1 mapping for all gpio
chips.
It is error prone, i.e. gpio_to_irq() can't fail, so you can't
tell if gpio to irq translation really happened or not. Plus
we might decide to not do 1:1 mapping for other gpio chips.
I think that this translation should go via gpiolib's callback
(there is no .to_irq callback, but we should implement one).
In the callback you can still do 1:1 mapping, but this mapping
will work only for this particular gpio chip, and not for others.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 9:12 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
On Tue, Sep 16, 2008 at 08:37:55AM -0400, Jon Smirl wrote:
On Tue, Sep 16, 2008 at 8:17 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
Hi Jon,
On Sun, Sep 14, 2008 at 11:06:23PM -0400, Jon Smirl wrote:
I have demultiplexing the GPIO interrupts working well enough to make
my hardware work. But now I've discovered that these interrupts can't
do what I need.
Anton, Grant - are either of you interested in this code? It's not
finished but the main ideas are in place.
I think there is a small issue that ruins the whole approach.. :-/
--- a/arch/powerpc/include/asm/gpio.h
+++ b/arch/powerpc/include/asm/gpio.h
@@ -38,17 +38,14 @@ static inline int gpio_cansleep(unsigned int gpio)
return __gpio_cansleep(gpio);
}
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
Well, I didn't say that it will not work, what I'm trying to say
is that I don't quite like the idea of 1:1 mapping for all gpio
chips.
It is error prone, i.e. gpio_to_irq() can't fail, so you can't
tell if gpio to irq translation really happened or not. Plus
we might decide to not do 1:1 mapping for other gpio chips.
From reading the ARM code my understanding is that gpio_to_irq() and
irq_to_gpio() are meant to be fast paths without error checking. In
the gpiolib doc it says these functions should only take a couple of
instructions.
You'll detect errors if you take an invalid IRQ from the function and
feed it into any of the rest of the IRQ API.
The idea for setting the GPIO number equal to the VIRQ number came out
of the ARM code. Making GPIO==VIRQ greatly simplified the code.
I think that this translation should go via gpiolib's callback
(there is no .to_irq callback, but we should implement one).
In the callback you can still do 1:1 mapping, but this mapping
will work only for this particular gpio chip, and not for others.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
--
Jon Smirl
[EMAIL PROTECTED]
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 09:36:22AM -0400, Jon Smirl wrote:
[...]
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
Well, I didn't say that it will not work, what I'm trying to say
is that I don't quite like the idea of 1:1 mapping for all gpio
chips.
It is error prone, i.e. gpio_to_irq() can't fail, so you can't
tell if gpio to irq translation really happened or not. Plus
we might decide to not do 1:1 mapping for other gpio chips.
From reading the ARM code my understanding is that gpio_to_irq() and
irq_to_gpio() are meant to be fast paths without error checking.
Nope. gpio_to_irq and irq_to_gpio don't have to be fast.
In
the gpiolib doc it says these functions should only take a couple of
instructions.
This is for gpio_get/set_value and gpio_set_direction*.
You'll detect errors if you take an invalid IRQ from the function and
feed it into any of the rest of the IRQ API.
Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still
valid virq b/c it is mapped for another IRQ controller (particularly
lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt,
the PIC and IRQ8 is widely used on PowerPC).
So gpio_to_irq will succeed, and request_irq will succeed too. Though
this would be not correct.
The idea for setting the GPIO number equal to the VIRQ number came out
of the ARM code. Making GPIO==VIRQ greatly simplified the code.
Adding .to_irq callback won't complicate code either, but will let
you do the things right.
As for the ARM code... ARM has been using GPIO API long before
GPIOLIB, and back then you didn't have many options.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
On Tue, Sep 16, 2008 at 09:36:22AM -0400, Jon Smirl wrote:
[...]
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
Well, I didn't say that it will not work, what I'm trying to say
is that I don't quite like the idea of 1:1 mapping for all gpio
chips.
It is error prone, i.e. gpio_to_irq() can't fail, so you can't
tell if gpio to irq translation really happened or not. Plus
we might decide to not do 1:1 mapping for other gpio chips.
From reading the ARM code my understanding is that gpio_to_irq() and
irq_to_gpio() are meant to be fast paths without error checking.
Nope. gpio_to_irq and irq_to_gpio don't have to be fast.
In
the gpiolib doc it says these functions should only take a couple of
instructions.
This is for gpio_get/set_value and gpio_set_direction*.
You'll detect errors if you take an invalid IRQ from the function and
feed it into any of the rest of the IRQ API.
Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still
valid virq b/c it is mapped for another IRQ controller (particularly
lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt,
the PIC and IRQ8 is widely used on PowerPC).
Set the base in the GPIO struct such that this won't happen. You can
set the base greater than MAX_IRQ.
Just because a CPU has a GPIO 8 in the manual does not mean that is
has to be assigned GPIO 8 in the kernel. The GPIO numbers in the
kernel are just handles, they can be any number. VIRQs don't use the
physical IRQ number.
In the code I posted all of the internal GPIO numbers were in the
150-180 range.
Assign GPIO numbers above the maximum VIRQ on the CPU...
#define IRQ_GPIO(x) (MPC52xx_IRQ_HIGHTESTHWIRQ + x)
#define IRQ_GPIO_WKUP(x) (IRQ_GPIO(32) + x)
Use the base of the GPIO struct to translate to the internal pin number.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
static int mpc52xx_wkup_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
struct mpc52xx_gpio_wkup __iomem *regs = mm_gc-regs;
unsigned int ret;
Adjust for the offset .,..
ret = (in_8(regs-wkup_ival) (7 - gpio - gc.base)) 1;
pr_debug(%s: gpio: %d ret: %d\n, __func__, gpio, ret);
return ret;
}
So gpio_to_irq will succeed, and request_irq will succeed too. Though
this would be not correct.
The idea for setting the GPIO number equal to the VIRQ number came out
of the ARM code. Making GPIO==VIRQ greatly simplified the code.
Adding .to_irq callback won't complicate code either, but will let
you do the things right.
As for the ARM code... ARM has been using GPIO API long before
GPIOLIB, and back then you didn't have many options.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
--
Jon Smirl
[EMAIL PROTECTED]
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov
[EMAIL PROTECTED] wrote:
On Tue, Sep 16, 2008 at 09:36:22AM -0400, Jon Smirl wrote:
[...]
-/*
- * Not implemented, yet.
- */
-static inline int gpio_to_irq(unsigned int gpio)
+static inline unsigned int gpio_to_irq(unsigned int gpio)
{
- return -ENOSYS;
+ return gpio;
GPIO 0 is valid gpio, but IRQ 0 isn't valid virq. So you
can't do 1:1 mapping. :-(
I changed the GPIO numbers inside of Linux to match the virqs.
ofchip-gc.base = IRQ_GPIO_WKUP(0);
Well, I didn't say that it will not work, what I'm trying to say
is that I don't quite like the idea of 1:1 mapping for all gpio
chips.
It is error prone, i.e. gpio_to_irq() can't fail, so you can't
tell if gpio to irq translation really happened or not. Plus
we might decide to not do 1:1 mapping for other gpio chips.
From reading the ARM code my understanding is that gpio_to_irq() and
irq_to_gpio() are meant to be fast paths without error checking.
Nope. gpio_to_irq and irq_to_gpio don't have to be fast.
You need to do gpio_to_irq in the interrupt handler doing the
demuxing. I hadn't written that piece yet.
In
the gpiolib doc it says these functions should only take a couple of
instructions.
This is for gpio_get/set_value and gpio_set_direction*.
You'll detect errors if you take an invalid IRQ from the function and
feed it into any of the rest of the IRQ API.
Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still
valid virq b/c it is mapped for another IRQ controller (particularly
lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt,
the PIC and IRQ8 is widely used on PowerPC).
So gpio_to_irq will succeed, and request_irq will succeed too. Though
this would be not correct.
The idea for setting the GPIO number equal to the VIRQ number came out
of the ARM code. Making GPIO==VIRQ greatly simplified the code.
Adding .to_irq callback won't complicate code either, but will let
you do the things right.
As for the ARM code... ARM has been using GPIO API long before
GPIOLIB, and back then you didn't have many options.
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
--
Jon Smirl
[EMAIL PROTECTED]
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Re: Please pull from 'for-2.6.27'
On Sep 12, 2008, at 3:47 PM, Kumar Gala wrote: Please pull from 'for-2.6.27' branch of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git for-2.6.27 to receive the following updates: arch/powerpc/boot/dts/mpc8610_hpcd.dts |8 +-- arch/powerpc/sysdev/cpm1.c | 74 ++ +-- 2 files changed, 56 insertions(+), 26 deletions(-) Jochen Friedrich (1): powerpc/cpm1: Fix race condition in CPM1 GPIO library. Timur Tabi (1): powerpc: fix interrupt values for DMA2 in MPC8610 HPCD device tree Paul, I know you are hiding out at ks, but what's going on with this fix? :) - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v5 0/2] powerpc: Board support for GE Fanuc SBC610
On Tue, 16 Sep 2008 09:54:59 -0500 Kumar Gala [EMAIL PROTECTED] wrote: On Sep 16, 2008, at 4:57 AM, Martyn Welch wrote: The following series implements basic board support for GE Fanuc's SBC610, a 6U single board computer, based on Freescale's MPC8641D. This series provides basic functionality: - The board can boot with a serial console. - Ethernet works, though the phys are polled. - The PCI bus is scanned and sata functions. Signed-off-by: Martyn Welch [EMAIL PROTECTED] what changed in v5? The patches as sent earlier today were the same as those sent on the 4th, as part of Paul's request for those wishing their patches to be included on the new patchwork page. The changes were: I have removed un-needed entries from of_bus_ids[] and added simple-bus compatible node to soc in the DTS. Sorry if you didn't get CCed on the previous release. I use STGit to push the patches and it seems to arbitrarily loose some CCed parties if multiple --CC options are given. It's seems happier with all CCs in a list. Martyn -- Martyn Welch MEng MPhil MIET (Principal Software Engineer) T:+44(0)1327322748 GE Fanuc Intelligent Platforms Ltd, |Registered in England and Wales Tove Valley Business Park, Towcester, |(3828642) at 100 Barbirolli Square, Northants, NN12 6PF, UK T:+44(0)1327359444 |Manchester,M2 3AB VAT:GB 729849476 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] sbc8560: fix compile warning on CPM pin array
On Sep 3, 2008, at 3:02 PM, Paul Gortmaker wrote: This is just a parallel of a5dc66e2ab2e2cf641346b056a69a67cfcf9458c applied to the sbc8560 board. Signed-off-by: Paul Gortmaker [EMAIL PROTECTED] --- arch/powerpc/platforms/85xx/sbc8560.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) applied to powerpc-next. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v5 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:
_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)
On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.
The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.
On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Changed flush_tlb_range to use pid form of invalidate and added a comment about
the fact that _tlbil_pid for fsl-booke is really an invalidate all.
- k
arch/powerpc/include/asm/reg_booke.h |7
arch/powerpc/include/asm/tlbflush.h | 13 +---
arch/powerpc/kernel/misc_32.S| 53 ++
arch/powerpc/kernel/ppc_ksyms.c |3 ++
4 files changed, 71 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index be980f4..6745376 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -109,6 +109,7 @@
#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
#define SPRN_L1CSR00x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
@@ -410,6 +411,12 @@
#define L2CSR0_L2LOA 0x0080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO0x0020 /* L2 Cache Lock Overflow */
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI 0x0002 /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI 0x0004 /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI 0x0040 /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI 0x0020 /* TLB3 Flash invalidate */
+
/* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/include/asm/tlbflush.h
b/arch/powerpc/include/asm/tlbflush.h
index 361cd5c..9f0f710 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -29,6 +29,9 @@
#include linux/mm.h
extern void _tlbie(unsigned long address, unsigned int pid);
+extern void _tlbil_all(void);
+extern void _tlbil_pid(unsigned int pid);
+extern void _tlbil_va(unsigned long address, unsigned int pid);
#if defined(CONFIG_40x) || defined(CONFIG_8xx)
#define _tlbia() asm volatile (tlbia; sync : : : memory)
@@ -38,31 +41,31 @@ extern void _tlbia(void);
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- _tlbia();
+ _tlbil_pid(mm-context.id);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ _tlbil_va(vmaddr, vma ? vma-vm_mm-context.id : 0);
}
static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ flush_tlb_page(vma, vmaddr);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- _tlbia();
+ _tlbil_pid(vma-vm_mm-context.id);
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
#elif defined(CONFIG_PPC32)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..98f9a2d 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -274,6 +274,9 @@ _GLOBAL(real_writeb)
/*
* Flush MMU TLB
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_all)
+#endif
_GLOBAL(_tlbia)
#if defined(CONFIG_40x)
sync/* Flush to memory before changing mapping */
@@ -344,6 +347,9 @@ _GLOBAL(_tlbia)
/*
* Flush MMU TLB for a particular address
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_va)
+#endif
_GLOBAL(_tlbie)
#if defined(CONFIG_40x)
/* We run the search with interrupts disabled because we have to change
@@ -436,6 +442,53 @@ _GLOBAL(_tlbie)
#endif /* ! CONFIG_40x */
blr
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * Flush MMU TLB, but only on the
[PATCH v5 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/kernel/head_fsl_booke.S | 26 +- 1 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3cb52fa..377e0c1 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -579,13 +579,19 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ - bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif #endif -/* Jump to common tlb load */ + bne 2f /* Bail if permission/valid mismach */ + + /* Jump to common tlb load */ b finish_tlb_load 2: /* The bailout. Restore registers to pre-exception conditions @@ -640,10 +646,20 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ + +#ifdef CONFIG_PTE_64BIT +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif +#endif + bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) + lwz r13,0(r12) #endif /* Jump to common TLB load point */ @@ -702,7 +718,7 @@ interrupt_base: /* * Both the instruction and data TLB miss get to this * point to load the TLB. - * r10 - EA of fault + * r10 - available to use * r11 - TLB (info from Linux PTE) * r12 - available to use * r13 - upper bits of PTE (if PTE_64BIT) or available to use -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v5 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a WARN_ON to set_pte_at to ensure the pte isn't present for
the 64-bit pte/SMP case (to ensure our assumption of this fact).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/highmem.h |2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 25 -
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/highmem.h
b/arch/powerpc/include/asm/highmem.h
index 5d99b64..91c5895 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum
km_type type, pgpro
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(kmap_pte-idx)));
#endif
- set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+ __set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..1b11955 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -652,16 +650,33 @@ static inline unsigned long long pte_update(pte_t *p,
* On machines which use an MMU hash table we avoid changing the
* _PAGE_HASHPTE bit.
*/
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
+#elif defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
#else
*ptep = pte;
#endif
}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ WARN_ON(pte_present(*ptep));
+#endif
+ __set_pte_at(mm, addr, ptep, pte);
+}
+
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
* for our hash-based implementation, we fix that up here.
--
1.5.5.1
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[PATCH v5 4/4] powerpc/mm: Implement _PAGE_SPECIAL pte_special() for 32-bit
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().
We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 15 +--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 1b11955..c2e58b4 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;
#define _PAGE_HWEXEC 0x0004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x0008 /* S: Page referenced */
#define _PAGE_DIRTY0x0010 /* S: Page dirty */
+#define _PAGE_SPECIAL 0x0020 /* S: Special page */
#define _PAGE_USER 0x0040 /* S: User page */
#define _PAGE_ENDIAN 0x0080 /* H: E bit */
#define _PAGE_GUARDED 0x0100 /* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xULL
+#define __HAVE_ARCH_PTE_SPECIAL
#elif defined(CONFIG_FSL_BOOKE)
/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;
#define _PAGE_COHERENT 0x00100 /* H: M bit */
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
#define _PAGE_WRITETHRU0x00400 /* H: W bit */
+#define _PAGE_SPECIAL 0x00800 /* S: Special page */
#ifdef CONFIG_PTE_64BIT
/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+#define __HAVE_ARCH_PTE_SPECIAL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
#define _PAGE_RW 0x400 /* software: user write access allowed */
+#define _PAGE_SPECIAL 0x800 /* software: Special page */
#define _PTE_NONE_MASK _PAGE_HASHPTE
@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;
/* Hash table based platforms need atomic updates of the linux PTE */
#define PTE_ATOMIC_UPDATES 1
+#define __HAVE_ARCH_PTE_SPECIAL
+
#endif
/*
@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU0
#endif
+#ifndef _PAGE_SPECIAL
+#define _PAGE_SPECIAL 0
+#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK _PMD_PRESENT
#endif
@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte) {
return pte_val(pte) _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte)
_PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte)
_PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte_val(pte)
_PAGE_FILE; }
-static inline int pte_special(pte_t pte) { return 0; }
+static inline int pte_special(pte_t pte) { return pte_val(pte)
_PAGE_SPECIAL; }
static inline void pte_uncache(pte_t pte) { pte_val(pte) |=
_PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte) { pte_val(pte) =
~_PAGE_NO_CACHE; }
@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {
static inline pte_t pte_mkyoung(pte_t pte) {
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- return pte; }
+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline unsigned long pte_pgprot(pte_t pte)
{
return __pgprot(pte_val(pte)) PAGE_PROT_BITS;
--
1.5.5.1
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Re: [PATCH] ib/ehca: add flush CQE generation
thanks, queued for 2.6.28. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 10:24:35AM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov [EMAIL PROTECTED] wrote: Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still valid virq b/c it is mapped for another IRQ controller (particularly lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt, the PIC and IRQ8 is widely used on PowerPC). Set the base in the GPIO struct such that this won't happen. You can set the base greater than MAX_IRQ. And then you'll conflict with some other subsystem that decides to engage in the same shenanigans. Just allocate a chunk of virq space like any other cascaded IRQ controller. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Please pull from 'for-2.6.27'
Kumar Gala writes: Jochen Friedrich (1): powerpc/cpm1: Fix race condition in CPM1 GPIO library. This looks like a biggish change for after -rc6, and the commit message doesn't tell me what dire things will happen if the patch doesn't go in, or what systems see this breakage, or whether this is a regression since 2.6.26 (I assume it isn't). It doesn't even tell me why not being thread-safe is a problem on a UP machine. So... why does this fix need to go in at this stage? Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v5 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_all();
}
I love making you respin your patches so what about the one above
becomes tlbil_pid(0) ? :-)
Cheers,
Ben.
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Re: demuxing irqs
On Tue, Sep 16, 2008 at 1:49 PM, Scott Wood [EMAIL PROTECTED] wrote: On Tue, Sep 16, 2008 at 10:24:35AM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov [EMAIL PROTECTED] wrote: Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still valid virq b/c it is mapped for another IRQ controller (particularly lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt, the PIC and IRQ8 is widely used on PowerPC). Set the base in the GPIO struct such that this won't happen. You can set the base greater than MAX_IRQ. And then you'll conflict with some other subsystem that decides to engage in the same shenanigans. That comment was target at GPIO's that don't support interrupts. Give those GPIO numbers greater than MAX_IRQ in case someone tries to use them with the IRQ subsystem. Then they'll get errors. Just allocate a chunk of virq space like any other cascaded IRQ controller. That is what I did. -Scott -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v6 4/4] powerpc/mm: Implement _PAGE_SPECIAL pte_special() for 32-bit
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().
We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 15 +--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 1b11955..c2e58b4 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;
#define _PAGE_HWEXEC 0x0004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x0008 /* S: Page referenced */
#define _PAGE_DIRTY0x0010 /* S: Page dirty */
+#define _PAGE_SPECIAL 0x0020 /* S: Special page */
#define _PAGE_USER 0x0040 /* S: User page */
#define _PAGE_ENDIAN 0x0080 /* H: E bit */
#define _PAGE_GUARDED 0x0100 /* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xULL
+#define __HAVE_ARCH_PTE_SPECIAL
#elif defined(CONFIG_FSL_BOOKE)
/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;
#define _PAGE_COHERENT 0x00100 /* H: M bit */
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
#define _PAGE_WRITETHRU0x00400 /* H: W bit */
+#define _PAGE_SPECIAL 0x00800 /* S: Special page */
#ifdef CONFIG_PTE_64BIT
/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+#define __HAVE_ARCH_PTE_SPECIAL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
#define _PAGE_RW 0x400 /* software: user write access allowed */
+#define _PAGE_SPECIAL 0x800 /* software: Special page */
#define _PTE_NONE_MASK _PAGE_HASHPTE
@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;
/* Hash table based platforms need atomic updates of the linux PTE */
#define PTE_ATOMIC_UPDATES 1
+#define __HAVE_ARCH_PTE_SPECIAL
+
#endif
/*
@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU0
#endif
+#ifndef _PAGE_SPECIAL
+#define _PAGE_SPECIAL 0
+#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK _PMD_PRESENT
#endif
@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte) {
return pte_val(pte) _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte)
_PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte)
_PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte_val(pte)
_PAGE_FILE; }
-static inline int pte_special(pte_t pte) { return 0; }
+static inline int pte_special(pte_t pte) { return pte_val(pte)
_PAGE_SPECIAL; }
static inline void pte_uncache(pte_t pte) { pte_val(pte) |=
_PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte) { pte_val(pte) =
~_PAGE_NO_CACHE; }
@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {
static inline pte_t pte_mkyoung(pte_t pte) {
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- return pte; }
+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline unsigned long pte_pgprot(pte_t pte)
{
return __pgprot(pte_val(pte)) PAGE_PROT_BITS;
--
1.5.5.1
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[PATCH v6 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a WARN_ON to set_pte_at to ensure the pte isn't present for
the 64-bit pte/SMP case (to ensure our assumption of this fact).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
arch/powerpc/include/asm/highmem.h |2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 25 -
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/highmem.h
b/arch/powerpc/include/asm/highmem.h
index 5d99b64..91c5895 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum
km_type type, pgpro
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(kmap_pte-idx)));
#endif
- set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+ __set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..1b11955 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -652,16 +650,33 @@ static inline unsigned long long pte_update(pte_t *p,
* On machines which use an MMU hash table we avoid changing the
* _PAGE_HASHPTE bit.
*/
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
+#elif defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
#else
*ptep = pte;
#endif
}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ WARN_ON(pte_present(*ptep));
+#endif
+ __set_pte_at(mm, addr, ptep, pte);
+}
+
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
* for our hash-based implementation, we fix that up here.
--
1.5.5.1
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[PATCH v6 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:
_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)
On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.
The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.
On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Used _tlbil_pid(0) for flush_tlb_kernel_range
- k
arch/powerpc/include/asm/reg_booke.h |7
arch/powerpc/include/asm/tlbflush.h | 13 +---
arch/powerpc/kernel/misc_32.S| 53 ++
arch/powerpc/kernel/ppc_ksyms.c |3 ++
4 files changed, 71 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index be980f4..6745376 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -109,6 +109,7 @@
#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
#define SPRN_L1CSR00x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
@@ -410,6 +411,12 @@
#define L2CSR0_L2LOA 0x0080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO0x0020 /* L2 Cache Lock Overflow */
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI 0x0002 /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI 0x0004 /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI 0x0040 /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI 0x0020 /* TLB3 Flash invalidate */
+
/* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/include/asm/tlbflush.h
b/arch/powerpc/include/asm/tlbflush.h
index 361cd5c..a2c6bfd 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -29,6 +29,9 @@
#include linux/mm.h
extern void _tlbie(unsigned long address, unsigned int pid);
+extern void _tlbil_all(void);
+extern void _tlbil_pid(unsigned int pid);
+extern void _tlbil_va(unsigned long address, unsigned int pid);
#if defined(CONFIG_40x) || defined(CONFIG_8xx)
#define _tlbia() asm volatile (tlbia; sync : : : memory)
@@ -38,31 +41,31 @@ extern void _tlbia(void);
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- _tlbia();
+ _tlbil_pid(mm-context.id);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ _tlbil_va(vmaddr, vma ? vma-vm_mm-context.id : 0);
}
static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ flush_tlb_page(vma, vmaddr);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- _tlbia();
+ _tlbil_pid(vma-vm_mm-context.id);
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_pid(0);
}
#elif defined(CONFIG_PPC32)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..98f9a2d 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -274,6 +274,9 @@ _GLOBAL(real_writeb)
/*
* Flush MMU TLB
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_all)
+#endif
_GLOBAL(_tlbia)
#if defined(CONFIG_40x)
sync/* Flush to memory before changing mapping */
@@ -344,6 +347,9 @@ _GLOBAL(_tlbia)
/*
* Flush MMU TLB for a particular address
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_va)
+#endif
_GLOBAL(_tlbie)
#if defined(CONFIG_40x)
/* We run the search with interrupts disabled because we have to change
@@ -436,6 +442,53 @@ _GLOBAL(_tlbie)
#endif /* ! CONFIG_40x */
blr
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * Flush MMU TLB, but only on the local processor (no broadcast)
+ */
+_GLOBAL(_tlbil_all)
+#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI |
[PATCH v6 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/kernel/head_fsl_booke.S | 26 +- 1 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3cb52fa..377e0c1 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -579,13 +579,19 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ - bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif #endif -/* Jump to common tlb load */ + bne 2f /* Bail if permission/valid mismach */ + + /* Jump to common tlb load */ b finish_tlb_load 2: /* The bailout. Restore registers to pre-exception conditions @@ -640,10 +646,20 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ + +#ifdef CONFIG_PTE_64BIT +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif +#endif + bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) + lwz r13,0(r12) #endif /* Jump to common TLB load point */ @@ -702,7 +718,7 @@ interrupt_base: /* * Both the instruction and data TLB miss get to this * point to load the TLB. - * r10 - EA of fault + * r10 - available to use * r11 - TLB (info from Linux PTE) * r12 - available to use * r13 - upper bits of PTE (if PTE_64BIT) or available to use -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 02:32:45PM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 1:49 PM, Scott Wood [EMAIL PROTECTED] wrote: On Tue, Sep 16, 2008 at 10:24:35AM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov [EMAIL PROTECTED] wrote: Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still valid virq b/c it is mapped for another IRQ controller (particularly lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt, the PIC and IRQ8 is widely used on PowerPC). Set the base in the GPIO struct such that this won't happen. You can set the base greater than MAX_IRQ. And then you'll conflict with some other subsystem that decides to engage in the same shenanigans. That comment was target at GPIO's that don't support interrupts. Give those GPIO numbers greater than MAX_IRQ in case someone tries to use them with the IRQ subsystem. Then they'll get errors. Or we can do the right thing, without messing all other gpio controllers, i.e. implementing MAX_IRQ hacks. Right? I still don't see any problems with .to_irq callback, can you point out any? -- Anton Vorontsov email: [EMAIL PROTECTED] irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 5:42 PM, Anton Vorontsov [EMAIL PROTECTED] wrote: On Tue, Sep 16, 2008 at 02:32:45PM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 1:49 PM, Scott Wood [EMAIL PROTECTED] wrote: On Tue, Sep 16, 2008 at 10:24:35AM -0400, Jon Smirl wrote: On Tue, Sep 16, 2008 at 10:14 AM, Anton Vorontsov [EMAIL PROTECTED] wrote: Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still valid virq b/c it is mapped for another IRQ controller (particularly lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt, the PIC and IRQ8 is widely used on PowerPC). Set the base in the GPIO struct such that this won't happen. You can set the base greater than MAX_IRQ. And then you'll conflict with some other subsystem that decides to engage in the same shenanigans. That comment was target at GPIO's that don't support interrupts. Give those GPIO numbers greater than MAX_IRQ in case someone tries to use them with the IRQ subsystem. Then they'll get errors. Or we can do the right thing, without messing all other gpio controllers, i.e. implementing MAX_IRQ hacks. Right? I still don't see any problems with .to_irq callback, can you point out any? You have to map between GPIO and IRQ inside the interrupt handlers so it has to be reasonably fast. This gets done on every shared interrupt so you will end up building mapping tables. Also, gpio_to_irq() doesn't take the gpio chip struct as a parameter. Why does this mess with all of ther GPIO controllers? If they generate interrupts they obviously have to coordinate with the VIRQ system. This may be an issue with the way gpio lib is designed, the API for the library assumes all gpios in the system are assigned unique identifiers. Is there any other problem with 1:1 other than it doesn't return an error if gpio_to_irq() is called with a gpio number that doesn't support irqs? You could always implement gpio_to_irq() like this: if (gpio MAX_HW_IRQ) return -ENOSYSl return gpio; Sure your proposal works too, it's just more complicated. 1:1 mapping is working for ARM, why does PowerPC need to be different? I initially started coding it the way you propose but then I stumbled across the ARM solution and it was way simpler. -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 06:08:34PM -0400, Jon Smirl wrote: You have to map between GPIO and IRQ inside the interrupt handlers so it has to be reasonably fast. This gets done on every shared interrupt so you will end up building mapping tables. Also, gpio_to_irq() doesn't take the gpio chip struct as a parameter. Well, that sucks. We should be removing magic global numberspaces, not adding them. Why does this mess with all of ther GPIO controllers? If they generate interrupts they obviously have to coordinate with the VIRQ system. And if they don't generate interrupts, and they decide they can also just park themselves at MAX_IRQ? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 7:24 PM, Scott Wood [EMAIL PROTECTED] wrote: On Tue, Sep 16, 2008 at 06:08:34PM -0400, Jon Smirl wrote: You have to map between GPIO and IRQ inside the interrupt handlers so it has to be reasonably fast. This gets done on every shared interrupt so you will end up building mapping tables. Also, gpio_to_irq() doesn't take the gpio chip struct as a parameter. Well, that sucks. We should be removing magic global numberspaces, not adding them. Why does this mess with all of ther GPIO controllers? If they generate interrupts they obviously have to coordinate with the VIRQ system. And if they don't generate interrupts, and they decide they can also just park themselves at MAX_IRQ? More coordination has to be going on here, as far as I can tell gpiolib has a built in assumption that all gpios in a system are uniquely numbered. I guess that since most systems can't dynamically add GPIO the problem hasn't been addressed. It could be fixed by creating a function for obtaining the max gpio id in use and then using it as a base for any that are added later. The core complain here is: what happens if you assign non-interrupting GPIOs to 1-8 which are also hardware IRQs and then use irq functions on these non-interrupting GPIO ids. My answer to that is don't assign GPIO ids that are legal hardware interrupts. The function for determing max GPIO ID in use may even exist in the ARM code, I haven't gone looking for it. In the mpc5200 most (maybe all?) GPIOs are capable of being an interrupt source so a 1:1 mapping with VIRQs is the natural solution. mpc5200_pic.h reserves 208 spots for hardware interrupts. I don't know why, there aren't that many possible. There are 56 GPIO pins, so you end up with 264 virqs total. PowerPC defaults to 512 virqs available. -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Safe in bedroom
Leave the safe in the closet and don't lock it. They will build it into the closet permanently. -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
