UCC GETH does not work on my MPC8360EA
Hello, I have a wired problems with my MPC8360EA using Linux 2.6.27-rc6. The UCC GEHT controller works fine with 100/Full but fails with 1000/Full. What I see is that the TX done interrupts come (ifconfig's TX packet counter goes up), but the messages does not show up on the wire. RX seems to work properly, though. Any idea what's going wrong? Does someone got it working with 1000/Full? TIA, Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
RE: UCC GETH does not work on my MPC8360EA
-Original Message- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] On Behalf Of Wolfgang Grandegger Sent: Wednesday, September 17, 2008 5:18 PM To: linuxppc-dev Subject: UCC GETH does not work on my MPC8360EA Hello, I have a wired problems with my MPC8360EA using Linux 2.6.27-rc6. The UCC GEHT controller works fine with 100/Full but fails with 1000/Full. What I see is that the TX done interrupts come (ifconfig's TX packet counter goes up), but the messages does not show up on the wire. RX seems to work properly, though. Any idea what's going wrong? Does someone got it working with 1000/Full? This looks like an old problem that RGMII Tx shouldn't use internal delay while Rx should use. So try to use 'rgmii-rxid' as phy-connection-type in device tree. Also there should have been a fixup in u-boot for this. So update to use latest u-boot might fix your problem. - Leo ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: Please pull from 'for-2.6.27'
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Paul, This looks like a biggish change for after -rc6, and the commit message doesn't tell me what dire things will happen if the patch doesn't go in, or what systems see this breakage, or whether this is a regression since 2.6.26 (I assume it isn't). It doesn't even tell me why not being thread-safe is a problem on a UP machine. This isn't a regression since the stuff is new in 2.6.27. IMHO this can wait until 2.6.28. Thanks, Jochen -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iQEVAwUBSNDcHcP9a9GOLSE6AQLqmgf+JwnbVciHzA3idXiTabS2x/k7vkBj+rUp SIw/OHk+G3jjr/wsZaJoZbtPsChoQ5vAqKJYXFKDSadWzo90zfRgKG29PIcjm3ME gCX3U/u31T6TdtUVSlhIxDeQuOHCpSSbDuW+++rAomAQkLmderyk997KBVUIALtY ExsxL5YUBj0NsmQoi0wtguTR1O38/uyiB3t+74hz0E5VoDxzNQFtDCHb/MFJdt6N OtavyY+ceCYNRmul4R1rmnRazu8Lf05p8inWsf87c7Y6dBPODlxqCIv/qOVa6AdY 8wUCzinTdCA3s1mnWjpfyHvFhFZ+QFolqZdYkYtikCEM+GOsVbKHuA== =taK6 -END PGP SIGNATURE- ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: demuxing irqs
On Tue, Sep 16, 2008 at 06:08:34PM -0400, Jon Smirl wrote:
[...]
Assume that GPIO 8 does not translate to any IRQ, but IRQ 8 is still
valid virq b/c it is mapped for another IRQ controller (particularly
lots of kernel code assumes that IRQ 8 is 8259 PIC's CMOS interrupt,
the PIC and IRQ8 is widely used on PowerPC).
Set the base in the GPIO struct such that this won't happen. You can
set the base greater than MAX_IRQ.
And then you'll conflict with some other subsystem that decides to engage
in the same shenanigans.
That comment was target at GPIO's that don't support interrupts. Give
those GPIO numbers greater than MAX_IRQ in case someone tries to use
them with the IRQ subsystem. Then they'll get errors.
Or we can do the right thing, without messing all other gpio
controllers, i.e. implementing MAX_IRQ hacks. Right?
I still don't see any problems with .to_irq callback, can you
point out any?
You have to map between GPIO and IRQ inside the interrupt handlers so
it has to be reasonably fast. This gets done on every shared interrupt
so you will end up building mapping tables.
I don't get it. The mapping for your gpio controller will be 1:1.
But only for your GPIO controller. You don't have to create any tables.
That is,
static unsigned int your_controller_gpio_to_irq(stuct gpio_chip *gc,
unsigned int gpio)
{
return gc-base + gpio; /* guaranteed for this particular
irq/gpio controller bundle, because
gc-base == virq_base AND we
use 1:1 mapping. */
}
gpio_chip-to_irq = your_controller_gpio_to_irq;
Where is the table?
Also, gpio_to_irq()
doesn't take the gpio chip struct as a parameter.
You don't need this, since gpio_to_irq will call gpiolib's
__gpio_to_irq(), and gpiolib will call gpio_to_chip() to get the
chip struct. The approach is the same as we do for
gpio_{get,set}_value via gpiolib.
Why does this mess with all of ther GPIO controllers? If they generate
interrupts they obviously have to coordinate with the VIRQ system.
Btw, why do you need the gpio_to_irq call in the first place?
Why don't you just configure a gpio to serve as an interrupt source
(inside one of irq_host_ops), and just specify interrupts =
along side with gpios = in the ir node?
For example,
gpio_wkup: [EMAIL PROTECTED] {
compatible = fsl,mpc5200b-gpio-wkup,fsl,mpc5200-gpio-wkup;
reg = 0xc00 0x40;
interrupts = 0x1 0x8 0x0 0x0 0x3 0x0;
interrupt-parent = mpc5200_pic;
gpio-controller;
#gpio-cells = 2;
interrupt-controller; -- added
#interrupt-cells = 2; -- added
};
ir {
interrupts = 0 1; -- notice that irq-specific flags
placed where they should.
interrupt-parent = gpio_wkup;
gpios = gpio_w 0 0; -- notice that 1:1 mapping is explicit
};
...and you don't need the gpio_to_irq.
(Plus. I would rather split the gpio-wkup node into two:
interrupt-controller, and gpio-controller).
This may be an issue with the way gpio lib is designed, the API for
the library assumes all gpios in the system are assigned unique
identifiers.
Is there any other problem with 1:1 other than it doesn't return an
error if gpio_to_irq() is called with a gpio number that doesn't
support irqs?
Yes. We might want non-1:1 mapping for other gpio controllers.
And we can't handle gpio_to_irq() for GPIO0 (yes, sure, we can
implement another hack: reserve GPIO0 for no use. ;-)
You could always implement gpio_to_irq() like this:
if (gpio MAX_HW_IRQ)
return -ENOSYSl
return gpio;
Don't know anything about MAX_HW_IRQ... maybe NR_IRQS? I heard
some rumors about making NR_IRQS dynamic...
Sure your proposal works too, it's just more complicated. 1:1 mapping
is working for ARM, why does PowerPC need to be different? I initially
started coding it the way you propose but then I stumbled across the
ARM solution and it was way simpler.
I don't see why adding one more gpiolib callback would complicate
things. Today you're _forcing_ every gpio controller to have 1:1
irq:gpio mapping. I think later we will encounter more problems
with it and then we will blame our lack of foresight...
--
Anton Vorontsov
email: [EMAIL PROTECTED]
irc://irc.freenode.net/bd2
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Re: demuxing irqs
Both solutions can be implemented. This is really a question of style. Since this impacts all of the PowerPC implementations we should get feedback from more people I'll go along with whatever the group wants. The basic question is: Should GPIOs and VIRQs each have their own namespace, or should there be a single unified namespace? -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] [2.6.27] ehea: Fix memory hotplug support
This patch implements the memory notifier to update the busmap instantly
instead of rebuilding the whole map. This is necessary because
walk_memory_resource provides different information than required during memory
hotplug.
Signed-off-by: Hannes Hering [EMAIL PROTECTED]
---
This patch is based on upstream-fixes in the netdev-2.6.git.
diff -Nurp -X dontdiff linux-netdev-2.6/drivers/net/ehea/ehea.h
patched_kernel/drivers/net/ehea/ehea.h
--- linux-netdev-2.6/drivers/net/ehea/ehea.h2008-09-17 16:09:25.729017931
+0200
+++ patched_kernel/drivers/net/ehea/ehea.h 2008-09-17 16:11:26.481026217
+0200
@@ -40,13 +40,13 @@
#include asm/io.h
#define DRV_NAME ehea
-#define DRV_VERSIONEHEA_0092
+#define DRV_VERSIONEHEA_0094
/* eHEA capability flags */
#define DLPAR_PORT_ADD_REM 1
#define DLPAR_MEM_ADD 2
#define DLPAR_MEM_REM 4
-#define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD)
+#define EHEA_CAPABILITIES (DLPAR_PORT_ADD_REM | DLPAR_MEM_ADD | DLPAR_MEM_REM)
#define EHEA_MSG_DEFAULT (NETIF_MSG_LINK | NETIF_MSG_TIMER \
| NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
diff -Nurp -X dontdiff linux-netdev-2.6/drivers/net/ehea/ehea_main.c
patched_kernel/drivers/net/ehea/ehea_main.c
--- linux-netdev-2.6/drivers/net/ehea/ehea_main.c 2008-09-17
16:09:25.729017931 +0200
+++ patched_kernel/drivers/net/ehea/ehea_main.c 2008-09-17 16:11:26.481026217
+0200
@@ -2863,7 +2863,7 @@ static void ehea_rereg_mrs(struct work_s
struct ehea_adapter *adapter;
mutex_lock(dlpar_mem_lock);
- ehea_info(LPAR memory enlarged - re-initializing driver);
+ ehea_info(LPAR memory changed - re-initializing driver);
list_for_each_entry(adapter, adapter_list, list)
if (adapter-active_ports) {
@@ -2900,13 +2900,6 @@ static void ehea_rereg_mrs(struct work_s
}
}
- ehea_destroy_busmap();
- ret = ehea_create_busmap();
- if (ret) {
- ehea_error(creating ehea busmap failed);
- goto out;
- }
-
clear_bit(__EHEA_STOP_XFER, ehea_driver_flags);
list_for_each_entry(adapter, adapter_list, list)
@@ -3519,9 +3512,20 @@ void ehea_crash_handler(void)
static int ehea_mem_notifier(struct notifier_block *nb,
unsigned long action, void *data)
{
+ struct memory_notify *arg = data;
switch (action) {
- case MEM_OFFLINE:
- ehea_info(memory has been removed);
+ case MEM_CANCEL_OFFLINE:
+ ehea_info(memory offlining canceled);
+ case MEM_ONLINE:
+ ehea_info(memory is going online);
+ if (ehea_add_sect_bmap(arg-start_pfn, arg-nr_pages))
+ return NOTIFY_BAD;
+ ehea_rereg_mrs(NULL);
+ break;
+ case MEM_GOING_OFFLINE:
+ ehea_info(memory is going offline);
+ if (ehea_rem_sect_bmap(arg-start_pfn, arg-nr_pages))
+ return NOTIFY_BAD;
ehea_rereg_mrs(NULL);
break;
default:
diff -Nurp -X dontdiff linux-netdev-2.6/drivers/net/ehea/ehea_qmr.c
patched_kernel/drivers/net/ehea/ehea_qmr.c
--- linux-netdev-2.6/drivers/net/ehea/ehea_qmr.c2008-09-17
16:09:25.729017931 +0200
+++ patched_kernel/drivers/net/ehea/ehea_qmr.c 2008-09-17 16:11:26.481026217
+0200
@@ -587,53 +587,81 @@ static inline int ehea_init_bmap(struct
return ehea_init_top_bmap(ehea_bmap-top[top], dir);
}
-static int ehea_create_busmap_callback(unsigned long pfn,
- unsigned long nr_pages, void *arg)
+static DEFINE_MUTEX(ehea_busmap_mutex);
+static unsigned long ehea_mr_len;
+
+#define EHEA_BUSMAP_ADD_SECT 1
+#define EHEA_BUSMAP_REM_SECT 0
+
+static int ehea_update_busmap(unsigned long pfn, unsigned long pgnum, int add)
{
- unsigned long i, mr_len, start_section, end_section;
- start_section = (pfn * PAGE_SIZE) / EHEA_SECTSIZE;
- end_section = start_section + ((nr_pages * PAGE_SIZE) / EHEA_SECTSIZE);
- mr_len = *(unsigned long *)arg;
+ unsigned long i, start_section, end_section;
if (!ehea_bmap)
ehea_bmap = kzalloc(sizeof(struct ehea_bmap), GFP_KERNEL);
if (!ehea_bmap)
return -ENOMEM;
+ start_section = (pfn * PAGE_SIZE) / EHEA_SECTSIZE;
+ end_section = start_section + ((pgnum * PAGE_SIZE) / EHEA_SECTSIZE);
+
for (i = start_section; i end_section; i++) {
- int ret;
- int top, dir, idx;
u64 vaddr;
+ int top = ehea_calc_index(i, EHEA_TOP_INDEX_SHIFT);
+ int dir = ehea_calc_index(i, EHEA_DIR_INDEX_SHIFT);
+ int idx = i EHEA_INDEX_MASK;
+
+ int ret = ehea_init_bmap(ehea_bmap, top, dir);
+ if (ret) {
+ if(add) {
+ return ret;
+
RE: demuxing irqs
It doesn't seem to me that the problem (hierarchical interrupts) is one that only happens with GPIOs, so why treat them specially? Since there seems to be a reasonable solution that keeps them in a separate namespace, that seems like the better way to go... Steve -Original Message- From: [EMAIL PROTECTED] [mailto:linuxppc-dev- [EMAIL PROTECTED] On Behalf Of Jon Smirl Sent: Wednesday, September 17, 2008 7:09 AM To: [EMAIL PROTECTED] Cc: Scott Wood; linuxppc-dev; Roland Dreier Subject: Re: demuxing irqs Both solutions can be implemented. This is really a question of style. Since this impacts all of the PowerPC implementations we should get feedback from more people I'll go along with whatever the group wants. The basic question is: Should GPIOs and VIRQs each have their own namespace, or should there be a single unified namespace? -- Jon Smirl [EMAIL PROTECTED] ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2] powerpc: implement support for MPC8349-compatible SOC GPIOs
This patch implements GPIOLIB support for MPC8349-compatible SOC GPIOs.
MPC8610 adopted this GPIO unit, so let's place it into sysdev.
We'll need these gpios to support IrDA transceiver on MPC8610HPCD.
Signed-off-by: Anton Vorontsov [EMAIL PROTECTED]
---
v2:
- Incorporated Peter Korsgaard's suggestion regarding order
of setting data/direction registers.
The patch applies on top of powerpc: add driver for simple GPIO banks.
arch/powerpc/sysdev/Kconfig| 10 ++
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_mpc8349_gpio.c | 161
3 files changed, 172 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/fsl_mpc8349_gpio.c
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 30d6e4d..4cbfda0 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -17,3 +17,13 @@ config OF_SIMPLE_GPIO
These are usually BCSRs used to control board's switches, LEDs,
chip-selects, Ethernet/USB PHY's power and various other small
on-board peripherals.
+
+config FSL_MPC8349_GPIO
+ bool Support for MPC8349-compatible GPIO controllers
+ depends on PPC32
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ help
+ Say Y here to support Freescale MPC8349-compatible GPIO controllers.
+ The controllers can be found in MPC831x, MPC834x, MPC837x and
+ MPC8610 processors.
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 239d7e8..afbc3a4 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_4xx) += ppc4xx_pci.o
endif
obj-$(CONFIG_OF_SIMPLE_GPIO) += of_simple_gpio.o
+obj-$(CONFIG_FSL_MPC8349_GPIO) += fsl_mpc8349_gpio.o
# Temporary hack until we have migrated to asm-powerpc
ifeq ($(ARCH),powerpc)
diff --git a/arch/powerpc/sysdev/fsl_mpc8349_gpio.c
b/arch/powerpc/sysdev/fsl_mpc8349_gpio.c
new file mode 100644
index 000..c8c77f4
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_mpc8349_gpio.c
@@ -0,0 +1,161 @@
+/*
+ * MPC8349-compatible SOC GPIOs
+ *
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Anton Vorontsov [EMAIL PROTECTED]
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/init.h
+#include linux/types.h
+#include linux/kernel.h
+#include linux/compiler.h
+#include linux/spinlock.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/gpio.h
+
+#define FSL_GPIO_PINS 32
+
+struct fsl_gpio_regs {
+ __be32 gpdir;
+ __be32 gpodr;
+ __be32 gpdat;
+ __be32 gpier;
+ __be32 gpimr;
+ __be32 gpicr;
+};
+
+struct fsl_gpio_chip {
+ struct of_mm_gpio_chip mm_gc;
+ spinlock_t lock;
+
+ /* shadowed data register to clear/set bits safely */
+ u32 gpdat;
+};
+
+static inline u32 pin2mask(unsigned int pin)
+{
+ return 1 (FSL_GPIO_PINS - 1 - pin);
+}
+
+static inline struct fsl_gpio_chip *
+to_fsl_gpio_chip(struct of_mm_gpio_chip *mm_gc)
+{
+ return container_of(mm_gc, struct fsl_gpio_chip, mm_gc);
+}
+
+static void fsl_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+ struct fsl_gpio_chip *fsl_gc = to_fsl_gpio_chip(mm_gc);
+ struct fsl_gpio_regs __iomem *regs = mm_gc-regs;
+
+ fsl_gc-gpdat = in_be32(regs-gpdat);
+}
+
+static int fsl_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct fsl_gpio_regs __iomem *regs = mm_gc-regs;
+
+ return in_be32(regs-gpdat) pin2mask(gpio);
+}
+
+static void fsl_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct fsl_gpio_chip *fsl_gc = to_fsl_gpio_chip(mm_gc);
+ struct fsl_gpio_regs __iomem *regs = mm_gc-regs;
+ unsigned long flags;
+
+ spin_lock_irqsave(fsl_gc-lock, flags);
+
+ if (val)
+ fsl_gc-gpdat |= pin2mask(gpio);
+ else
+ fsl_gc-gpdat = ~pin2mask(gpio);
+
+ out_be32(regs-gpdat, fsl_gc-gpdat);
+
+ spin_unlock_irqrestore(fsl_gc-lock, flags);
+}
+
+static int fsl_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+ struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+ struct fsl_gpio_chip *fsl_gc = to_fsl_gpio_chip(mm_gc);
+ struct fsl_gpio_regs __iomem *regs = mm_gc-regs;
+ unsigned long flags;
+
+ spin_lock_irqsave(fsl_gc-lock, flags);
+ clrbits32(regs-gpdir, pin2mask(gpio));
+ spin_unlock_irqrestore(fsl_gc-lock, flags);
+ return 0;
+}
+
+static int fsl_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio,
+
Re: build failure with current linus tree
Christoph Hellwig wrote: On Fri, Sep 05, 2008 at 03:06:18AM +0200, Christoph Hellwig wrote: Current linus tree fail to build for me for a 64bit powerpc config with: This is cause by commit 7563dc64585324f443f5ac107eb6d89ee813a2d2 Author: Tony Breeds [EMAIL PROTECTED] Date: Tue Sep 2 16:50:38 2008 +1000 powerpc: Work around gcc's -fno-omit-frame-pointer bug Is there a proper fix other than simply reverting that commit? Chris ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: build failure with current linus tree
Chris Friesen writes: Is there a proper fix other than simply reverting that commit? It appears that we have a choice between having CONFIG_FTRACE work with gcc 4 and not gcc 3 (the current situation), and having CONFIG_FTRACE work with gcc 3 and not gcc 4 (which is what we would have if that commit was reverted). I think more people use gcc 4 than gcc 3 these days, which is why I haven't reverted that commit. Paul. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc: implement support for MPC8349-compatible SOC GPIOs
Anton == Anton Vorontsov [EMAIL PROTECTED] writes:
Hi,
Anton This patch implements GPIOLIB support for MPC8349-compatible SOC GPIOs.
Anton MPC8610 adopted this GPIO unit, so let's place it into sysdev.
Anton We'll need these gpios to support IrDA transceiver on MPC8610HPCD.
It seems basically the same as my patch (gpio driver for
mpc831x/mpc834x/mpc837x with OF bindings) from September 5th except
you don't have any documentation and the Kconfig doesn't depend on
831x/834x/837x.
Galak, did you have time to look at these patches yet?
Anton +struct fsl_gpio_chip {
Anton + struct of_mm_gpio_chip mm_gc;
Anton + spinlock_t lock;
Anton +
Anton + /* shadowed data register to clear/set bits safely */
Anton + u32 gpdat;
Why do you need this when you have the lock?
--
Bye, Peter Korsgaard
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Re: [PATCH] powerpc: add SSI-to-DMA properties to Freescale MPC8610 HPCD device tree
On Aug 6, 2008, at 11:48 AM, Timur Tabi wrote: Add the fsl,playback-dma and fsl,capture-dma properties to the Freescale MPC8610 HPCD device tree. These properties connect the SSI nodes to the DMA nodes for the DMA channels that the SSI should use. Also update the ssi.txt documentation. These properties will be needed when the ASoC V2 version of the Freescale MPC8610 device drivers are merged into the mainline. Signed-off-by: Timur Tabi [EMAIL PROTECTED] --- Documentation/powerpc/dts-bindings/fsl/ssi.txt | 15 +++ arch/powerpc/boot/dts/mpc8610_hpcd.dts |8 +--- 2 files changed, 20 insertions(+), 3 deletions(-) applied. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
device tree interrupt-map/interrupt-map-mask properties for a 405EP board
Hi,
I am trying to setup a device tree for a 405EP based board.
I did not fully understand how to setup the interrupt-map-mask and
interrupt-map properties for the PCI node:
...
PCI0: [EMAIL PROTECTED] {
...
interrupt-map-mask = 0x 0x0 0x0 0x0;
interrupt-map =
/* slot1: IDSEL AD12 - ext. Irq 4 */
0x 0x0 0x0 0x0 UIC0 29 0x8
/* slot2: IDSEL AD13 - ext. Irq 5 */
0x 0x0 0x0 0x0 UIC0 30 0x8
/* slot3: IDSEL AD14 - ext. Irq 6 */
0x 0x0 0x0 0x0 UIC0 31 0x8
;
};
I have three PCI slots on the board. How do I have to fill out the fields
above? ADxx - IDSEL connection can be taken from the comments. Each slot
has its interrupt lines INTA..D connected to a single 405 external interrupt
input.
Where can I find any docs about this?
Matthias
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[PATCH v7 1/4] powerpc: Introduce local (non-broadcast) forms of tlb invalidates
Introduced a new set of low level tlb invalidate functions that do not
broadcast invalidates on the bus:
_tlbil_all - invalidate all
_tlbil_pid - invalidate based on process id (or mm context)
_tlbil_va - invalidate based on virtual address (ea + pid)
On non-SMP configs _tlbil_all should be functionally equivalent to _tlbia and
_tlbil_va should be functionally equivalent to _tlbie.
The intent of this change is to handle SMP based invalidates via IPIs instead
of broadcasts as the mechanism scales better for larger number of cores.
On e500 (fsl-booke mmu) based cores move to using MMUCSR for invalidate alls
and tlbsx/tlbwe for invalidate virtual address.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Fixed build issue with non-fsl-book-e not having a version of _tlbil_pid().
- k
arch/powerpc/include/asm/reg_booke.h |7
arch/powerpc/include/asm/tlbflush.h | 13 +---
arch/powerpc/kernel/misc_32.S| 54 ++
arch/powerpc/kernel/ppc_ksyms.c |3 ++
4 files changed, 72 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index be980f4..6745376 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -109,6 +109,7 @@
#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
#define SPRN_L1CSR00x3F2 /* L1 Cache Control and Status Register 0 */
#define SPRN_L1CSR10x3F3 /* L1 Cache Control and Status Register 1 */
+#define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
#define SPRN_L2CSR00x3F9 /* L2 Data Cache Control and Status Register 0
*/
@@ -410,6 +411,12 @@
#define L2CSR0_L2LOA 0x0080 /* L2 Cache Lock Overflow Allocate */
#define L2CSR0_L2LO0x0020 /* L2 Cache Lock Overflow */
+/* Bit definitions for MMUCSR0 */
+#define MMUCSR0_TLB1FI 0x0002 /* TLB1 Flash invalidate */
+#define MMUCSR0_TLB0FI 0x0004 /* TLB0 Flash invalidate */
+#define MMUCSR0_TLB2FI 0x0040 /* TLB2 Flash invalidate */
+#define MMUCSR0_TLB3FI 0x0020 /* TLB3 Flash invalidate */
+
/* Bit definitions for SGR. */
#define SGR_NORMAL 0 /* Speculative fetching allowed. */
#define SGR_GUARDED1 /* Speculative fetching disallowed. */
diff --git a/arch/powerpc/include/asm/tlbflush.h
b/arch/powerpc/include/asm/tlbflush.h
index 361cd5c..a2c6bfd 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -29,6 +29,9 @@
#include linux/mm.h
extern void _tlbie(unsigned long address, unsigned int pid);
+extern void _tlbil_all(void);
+extern void _tlbil_pid(unsigned int pid);
+extern void _tlbil_va(unsigned long address, unsigned int pid);
#if defined(CONFIG_40x) || defined(CONFIG_8xx)
#define _tlbia() asm volatile (tlbia; sync : : : memory)
@@ -38,31 +41,31 @@ extern void _tlbia(void);
static inline void flush_tlb_mm(struct mm_struct *mm)
{
- _tlbia();
+ _tlbil_pid(mm-context.id);
}
static inline void flush_tlb_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ _tlbil_va(vmaddr, vma ? vma-vm_mm-context.id : 0);
}
static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- _tlbie(vmaddr, vma ? vma-vm_mm-context.id : 0);
+ flush_tlb_page(vma, vmaddr);
}
static inline void flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- _tlbia();
+ _tlbil_pid(vma-vm_mm-context.id);
}
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- _tlbia();
+ _tlbil_pid(0);
}
#elif defined(CONFIG_PPC32)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 7a6dfbc..e9c8ab6 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -274,6 +274,10 @@ _GLOBAL(real_writeb)
/*
* Flush MMU TLB
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_all)
+_GLOBAL(_tlbil_pid)
+#endif
_GLOBAL(_tlbia)
#if defined(CONFIG_40x)
sync/* Flush to memory before changing mapping */
@@ -344,6 +348,9 @@ _GLOBAL(_tlbia)
/*
* Flush MMU TLB for a particular address
*/
+#ifndef CONFIG_FSL_BOOKE
+_GLOBAL(_tlbil_va)
+#endif
_GLOBAL(_tlbie)
#if defined(CONFIG_40x)
/* We run the search with interrupts disabled because we have to change
@@ -436,6 +443,53 @@ _GLOBAL(_tlbie)
#endif /* ! CONFIG_40x */
blr
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * Flush MMU TLB, but only on the local processor (no broadcast)
+ */
[PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP support
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a check to set_pte_at to clear the pte if it happened to be set.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Changed the set_pte_at checking to deal with the case that it's called
with a pte that has pte_present and clearing it w/proper ordering.
- k
arch/powerpc/include/asm/highmem.h |2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 28 +++-
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/highmem.h
b/arch/powerpc/include/asm/highmem.h
index 5d99b64..91c5895 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum
km_type type, pgpro
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(kmap_pte-idx)));
#endif
- set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+ __set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..d1d23b9 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep)do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#definepmd_bad(pmd)(pmd_val(pmd) _PMD_BAD)
@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -652,16 +650,36 @@ static inline unsigned long long pte_update(pte_t *p,
* On machines which use an MMU hash table we avoid changing the
* _PAGE_HASHPTE bit.
*/
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
+#elif defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
#else
*ptep = pte;
#endif
}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if defined(CONFIG_PTE_64BIT)
+ if (unlikely(pte_present(*ptep))) {
+ pte_clear(mm, addr, ptep);
+ smp_wmb();
+ }
+#endif
+ __set_pte_at(mm, addr, ptep, pte);
+}
+
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
* for our hash-based implementation, we fix that up here.
--
1.5.5.1
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[PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of the pte are done in the right order. Signed-off-by: Kumar Gala [EMAIL PROTECTED] --- arch/powerpc/kernel/head_fsl_booke.S | 26 +- 1 files changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 3cb52fa..377e0c1 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -579,13 +579,19 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ - bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif #endif -/* Jump to common tlb load */ + bne 2f /* Bail if permission/valid mismach */ + + /* Jump to common tlb load */ b finish_tlb_load 2: /* The bailout. Restore registers to pre-exception conditions @@ -640,10 +646,20 @@ interrupt_base: FIND_PTE andc. r13,r13,r11 /* Check permission */ + +#ifdef CONFIG_PTE_64BIT +#ifdef CONFIG_SMP + subfr10,r11,r12 /* create false data dep */ + lwzxr13,r11,r10 /* Get upper pte bits */ +#else + lwz r13,0(r12) /* Get upper pte bits */ +#endif +#endif + bne 2f /* Bail if permission mismach */ #ifdef CONFIG_PTE_64BIT - lwz r13, 0(r12) + lwz r13,0(r12) #endif /* Jump to common TLB load point */ @@ -702,7 +718,7 @@ interrupt_base: /* * Both the instruction and data TLB miss get to this * point to load the TLB. - * r10 - EA of fault + * r10 - available to use * r11 - TLB (info from Linux PTE) * r12 - available to use * r13 - upper bits of PTE (if PTE_64BIT) or available to use -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL pte_special() for 32-bit
Implement _PAGE_SPECIAL and pte_special() for 32-bit powerpc. This bit will
be used by the fast get_user_pages() to differenciate PTEs that correspond
to a valid struct page from special mappings that don't such as IO mappings
obtained via io_remap_pfn_ranges().
We currently only implement this on sub-arch that support SMP or will so
in the future (6xx, 44x, FSL-BookE) and not (8xx, 40x).
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
Acked-by: Benjamin Herrenschmidt [EMAIL PROTECTED]
---
arch/powerpc/include/asm/pgtable-ppc32.h | 15 +--
1 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index d1d23b9..e8f31a5 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -261,6 +261,7 @@ extern int icache_44x_need_flush;
#define _PAGE_HWEXEC 0x0004 /* H: Execute permission */
#define _PAGE_ACCESSED 0x0008 /* S: Page referenced */
#define _PAGE_DIRTY0x0010 /* S: Page dirty */
+#define _PAGE_SPECIAL 0x0020 /* S: Special page */
#define _PAGE_USER 0x0040 /* S: User page */
#define _PAGE_ENDIAN 0x0080 /* H: E bit */
#define _PAGE_GUARDED 0x0100 /* H: G bit */
@@ -276,6 +277,7 @@ extern int icache_44x_need_flush;
/* ERPN in a PTE never gets cleared, ignore it */
#define _PTE_NONE_MASK 0xULL
+#define __HAVE_ARCH_PTE_SPECIAL
#elif defined(CONFIG_FSL_BOOKE)
/*
@@ -305,6 +307,7 @@ extern int icache_44x_need_flush;
#define _PAGE_COHERENT 0x00100 /* H: M bit */
#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
#define _PAGE_WRITETHRU0x00400 /* H: W bit */
+#define _PAGE_SPECIAL 0x00800 /* S: Special page */
#ifdef CONFIG_PTE_64BIT
/* ERPN in a PTE never gets cleared, ignore it */
@@ -315,6 +318,8 @@ extern int icache_44x_need_flush;
#define _PMD_PRESENT_MASK (PAGE_MASK)
#define _PMD_BAD (~PAGE_MASK)
+#define __HAVE_ARCH_PTE_SPECIAL
+
#elif defined(CONFIG_8xx)
/* Definitions for 8xx embedded chips. */
#define _PAGE_PRESENT 0x0001 /* Page is valid */
@@ -362,6 +367,7 @@ extern int icache_44x_need_flush;
#define _PAGE_ACCESSED 0x100 /* R: page referenced */
#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
#define _PAGE_RW 0x400 /* software: user write access allowed */
+#define _PAGE_SPECIAL 0x800 /* software: Special page */
#define _PTE_NONE_MASK _PAGE_HASHPTE
@@ -372,6 +378,8 @@ extern int icache_44x_need_flush;
/* Hash table based platforms need atomic updates of the linux PTE */
#define PTE_ATOMIC_UPDATES 1
+#define __HAVE_ARCH_PTE_SPECIAL
+
#endif
/*
@@ -404,6 +412,9 @@ extern int icache_44x_need_flush;
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU0
#endif
+#ifndef _PAGE_SPECIAL
+#define _PAGE_SPECIAL 0
+#endif
#ifndef _PMD_PRESENT_MASK
#define _PMD_PRESENT_MASK _PMD_PRESENT
#endif
@@ -534,7 +545,7 @@ static inline int pte_write(pte_t pte) {
return pte_val(pte) _PAGE_RW; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte)
_PAGE_DIRTY; }
static inline int pte_young(pte_t pte) { return pte_val(pte)
_PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte_val(pte)
_PAGE_FILE; }
-static inline int pte_special(pte_t pte) { return 0; }
+static inline int pte_special(pte_t pte) { return pte_val(pte)
_PAGE_SPECIAL; }
static inline void pte_uncache(pte_t pte) { pte_val(pte) |=
_PAGE_NO_CACHE; }
static inline void pte_cache(pte_t pte) { pte_val(pte) =
~_PAGE_NO_CACHE; }
@@ -553,7 +564,7 @@ static inline pte_t pte_mkdirty(pte_t pte) {
static inline pte_t pte_mkyoung(pte_t pte) {
pte_val(pte) |= _PAGE_ACCESSED; return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- return pte; }
+ pte_val(pte) |= _PAGE_SPECIAL; return pte; }
static inline unsigned long pte_pgprot(pte_t pte)
{
return __pgprot(pte_val(pte)) PAGE_PROT_BITS;
--
1.5.5.1
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Re: Linuxppc-dev Digest, Vol 49, Issue 89
2008-09-18
limitjiang
发件人： [EMAIL PROTECTED]
发送时间： 2008-09-18 09:55:11
收件人： linuxppc-dev@ozlabs.org
抄送：
主题： Linuxppc-dev Digest, Vol 49, Issue 89
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When replying, please edit your Subject line so it is more specific
than Re: Contents of Linuxppc-dev digest...
Today's Topics:
1. [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP
support (Kumar Gala)
2. [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading
for SMP support (Kumar Gala)
3. [PATCH v7 4/4] powerpc/mm: Implement _PAGE_SPECIAL
pte_special() for 32-bit (Kumar Gala)
--
Message: 1
Date: Wed, 17 Sep 2008 18:00:03 -0500
From: Kumar Gala [EMAIL PROTECTED]
Subject: [PATCH v7 2/4] powerpc: Fixes for CONFIG_PTE_64BIT for SMP
support
To: linuxppc-dev@ozlabs.org
Message-ID:
[EMAIL PROTECTED]
There are some minor issues with support 64-bit PTEs on a 32-bit processor
when dealing with SMP.
* We need to order the stores in set_pte_at to make sure the flag word
is set second.
* Change pte_clear to use pte_update so only the flag word is cleared
* Added a check to set_pte_at to clear the pte if it happened to be set.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
Changed the set_pte_at checking to deal with the case that it's called
with a pte that has pte_present and clearing it w/proper ordering.
- k
arch/powerpc/include/asm/highmem.h |2 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 28 +++-
2 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/highmem.h
b/arch/powerpc/include/asm/highmem.h
index 5d99b64..91c5895 100644
--- a/arch/powerpc/include/asm/highmem.h
+++ b/arch/powerpc/include/asm/highmem.h
@@ -84,7 +84,7 @@ static inline void *kmap_atomic_prot(struct page *page, enum
km_type type, pgpro
#ifdef CONFIG_DEBUG_HIGHMEM
BUG_ON(!pte_none(*(kmap_pte-idx)));
#endif
- set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
+ __set_pte_at(init_mm, vaddr, kmap_pte-idx, mk_pte(page, prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h
b/arch/powerpc/include/asm/pgtable-ppc32.h
index 6fe39e3..d1d23b9 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -517,7 +517,8 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
#define pte_none(pte) ((pte_val(pte) ~_PTE_NONE_MASK) == 0)
#define pte_present(pte) (pte_val(pte) _PAGE_PRESENT)
-#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep),
__pte(0)); } while (0)
+#define pte_clear(mm, addr, ptep) \
+ do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
#define pmd_none(pmd) (!pmd_val(pmd))
#define pmd_bad(pmd) (pmd_val(pmd) _PMD_BAD)
@@ -612,9 +613,6 @@ static inline unsigned long pte_update(pte_t *p,
return old;
}
#else /* CONFIG_PTE_64BIT */
-/* TODO: Change that to only modify the low word and move set_pte_at()
- * out of line
- */
static inline unsigned long long pte_update(pte_t *p,
unsigned long clr,
unsigned long set)
@@ -652,16 +650,36 @@ static inline unsigned long long pte_update(pte_t *p,
* On machines which use an MMU hash table we avoid changing the
* _PAGE_HASHPTE bit.
*/
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
pte_t *ptep, pte_t pte)
{
#if _PAGE_HASHPTE != 0
pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) ~_PAGE_HASHPTE);
+#elif defined(CONFIG_PTE_64BIT) defined(CONFIG_SMP)
+ __asm__ __volatile__(\
+ stw%U0%X0 %2,%0\n\
+ eieio\n\
+ stw%U0%X0 %L2,%1
+ : =m (*ptep), =m (*((unsigned char *)ptep+4))
+ : r (pte) : memory);
#else
*ptep = pte;
#endif
}
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+#if defined(CONFIG_PTE_64BIT)
+ if (unlikely(pte_present(*ptep))) {
+ pte_clear(mm, addr, ptep);
+ smp_wmb();
+ }
+#endif
+ __set_pte_at(mm, addr, ptep, pte);
+}
+
/*
* 2.6 calls this without flushing the TLB entry; this is wrong
* for our hash-based implementation, we fix that up here.
--
1.5.5.1
--
Message: 2
Date: Wed, 17 Sep 2008 18:00:04 -0500
From: Kumar Gala [EMAIL PROTECTED]
Subject: [PATCH v7 3/4] powerpc/fsl-booke: Fixup 64-bit PTE reading
for SMP support
To: linuxppc-dev@ozlabs.org
Message-ID:
[EMAIL PROTECTED]
We need to create a false data dependency to ensure the loads of
the pte are done in the right order.
Signed-off-by: Kumar Gala [EMAIL PROTECTED]
---
