Re: [RFC] Moving toward smarter disabling of FPRs, VRs, and VSRs in the MSR
We can do some VMX testing on existing POWER6 machines. The VSX
instruction set hasn't been fully implemented in GCC yet so we'll need
to wait a bit for that. Does anyone have an idea for a good VMX/Altivec
benchmark?
Note that there are two aspects to the problem:
- Lazy save/restore on SMP. This would avoid both the save and restore
phases, thus is where the most potential gain is to be made. At the
expense of some tricky IPI work when processes migrate between CPUs.
However, it will only be useful -if- a process using FP/VMX/VSX is
interrupted by another process that isn't using them. For example, a
kernel thread. So it's unclear whether that's worth it in practice, ie,
does this happen that often ?
- Always restoring the FP/VMX/VSX state on context switch in rather
than taking a fault. This is reasonably simple, but at the potential
expense of adding the save/restore overhead to applications that only
seldomly use these facilities. (Some heuristics might help here).
However, the question here what do this buy us ?
IE, In the worst case scenario, which is HZ=1000, so every 1ms, the
process would have the overhead of an interrupt to do the restore of the
state. IE. The restore state itself doesn't count since it would be done
either way (at context switch vs. in the unavailable interrupt), so all
we win here is the overhead of the actual interrupt, which is
implemented as a fast interrupt in assembly. So we have what here ? 1000
cycles to be pessimistic ? On a 1Ghz CPU, that is 1/1000 of the time
slice, and both of these are rather pessimistic numbers.
So that leaves us with the possible case of 2 tasks using the facility
and running a fraction of the timeslice each, for example because they
are ping-ponging with each other.
Is that something that happens in practice to make it noticeable ?
I hacked up the below to put stats in /proc/self/sched.
A quick grep through /proc on a rhel5.2 machine (egrep
'(fp_count|switch_count)' /proc/*/sched) shows a few apps use fp a few
dozen times but then stop. This is only init apps like hald, so need to
check some real world apps too.
Ryan: let me know if this allows you to collect some useful stats.
Subject: [PATCH] powerpc: add context switch, fpr vr stats to
/proc/self/sched.
Add a counter for every task switch, fp and vr exception to
/proc/self/sched.
[r...@p5-20-p6-e0 ~]# cat /proc/3422/sched |tail -3
switch_count : 559
fp_count : 317
vr_count :0
[r...@p5-20-p6-e0 ~]#
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/processor.h |3 +++
arch/powerpc/kernel/asm-offsets.c|3 +++
arch/powerpc/kernel/fpu.S|3 +++
arch/powerpc/kernel/process.c|3 +++
arch/powerpc/kernel/setup-common.c | 10 ++
include/linux/seq_file.h | 12
kernel/sched_debug.c | 16
7 files changed, 38 insertions(+), 12 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/processor.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/processor.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/processor.h
@@ -174,11 +174,13 @@ struct thread_struct {
} fpscr;
int fpexc_mode; /* floating-point exception mode */
unsigned intalign_ctl; /* alignment handling control */
+ unsigned long fp_count; /* FP restore count */
#ifdef CONFIG_PPC64
unsigned long start_tb; /* Start purr when proc switched in */
unsigned long accum_tb; /* Total accumilated purr for process */
#endif
unsigned long dabr; /* Data address breakpoint register */
+ unsigned long switch_count; /* switch count */
#ifdef CONFIG_ALTIVEC
/* Complete AltiVec register set */
vector128 vr[32] __attribute__((aligned(16)));
@@ -186,6 +188,7 @@ struct thread_struct {
vector128 vscr __attribute__((aligned(16)));
unsigned long vrsave;
int used_vr;/* set if process has used altivec */
+ unsigned long vr_count; /* VSX restore count */
#endif /* CONFIG_ALTIVEC */
#ifdef CONFIG_VSX
/* VSR status */
Index: linux-2.6-ozlabs/arch/powerpc/kernel/asm-offsets.c
===
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/asm-offsets.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/asm-offsets.c
@@ -74,14 +74,17 @@ int main(void)
DEFINE(KSP, offsetof(struct thread_struct, ksp));
DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
+ DEFINE(THREAD_SWITCHCOUNT, offsetof(struct thread_struct,
[PATCH] powerpc/cell: fix unused variable warning in interrupt.c
arch/powerpc/platforms/cell/interrupt.c: In function 'handle_iic_irq':
arch/powerpc/platforms/cell/interrupt.c:240: warning: unused variable 'cpu'
Signed-off-by: Stephen Rothwell s...@canb.auug.org.au
---
arch/powerpc/platforms/cell/interrupt.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
On Mon, 2 Feb 2009 17:48:17 +1100 Stephen Rothwell s...@canb.auug.org.au
wrote:
Today's linux-next build (powerpc ppc64_defconfig) produced this warning:
arch/powerpc/platforms/cell/interrupt.c: In function 'handle_iic_irq':
arch/powerpc/platforms/cell/interrupt.c:240: warning: unused variable 'cpu'
Caused by commit dee4102a9a5882b4f7d5cc165ba29e8cc63cf92e (sparseirq:
use kstat_irqs_cpu instead).
This patch is relative to next-20090312 and updates the sparseirq tree.
diff --git a/arch/powerpc/platforms/cell/interrupt.c
b/arch/powerpc/platforms/cell/interrupt.c
index 1f0d774..882e470 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -237,8 +237,6 @@ extern int noirqdebug;
static void handle_iic_irq(unsigned int irq, struct irq_desc *desc)
{
- const unsigned int cpu = smp_processor_id();
-
spin_lock(desc-lock);
desc-status = ~(IRQ_REPLAY | IRQ_WAITING);
--
1.6.2
--
Cheers,
Stephen Rothwells...@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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Re: DTS file PCI / i8259 for Xilinx ML510
Original-Nachricht Datum: Sun, 15 Mar 2009 11:43:13 +0100 Von: Gerhard Pircher gerhard_pirc...@gmx.net An: Roderick Colenbrander thunderbir...@gmx.net, linuxppc-dev@ozlabs.org Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 Original-Nachricht Datum: Sun, 15 Mar 2009 09:38:26 +0100 Von: Roderick Colenbrander thunderbir...@gmx.net An: Gerhard Pircher gerhard_pirc...@gmx.net, linuxppc-dev@ozlabs.org Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 At some point in the file they create some (dummy?) pcie section in which they define a uli1575, an isa bus and attached to that isa bus a i8259. Is this the correct way of doing things? The i8259 driver seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined below but how are those mapped to the south bridge? I have seen some code in kernel/isa-bridge, is that code indeed responsible for setting up these ports? Yes, the pcie node is the PCI host bridge node and the uli1571 node acts as PCI2ISA bridge node. AFAIK their ranges properties are parsed by pci_process_bridge_OF_ranges(). IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only for now. The I/O addresses for the i8259 PIC are currently hardcoded and setup (request_resource()) in sysdev/i8259.c. I got the i8259 south bridge working now after adding an io_base_virt offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all the troubles to add ppc32 support to isa-bridge.c? The whole point of the code is basically to remap the io memory to low addresses for these 64-bit ppc systems (mainly freescale boards with a i8259 and pseries systems with a i8259). pci_process_bridge_OF_ranges() should ioremap io_base_virt for you, if your board has only one PCI I/O space. It also sets isa_io_base to io_base_virt on PPC32, but expects that the ISA I/O space is mapped to PCI I/O address 0x0. Isn't that the case for your board? As far as I have seen it is only needed for i8259 interrupt controllers. Personally I think it would be better to pass a io base offset to i8259_setup or so. Or perhaps do some dts file parsing in i8259.c. I'm not sure what the proper layout would be for this in the dts file though. I think adding an io base offset parameter to i8259_setup isn't the right way to do it. I would expect other problems too, if ISA I/O space isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more experienced kernel developer can comment on this? I'm now back behind my ML510 board and have been doing some tests. As I mentioned before I was doing inb(isa_io_base + port) / outb(val, isa_io_base + port) which worked fine. As far as I see it the problem is the definition of inb/outb on ppc32 they don't take isa_io_base into account. They are: __do_in_asm(_rec_inb, lbzx) __do_out_asm(_rec_outb, stbx) #define __do_outb(val, port)_rec_outb(val, port) #define __do_inb(port) _rec_inb(port) While on 64-bit ppc they are: #define __do_outb(val, port)writeb(val,(PCI_IO_ADDR)_IO_BASE+port); #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); (On ppc32 _IO_BASE is isa_io_base but on 64-bit it is set to pci_io_base) Am I correct that inb/outb are broken on ppc32? If so what is the right way to fix them? Regards, Roderick -- Pt! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger01 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 0/3] PowerPC: MPC85xx: TQM85xx: dts and defconfig fixes
The following patch series fixes some issues with the DTS files of the TQM85xx modules and the defconfig for the TQM8548 modules. The patches are against the next branch of Kumar's powerpc GIT tree. Wolfgang. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/3] PowerPC: MPC85xx: TQM85xx: correct address of LM75 I2C device nodes
Commit 0f73a449a649acfca91404a98a35353a618b9555 added I2C device nodes
for the LM75 thermal sensor on the TQM85xx modules, unfortunately with
the wrong I2C address. The LM75s are located at address 0x48.
Signed-off-by: Wolfgang Grandegger w...@grandegger.com
---
arch/powerpc/boot/dts/tqm8540.dts |4 ++--
arch/powerpc/boot/dts/tqm8541.dts |4 ++--
arch/powerpc/boot/dts/tqm8548-bigflash.dts |4 ++--
arch/powerpc/boot/dts/tqm8548.dts |4 ++--
arch/powerpc/boot/dts/tqm8555.dts |4 ++--
arch/powerpc/boot/dts/tqm8560.dts |4 ++--
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/boot/dts/tqm8540.dts
b/arch/powerpc/boot/dts/tqm8540.dts
index 39e55ab..da137d8 100644
--- a/arch/powerpc/boot/dts/tqm8540.dts
+++ b/arch/powerpc/boot/dts/tqm8540.dts
@@ -84,9 +84,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
diff --git a/arch/powerpc/boot/dts/tqm8541.dts
b/arch/powerpc/boot/dts/tqm8541.dts
index 58ae8bc..b25fc4c 100644
--- a/arch/powerpc/boot/dts/tqm8541.dts
+++ b/arch/powerpc/boot/dts/tqm8541.dts
@@ -83,9 +83,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index bff380a..dd43dbe 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -85,9 +85,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
diff --git a/arch/powerpc/boot/dts/tqm8548.dts
b/arch/powerpc/boot/dts/tqm8548.dts
index 112ac90..b949a8c 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -85,9 +85,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
diff --git a/arch/powerpc/boot/dts/tqm8555.dts
b/arch/powerpc/boot/dts/tqm8555.dts
index 4b7da89..fd3777e 100644
--- a/arch/powerpc/boot/dts/tqm8555.dts
+++ b/arch/powerpc/boot/dts/tqm8555.dts
@@ -83,9 +83,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
diff --git a/arch/powerpc/boot/dts/tqm8560.dts
b/arch/powerpc/boot/dts/tqm8560.dts
index 3fa552f..89a7beb 100644
--- a/arch/powerpc/boot/dts/tqm8560.dts
+++ b/arch/powerpc/boot/dts/tqm8560.dts
@@ -85,9 +85,9 @@
interrupt-parent = mpic;
dfsrr;
- d...@50 {
+ d...@48 {
compatible = national,lm75;
- reg = 0x50;
+ reg = 0x48;
};
r...@68 {
--
1.6.0.6
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[PATCH 2/3] PowerPC: MPC85xx: TQM8548: use proper phy-handles for enet2 and enet3
For enet2 and enet3 the wrong phy-handles have been used in DTS files
of the TQM8548 modules.
Signed-off-by: Wolfgang Grandegger w...@grandegger.com
---
arch/powerpc/boot/dts/tqm8548-bigflash.dts |4 ++--
arch/powerpc/boot/dts/tqm8548.dts |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
index dd43dbe..29a2b6f 100644
--- a/arch/powerpc/boot/dts/tqm8548-bigflash.dts
+++ b/arch/powerpc/boot/dts/tqm8548-bigflash.dts
@@ -262,7 +262,7 @@
interrupts = 31 2 32 2 33 2;
interrupt-parent = mpic;
tbi-handle = tbi2;
- phy-handle = phy3;
+ phy-handle = phy4;
};
enet3: ether...@27000 {
@@ -275,7 +275,7 @@
interrupts = 37 2 38 2 39 2;
interrupt-parent = mpic;
tbi-handle = tbi3;
- phy-handle = phy4;
+ phy-handle = phy5;
};
serial0: ser...@4500 {
diff --git a/arch/powerpc/boot/dts/tqm8548.dts
b/arch/powerpc/boot/dts/tqm8548.dts
index b949a8c..81d3fbb 100644
--- a/arch/powerpc/boot/dts/tqm8548.dts
+++ b/arch/powerpc/boot/dts/tqm8548.dts
@@ -262,7 +262,7 @@
interrupts = 31 2 32 2 33 2;
interrupt-parent = mpic;
tbi-handle = tbi2;
- phy-handle = phy3;
+ phy-handle = phy4;
};
enet3: ether...@27000 {
@@ -275,7 +275,7 @@
interrupts = 37 2 38 2 39 2;
interrupt-parent = mpic;
tbi-handle = tbi3;
- phy-handle = phy4;
+ phy-handle = phy5;
};
serial0: ser...@4500 {
--
1.6.0.6
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[PATCH 3/3] PowerPC: MPC85xx: TQM8548: update defconfig
Enable highmem support for the TQM8548-AG modules and NAND support for the TQM8548-BE modules. Furthermore disable USB, Wireless and IDE support because it's not available on the STK85xx starter kit. Signed-off-by: Wolfgang Grandegger w...@grandegger.com --- arch/powerpc/configs/85xx/tqm8548_defconfig | 164 --- 1 files changed, 48 insertions(+), 116 deletions(-) diff --git a/arch/powerpc/configs/85xx/tqm8548_defconfig b/arch/powerpc/configs/85xx/tqm8548_defconfig index 0bc4597..43030fe 100644 --- a/arch/powerpc/configs/85xx/tqm8548_defconfig +++ b/arch/powerpc/configs/85xx/tqm8548_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.29-rc2 -# Mon Jan 26 15:36:20 2009 +# Linux kernel version: 2.6.29-rc7 +# Mon Mar 16 09:03:28 2009 # # CONFIG_PPC64 is not set @@ -22,6 +22,7 @@ CONFIG_FSL_EMB_PERFMON=y # CONFIG_PHYS_64BIT is not set CONFIG_SPE=y CONFIG_PPC_MMU_NOHASH=y +CONFIG_PPC_BOOK3E_MMU=y # CONFIG_PPC_MM_SLICES is not set # CONFIG_SMP is not set CONFIG_PPC32=y @@ -75,6 +76,15 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 CONFIG_GROUP_SCHED=y @@ -152,11 +162,6 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED=anticipatory -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_FREEZER is not set # @@ -202,7 +207,7 @@ CONFIG_MPIC=y # # Kernel options # -# CONFIG_HIGHMEM is not set +CONFIG_HIGHMEM=y CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -244,6 +249,7 @@ CONFIG_UNEVICTABLE_LRU=y CONFIG_PPC_4K_PAGES=y # CONFIG_PPC_16K_PAGES is not set # CONFIG_PPC_64K_PAGES is not set +# CONFIG_PPC_256K_PAGES is not set CONFIG_FORCE_MAX_ZONEORDER=11 CONFIG_PROC_DEVICETREE=y # CONFIG_CMDLINE_BOOL is not set @@ -259,6 +265,7 @@ CONFIG_ZONE_DMA=y CONFIG_PPC_INDIRECT_PCI=y CONFIG_FSL_SOC=y CONFIG_FSL_PCI=y +CONFIG_FSL_LBC=y CONFIG_PPC_PCI_CHOICE=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y @@ -284,10 +291,11 @@ CONFIG_ARCH_SUPPORTS_MSI=y # Default settings for advanced configuration options are used # CONFIG_LOWMEM_SIZE=0x3000 +CONFIG_LOWMEM_CAM_NUM=3 CONFIG_PAGE_OFFSET=0xc000 CONFIG_KERNEL_START=0xc000 CONFIG_PHYSICAL_START=0x -CONFIG_PHYSICAL_ALIGN=0x1000 +CONFIG_PHYSICAL_ALIGN=0x0400 CONFIG_TASK_SIZE=0xc000 CONFIG_NET=y @@ -363,12 +371,7 @@ CONFIG_DEFAULT_TCP_CONG=cubic # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_PHONET is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -# CONFIG_WIRELESS_EXT is not set -# CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set +# CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -471,27 +474,18 @@ CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_NANDSIM is not set # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_NAND_FSL_ELBC is not set -# CONFIG_MTD_NAND_FSL_UPM is not set +CONFIG_MTD_NAND_FSL_UPM=y # CONFIG_MTD_ONENAND is not set # # LPDDR flash memory drivers # # CONFIG_MTD_LPDDR is not set -# CONFIG_MTD_QINFO_PROBE is not set # # UBI - Unsorted block images # -CONFIG_MTD_UBI=m -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -CONFIG_MTD_UBI_BEB_RESERVE=1 -# CONFIG_MTD_UBI_GLUEBI is not set - -# -# UBI debugging options -# -# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI is not set CONFIG_OF_DEVICE=y CONFIG_OF_I2C=y # CONFIG_PARPORT is not set @@ -515,69 +509,21 @@ CONFIG_BLK_DEV_RAM_SIZE=32768 # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set -# CONFIG_EEPROM_93CX6 is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y -CONFIG_IDE=y - -# -# Please see Documentation/ide/ide.txt for help/info on IDE drives -# -CONFIG_IDE_TIMINGS=y -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_IDE_GD=y -CONFIG_IDE_GD_ATA=y -# CONFIG_IDE_GD_ATAPI is not set -# CONFIG_BLK_DEV_IDECD is not set -# CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_IDE_TASK_IOCTL is not set -CONFIG_IDE_PROC_FS=y - -# -# IDE chipset support/bugfixes -# -# CONFIG_BLK_DEV_PLATFORM is not set -CONFIG_BLK_DEV_IDEDMA_SFF=y - -# -# PCI IDE chipsets support -# -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_PCIBUS_ORDER=y -#
Re: DTS file PCI / i8259 for Xilinx ML510
Original-Nachricht Datum: Mon, 16 Mar 2009 09:18:54 +0100 Von: Roderick Colenbrander thunderbir...@gmx.net An: Gerhard Pircher gerhard_pirc...@gmx.net, linuxppc-dev@ozlabs.org Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 Original-Nachricht Datum: Sun, 15 Mar 2009 11:43:13 +0100 Von: Gerhard Pircher gerhard_pirc...@gmx.net An: Roderick Colenbrander thunderbir...@gmx.net, linuxppc-dev@ozlabs.org Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 Original-Nachricht Datum: Sun, 15 Mar 2009 09:38:26 +0100 Von: Roderick Colenbrander thunderbir...@gmx.net An: Gerhard Pircher gerhard_pirc...@gmx.net, linuxppc-dev@ozlabs.org Betreff: Re: DTS file PCI / i8259 for Xilinx ML510 At some point in the file they create some (dummy?) pcie section in which they define a uli1575, an isa bus and attached to that isa bus a i8259. Is this the correct way of doing things? The i8259 driver seems to use io ports 0x20-21/0xa0-0xa1/0x4d0-0x4d1 those are also defined below but how are those mapped to the south bridge? I have seen some code in kernel/isa-bridge, is that code indeed responsible for setting up these ports? Yes, the pcie node is the PCI host bridge node and the uli1571 node acts as PCI2ISA bridge node. AFAIK their ranges properties are parsed by pci_process_bridge_OF_ranges(). IIRC the code in kernel/isa-bridge is used for 64bit PPC machines only for now. The I/O addresses for the i8259 PIC are currently hardcoded and setup (request_resource()) in sysdev/i8259.c. I got the i8259 south bridge working now after adding an io_base_virt offset to all inb/outb lines in sysdev/i8259.c. Would it be worth all the troubles to add ppc32 support to isa-bridge.c? The whole point of the code is basically to remap the io memory to low addresses for these 64-bit ppc systems (mainly freescale boards with a i8259 and pseries systems with a i8259). pci_process_bridge_OF_ranges() should ioremap io_base_virt for you, if your board has only one PCI I/O space. It also sets isa_io_base to io_base_virt on PPC32, but expects that the ISA I/O space is mapped to PCI I/O address 0x0. Isn't that the case for your board? As far as I have seen it is only needed for i8259 interrupt controllers. Personally I think it would be better to pass a io base offset to i8259_setup or so. Or perhaps do some dts file parsing in i8259.c. I'm not sure what the proper layout would be for this in the dts file though. I think adding an io base offset parameter to i8259_setup isn't the right way to do it. I would expect other problems too, if ISA I/O space isn't mapped 1:1 to PCI I/O space on a PPC32 system. Maybe a more experienced kernel developer can comment on this? I'm now back behind my ML510 board and have been doing some tests. As I mentioned before I was doing inb(isa_io_base + port) / outb(val, isa_io_base + port) which worked fine. As far as I see it the problem is the definition of inb/outb on ppc32 they don't take isa_io_base into account. They are: __do_in_asm(_rec_inb, lbzx) __do_out_asm(_rec_outb, stbx) #define __do_outb(val, port)_rec_outb(val, port) #define __do_inb(port) _rec_inb(port) While on 64-bit ppc they are: #define __do_outb(val, port)writeb(val,(PCI_IO_ADDR)_IO_BASE+port); #define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port); (On ppc32 _IO_BASE is isa_io_base but on 64-bit it is set to pci_io_base) Am I correct that inb/outb are broken on ppc32? If so what is the right way to fix them? Regards, Roderick I just talked about this on IRC with Benjamin Herrenschmidt and I misunderstood the inb/outb command. the commands are using _IO_PORTS and I must be doing something wrong. Roderick -- Nur bis 16.03.! DSL-Komplettanschluss inkl. WLAN-Modem für nur 17,95 ¿/mtl. + 1 Monat gratis!* http://dsl.gmx.de/?ac=OM.AD.PD003K11308T4569a ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH] powerpc: Enable CPU_FTR_NEED_COHERENT for MPC52xx
BestComm, a DMA engine in MPC52xx SoC, requires snooping when CPU caches are enabled to work properly. Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code'. Signed-off-by: Piotr Ziecik ko...@semihalf.com --- This patch was succesfully tested on our MPC5200-based. Ben, Gerhard could you ack this patch, as it implements your suggestion. arch/powerpc/include/asm/cputable.h |4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index b18358f..22dc2d8 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -241,9 +241,11 @@ extern const char *powerpc_base_platform; /* We need to mark all pages as being coherent if we're SMP or we have a * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II * require it for PCI streaming/prefetch to work properly. + * This is also required by 52xx family. */ #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ - || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) + || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ + || defined(CONFIG_PPC_MPC52xx) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT #else #define CPU_FTR_COMMON 0 -- 1.6.0.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 0/2 v2] powerpc/86xx: Board support for GE Fanuc PPC9A
The following series implements basic support for the GE Fanuc PPC9A, a 6U single board computer, based on the Freescale MPC8641D. This series provides: - The ability to boot the board with a serial console. - Ethernet support. - Sata and USB. - Support for one of the 2 available watchdog timers. - Support for the onboard temperature sensors - Support for the onboard RTC v2: Corrections to DTS as suggested by David Gibson Martyn ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
v2: Corrections to DTS (soc compatible, remove device_type) as suggesed by
David Gibson.
arch/powerpc/boot/dts/gef_ppc9a.dts | 362 +++
arch/powerpc/platforms/86xx/Kconfig | 10 +
arch/powerpc/platforms/86xx/Makefile|1
arch/powerpc/platforms/86xx/gef_ppc9a.c | 223 +++
drivers/watchdog/Kconfig|2
5 files changed, 596 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts
b/arch/powerpc/boot/dts/gef_ppc9a.dts
new file mode 100644
index 000..055f0b7
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -0,0 +1,362 @@
+/*
+ * GE Fanuc PPC9A Device Tree Source
+ *
+ * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: SBS CM6 Device Tree Source
+ * Copyright 2007 SBS Technologies GmbH Co. KG
+ * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
+ * Copyright 2006 Freescale Semiconductor Inc.
+ */
+
+/*
+ * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
+ */
+
+/dts-v1/;
+
+/ {
+ model = GEF_PPC9A;
+ compatible = gef,ppc9a;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ ethernet0 = enet0;
+ ethernet1 = enet1;
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ PowerPC,8...@1 {
+ device_type = cpu;
+ reg = 1;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 32768; // L1, 32K
+ i-cache-size = 32768; // L1, 32K
+ timebase-frequency = 0; // From uboot
+ bus-frequency = 0;// From uboot
+ clock-frequency = 0; // From uboot
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x4000; // set by uboot
+ };
+
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
+ reg = 0x0 0x0 0x100;
+ bank-width = 4;
+ device-width = 2;
+ #address-cells = 1;
+ #size-cells = 1;
+ partit...@0 {
+ label = firmware;
+ reg = 0x0 0x100;
+ read-only;
+ };
+ };
+ */
+
+ fl...@1,0 {
+ compatible = cfi-flash;
+ reg = 0x1 0x0 0x800;
+ bank-width = 4;
+ device-width = 2;
+
[PATCH v2 2/2] powerpc/86xx: Default configuration for GE Fanuc's PPC9A
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC MPC8641D). This is the default config file for GE Fanuc's PPC9A, a 6U single board computer, based on Freescale's MPC8641D. Signed-off-by: Martyn Welch martyn.we...@gefanuc.com --- arch/powerpc/configs/86xx/gef_ppc9a_defconfig | 1889 + 1 files changed, 1889 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig new file mode 100644 index 000..df2c163 --- /dev/null +++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig @@ -0,0 +1,1889 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Fri Mar 13 15:36:11 2009 +# +# CONFIG_PPC64 is not set + +# +# Processor support +# +CONFIG_6xx=y +# CONFIG_PPC_85xx is not set +# CONFIG_PPC_8xx is not set +# CONFIG_40x is not set +# CONFIG_44x is not set +# CONFIG_E200 is not set +CONFIG_PPC_FPU=y +# CONFIG_PHYS_64BIT is not set +CONFIG_ALTIVEC=y +CONFIG_PPC_STD_MMU=y +CONFIG_PPC_STD_MMU_32=y +# CONFIG_PPC_MM_SLICES is not set +CONFIG_SMP=y +CONFIG_NR_CPUS=2 +CONFIG_PPC32=y +CONFIG_WORD_SIZE=32 +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_MMU=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set +CONFIG_IRQ_PER_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_ARCH_HAS_ILOG2_U32=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_NO_VIRT_TO_BUS is not set +CONFIG_PPC=y +CONFIG_EARLY_PRINTK=y +CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_PPC_OF=y +CONFIG_OF=y +CONFIG_PPC_UDBG_16550=y +CONFIG_GENERIC_TBSYNC=y +CONFIG_AUDIT_ARCH=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFAULT_UIMAGE=y +# CONFIG_PPC_DCR_NATIVE is not set +# CONFIG_PPC_DCR_MMIO is not set +CONFIG_DEFCONFIG_LIST=/lib/modules/$UNAME_RELEASE/.config + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION= +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE= +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED=cfq +# CONFIG_FREEZER is not set + +# +# Platform support +# +CONFIG_PPC_MULTIPLATFORM=y +CONFIG_CLASSIC32=y +# CONFIG_PPC_CHRP is not set +# CONFIG_MPC5121_ADS is not set +# CONFIG_MPC5121_GENERIC is not set +# CONFIG_PPC_MPC52xx is not set +# CONFIG_PPC_PMAC is not set +# CONFIG_PPC_CELL is not set +#
Re: [RFC] [PATCH v2] MPC5121 TLB errata workaround
On Friday 13 March 2009 16:23:15 Kumar Gala wrote: [...] This errata impacts a number of cores and so we should make this a CPU feature fixup rather than #ifdef code. It should impact only MPC5121e and probably MPC5123, but according to Freescale no other processors that use this core... Not sure about that.. But the errata impacts all e300c2/c3/c4 parts. Can someone please check if this is true? There should be errata's for all other parts that use one of these cores then. Anyway, I'll try to investigate about how to write a CPU feature fixup, I've never done that before (If you could give me a hint?) I've posted a patch that should add the CPU feature support. This is only compile tested. You'll need to try it out on real HW :) That's a problem right now: The only useable kernel for the MPC5121e is the one on the 'ads5121' head from denx, and that is version 2.6.24.6. Your patch (v3) does not apply to that kernel, so I would have to change a few things before I can actually try it out: #define CPU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x0001) In 2.6.24.6 this constant is used for something else. Would it be possible to pick anotherone, in order to make dual-kernel patches easier to maintain for now? + mfspr r3,SPRN_DMISS + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ + lis r2,l...@ha /* Search index in lrw[] */ + addir2,r2,l...@l + tophys(r2,r2) + lwzxr1,r3,r2 /* Get item from lrw[] */ + cmpwi 0,r1,0 /* Was it way 0 last time? */ Why not use a bit vector since we only need one bit of information. Additionally we can use a single SPRG at that point instead to keep track of the LRU information. Sounds interesting. I am just learning my first steps in powerpc- assembly, so please forgive if this is a little inefficient still. I'll try again next week. Not at all. This has been on my todo list just not high priority so I'm happy to get someone to work on it and have setup already that can show perf differences. On your Todo list? Does that mean you know about another processor that has the same problem? I might work up a newer version w/the SPRG idea if I'm feeling up to it. Do you mean it is possible to just pick an SPRG that will be used only by this handler and make sure no other piece of software will touch it? Would be great. Is there a way of knowing which SPRG's are used by linux? I read in the e300 core-RM, that SPRG4...7 are unique to this iteration of the G2 anyway, so one of those might be a good candidate? I have quite a lot of work pressure right now, and unfortunately very little time I can dedicate to this. Given the fact that I also cannot test patches for mainline, because MPC5121e support is just not complete enough yet, do you agree if I modify my own patch (with ifdef's instead of CPU_FTR...) to give you feedback on performance impacts, while you implement it as CPU_FTR afterwards for mainline? That way I can avoid doing double work, and spend more time on testing it actually If you agree, I'll start hacking away on the SPRG version immediately :-) Best regards, -- David Jander Protonic Holland. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC] Moving toward smarter disabling of FPRs, VRs, and VSRs in the MSR
On Sat, Mar 14, 2009 at 02:49:02PM +0100, Segher Boessenkool wrote: Another option might be simply to say that if an app has used FP, VMX or VSX -once-, then it's likely to do it again and just keep re-enabling it :-) I'm serious here, do we know that many cases where these things are used seldomly once in a while ? For FP, I believe many apps use it only sporadically. But for VMX and VSX, yeah, it might well be optimal to keep it enabled all the time. Someone should do some profiling... I concur. I have some apps who are mostly integer but from time to time perform some statistics which are so much easier to write declaring a few double variables. On the other hand when you start with vector instructions, it often means that you are going to use them for a while. This said, I'm not opposed to an heuristic like: if the app has used the FP/VMX/VSX registers systematically after having been scheduled a few times (2 for VMX/VSX, 5 for FP), load the corresponding registers on every schedule for the next n schedules, where n would be about 20 for VSX/VMX, and perhaps only 5 for FP. Gabriel ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC] [PATCH v2] MPC5121 TLB errata workaround
On Mar 16, 2009, at 5:44 AM, David Jander wrote: On Friday 13 March 2009 16:23:15 Kumar Gala wrote: [...] This errata impacts a number of cores and so we should make this a CPU feature fixup rather than #ifdef code. It should impact only MPC5121e and probably MPC5123, but according to Freescale no other processors that use this core... Not sure about that.. But the errata impacts all e300c2/c3/c4 parts. Can someone please check if this is true? There should be errata's for all other parts that use one of these cores then. Anyway, I'll try to investigate about how to write a CPU feature fixup, I've never done that before (If you could give me a hint?) I've posted a patch that should add the CPU feature support. This is only compile tested. You'll need to try it out on real HW :) That's a problem right now: The only useable kernel for the MPC5121e is the one on the 'ads5121' head from denx, and that is version 2.6.24.6. Your patch (v3) does not apply to that kernel, so I would have to change a few things before I can actually try it out: #define CPU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x0001) In 2.6.24.6 this constant is used for something else. Would it be possible to pick anotherone, in order to make dual-kernel patches easier to maintain for now? + mfspr r3,SPRN_DMISS + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ + lis r2,l...@ha /* Search index in lrw[] */ + addir2,r2,l...@l + tophys(r2,r2) + lwzxr1,r3,r2 /* Get item from lrw[] */ + cmpwi 0,r1,0 /* Was it way 0 last time? */ Why not use a bit vector since we only need one bit of information. Additionally we can use a single SPRG at that point instead to keep track of the LRU information. Sounds interesting. I am just learning my first steps in powerpc- assembly, so please forgive if this is a little inefficient still. I'll try again next week. Not at all. This has been on my todo list just not high priority so I'm happy to get someone to work on it and have setup already that can show perf differences. On your Todo list? Does that mean you know about another processor that has the same problem? Yes, I work at Freescale and am aware that the errata impacts all c2/ c3/c4 class chips. I might work up a newer version w/the SPRG idea if I'm feeling up to it. Do you mean it is possible to just pick an SPRG that will be used only by this handler and make sure no other piece of software will touch it? Would be great. Is there a way of knowing which SPRG's are used by linux? I read in the e300 core-RM, that SPRG4...7 are unique to this iteration of the G2 anyway, so one of those might be a good candidate? I was thinking one from SPRG4..7 should be fine since Linux doesn't use them for anything. We should try this w/SPRG w/memory to see if we notice any perf difference. I have quite a lot of work pressure right now, and unfortunately very little time I can dedicate to this. Given the fact that I also cannot test patches for mainline, because MPC5121e support is just not complete enough yet, do you agree if I modify my own patch (with ifdef's instead of CPU_FTR...) to give you feedback on performance impacts, while you implement it as CPU_FTR afterwards for mainline? That way I can avoid doing double work, and spend more time on testing it actually If you agree, I'll start hacking away on the SPRG version immediately :-) I think that's fine. The CPU feature bit is minor to deal with and Ben has stated he wants it to be a MMU feature which is something new as well. It should be easy to convert the CPU_FTR wrapping into #ifdefs instead. I have a few other patches related to this that I am not sure if they will apply to the 2.6.24.6 tree you are based on. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 1/3] powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW TLB load machines
Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing it out before we setup the SW TLB. Today all the SW TLB machines (603/e300) that we support are non-SMP, however there are some errata on some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- Note: I've only compiled tested this and not booted on real HW. - k arch/powerpc/kernel/head_32.S |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index f8c2e6b..6da5505 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -514,7 +514,7 @@ InstructionTLBMiss: and r1,r1,r2/* writable if _RW and _DIRTY */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ + ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_IMISS @@ -588,7 +588,7 @@ DataLoadTLBMiss: and r1,r1,r2/* writable if _RW and _DIRTY */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ + ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS @@ -656,7 +656,7 @@ DataStoreTLBMiss: stw r3,0(r2)/* update PTE (accessed/dirty bits) */ /* Convert linux-style PTE to low word of PPC-style PTE */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - li r1,0xe15/* clear out reserved bits and M */ + li r1,0xe05/* clear out reserved bits PP lsb */ andcr1,r3,r1/* PP = user? 2: 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS -- 1.5.6.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 2/3] powerpc/mm: Remove unused register usage in SW TLB miss handling
Long ago we had some code that actually used the CTR in the SW TLB miss handlers (603/e300). Since we don't use it no reason to waste cycles saving it off and restoring it (we actually didn't restore it in the fast path case). Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- Note: I've only compiled tested this and not booted on real HW. - k arch/powerpc/kernel/head_32.S | 11 +++ 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 6da5505..aafb469 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -475,12 +475,11 @@ SystemCall: . = 0x1000 InstructionTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_IMISS lis r1,page_off...@h/* check if kernel address */ @@ -528,7 +527,6 @@ InstructionAddressInvalid: addis r1,r1,0x2000 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ - mtctr r0 /* Restore CTR */ andi. r2,r3,0x/* Clear upper bits of SRR1 */ or r2,r2,r1 mtspr SPRN_SRR1,r2 @@ -549,12 +547,11 @@ InstructionAddressInvalid: . = 0x1100 DataLoadTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ @@ -601,7 +598,6 @@ DataAddressInvalid: rlwinm r1,r3,9,6,6 /* Get load/store bit */ addis r1,r1,0x2000 mtspr SPRN_DSISR,r1 - mtctr r0 /* Restore CTR */ andi. r2,r3,0x/* Clear upper bits of SRR1 */ mtspr SPRN_SRR1,r2 mfspr r1,SPRN_DMISS /* Get failing address */ @@ -621,12 +617,11 @@ DataAddressInvalid: . = 0x1200 DataStoreTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ -- 1.5.6.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFC][PATCH 3/3] powerpc/mm: Used free register to save a few cycles in SW TLB miss handling
Now that r0 is free we can keep the value of I/DMISS in r3 and not reload it before doing the tlbli/d. This saves us a few cycles in the fast path case. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- There might be better uses of the free r0 to save more cycles in these code paths. If anyone has suggestions I'm willing to look at them. - k arch/powerpc/kernel/head_32.S | 51 +++- 1 files changed, 24 insertions(+), 27 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index aafb469..b6c5955 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -498,25 +498,24 @@ InstructionTLBMiss: rlwinm. r2,r2,0,0,19/* extract address of pte page */ beq-InstructionAddressInvalid /* return if no mapping */ rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2)/* get linux-style pte */ - andc. r1,r1,r3/* check access ~permission */ + lwz r0,0(r2)/* get linux-style pte */ + andc. r1,r1,r0/* check access ~permission */ bne-InstructionAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ + ori r0,r0,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ /* * NOTE! We are assuming this is not an SMP system, otherwise * we would need to update the pte atomically with lwarx/stwcx. */ - stw r3,0(r2)/* update PTE (accessed bit) */ + stw r0,0(r2)/* update PTE (accessed bit) */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW - PP lsb */ - rlwinm r2,r3,32-7,31,31/* _PAGE_DIRTY - PP lsb */ + rlwinm r1,r0,32-10,31,31 /* _PAGE_RW - PP lsb */ + rlwinm r2,r0,32-7,31,31/* _PAGE_DIRTY - PP lsb */ and r1,r1,r2/* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ + rlwimi r0,r0,32-1,30,30/* _PAGE_USER - PP msb */ + rlwimi r0,r0,32-1,31,31/* _PAGE_USER - PP lsb */ ori r1,r1,0xe04 /* clear out reserved bits */ - andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ + andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 - mfspr r3,SPRN_IMISS tlbli r3 mfspr r3,SPRN_SRR1/* Need to restore CR0 */ mtcrf 0x80,r3 @@ -570,25 +569,24 @@ DataLoadTLBMiss: rlwinm. r2,r2,0,0,19/* extract address of pte page */ beq-DataAddressInvalid /* return if no mapping */ rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2)/* get linux-style pte */ - andc. r1,r1,r3/* check access ~permission */ + lwz r0,0(r2)/* get linux-style pte */ + andc. r1,r1,r0/* check access ~permission */ bne-DataAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ + ori r0,r0,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ /* * NOTE! We are assuming this is not an SMP system, otherwise * we would need to update the pte atomically with lwarx/stwcx. */ - stw r3,0(r2)/* update PTE (accessed bit) */ + stw r0,0(r2)/* update PTE (accessed bit) */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW - PP lsb */ - rlwinm r2,r3,32-7,31,31/* _PAGE_DIRTY - PP lsb */ + rlwinm r1,r0,32-10,31,31 /* _PAGE_RW - PP lsb */ + rlwinm r2,r0,32-7,31,31/* _PAGE_DIRTY - PP lsb */ and r1,r1,r2/* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ + rlwimi r0,r0,32-1,30,30/* _PAGE_USER - PP msb */ + rlwimi r0,r0,32-1,31,31/* _PAGE_USER - PP lsb */ ori r1,r1,0xe04 /* clear out reserved bits */ - andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ + andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 - mfspr r3,SPRN_DMISS tlbld r3 mfspr r3,SPRN_SRR1/* Need to restore CR0 */ mtcrf 0x80,r3 @@ -640,21 +638,20 @@ DataStoreTLBMiss: rlwinm. r2,r2,0,0,19/*
Re: [RFC][PATCH v3] powerpc: e300c2/c3/c4 TLB errata workaround
On Mar 13, 2009, at 5:06 PM, Kumar Gala wrote:
On Mar 13, 2009, at 4:26 PM, Benjamin Herrenschmidt wrote:
+BEGIN_FTR_SECTION
+ b TlbWo/* Code for TLB-errata workaround doesn't fit
here */
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
+RFTlbWo:
Can you use nicer label names ? :-)
Also, that's a lot of code for such a hot path...
Cheers,
Ben.
The code needs reworking. However, we are doing SW LRU, not sure
how we reduce this in the hot path.
Ben, David,
Here's my attempt at reworking the code to use an SPRG, remove
branches, optimize it down, etc. I haven't validated that this is
even correct. It should be easy to replace the m{f,t}spr SPRG w/lwz/
stw if we want to keep the LRU state in memory instead.
Ben, do you think we can optimize this further with some random LRU
selection?
mtspr SPRN_RPA,r1
mfspr r2,SPRN_SRR1/* Need to restore CR0 */
mtcrf 0x80,r2
#if 1
li r0,1
mfspr r1,SPRN_SPRG4 /* could replace w/lwz
r1,sw_way_...@l(0) */
rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */
slw r0,r0,r3
xor r1,r0,r1
srw r0,r1,r3
mtspr SPRN_SPRG4,r1 /* could replace w/stw
r1,sw_way_...@l(0) */
rlwimi r2,r0,31-14,14,14
#endif
tlbld r3
rfi
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[PATCH] Fix RTAS watchdog driver temperature read functionality
Using the RTAS watchdog driver to read out the temperature crashes on a PXCAB: Unable to handle kernel paging request for data at address 0xfe347b50 Faulting instruction address: 0xc001af64 Oops: Kernel access of bad area, sig: 11 [#1] This (removing (void *)__pa) fixes it. Signed-off-by: Adrian Reber adr...@lisas.de --- drivers/watchdog/wdrtas.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) Fix for: Unable to handle kernel paging request for data at address 0xfe347b50 Faulting instruction address: 0xc001af64 Oops: Kernel access of bad area, sig: 11 [#1] SMP NR_CPUS=4 NUMA Cell Modules linked in: NIP: c001af64 LR: c001af28 CTR: c0281888 REGS: c000fe3477a0 TRAP: 0300 Not tainted (2.6.29-rc6-11955-g2450cf5) MSR: 90001032 ME,IR,DR CR: 22000422 XER: DAR: fe347b50, DSISR: 4200 TASK = c000fe4886f0[1184] 'a.out' THREAD: c000fe344000 CPU: 1 GPR00: 002a c000fe347a20 c0ab2160 c0007bc0 GPR04: 22000422 c0281888 041e6138 GPR08: 0008 c0b23ce4 0008 fe347b54 GPR12: 82000424 c0b23680 c03b37b0 c0441620 GPR16: c04412e0 c0441130 0e154ec8 c03b4580 GPR20: 100a0370 100a0390 c0b23cc8 GPR24: 0001 0002 fe347b50 0002 GPR28: 0010 c0b23cb0 c0a59588 0002 NIP [c001af64] .rtas_call+0x1ac/0x1f8 LR [c001af28] .rtas_call+0x170/0x1f8 Call Trace: [c000fe347a20] [c001af28] .rtas_call+0x170/0x1f8 (unreliable) [c000fe347ae0] [c02812e8] .wdrtas_get_temperature+0x48/0xa8 [c000fe347b70] [c0281948] .wdrtas_ioctl+0xc0/0x300 [c000fe347c00] [c00f58a4] .vfs_ioctl+0x54/0x138 [c000fe347c90] [c00f5a20] .do_vfs_ioctl+0x98/0x738 [c000fe347d80] [c00f6114] .SyS_ioctl+0x54/0xc8 [c000fe347e30] [c00074b4] syscall_exit+0x0/0x40 Instruction dump: 2fba 419e0034 3939fffe 3944 79290020 39290002 79281764 e93d0070 7d7a5214 7c09502e 394a0004 7faa4000 900bfffc 409effe8 e93d0070 ebe90002 ---[ end trace 084fb7ab3feda750 ]--- diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c index 5d3b1a8..30ee1f2 100644 --- a/drivers/watchdog/wdrtas.c +++ b/drivers/watchdog/wdrtas.c @@ -218,8 +218,7 @@ static int wdrtas_get_temperature(void) int temperature = 0; result = rtas_call(wdrtas_token_get_sensor_state, 2, 2, - (void *)__pa(temperature), - WDRTAS_THERMAL_SENSOR, 0); + temperature, WDRTAS_THERMAL_SENSOR, 0); if (result 0) printk(KERN_WARNING wdrtas: reading the thermal sensor -- 1.5.6.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFC][PATCH v4] powerpc/mm: e300c2/c3/c4 TLB errata workaround
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Based on patch from David Jander da...@protonic.nl
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/mmu.h |6 ++
arch/powerpc/kernel/cputable.c |9 ++---
arch/powerpc/kernel/head_32.S | 32
3 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 10476a8..cbf1543 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -46,6 +46,12 @@
*/
#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x0010)
+/* This indicates that the processor doesn't handle way selection
+ * properly and needs SW to track and update the LRU state. This
+ * is specific to an errata on e300c2/c3/c4 class parts
+ */
+#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x0020)
+
#ifndef __ASSEMBLY__
#include asm/cputable.h
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index ccea243..cd1b687 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1090,7 +1090,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c2,
.cpu_features = CPU_FTRS_E300C2,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
@@ -1103,7 +1104,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c3,
.cpu_features = CPU_FTRS_E300,
.cpu_user_features = COMMON_USER,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
@@ -1118,7 +1120,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c4,
.cpu_features = CPU_FTRS_E300,
.cpu_user_features = COMMON_USER,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index b6c5955..d59771d 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -587,9 +587,19 @@ DataLoadTLBMiss:
ori r1,r1,0xe04 /* clear out reserved bits */
andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */
mtspr SPRN_RPA,r1
+ mfspr r2,SPRN_SRR1/* Need to restore CR0 */
+ mtcrf 0x80,r2
+BEGIN_MMU_FTR_SECTION
+ li r0,1
+ lwz r1,sw_way_...@l(0)
+ rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */
+ slw r0,r0,r3
+ xor r1,r0,r1
+ srw r0,r1,r3
+ stw r1,sw_way_...@l(0)
+ rlwimi r2,r0,31-14,14,14
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
tlbld r3
- mfspr r3,SPRN_SRR1/* Need to restore CR0 */
- mtcrf 0x80,r3
rfi
DataAddressInvalid:
mfspr r3,SPRN_SRR1
@@ -652,11 +662,25 @@ DataStoreTLBMiss:
li r1,0xe05/* clear out reserved bits PP lsb */
andcr1,r0,r1/* PP = user? 2: 0 */
mtspr SPRN_RPA,r1
+ mfspr r2,SPRN_SRR1/* Need to restore CR0 */
+ mtcrf 0x80,r2
+BEGIN_MMU_FTR_SECTION
+ li r0,1
+ lwz r1,sw_way_...@l(0)
+ rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */
+ slw r0,r0,r3
+ xor r1,r0,r1
+ srw r0,r1,r3
+ stw r1,sw_way_...@l(0)
+ rlwimi r2,r0,31-14,14,14
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
tlbld r3
- mfspr r3,SPRN_SRR1/* Need to restore CR0 */
- mtcrf 0x80,r3
rfi
+ .balign L1_CACHE_BYTES
+sw_way_lru:
+ .long 0
+
#ifndef CONFIG_ALTIVEC
#define altivec_assist_exception unknown_exception
#endif
--
1.5.6.6
Re: [PATCH 4/7] parisc: rtc: Rename rtc-parisc to rtc-generic
On Mon, Mar 09, 2009 at 02:26:20PM +0100, Geert Uytterhoeven wrote: The rtc-parisc driver is not PA-RISC specific at all, as it uses the existing (but deprecated) generic RTC infrastructure ([gs]et_rtc_time()). Rename the driver from rtc-parisc to rtc-generic. Maybe it should be called rtc-legacy instead? ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFC][PATCH v4] MPC5121 TLB errata workaround
Complete workaround for DTLB errata in MPC5121e processors of die M36P and older (all currently existing versions). Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table encoded in 32 bits of SPRG6 for chosing the TLB-way. Signed-off-by: David Jander da...@protonic.nl --- diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0f4fac5..6cc0cd3 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -540,9 +540,13 @@ DataLoadTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ + mfspr r3,SPRN_DMISS +#ifdef CONFIG_PPC_MPC512x + b e300_read_tlb_fix/* Code for TLB-errata workaround doesn't fit here */ +e300_read_tlb_fix_ret: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ cmplw 0,r1,r3 mfspr r2,SPRN_SPRG3 @@ -612,9 +616,32 @@ DataStoreTLBMiss: * r2: ptr to linux-style pte * r3: scratch */ + mfspr r3,SPRN_DMISS +#ifdef CONFIG_PPC_MPC512x +/* MPC512x: workaround for errata in die M36P and earlier: + * Implement LRW for TLB way. + */ + rlwinm r0,r3,17,27,31 /* Get Address bits 19:15 */ + li r1,1 + slw r0,r1,r0 /* Make bitmask */ + mfspr r2,SPRN_SPRG6 /* Get lrw table */ + and.r1,r2,r0 /* Check entry in lrw */ + beq-0,113f /* 0? Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + andcr2,r2,r0 + mtspr SPRN_SPRG6,r2 + b 114f +113: + or r2,r2,r0 + mtspr SPRN_SPRG6,r2 +114: +#endif mfctr r0 /* Get PTE (linux-style) and check access */ - mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ cmplw 0,r1,r3 mfspr r2,SPRN_SPRG3 @@ -688,6 +715,29 @@ DataStoreTLBMiss: .globl mol_trampoline .set mol_trampoline, i0x2f00 +#ifdef CONFIG_PPC_MPC512x +e300_read_tlb_fix: + rlwinm r0,r3,17,27,31 /* Get Address bits 19:15 */ + li r1,1 + slw r0,r1,r0 /* Make bitmask */ + mfspr r2,SPRN_SPRG6 /* Get lrw table */ + and.r1,r2,r0 /* Check entry in lrw */ + beq-0,113f /* 0? Then goto 113: */ + + mfspr r1,SPRN_SRR1 + rlwinm r1,r1,0,15,13 /* Mask out SRR1[WAY] */ + mtspr SPRN_SRR1,r1 + + andcr2,r2,r0 + mtspr SPRN_SPRG6,r2 + b 114f +113: + or r2,r2,r0 + mtspr SPRN_SPRG6,r2 +114: + b e300_read_tlb_fix_ret +#endif + . = 0x3000 AltiVecUnavailable: ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v4] MPC5121 TLB errata workaround
Ooops, ok I think I just missed your proposal, Kumar. Anyway, I'll post my benchmark results to this here: 1.- mplayer -nosound -benchmark testfile.mpeg (a DVD-mpeg2 file): No fix at all: VC: 30.5s VO: 53.4s Sys:1.95s Total: 85.8s First fix (force writes to way 0): VC: 24.3s VO: 40.6s Sys:1.95s Total: 66.9s Second fix (implementing lrw): VC: 23.1s VO: 31.5s Sys:1.03s Total: 55.6s Third fix (patch v4, lrw in SPRG6): VC: 21.055s VO: 28.289s Sys:0.972s Total: 50.316s 2.- prboom -timedemo doombench1 (where doombench1.lmp is prerecorded demo): No fix at all: 14.1 fps First fix (force writes to way 0): 16.7 fps Second fix (implementing lrw): 18.1 fps Third fix (patch v4, lrw in SPRG6): 19.9 fps 3.- Synthetic and pathologic memcpy() benchmark: No fix at all: 26 Mbyte/s First fix (force writes to way 0): 160 MByte/s Second fix (implementing lrw): 163 MByte/s Third fix (patch v4, lrw in SPRG6): 180 MByte/s Best regards, -- David Jander Protonic Holland. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: use generic pci_assign_unassign_resources
Hehe, and that opens up an entirely different can of worms with our board. Thanks, however. Mark Benjamin Herrenschmidt wrote: On Fri, 2009-03-13 at 16:42 -0600, Mark Takatz wrote: Ben, We're looking at the fixes you put in place for the various PCI errors and we think this is the solution we need for our system, a GE Fanuc CM6 PPC board (single 8641), but your patches appear to apply either to 2.6.24 or 2.6.25, and we have 2.6.23. Do you know of any similar work done on the 2.6.23 release? Thanks in advance for any help you can provide, No, you would have to backport major chunks of the PCI rework I did in between, along with fixes I did after that. At this stage I would recommend considering an update to 2.6.27 or 2.6.28. Cheers, Ben. -- Mark J. Takatz Pericle Communications Company 1910 Vindicator Drive, Suite 100 Colorado Springs, CO 80919 Office: (719) 548-1170 Cell: (719) 287-5267 Fax: (719) 548-1211 tak...@pericle.com ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v4] powerpc/mm: e300c2/c3/c4 TLB errata workaround
Ok, I was analysing your code (which seems much more compact than mine): On Monday 16 March 2009 14:02:18 Kumar Gala wrote: [...] --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -587,9 +587,19 @@ DataLoadTLBMiss: ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +BEGIN_MMU_FTR_SECTION + li r0,1 + lwz r1,sw_way_...@l(0) + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ This should be 'rlwinm r3,r3,17,27,31' now, since you address bits, not ints. Note that you are trashing r3 (SPRN_DMISS) here! + slw r0,r0,r3 + xor r1,r0,r1 + srw r0,r1,r3 + stw r1,sw_way_...@l(0) + rlwimi r2,r0,31-14,14,14 +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) tlbld r3 And now you load r3 into the tlb, is this right? It doesn't seem right to me - mfspr r3,SPRN_SRR1/* Need to restore CR0 */ - mtcrf 0x80,r3 rfi DataAddressInvalid: mfspr r3,SPRN_SRR1 @@ -652,11 +662,25 @@ DataStoreTLBMiss: li r1,0xe05/* clear out reserved bits PP lsb */ andcr1,r0,r1/* PP = user? 2: 0 */ mtspr SPRN_RPA,r1 + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +BEGIN_MMU_FTR_SECTION + li r0,1 + lwz r1,sw_way_...@l(0) + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ + slw r0,r0,r3 + xor r1,r0,r1 + srw r0,r1,r3 + stw r1,sw_way_...@l(0) + rlwimi r2,r0,31-14,14,14 +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) tlbld r3 Same thing here, r3 is trashed. - mfspr r3,SPRN_SRR1/* Need to restore CR0 */ - mtcrf 0x80,r3 rfi + .balign L1_CACHE_BYTES +sw_way_lru: + .long 0 + Ok, I'll try to do it like this, but with lru stored in SPRG6 Best regards, -- David Jander Protonic Holland. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v4] powerpc/mm: e300c2/c3/c4 TLB errata workaround
On Mar 16, 2009, at 10:02 AM, David Jander wrote: Ok, I was analysing your code (which seems much more compact than mine): On Monday 16 March 2009 14:02:18 Kumar Gala wrote: [...] --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -587,9 +587,19 @@ DataLoadTLBMiss: ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +BEGIN_MMU_FTR_SECTION + li r0,1 + lwz r1,sw_way_...@l(0) + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ This should be 'rlwinm r3,r3,17,27,31' now, since you address bits, not ints. was just copying/pasting what you had :) Note that you are trashing r3 (SPRN_DMISS) here! good catch.. + slw r0,r0,r3 + xor r1,r0,r1 + srw r0,r1,r3 + stw r1,sw_way_...@l(0) + rlwimi r2,r0,31-14,14,14 +END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU) tlbld r3 And now you load r3 into the tlb, is this right? It doesn't seem right to me correct.. I wasn't thinking about the fact that tlbld was using r3. - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v4] powerpc/mm: e300c2/c3/c4 TLB errata workaround
On Mar 16, 2009, at 10:06 AM, Kumar Gala wrote: On Mar 16, 2009, at 10:02 AM, David Jander wrote: Ok, I was analysing your code (which seems much more compact than mine): On Monday 16 March 2009 14:02:18 Kumar Gala wrote: [...] --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -587,9 +587,19 @@ DataLoadTLBMiss: ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +BEGIN_MMU_FTR_SECTION + li r0,1 + lwz r1,sw_way_...@l(0) + rlwinm r3,r3,19,25,29 /* Get Address bits 19:15 */ This should be 'rlwinm r3,r3,17,27,31' now, since you address bits, not ints. was just copying/pasting what you had :) Note that you are trashing r3 (SPRN_DMISS) here! good catch.. + slw r0,r0,r3 + xor r1,r0,r1 + srw r0,r1,r3 + stw r1,sw_way_...@l(0) + rlwimi r2,r0,31-14,14,14 I'm also missing a: mtspr SPRN_SRR1,r2 - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: node /dev/ttyCPM2 not created
Thanks, I don't see any mdev process running. Just wonder who is creating /dev/ttyCPM1 since in the device table file (device_table.txt) I have only node: 204 (major) 46 (minor) defined. But I can see /dev/ttyCPM1 (204 47) Liran. On Fri, Mar 13, 2009 at 4:18 PM, Timur Tabi ti...@tabi.org wrote: On Fri, Mar 13, 2009 at 1:56 PM, liran raz liranrazli...@gmail.com wrote: Does anyone know what I'm missing? or what do I need to configure in order to have: /dev/ttyCPM2 ? My guess is that you don't have udev or mdev running. -- Timur Tabi Linux kernel developer at Freescale ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFC][PATCH v5] MPC5121 TLB errata workaround
Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: David Jander da...@protonic.nl --- diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 0f4fac5..3971ee4 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -578,9 +578,21 @@ DataLoadTLBMiss: andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +#ifdef CONFIG_PPC_MPC512x + li r0,1 + mfspr r1,SPRN_SPRG6 + rlwinm r2,r3,17,27,31 /* Get Address bits 19:15 */ + slw r0,r0,r2 + xor r1,r0,r1 + srw r0,r1,r2 + mtspr SPRN_SPRG6,r1 + mfspr r2,SPRN_SRR1 + rlwimi r2,r0,31-14,14,14 + mtspr SPRN_SRR1,r2 +#endif tlbld r3 - mfspr r3,SPRN_SRR1/* Need to restore CR0 */ - mtcrf 0x80,r3 rfi DataAddressInvalid: mfspr r3,SPRN_SRR1 @@ -646,9 +658,21 @@ DataStoreTLBMiss: andcr1,r3,r1/* PP = user? 2: 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +#ifdef CONFIG_PPC_MPC512x + li r0,1 + mfspr r1,SPRN_SPRG6 + rlwinm r2,r3,17,27,31 /* Get Address bits 19:15 */ + slw r0,r0,r2 + xor r1,r0,r1 + srw r0,r1,r2 + mtspr SPRN_SPRG6,r1 + mfspr r2,SPRN_SRR1 + rlwimi r2,r0,31-14,14,14 + mtspr SPRN_SRR1,r2 +#endif tlbld r3 - mfspr r3,SPRN_SRR1/* Need to restore CR0 */ - mtcrf 0x80,r3 rfi #ifndef CONFIG_ALTIVEC ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
In this patch, I placed the LRW table in SPRG6 like before, but Kumar's code seems a little more compact, so I decided to use that one and fix it ;-) It's a pity we seem to have one register short in the handler, so we need to load SPRN_SRR1 twice :-( Allthough the code-path now has 1 instruction less than my previous version most of the time (and 2 instructions more when way is not adjusted), benchmark results are barely affected by this: 1.- mplayer: Total time: 50.392s (50.316s previous patch) 2.- prboom timedemo: 20.1 fps (19.9 fps previous patch) 3.- memcpy speed: 179 MByte/s (180 Mbyte/s previous patch) Conclusion: difference not measurable between v4 and v5. Best regards, -- David Jander Protonic Holland. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH next] powerpc/5200: fix building GPT driver without sysfs
On Mon, Mar 16, 2009 at 10:17 AM, Alexander Beregalov a.berega...@gmail.com wrote: arch/powerpc/platforms/52xx/mpc52xx_gpt.c: In function 'mpc52xx_gpt_create_attribs': arch/powerpc/platforms/52xx/mpc52xx_gpt.c:373: error: parameter name omitted arch/powerpc/platforms/52xx/mpc52xx_gpt.c:373: warning: 'return' with a value, in function returning void Signed-off-by: Alexander Beregalov a.berega...@gmail.com A patch has already been queued in the next branch of git://git.secretlab.ca/git/linux-2.6-mpc52xx which removes the sysfs code from this driver entirely. Ben just hasn't pulled it into his -next branch yet. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
On Mon, 2009-03-16 at 16:52 +0100, David Jander wrote: Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: David Jander da...@protonic.nl I think we have a winner. with one instruction slot left :) I tried your V4 and V5 and could not see any difference in speed. Acked-by: Kenneth Johansson kenn...@southpole.se ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH next] powerpc/5200: fix building GPT driver without sysfs
arch/powerpc/platforms/52xx/mpc52xx_gpt.c: In function
'mpc52xx_gpt_create_attribs':
arch/powerpc/platforms/52xx/mpc52xx_gpt.c:373: error: parameter name omitted
arch/powerpc/platforms/52xx/mpc52xx_gpt.c:373: warning: 'return' with a value,
in function returning void
Signed-off-by: Alexander Beregalov a.berega...@gmail.com
---
arch/powerpc/platforms/52xx/mpc52xx_gpt.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index cb038dc..ef81cce 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -370,7 +370,7 @@ static void mpc52xx_gpt_create_attribs(struct
mpc52xx_gpt_priv *gpt)
}
#else /* defined(CONFIG_SYSFS) */
-static void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *) { return 0; }
+static inline void mpc52xx_gpt_create_attribs(struct mpc52xx_gpt_priv *gpt) {}
#endif /* defined(CONFIG_SYSFS) */
/* -
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Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
On Mar 16, 2009, at 11:09 AM, David Jander wrote: In this patch, I placed the LRW table in SPRG6 like before, but Kumar's code seems a little more compact, so I decided to use that one and fix it ;-) It's a pity we seem to have one register short in the handler, so we need to load SPRN_SRR1 twice :-( Allthough the code-path now has 1 instruction less than my previous version most of the time (and 2 instructions more when way is not adjusted), benchmark results are barely affected by this: 1.- mplayer: Total time: 50.392s (50.316s previous patch) 2.- prboom timedemo: 20.1 fps (19.9 fps previous patch) 3.- memcpy speed: 179 MByte/s (180 Mbyte/s previous patch) Conclusion: difference not measurable between v4 and v5. Can we try this memory instead of the SPRG to see if any noticeable difference? - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [RFC][PATCH v5] MPC5121 TLB errata workaround
On Mar 16, 2009, at 10:52 AM, David Jander wrote: Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Signed-off-by: Kumar Gala ga...@kernel.crashing.org Signed-off-by: David Jander da...@protonic.nl --- diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/ head_32.S index 0f4fac5..3971ee4 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -578,9 +578,21 @@ DataLoadTLBMiss: andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS + mfspr r2,SPRN_SRR1/* Need to restore CR0 */ + mtcrf 0x80,r2 +#ifdef CONFIG_PPC_MPC512x + li r0,1 + mfspr r1,SPRN_SPRG6 + rlwinm r2,r3,17,27,31 /* Get Address bits 19:15 */ Don't we want: rlwinm r2,r3,20,27,31 /* Get address bits 15:19 */ + slw r0,r0,r2 + xor r1,r0,r1 + srw r0,r1,r2 + mtspr SPRN_SPRG6,r1 + mfspr r2,SPRN_SRR1 + rlwimi r2,r0,31-14,14,14 + mtspr SPRN_SRR1,r2 +#endif tlbld r3 - mfspr r3,SPRN_SRR1/* Need to restore CR0 */ - mtcrf 0x80,r3 rfi - k ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH 1/3] powerpc: bare minimum checkpoint/restart implementation
Oren Laadan or...@cs.columbia.edu wrote: Nathan Lynch wrote: Nathan Lynch n...@pobox.com wrote: Oren Laadan wrote: Nathan Lynch wrote: What doesn't work: * restarting a 32-bit task from a 64-bit task and vice versa Is there a test to bail if we attempt to checkpoint such tasks ? No, but I'll add one if it looks too hard to fix for the next round. Unfortunately, adding a check for this is hard. The point of no return in the restart path is cr_read_mm, which tears down current's address space. cr_read_mm runs way before cr_read_cpu, which is the only restart method I've implemented for powerpc so far. So, checking for this condition in cr_read_cpu is too late if I want restart(2) to return an error and leave the caller's memory map intact. (And I do want this: restart should be as robust as execve.) In the case of restarting a container, I think it's ok if a restarting tasks dies in an ugly way -- this will be observed and handled by the initiating task outside the container, which will gracefully report to the caller/user. How would task exit be observed? Are all tasks in a restarted container guaranteed to be children (in the sense that wait(2) would work) of the initiating task? Even if you close this hole, then any other failure later on during restart - even a failure to allocate kernel memory due to memory pressure, will give that undesired effect that you are trying to avoid. Kernel memory allocation failure is not the kind of problem I'm trying to address. I am trying to address the case of restarting a checkpoint image that needs features that are not present, where the set of features used by the checkpoint image can be compared against the set of features the platform provides. That said, any difference in the architecture that may cause restart to fail is probably best placed in cr_write_head_arch. I think I explained in my earlier mail why the current implementation's cr_write_head_arch doesn't help in this case: Well okay then, cr_read_head_arch seems to be the right place in the restart sequence for the architecture code to handle this. However, cr_write_head_arch (which produces the buffer that cr_read_head_arch consumes) is not provided a reference to the task to be checkpointed, nor can it assume that it's operating on current. I need a reference to a task before I can determine whether it's running in 32- or 64-bit mode, or using the FPU, Altivec, SPE, whatever. In any case, mixing 32- and 64-bit tasks across restart is something I eventually want to support, not reject. But the problem I've outlined applies to FPU state and vector extensions (VMX, SPE), as well as sanity-checking debug register (DABR) contents. We'll need to be able to error out gracefully from restart when a checkpoint image specifies a feature unsupported by the current kernel or hardware. But I don't see how to do it with the current architecture. Am I missing something? More specifically, I envision restart to work like this: 1) user invokes user-land utility (e.g. cr --restart ... 2) 'cr' will create a new container 3) 'cr' will start a child in that container 4) child will create rest of tree (in kernel or in user space - tbd) 5) each task in that tree will restore itself 6) 'cr' monitors this process 7) if all goes well - 'cr' report ok. 8) if something goes bad, 'cr' notices and notifies caller/user Again, how would 'cr' obtain exit status for these tasks, and how would it distinguish failure from normal operation? ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[tip:irq/sparseirq] sparseirq, powerpc/cell: fix unused variable warning in interrupt.c
Commit-ID: a6bc3262c561780d2a6587aa3d5715b1e7d8fa13
Gitweb: http://git.kernel.org/tip/a6bc3262c561780d2a6587aa3d5715b1e7d8fa13
Author: Stephen Rothwell s...@canb.auug.org.au
AuthorDate: Mon, 16 Mar 2009 18:52:56 +1100
Commit: Ingo Molnar mi...@elte.hu
CommitDate: Mon, 16 Mar 2009 09:21:57 +0100
sparseirq, powerpc/cell: fix unused variable warning in interrupt.c
This new compiler warning:
arch/powerpc/platforms/cell/interrupt.c: In function 'handle_iic_irq':
arch/powerpc/platforms/cell/interrupt.c:240: warning: unused variable 'cpu'
Triggers because the local variable 'cpu' became unused due to commit:
dee4102: sparseirq: use kstat_irqs_cpu instead
Remove the variable.
Signed-off-by: Stephen Rothwell s...@canb.auug.org.au
Cc: Yinghai Lu ying...@kernel.org
Cc: ppc-dev linuxppc-dev@ozlabs.org
LKML-Reference: 20090316185256.4a160374@canb.auug.org.au
Signed-off-by: Ingo Molnar mi...@elte.hu
---
arch/powerpc/platforms/cell/interrupt.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/cell/interrupt.c
b/arch/powerpc/platforms/cell/interrupt.c
index 1f0d774..882e470 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -237,8 +237,6 @@ extern int noirqdebug;
static void handle_iic_irq(unsigned int irq, struct irq_desc *desc)
{
- const unsigned int cpu = smp_processor_id();
-
spin_lock(desc-lock);
desc-status = ~(IRQ_REPLAY | IRQ_WAITING);
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Re: [PATCH 05/13] sdhci: Add support for card-detection polling
On Sun, Mar 08, 2009 at 03:11:21PM +0100, Pierre Ossman wrote:
On Wed, 4 Mar 2009 20:49:17 +0300
Anton Vorontsov avoront...@ru.mvista.com wrote:
On Sat, Feb 21, 2009 at 04:58:21PM +0100, Pierre Ossman wrote:
Just modify the if-clause and
things will work.
That would look horrid...
if ((!(host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
!(sdhci_readl(host, SDHCI_PRESENT_STATE)
SDHCI_CARD_PRESENT)) ||
(host-flags SDHCI_DEVICE_DEAD)) {
There are worse ones in that code, but I see your point. :)
Might want to add a comment also to make it more obvious what the
if-clause does.
Let's try to avoid the if-clause above? How about this:
Looks ok.
@@ -1096,6 +1099,7 @@ out:
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct sdhci_host *host;
+ bool present;
unsigned long flags;
host = mmc_priv(mmc);
Can we use bool in the kernel?
Sure, it's widely used in the kernel, even in such places as
mm/ or kernel/.
Thanks for the review!
--
Anton Vorontsov
email: cbouatmai...@gmail.com
irc://irc.freenode.net/bd2
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[PATCH v3 0/11] FSL eSDHC support
Hi all, Here comes another version, let's hope that one is final. ;-) Changes since v2: - Introduced MMC_SDHCI_IO_ACCESSORS Kconfig symbol. If not selected, SDHCI will just use PCI memory accessors unconditionally. - Added MAINTAINERS entry. Changes since v1: - Add support for bus-specific IO memory accessors patch no longer touches sdhci-pci. The changes were no longer needed since I dropped Add type checking ... patch back in RFCv2; - Patch Add support for hosts with strict 32 bit addressing dropped. Now we handle the 32 bit magic in eSDHC's writew() accessor; - Patch Add quirk for controllers with max. block size up to 4096 bytes replaced by Add quirk for forcing maximum block size to 2048 bytes; - SDHCI_INT_ALL_MASK changed to (unsigned int)-1; - Addressed Pierre's comments in Add support for card-detection polling patch. Changes since the third RFC: - Use uninitialized_var() (suggested by Laurent Pinchart); - Fixed a bug in eSDHC SDCLK prescaler calculations because of which we were over-clocking the SDCLK, and that caused CRC errors using some SD cards; - Not a change, but some status: SDHS (50 MHz) cards were tested to NOT work (at least on MPC837x boards) -- this is to be investigated further. SDHC ( 4 GB) cards were not tested, yet. Changes since the second RFC: - Addressed all comments that were raised by Pierre Ossman. There were too many to mention them all, so here is the link: http://lkml.org/lkml/2009/2/6/320 Changes since the first RFC: - Use of_iomap() in sdhci-of.c (suggested by Arnd Bergmann). Also added Arnd's Acked-by: line for the sdhci-of patch. - Kconfig help text improved (thanks to Matt Sealey and M. Warner Losh). - In sdhci: Add quirk to suppress PIO interrupts during DMA transfers patch: sdhci_init() now clears SDHCI_PIO_DISABLED flag, otherwise we won't disable PIO interrupts after suspend. - New patch: sdhci: Add type checking for IO memory accessors -- Anton Vorontsov email: cbouatmai...@gmail.com irc://irc.freenode.net/bd2 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH 01/11] sdhci: Add support for bus-specific IO memory accessors
Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).
With this patch drivers may change memory accessors, so that we can
support hosts with weird IO memory access requirments.
For example, in FSL eSDHC SDHCI hardware all registers are 32 bit
width, with big-endian addressing. That is, readb(0x2f) should turn
into readb(0x2c), and readw(0x2c) should be translated to
le16_to_cpu(readw(0x2e)).
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/Kconfig |7 ++
drivers/mmc/host/sdhci.c | 159 ++---
drivers/mmc/host/sdhci.h | 95 +++
3 files changed, 180 insertions(+), 81 deletions(-)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 99d4b28..e032a42 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -37,6 +37,13 @@ config MMC_SDHCI
If unsure, say N.
+config MMC_SDHCI_IO_ACCESSORS
+ bool
+ depends on MMC_SDHCI
+ help
+ This is silent Kconfig symbol that is selected by the drivers that
+ need to overwrite SDHCI IO memory accessors.
+
config MMC_SDHCI_PCI
tristate SDHCI support on PCI bus
depends on MMC_SDHCI PCI
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index accb592..fd36b82 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -48,35 +48,35 @@ static void sdhci_dumpregs(struct sdhci_host *host)
printk(KERN_DEBUG DRIVER_NAME : == REGISTER DUMP
==\n);
printk(KERN_DEBUG DRIVER_NAME : Sys addr: 0x%08x | Version: 0x%08x\n,
- readl(host-ioaddr + SDHCI_DMA_ADDRESS),
- readw(host-ioaddr + SDHCI_HOST_VERSION));
+ sdhci_readl(host, SDHCI_DMA_ADDRESS),
+ sdhci_readw(host, SDHCI_HOST_VERSION));
printk(KERN_DEBUG DRIVER_NAME : Blk size: 0x%08x | Blk cnt: 0x%08x\n,
- readw(host-ioaddr + SDHCI_BLOCK_SIZE),
- readw(host-ioaddr + SDHCI_BLOCK_COUNT));
+ sdhci_readw(host, SDHCI_BLOCK_SIZE),
+ sdhci_readw(host, SDHCI_BLOCK_COUNT));
printk(KERN_DEBUG DRIVER_NAME : Argument: 0x%08x | Trn mode: 0x%08x\n,
- readl(host-ioaddr + SDHCI_ARGUMENT),
- readw(host-ioaddr + SDHCI_TRANSFER_MODE));
+ sdhci_readl(host, SDHCI_ARGUMENT),
+ sdhci_readw(host, SDHCI_TRANSFER_MODE));
printk(KERN_DEBUG DRIVER_NAME : Present: 0x%08x | Host ctl: 0x%08x\n,
- readl(host-ioaddr + SDHCI_PRESENT_STATE),
- readb(host-ioaddr + SDHCI_HOST_CONTROL));
+ sdhci_readl(host, SDHCI_PRESENT_STATE),
+ sdhci_readb(host, SDHCI_HOST_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Power:0x%08x | Blk gap: 0x%08x\n,
- readb(host-ioaddr + SDHCI_POWER_CONTROL),
- readb(host-ioaddr + SDHCI_BLOCK_GAP_CONTROL));
+ sdhci_readb(host, SDHCI_POWER_CONTROL),
+ sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Wake-up: 0x%08x | Clock:0x%08x\n,
- readb(host-ioaddr + SDHCI_WAKE_UP_CONTROL),
- readw(host-ioaddr + SDHCI_CLOCK_CONTROL));
+ sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
+ sdhci_readw(host, SDHCI_CLOCK_CONTROL));
printk(KERN_DEBUG DRIVER_NAME : Timeout: 0x%08x | Int stat: 0x%08x\n,
- readb(host-ioaddr + SDHCI_TIMEOUT_CONTROL),
- readl(host-ioaddr + SDHCI_INT_STATUS));
+ sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
+ sdhci_readl(host, SDHCI_INT_STATUS));
printk(KERN_DEBUG DRIVER_NAME : Int enab: 0x%08x | Sig enab: 0x%08x\n,
- readl(host-ioaddr + SDHCI_INT_ENABLE),
- readl(host-ioaddr + SDHCI_SIGNAL_ENABLE));
+ sdhci_readl(host, SDHCI_INT_ENABLE),
+ sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
printk(KERN_DEBUG DRIVER_NAME : AC12 err: 0x%08x | Slot int: 0x%08x\n,
- readw(host-ioaddr + SDHCI_ACMD12_ERR),
- readw(host-ioaddr + SDHCI_SLOT_INT_STATUS));
+ sdhci_readw(host, SDHCI_ACMD12_ERR),
+ sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
printk(KERN_DEBUG DRIVER_NAME : Caps: 0x%08x | Max curr: 0x%08x\n,
- readl(host-ioaddr + SDHCI_CAPABILITIES),
- readl(host-ioaddr + SDHCI_MAX_CURRENT));
+ sdhci_readl(host, SDHCI_CAPABILITIES),
+ sdhci_readl(host, SDHCI_MAX_CURRENT));
printk(KERN_DEBUG DRIVER_NAME :
===\n);
}
@@ -92,12 +92,12 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
unsigned long timeout;
if (host-quirks SDHCI_QUIRK_NO_CARD_NO_RESET) {
- if (!(readl(host-ioaddr + SDHCI_PRESENT_STATE)
+ if
[PATCH 02/11] sdhci: Split card-detection IRQs management from sdhci_init()
Card detection interrupts should be handled separately as they should
not be enabled before mmc_add_host() returns and should be disabled
before calling mmc_remove_host(). The same is for suspend and resume
routines.
sdhci_init() no longer enables card-detection irqs. Instead, two new
functions implemented: sdhci_enable_card_detection() and
sdhci_disable_card_detection().
New sdhci_reinit() call implemented to behave the same way as the old
sdhci_init().
Also, this patch implements and uses few new helpers to manage IRQs in
a more conveinient way, that is:
- sdhci_clear_set_irqs()
- sdhci_unmask_irqs()
- sdhci_mask_irqs()
- SDHCI_INT_ALL_MASK constant
sdhci_enable_sdio_irq() converted to these new helpers, plus the
helpers will be used by the subsequent patches.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 78 --
drivers/mmc/host/sdhci.h |1 +
2 files changed, 62 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fd36b82..bd5acfb 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -87,6 +87,47 @@ static void sdhci_dumpregs(struct sdhci_host *host)
* *
\*/
+static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
+{
+ u32 ier;
+
+ ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+ ier = ~clear;
+ ier |= set;
+ sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+}
+
+static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
+{
+ sdhci_clear_set_irqs(host, 0, irqs);
+}
+
+static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
+{
+ sdhci_clear_set_irqs(host, irqs, 0);
+}
+
+static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
+{
+ u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
+
+ if (enable)
+ sdhci_unmask_irqs(host, irqs);
+ else
+ sdhci_mask_irqs(host, irqs);
+}
+
+static void sdhci_enable_card_detection(struct sdhci_host *host)
+{
+ sdhci_set_card_detection(host, true);
+}
+
+static void sdhci_disable_card_detection(struct sdhci_host *host)
+{
+ sdhci_set_card_detection(host, false);
+}
+
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
@@ -120,20 +161,21 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
static void sdhci_init(struct sdhci_host *host)
{
- u32 intmask;
-
sdhci_reset(host, SDHCI_RESET_ALL);
- intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+ sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
+ SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
- SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
- SDHCI_INT_ADMA_ERROR;
+ SDHCI_INT_ADMA_ERROR);
+}
- sdhci_writel(host, intmask, SDHCI_INT_ENABLE);
- sdhci_writel(host, intmask, SDHCI_SIGNAL_ENABLE);
+static void sdhci_reinit(struct sdhci_host *host)
+{
+ sdhci_init(host);
+ sdhci_enable_card_detection(host);
}
static void sdhci_activate_led(struct sdhci_host *host)
@@ -1032,7 +1074,7 @@ static void sdhci_set_ios(struct mmc_host *mmc, struct
mmc_ios *ios)
*/
if (ios-power_mode == MMC_POWER_OFF) {
sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
- sdhci_init(host);
+ sdhci_reinit(host);
}
sdhci_set_clock(host, ios-clock);
@@ -1093,7 +1135,6 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
{
struct sdhci_host *host;
unsigned long flags;
- u32 ier;
host = mmc_priv(mmc);
@@ -1102,15 +1143,10 @@ static void sdhci_enable_sdio_irq(struct mmc_host *mmc,
int enable)
if (host-flags SDHCI_DEVICE_DEAD)
goto out;
- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
-
- ier = ~SDHCI_INT_CARD_INT;
if (enable)
- ier |= SDHCI_INT_CARD_INT;
-
- sdhci_writel(host, ier, SDHCI_INT_ENABLE);
- sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
-
+ sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
+ else
+ sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
out:
mmiowb();
@@ -1452,6 +1488,8 @@ int sdhci_suspend_host(struct sdhci_host *host,
pm_message_t state)
{
int ret;
+ sdhci_disable_card_detection(host);
+
ret = mmc_suspend_host(host-mmc,
[PATCH 03/11] sdhci: Enable only relevant (DMA/PIO) interrupts during transfers
Some hosts (that is, FSL eSDHC) throw PIO interrupts during DMA
transfers, this causes tons of unneeded interrupts, and thus highly
degraded speed.
This patch modifies the driver so that now we only enable relevant
(DMA or PIO) interrupts during transfers.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index bd5acfb..6fbbc00 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -167,9 +167,7 @@ static void sdhci_init(struct sdhci_host *host)
SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
- SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
- SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
- SDHCI_INT_ADMA_ERROR);
+ SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
}
static void sdhci_reinit(struct sdhci_host *host)
@@ -603,6 +601,17 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host,
struct mmc_data *data)
return count;
}
+static void sdhci_set_transfer_irqs(struct sdhci_host *host)
+{
+ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
+
+ if (host-flags SDHCI_REQ_USE_DMA)
+ sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
+ else
+ sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
+}
+
static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
{
u8 count;
@@ -751,6 +760,8 @@ static void sdhci_prepare_data(struct sdhci_host *host,
struct mmc_data *data)
host-blocks = data-blocks;
}
+ sdhci_set_transfer_irqs(host);
+
/* We do not handle DMA boundaries, so set it to max (512 KiB) */
sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data-blksz), SDHCI_BLOCK_SIZE);
sdhci_writew(host, data-blocks, SDHCI_BLOCK_COUNT);
--
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[PATCH 04/11] sdhci: Add support for card-detection polling
This patch adds SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk. When specified,
sdhci driver will set MMC_CAP_NEEDS_POLL MMC host capability, and won't
enable card insert/remove interrupts.
This is needed for hosts with unreliable card detection, such as FSL
eSDHC. The original eSDHC driver was tring to debounce card-detection
IRQs by reading present state and disabling particular interrupts. But
with this debouncing scheme I noticed that sometimes we miss card
insertion/removal events.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 17 +++--
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 6fbbc00..fc7cb48 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -112,6 +112,9 @@ static void sdhci_set_card_detection(struct sdhci_host
*host, bool enable)
{
u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ return;
+
if (enable)
sdhci_unmask_irqs(host, irqs);
else
@@ -1041,6 +1044,7 @@ out:
static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct sdhci_host *host;
+ bool present;
unsigned long flags;
host = mmc_priv(mmc);
@@ -1055,8 +1059,14 @@ static void sdhci_request(struct mmc_host *mmc, struct
mmc_request *mrq)
host-mrq = mrq;
- if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) SDHCI_CARD_PRESENT)
- || (host-flags SDHCI_DEVICE_DEAD)) {
+ /* If polling, assume that the card is always present. */
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ present = true;
+ else
+ present = sdhci_readl(host, SDHCI_PRESENT_STATE)
+ SDHCI_CARD_PRESENT;
+
+ if (!present || host-flags SDHCI_DEVICE_DEAD) {
host-mrq-cmd-error = -ENOMEDIUM;
tasklet_schedule(host-finish_tasklet);
} else
@@ -1690,6 +1700,9 @@ int sdhci_add_host(struct sdhci_host *host)
if (caps SDHCI_CAN_DO_HISPD)
mmc-caps |= MMC_CAP_SD_HIGHSPEED;
+ if (host-quirks SDHCI_QUIRK_BROKEN_CARD_DETECTION)
+ mmc-caps |= MMC_CAP_NEEDS_POLL;
+
mmc-ocr_avail = 0;
if (caps SDHCI_CAN_VDD_330)
mmc-ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index a9e25c6..968d713 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -214,6 +214,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (113)
/* Controller does not provide transfer-complete interrupt when not busy */
#define SDHCI_QUIRK_NO_BUSY_IRQ(114)
+/* Controller has unreliable card detection */
+#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (115)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 05/11] sdhci: Add support for hosts reporting inverted write-protect state
This patch adds SDHCI_QUIRK_INVERTED_WRITE_PROTECT quirk. When
specified, the sdhci driver will invert WP state.
p.s. Actually, the quirk is more board-specific than
controller-specific.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |2 ++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fc7cb48..c814220 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1149,6 +1149,8 @@ static int sdhci_get_ro(struct mmc_host *mmc)
spin_unlock_irqrestore(host-lock, flags);
+ if (host-quirks SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
+ return !!(present SDHCI_WRITE_PROTECT);
return !(present SDHCI_WRITE_PROTECT);
}
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 968d713..6980f27 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -216,6 +216,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_NO_BUSY_IRQ(114)
/* Controller has unreliable card detection */
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (115)
+/* Controller reports inverted write-protect state */
+#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (116)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 06/11] sdhci: Add get_{max,timeout}_clock callbacks
From: Ben Dooks ben-li...@fluff.org
Some controllers do not provide clock information in their capabilities
(in the Samsung case, it is because there are multiple clock sources
available to the controller). Add hooks to allow the system to supply
clock information.
p.s.
In the original Ben's patch there was a bug that makes sdhci_add_host()
return -ENODEV even if callbacks were specified. This is fixed now.
Signed-off-by: Ben Dooks ben-li...@fluff.org
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 22 +++---
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c814220..34ab77b 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1674,19 +1674,27 @@ int sdhci_add_host(struct sdhci_host *host)
host-max_clk =
(caps SDHCI_CLOCK_BASE_MASK) SDHCI_CLOCK_BASE_SHIFT;
+ host-max_clk *= 100;
if (host-max_clk == 0) {
- printk(KERN_ERR %s: Hardware doesn't specify base clock
- frequency.\n, mmc_hostname(mmc));
- return -ENODEV;
+ if (!host-ops-get_max_clock) {
+ printk(KERN_ERR
+ %s: Hardware doesn't specify base clock
+ frequency.\n, mmc_hostname(mmc));
+ return -ENODEV;
+ }
+ host-max_clk = host-ops-get_max_clock(host);
}
- host-max_clk *= 100;
host-timeout_clk =
(caps SDHCI_TIMEOUT_CLK_MASK) SDHCI_TIMEOUT_CLK_SHIFT;
if (host-timeout_clk == 0) {
- printk(KERN_ERR %s: Hardware doesn't specify timeout clock
- frequency.\n, mmc_hostname(mmc));
- return -ENODEV;
+ if (!host-ops-get_timeout_clock) {
+ printk(KERN_ERR
+ %s: Hardware doesn't specify timeout clock
+ frequency.\n, mmc_hostname(mmc));
+ return -ENODEV;
+ }
+ host-timeout_clk = host-ops-get_timeout_clock(host);
}
if (caps SDHCI_TIMEOUT_CLK_UNIT)
host-timeout_clk *= 1000;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 6980f27..aab0652 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -285,6 +285,8 @@ struct sdhci_ops {
#endif
int (*enable_dma)(struct sdhci_host *host);
+ unsigned int(*get_max_clock)(struct sdhci_host *host);
+ unsigned int(*get_timeout_clock)(struct sdhci_host *host);
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
--
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[PATCH 07/11] sdhci: Add set_clock callback and a quirk for nonstandard clocks
FSL eSDHC hosts have incompatible register map to manage the SDCLK.
This patch adds set_clock callback so that drivers could overwrite
set_clock behaviour.
Similar patch[1] was posted by Ben Dooks, though in Ben's version the
callback is named change_clock, plus the patch has some unrelated bits
that makes the patch difficult to reuse.
[1] http://lkml.org/lkml/2008/12/2/160
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |6 ++
drivers/mmc/host/sdhci.h |4
2 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 34ab77b..75d0ecb 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -949,6 +949,12 @@ static void sdhci_set_clock(struct sdhci_host *host,
unsigned int clock)
if (clock == host-clock)
return;
+ if (host-ops-set_clock) {
+ host-ops-set_clock(host, clock);
+ if (host-quirks SDHCI_QUIRK_NONSTANDARD_CLOCK)
+ return;
+ }
+
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index aab0652..b9bc622 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -218,6 +218,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (115)
/* Controller reports inverted write-protect state */
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (116)
+/* Controller has nonstandard clock management */
+#define SDHCI_QUIRK_NONSTANDARD_CLOCK (117)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
@@ -284,6 +286,8 @@ struct sdhci_ops {
void(*writeb)(struct sdhci_host *host, u8 val, int reg);
#endif
+ void(*set_clock)(struct sdhci_host *host, unsigned int clock);
+
int (*enable_dma)(struct sdhci_host *host);
unsigned int(*get_max_clock)(struct sdhci_host *host);
unsigned int(*get_timeout_clock)(struct sdhci_host *host);
--
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[PATCH 08/11] sdhci: Add quirk for controllers that need small delays for PIO
Small udelay is needed to make eSDHC work in PIO mode. Without
the delay reading causes endless interrupt storm, and writing
corrupts data. The first guess would be that we must wait for
some bit in some register, but I didn't find any reliable bits
that change before and after the delay.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |3 +++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 75d0ecb..cd6dab3 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -336,6 +336,9 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
mask = ~0;
while (sdhci_readl(host, SDHCI_PRESENT_STATE) mask) {
+ if (host-quirks SDHCI_QUIRK_PIO_NEEDS_DELAY)
+ udelay(100);
+
if (host-data-flags MMC_DATA_READ)
sdhci_read_block_pio(host);
else
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index b9bc622..c5ce9ee 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -220,6 +220,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (116)
/* Controller has nonstandard clock management */
#define SDHCI_QUIRK_NONSTANDARD_CLOCK (117)
+/* Controller does not like fast PIO transfers */
+#define SDHCI_QUIRK_PIO_NEEDS_DELAY(118)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 09/11] sdhci: Add quirk for controllers that need IRQ re-init after reset
FSL eSDHC controllers losing signal/interrupt enable states after
reset, so we should re-enable them.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c |7 +++
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cd6dab3..3a72fe2 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -134,6 +134,7 @@ static void sdhci_disable_card_detection(struct sdhci_host
*host)
static void sdhci_reset(struct sdhci_host *host, u8 mask)
{
unsigned long timeout;
+ u32 uninitialized_var(ier);
if (host-quirks SDHCI_QUIRK_NO_CARD_NO_RESET) {
if (!(sdhci_readl(host, SDHCI_PRESENT_STATE)
@@ -141,6 +142,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
return;
}
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+ ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
if (mask SDHCI_RESET_ALL)
@@ -160,6 +164,9 @@ static void sdhci_reset(struct sdhci_host *host, u8 mask)
timeout--;
mdelay(1);
}
+
+ if (host-quirks SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+ sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
}
static void sdhci_init(struct sdhci_host *host)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c5ce9ee..2962102 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -222,6 +222,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_NONSTANDARD_CLOCK (117)
/* Controller does not like fast PIO transfers */
#define SDHCI_QUIRK_PIO_NEEDS_DELAY(118)
+/* Controller losing signal/interrupt enable states after reset */
+#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (119)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 10/11] sdhci: Add quirk for forcing maximum block size to 2048 bytes
FSL eSDHC controllers can support maximum block size up to 4096 bytes,
the MBL (Maximum Block Length) field in the capabilities register
extended by one bit, and is set to 0x3.
But the SDHCI core doesn't support blocks of 4096 bytes, and thus
forces blksz to the lowest value -- 512 bytes. With this patch we can
pin up the blksz to the maximum supported block size, i.e. 2048 bytes.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
---
drivers/mmc/host/sdhci.c | 20 +---
drivers/mmc/host/sdhci.h |2 ++
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 3a72fe2..30d8e3d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1777,13 +1777,19 @@ int sdhci_add_host(struct sdhci_host *host)
* Maximum block size. This varies from controller to controller and
* is specified in the capabilities register.
*/
- mmc-max_blk_size = (caps SDHCI_MAX_BLOCK_MASK)
SDHCI_MAX_BLOCK_SHIFT;
- if (mmc-max_blk_size = 3) {
- printk(KERN_WARNING %s: Invalid maximum block size,
- assuming 512 bytes\n, mmc_hostname(mmc));
- mmc-max_blk_size = 512;
- } else
- mmc-max_blk_size = 512 mmc-max_blk_size;
+ if (host-quirks SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
+ mmc-max_blk_size = 2;
+ } else {
+ mmc-max_blk_size = (caps SDHCI_MAX_BLOCK_MASK)
+ SDHCI_MAX_BLOCK_SHIFT;
+ if (mmc-max_blk_size = 3) {
+ printk(KERN_WARNING %s: Invalid maximum block size,
+ assuming 512 bytes\n, mmc_hostname(mmc));
+ mmc-max_blk_size = 0;
+ }
+ }
+
+ mmc-max_blk_size = 512 mmc-max_blk_size;
/*
* Maximum block count.
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 2962102..f20a834 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -224,6 +224,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_PIO_NEEDS_DELAY(118)
/* Controller losing signal/interrupt enable states after reset */
#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (119)
+/* Controller has to be forced to use block size of 2048 bytes */
+#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (120)
int irq;/* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
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[PATCH 11/11] mmc: Add OpenFirmware bindings for SDHCI driver
This patch adds a new driver: sdhci-of. The driver is similar to
the sdhci-pci, it contains common probe code, and controller-specific
ops and quirks.
So far there are only Freescale eSDHC ops and quirks.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
Acked-by: Arnd Bergmann a...@arndb.de
---
MAINTAINERS |7 +
drivers/mmc/host/Kconfig| 11 ++
drivers/mmc/host/Makefile |1 +
drivers/mmc/host/sdhci-of.c | 309 +++
4 files changed, 328 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/host/sdhci-of.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 4a1cfca..77c3ec0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3837,6 +3837,13 @@ M: drzeus-sd...@drzeus.cx
L: sdhci-de...@list.drzeus.cx
S: Maintained
+SECURE DIGITAL HOST CONTROLLER INTERFACE, OPEN FIRMWARE BINDINGS (SDHCI-OF)
+P: Anton Vorontsov
+M: avoront...@ru.mvista.com
+L: linuxppc-dev@ozlabs.org
+L: sdhci-de...@list.drzeus.cx
+S: Maintained
+
SECURITY SUBSYSTEM
F: security/
P: James Morris
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index e032a42..69bd124 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -72,6 +72,17 @@ config MMC_RICOH_MMC
If unsure, say Y.
+config MMC_SDHCI_OF
+ tristate SDHCI support on OpenFirmware platforms
+ depends on MMC_SDHCI PPC_OF
+ select MMC_SDHCI_IO_ACCESSORS
+ help
+ This selects the OF support for Secure Digital Host Controller
+ Interfaces. So far, only the Freescale eSDHC controller is known
+ to exist on OF platforms.
+
+ If unsure, say N.
+
config MMC_OMAP
tristate TI OMAP Multimedia Card Interface support
depends on ARCH_OMAP
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index dedec55..dd512d9 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MMC_MXC) += mxcmmc.o
obj-$(CONFIG_MMC_SDHCI)+= sdhci.o
obj-$(CONFIG_MMC_SDHCI_PCI)+= sdhci-pci.o
obj-$(CONFIG_MMC_RICOH_MMC)+= ricoh_mmc.o
+obj-$(CONFIG_MMC_SDHCI_OF) += sdhci-of.o
obj-$(CONFIG_MMC_WBSD) += wbsd.o
obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
obj-$(CONFIG_MMC_OMAP) += omap.o
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
new file mode 100644
index 000..3ff4ac3
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of.c
@@ -0,0 +1,309 @@
+/*
+ * OpenFirmware bindings for Secure Digital Host Controller Interface.
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ *
+ * Authors: Xiaobo Xie x@freescale.com
+ * Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ */
+
+#include linux/module.h
+#include linux/init.h
+#include linux/io.h
+#include linux/interrupt.h
+#include linux/delay.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/mmc/host.h
+#include sdhci.h
+
+struct sdhci_of_data {
+ unsigned int quirks;
+ struct sdhci_ops ops;
+};
+
+struct sdhci_of_host {
+ unsigned int clock;
+ u16 xfer_mode_shadow;
+};
+
+/*
+ * Ops and quirks for the Freescale eSDHC controller.
+ */
+
+#define ESDHC_DMA_SYSCTL 0x40c
+#define ESDHC_DMA_SNOOP0x0040
+
+#define ESDHC_SYSTEM_CONTROL 0x2c
+#define ESDHC_CLOCK_MASK 0xfff0
+#define ESDHC_PREDIV_SHIFT 8
+#define ESDHC_DIVIDER_SHIFT4
+#define ESDHC_CLOCK_PEREN 0x0004
+#define ESDHC_CLOCK_HCKEN 0x0002
+#define ESDHC_CLOCK_IPGEN 0x0001
+
+static u32 esdhc_readl(struct sdhci_host *host, int reg)
+{
+ return in_be32(host-ioaddr + reg);
+}
+
+static u16 esdhc_readw(struct sdhci_host *host, int reg)
+{
+ return in_be16(host-ioaddr + (reg ^ 0x2));
+}
+
+static u8 esdhc_readb(struct sdhci_host *host, int reg)
+{
+ return in_8(host-ioaddr + (reg ^ 0x3));
+}
+
+static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
+{
+ out_be32(host-ioaddr + reg, val);
+}
+
+static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
+{
+ struct sdhci_of_host *of_host = sdhci_priv(host);
+ int base = reg ~0x3;
+ int shift = (reg 0x2) * 8;
+
+ switch (reg) {
+ case SDHCI_TRANSFER_MODE:
+ /*
+* Postpone this write, we must do it together with a
+* command write that is down below.
+*/
+ of_host-xfer_mode_shadow = val;
+ return;
+ case SDHCI_COMMAND:
+ esdhc_writel(host, val 16 | of_host-xfer_mode_shadow,
+
[PATCH v2 1/4] powerpc/mm: Respect _PAGE_COHERENT on classic ppc32 SW TLB load machines
Since we now set _PAGE_COHERENT in the Linux PTE we shouldn't be clearing it out before we setup the SW TLB. Today all the SW TLB machines (603/e300) that we support are non-SMP, however there are some errata on some devices that cause us to set _PAGE_COHERENT via CPU_FTR_NEED_COHERENT. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * We need to respect how CPU_FTR_NEED_COHERENT is set arch/powerpc/kernel/head_32.S | 15 --- 1 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index f8c2e6b..d0bad4b 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -514,8 +514,11 @@ InstructionTLBMiss: and r1,r1,r2/* writable if _RW and _DIRTY */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ + ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ +BEGIN_FTR_SECTION + rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ +END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 mfspr r3,SPRN_IMISS tlbli r3 @@ -588,8 +591,11 @@ DataLoadTLBMiss: and r1,r1,r2/* writable if _RW and _DIRTY */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ - ori r1,r1,0xe14 /* clear out reserved bits and M */ + ori r1,r1,0xe04 /* clear out reserved bits */ andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ +BEGIN_FTR_SECTION + rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ +END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS tlbld r3 @@ -656,8 +662,11 @@ DataStoreTLBMiss: stw r3,0(r2)/* update PTE (accessed/dirty bits) */ /* Convert linux-style PTE to low word of PPC-style PTE */ rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - li r1,0xe15/* clear out reserved bits and M */ + li r1,0xe05/* clear out reserved bits PP lsb */ andcr1,r3,r1/* PP = user? 2: 0 */ +BEGIN_FTR_SECTION + rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ +END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 mfspr r3,SPRN_DMISS tlbld r3 -- 1.5.6.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 2/4] powerpc/mm: Remove unused register usage in SW TLB miss handling
Long ago we had some code that actually used the CTR in the SW TLB miss handlers (603/e300). Since we don't use it no reason to waste cycles saving it off and restoring it (we actually didn't restore it in the fast path case). Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/kernel/head_32.S | 11 +++ 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index d0bad4b..f37df0c 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -475,12 +475,11 @@ SystemCall: . = 0x1000 InstructionTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_IMISS lis r1,page_off...@h/* check if kernel address */ @@ -531,7 +530,6 @@ InstructionAddressInvalid: addis r1,r1,0x2000 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ - mtctr r0 /* Restore CTR */ andi. r2,r3,0x/* Clear upper bits of SRR1 */ or r2,r2,r1 mtspr SPRN_SRR1,r2 @@ -552,12 +550,11 @@ InstructionAddressInvalid: . = 0x1100 DataLoadTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ @@ -607,7 +604,6 @@ DataAddressInvalid: rlwinm r1,r3,9,6,6 /* Get load/store bit */ addis r1,r1,0x2000 mtspr SPRN_DSISR,r1 - mtctr r0 /* Restore CTR */ andi. r2,r3,0x/* Clear upper bits of SRR1 */ mtspr SPRN_SRR1,r2 mfspr r1,SPRN_DMISS /* Get failing address */ @@ -627,12 +623,11 @@ DataAddressInvalid: . = 0x1200 DataStoreTLBMiss: /* - * r0: stored ctr + * r0: scratch * r1: linux style pte ( later becomes ppc hardware pte ) * r2: ptr to linux-style pte * r3: scratch */ - mfctr r0 /* Get PTE (linux-style) and check access */ mfspr r3,SPRN_DMISS lis r1,page_off...@h/* check if kernel address */ -- 1.5.6.6 ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[PATCH v2 3/4] powerpc/mm: Used free register to save a few cycles in SW TLB miss handling
Now that r0 is free we can keep the value of I/DMISS in r3 and not reload it before doing the tlbli/d. This saves us a few cycles in the fast path case. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- arch/powerpc/kernel/head_32.S | 51 +++- 1 files changed, 24 insertions(+), 27 deletions(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index f37df0c..58dcc7c 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -498,28 +498,27 @@ InstructionTLBMiss: rlwinm. r2,r2,0,0,19/* extract address of pte page */ beq-InstructionAddressInvalid /* return if no mapping */ rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2)/* get linux-style pte */ - andc. r1,r1,r3/* check access ~permission */ + lwz r0,0(r2)/* get linux-style pte */ + andc. r1,r1,r0/* check access ~permission */ bne-InstructionAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ + ori r0,r0,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ /* * NOTE! We are assuming this is not an SMP system, otherwise * we would need to update the pte atomically with lwarx/stwcx. */ - stw r3,0(r2)/* update PTE (accessed bit) */ + stw r0,0(r2)/* update PTE (accessed bit) */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW - PP lsb */ - rlwinm r2,r3,32-7,31,31/* _PAGE_DIRTY - PP lsb */ + rlwinm r1,r0,32-10,31,31 /* _PAGE_RW - PP lsb */ + rlwinm r2,r0,32-7,31,31/* _PAGE_DIRTY - PP lsb */ and r1,r1,r2/* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ + rlwimi r0,r0,32-1,30,30/* _PAGE_USER - PP msb */ + rlwimi r0,r0,32-1,31,31/* _PAGE_USER - PP lsb */ ori r1,r1,0xe04 /* clear out reserved bits */ - andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ + andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ BEGIN_FTR_SECTION rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 - mfspr r3,SPRN_IMISS tlbli r3 mfspr r3,SPRN_SRR1/* Need to restore CR0 */ mtcrf 0x80,r3 @@ -573,28 +572,27 @@ DataLoadTLBMiss: rlwinm. r2,r2,0,0,19/* extract address of pte page */ beq-DataAddressInvalid /* return if no mapping */ rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ - lwz r3,0(r2)/* get linux-style pte */ - andc. r1,r1,r3/* check access ~permission */ + lwz r0,0(r2)/* get linux-style pte */ + andc. r1,r1,r0/* check access ~permission */ bne-DataAddressInvalid /* return if access not permitted */ - ori r3,r3,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ + ori r0,r0,_PAGE_ACCESSED/* set _PAGE_ACCESSED in pte */ /* * NOTE! We are assuming this is not an SMP system, otherwise * we would need to update the pte atomically with lwarx/stwcx. */ - stw r3,0(r2)/* update PTE (accessed bit) */ + stw r0,0(r2)/* update PTE (accessed bit) */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r3,32-10,31,31 /* _PAGE_RW - PP lsb */ - rlwinm r2,r3,32-7,31,31/* _PAGE_DIRTY - PP lsb */ + rlwinm r1,r0,32-10,31,31 /* _PAGE_RW - PP lsb */ + rlwinm r2,r0,32-7,31,31/* _PAGE_DIRTY - PP lsb */ and r1,r1,r2/* writable if _RW and _DIRTY */ - rlwimi r3,r3,32-1,30,30/* _PAGE_USER - PP msb */ - rlwimi r3,r3,32-1,31,31/* _PAGE_USER - PP lsb */ + rlwimi r0,r0,32-1,30,30/* _PAGE_USER - PP msb */ + rlwimi r0,r0,32-1,31,31/* _PAGE_USER - PP lsb */ ori r1,r1,0xe04 /* clear out reserved bits */ - andcr1,r3,r1/* PP = user? (rwdirty? 2: 3): 0 */ + andcr1,r0,r1/* PP = user? (rwdirty? 2: 3): 0 */ BEGIN_FTR_SECTION rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) mtspr SPRN_RPA,r1 - mfspr r3,SPRN_DMISS tlbld r3 mfspr r3,SPRN_SRR1
[PATCH v2 4/4] powerpc/mm: e300c2/c3/c4 TLB errata workaround
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
Based on patch from David Jander da...@protonic.nl
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/mmu.h |6 ++
arch/powerpc/kernel/cputable.c |9 ++---
arch/powerpc/kernel/head_32.S | 32
3 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 10476a8..cbf1543 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -46,6 +46,12 @@
*/
#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x0010)
+/* This indicates that the processor doesn't handle way selection
+ * properly and needs SW to track and update the LRU state. This
+ * is specific to an errata on e300c2/c3/c4 class parts
+ */
+#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x0020)
+
#ifndef __ASSEMBLY__
#include asm/cputable.h
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index ccea243..cd1b687 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1090,7 +1090,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c2,
.cpu_features = CPU_FTRS_E300C2,
.cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
@@ -1103,7 +1104,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c3,
.cpu_features = CPU_FTRS_E300,
.cpu_user_features = COMMON_USER,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
@@ -1118,7 +1120,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_name = e300c4,
.cpu_features = CPU_FTRS_E300,
.cpu_user_features = COMMON_USER,
- .mmu_features = MMU_FTR_USE_HIGH_BATS,
+ .mmu_features = MMU_FTR_USE_HIGH_BATS |
+ MMU_FTR_NEED_DTLB_SW_LRU,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 58dcc7c..0837ec4 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -593,9 +593,21 @@ BEGIN_FTR_SECTION
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
mtspr SPRN_RPA,r1
+ mfspr r2,SPRN_SRR1/* Need to restore CR0 */
+ mtcrf 0x80,r2
+BEGIN_MMU_FTR_SECTION
+ li r0,1
+ mfspr r1,SPRN_SPRG6
+ rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
+ slw r0,r0,r2
+ xor r1,r0,r1
+ srw r0,r1,r2
+ mtspr SPRN_SPRG6,r1
+ mfspr r2,SPRN_SRR1
+ rlwimi r2,r0,31-14,14,14
+ mtspr SPRN_SRR1,r2
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
tlbld r3
- mfspr r3,SPRN_SRR1/* Need to restore CR0 */
- mtcrf 0x80,r3
rfi
DataAddressInvalid:
mfspr r3,SPRN_SRR1
@@ -661,9 +673,21 @@ BEGIN_FTR_SECTION
rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
mtspr SPRN_RPA,r1
+ mfspr r2,SPRN_SRR1/* Need to restore CR0 */
+ mtcrf 0x80,r2
+BEGIN_MMU_FTR_SECTION
+ li r0,1
+ mfspr r1,SPRN_SPRG6
+ rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
+ slw r0,r0,r2
+ xor r1,r0,r1
+ srw r0,r1,r2
+ mtspr SPRN_SPRG6,r1
+ mfspr r2,SPRN_SRR1
+ rlwimi r2,r0,31-14,14,14
+ mtspr SPRN_SRR1,r2
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
tlbld r3
- mfspr r3,SPRN_SRR1/* Need to restore CR0 */
- mtcrf 0x80,r3
rfi
#ifndef CONFIG_ALTIVEC
--
1.5.6.6
___
Linuxppc-dev mailing list
Re: [RFC] drivers/base: Add bus_register_notifier_alldev() variant
On Wed, Mar 11, 2009 at 11:00 AM, Greg KH gre...@suse.de wrote: On Wed, Mar 11, 2009 at 10:35:29AM -0600, Grant Likely wrote: On Wed, Mar 11, 2009 at 10:26 AM, Greg KH gre...@suse.de wrote: On Fri, Mar 06, 2009 at 09:10:19AM -0700, Grant Likely wrote: From: Grant Likely grant.lik...@secretlab.ca bus_register_notifier_alldev() is a variation on bus_register_notifier() which also triggers the notifier callback for devices already on the bus and already bound to drivers. This function is useful for the case where a driver needs to get a reference to a struct device other than the one it is bound to and it is not known if the device will be bound before or after this function is called. For example, an Ethernet device connected to a PHY that is probed separately. Can't you just walk the list of all devices already on the bus to get notified of them, and then register your notifier handler as well (or register it first, and then walk the list, which is pretty much what your patch does)? Yes, and I originally did, but it looks to me like a useful common pattern that is less error prone than open coding it. How about we wait, and if someone else does the same thing, we then add it to the core like this? I'm okay with that. Actually, I had two drivers that were using this, but that need has gone away because I've learned that I can defer locating the other device to open() time. I still think that it may be useful, but I agree that simply theoretical usage is not a good reason to add the API. Actually, wouldn't it make more sense to just change the default bus_register_notifier to do this? Is there some reason that the caller would not want this kind of thing to happen? It doesn't look like there are many users of this facility, and from looking at them it appears that adding the reporting of already registered bound devices would make sense. However, to do this my patch would need to be fixed to eliminate the race condition where an add or bind event could get reported more than once on a single device. It looks like the existing users expect never to be called more than once for each device. Unfortunately, I don't know how to fix the race. I need to research more. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Compilation of PREEMPT_RT on PowerPC (ppc440)
Hi all,
The latest RT patch patch-2.6.29-rc6-rt3 is throwing following compilation
errors for POWERPC linux kernel 2.6.29-rc6 :-
As I used plain vanilla kernel i.e - Linux-2.6.28 + patch-2.6.29-rc6 +
patch-2.6.29-rc6-rt3
While compiling for ppc440...
[r...@srikanth linux-2.6.29-rc6]# make ARCH=powerpc CROSS_COMPILE=ppc_440-
zImage
CHK include/linux/version.h
CHK include/linux/utsrelease.h
SYMLINK include/asm - include/asm-powerpc
CC kernel/bounds.s
GEN include/linux/bounds.h
CC arch/powerpc/kernel/asm-offsets.s
In file included from include/linux/rwsem.h:37,
from include/linux/mm_types.h:11,
from include/linux/sched.h:61,
from arch/powerpc/kernel/asm-offsets.c:17:
/opt/mlg-rt-test/linux-2.6.29-rc6/arch/powerpc/include/asm/rwsem.h:24:
error: redefinition of ‘struct rw_semaphore’
In file included from
include/linux/rwsem.h:37,
from
include/linux/mm_types.h:11,
from
include/linux/sched.h:61,
from
arch/powerpc/kernel/asm-offsets.c:17:
/opt/mlg-rt-test/linux-2.6.29-rc6/arch/powerpc/include/asm/rwsem.h:46:1:
warning: __RWSEM_INITIALIZER redefined
In file included from
include/linux/spinlock.h:118,
from
include/linux/seqlock.h:34,
from include/linux/time.h:8,
from include/linux/timex.h:56,
from include/linux/sched.h:54,
from arch/powerpc/kernel/asm-offsets.c:17:
include/linux/rt_lock.h:191:1: warning: this is the location of the previous
definition
In file included from include/linux/rwsem.h:37,
from include/linux/mm_types.h:11,
from include/linux/sched.h:61,
from arch/powerpc/kernel/asm-offsets.c:17:
/opt/mlg-rt-test/linux-2.6.29-rc6/arch/powerpc/include/asm/rwsem.h:50:1:
warning: DECLARE_RWSEM redefined
In file included from include/linux/spinlock.h:118,
from include/linux/seqlock.h:34,
from include/linux/time.h:8,
from include/linux/timex.h:56,
from include/linux/sched.h:54,
from arch/powerpc/kernel/asm-offsets.c:17:
include/linux/rt_lock.h:195:1: warning: this is the location of the previous
definition
In file included from include/linux/rwsem.h:37,
from include/linux/mm_types.h:11,
from include/linux/sched.h:61,
from arch/powerpc/kernel/asm-offsets.c:17:
/opt/mlg-rt-test/linux-2.6.29-rc6/arch/powerpc/include/asm/rwsem.h:61:1:
warning: init_rwsem redefined
In file included from include/linux/spinlock.h:118,
from include/linux/seqlock.h:34,
from include/linux/time.h:8,
from include/linux/timex.h:56,
from include/linux/sched.h:54,
from arch/powerpc/kernel/asm-offsets.c:17:
include/linux/rt_lock.h:232:1: warning: this is the location of the previous
definition
/opt/mlg-rt-test/linux-2.6.29-rc6/arch/powerpc/include/asm/rwsem.h:167:
error: expected identifier or ‘(’ before ‘{’ token
make[1]: *** [arch/powerpc/kernel/asm-offsets.s] Error 1
make: *** [prepare0] Error 2
[r...@srikanth linux-2.6.29-rc6]#
Has anybody come across this ? If any fixes brought up for build of RT on
PowerPC, pls reply back.
Regards
Srikant
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Re: [PATCH v2 1/2] powerpc/86xx: Board support for GE Fanuc's PPC9A
On Mon, Mar 16, 2009 at 10:32:18AM +, Martyn Welch wrote:
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Uh.. sorry. Should have noticed these little nitpicks the first time
around.
+ local...@fef05000 {
+ #address-cells = 2;
+ #size-cells = 1;
+ compatible = fsl,mpc8641-localbus, simple-bus;
+ reg = 0xfef05000 0x1000;
+ interrupts = 19 2;
+ interrupt-parent = mpic;
+
+ ranges = 0 0 0xff00 0x0100 // 16MB Boot flash
+ 1 0 0xe800 0x0800 // Paged Flash 0
+ 2 0 0xe000 0x0800 // Paged Flash 1
+ 3 0 0xfc10 0x0002 // NVRAM
+ 4 0 0xfc00 0x8000 // FPGA
+ 5 0 0xfc008000 0x8000 // AFIX FPGA
+ 6 0 0xfd00 0x0080 // IO FPGA (8-bit)
+ 7 0 0xfd80 0x0080; // IO FPGA (32-bit)
+
+ /* fl...@0,0 is a mirror of part of the memory in fl...@1,0
+ fl...@0,0 {
+ compatible = cfi-flash;
It would be nice to have the actual type of flash chips here, although
it's not essential.
[snip]
+ f...@4,0 {
+ compatible = gef,fpga-regs;
I don't imagine this is the only set of FPGA based control regs GE
Fanuc will ever make, so this should be more precise. Including the
board type here is probably the way to go.
+ reg = 0x4 0x0 0x40;
+ };
+
+ w...@4,2000 {
+ compatible = gef,fpga-wdt;
And likewise here.
+ reg = 0x4 0x2000 0x8;
+ interrupts = 0x1a 0x4;
+ interrupt-parent = gef_pic;
+ };
+ /* Second watchdog available, driver currently supports one.
+ w...@4,2010 {
+ compatible = gef,fpga-wdt;
+ reg = 0x4 0x2010 0x8;
+ interrupts = 0x1b 0x4;
+ interrupt-parent = gef_pic;
+ };
+ */
+ gef_pic: p...@4,4000 {
+ #interrupt-cells = 1;
+ interrupt-controller;
+ compatible = gef,fpga-pic;
And possibly here, although in this case I imagine several boards
might have compatible FPGA PICs.
+ i2c1: i...@3000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl-i2c;
This should list include a compatible string specific to the
particular SoC model before the general name.
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Re: [PATCH] powerpc: Enable CPU_FTR_NEED_COHERENT for MPC52xx
On Mon, Mar 16, 2009 at 4:05 AM, Piotr Ziecik ko...@semihalf.com wrote: BestComm, a DMA engine in MPC52xx SoC, requires snooping when CPU caches are enabled to work properly. Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code'. Signed-off-by: Piotr Ziecik ko...@semihalf.com --- This patch was succesfully tested on our MPC5200-based. Ben, Gerhard could you ack this patch, as it implements your suggestion. arch/powerpc/include/asm/cputable.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index b18358f..22dc2d8 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -241,9 +241,11 @@ extern const char *powerpc_base_platform; /* We need to mark all pages as being coherent if we're SMP or we have a * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II * require it for PCI streaming/prefetch to work properly. + * This is also required by 52xx family. */ #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ - || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) + || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ + || defined(CONFIG_PPC_MPC52xx) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT #else #define CPU_FTR_COMMON 0 Aside from the fact that MPC10X_BRIDGE, PPC83xx and 8260 are already doing it, adding the feature bit this way isn't multiplatform friendly. Essentially it means that all selected platforms will have CPU_FTR_NEED_COHERENT enabled if CONFIG_PPC_MPC52xx is enabled. Adding a new section to cputable.c for PVR=0x8082201x and applying the bit there would contain the impact to only G2 cores, but it's not perfect. Some of the 82xx parts have the same PVR and so would also be impacted. Maybe I'm fretting over nothing. Ben, what's the right thing to do here? Otherwise, I've pulled this into my tree and while I'm not affected by the bug, I don't see any new problems with the patch either. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
Re: [PATCH] powerpc: Enable CPU_FTR_NEED_COHERENT for MPC52xx
On Mon, Mar 16, 2009 at 9:54 PM, Grant Likely grant.lik...@secretlab.ca wrote: On Mon, Mar 16, 2009 at 4:05 AM, Piotr Ziecik ko...@semihalf.com wrote: BestComm, a DMA engine in MPC52xx SoC, requires snooping when CPU caches are enabled to work properly. Adding CPU_FTR_NEED_COHERENT fixes NFS problems on MPC52xx machines introduced by 'powerpc/mm: Fix handling of _PAGE_COHERENT in BAT setup code'. [...] #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ - || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) + || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ + || defined(CONFIG_PPC_MPC52xx) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT #else #define CPU_FTR_COMMON 0 Aside from the fact that MPC10X_BRIDGE, PPC83xx and 8260 are already doing it, adding the feature bit this way isn't multiplatform friendly. Essentially it means that all selected platforms will have CPU_FTR_NEED_COHERENT enabled if CONFIG_PPC_MPC52xx is enabled. Here's my counter-patch. It contains the change to just G2_LE cores when MPC52xx is selected. However, this change will also affect some of the MPC82xx parts. However CPU_FTR_NEED_COHERENT shouldn't actually hurt anything, so maybe it would be better to just enable it unconditionally for the G2_LE core. Kumar/Ben, thoughts? g. --- diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cput index 4911104..48d7f5f 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -348,8 +348,15 @@ extern const char *powerpc_base_platform; CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) + +#if defined(CONFIG_PPC_MPC52xx) +#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ + CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NEED_COHERENT) +#else #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) +#endif + #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ CPU_FTR_COMMON) -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
[RFC] powerpc/8xxx: Clean up setting of CPU_FTR_NEED_COHERENT
From: Grant Likely grant.lik...@secretlab.ca Method used to set CPU_FTR_NEED_COHERENT was unfriendly for multiplatform kernels. This patch cleans it up. Signed-off-by: Grant Likely grant.lik...@secretlab.ca --- I haven't even compile tested this. But I want to see if there are any objections before I do the legwork. g. arch/powerpc/include/asm/cputable.h |9 - 1 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 48d7f5f..a36494e 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -242,8 +242,7 @@ extern const char *powerpc_base_platform; * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II * require it for PCI streaming/prefetch to work properly. */ -#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ - || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) +#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT #else #define CPU_FTR_COMMON 0 @@ -347,7 +346,7 @@ extern const char *powerpc_base_platform; CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ - CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) + CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_NEED_COHERENT) #if defined(CONFIG_PPC_MPC52xx) #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ @@ -359,10 +358,10 @@ extern const char *powerpc_base_platform; #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ - CPU_FTR_COMMON) + CPU_FTR_COMMON | CPU_FTR_NEED_COHERENT) #define CPU_FTRS_E300C2(CPU_FTR_MAYBE_CAN_DOZE | \ CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ - CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) + CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NEED_COHERENT) #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) #define CPU_FTRS_8XX (CPU_FTR_USE_TB) #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-dev
