[PATCH v3] mpc5200: support for the MAN mpc5200 based board uc101
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- I2C with PCF8563 and Temp. Sensor ADM9240
- IDE support
Signed-off-by: Heiko Schocher h...@denx.de
---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
- checked with:
$ ./scripts/checkpatch.pl
0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch
total: 0 errors, 0 warnings, 317 lines checked
0001-mpc5200-support-for-the-MAN-mpc5200-based-board-uc1.patch has no obvious
style problems and is ready for submission.
$
changes since v1:
- add comments from Grant Likely grant.lik...@secretlab.ca
use mpc5200_defconfig as default configuration
- add comments from Wolfram Sang w.s...@pengutronix.de
- rebase against current next
changes since v2:
- add comment from Wolfram Sang
remove unofficial binding
arch/powerpc/boot/dts/uc101.dts | 310 ++
arch/powerpc/platforms/52xx/mpc5200_simple.c |1 +
2 files changed, 311 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/uc101.dts
diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
new file mode 100644
index 000..bfb8dd9
--- /dev/null
+++ b/arch/powerpc/boot/dts/uc101.dts
@@ -0,0 +1,310 @@
+/*
+ * uc101 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher h...@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = manroland,uc101;
+ compatible = manroland,uc101;
+ #address-cells = 1;
+ #size-cells = 1;
+ interrupt-parent = mpc5200_pic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,5...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32;
+ i-cache-line-size = 32;
+ d-cache-size = 0x4000;// L1, 16K
+ i-cache-size = 0x4000;// L1, 16K
+ timebase-frequency = 0; // from bootloader
+ bus-frequency = 0;// from bootloader
+ clock-frequency = 0; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x0400; // 64MB
+ };
+
+ soc5...@f000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc5200-immr,
+ fsl,mpc5200b-immr;
+ ranges = 0 0xf000 0xc000;
+ reg = 0xf000 0x0100;
+ bus-frequency = 0;// from bootloader
+ system-frequency = 0; // from bootloader
+
+ c...@200 {
+ compatible = fsl,mpc5200b-cdm,fsl,mpc5200-cdm;
+ reg = 0x200 0x38;
+ };
+
+ mpc5200_pic: interrupt-control...@500 {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ compatible = fsl,mpc5200b-pic,fsl,mpc5200-pic;
+ reg = 0x500 0x80;
+ interrupts = 0 0 3;
+ };
+
+ gpt0: ti...@600 { // GPT 0 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x600 0x10;
+ interrupts = 1 9 0;
+ gpio-controller;
+ };
+
+ gpt1: ti...@610 { // GPT 1 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x610 0x10;
+ interrupts = 1 10 0;
+ gpio-controller;
+ };
+
+ gpt2: ti...@620 { // GPT 2 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x620 0x10;
+ interrupts = 1 11 0;
+ gpio-controller;
+ };
+
+ gpt3: ti...@630 { // GPT 3 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg
[PATCH v3] mpc5200: support for the MAN mpc5200 based board mucmc52
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by: Heiko Schocher h...@denx.de
---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
- checked with:
$ ./scripts/checkpatch.pl
0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 361 lines checked
0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious
style problems and is ready for submission.
$
changes since v1:
- add comments from Grant Likely grant.lik...@secretlab.ca
use mpc5200_defconfig as default configuration, therefore added
SIMPLE_GPIO support in it, because this is not selectable as a
module.
- add comments from Wolfram Sang w.s...@pengutronix.de
- rebase against current next
changes since v2:
- add comment from Wolfram Sang
remove unofficial binding
arch/powerpc/boot/dts/mucmc52.dts| 346 ++
arch/powerpc/configs/mpc5200_defconfig |2 +-
arch/powerpc/platforms/52xx/mpc5200_simple.c |1 +
3 files changed, 348 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mucmc52.dts
diff --git a/arch/powerpc/boot/dts/mucmc52.dts
b/arch/powerpc/boot/dts/mucmc52.dts
new file mode 100644
index 000..3924811
--- /dev/null
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -0,0 +1,346 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher h...@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = manroland,mucmc52;
+ compatible = manroland,mucmc52;
+ #address-cells = 1;
+ #size-cells = 1;
+ interrupt-parent = mpc5200_pic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,5...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32;
+ i-cache-line-size = 32;
+ d-cache-size = 0x4000;// L1, 16K
+ i-cache-size = 0x4000;// L1, 16K
+ timebase-frequency = 0; // from bootloader
+ bus-frequency = 0;// from bootloader
+ clock-frequency = 0; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x0400; // 64MB
+ };
+
+ soc5...@f000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc5200-immr,
+ fsl,mpc5200b-immr;
+ ranges = 0 0xf000 0xc000;
+ reg = 0xf000 0x0100;
+ bus-frequency = 0;// from bootloader
+ system-frequency = 0; // from bootloader
+
+ c...@200 {
+ compatible = fsl,mpc5200b-cdm,fsl,mpc5200-cdm;
+ reg = 0x200 0x38;
+ };
+
+ mpc5200_pic: interrupt-control...@500 {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ compatible = fsl,mpc5200b-pic,fsl,mpc5200-pic;
+ reg = 0x500 0x80;
+ interrupts = 0 0 3;
+ };
+
+ gpt0: ti...@600 { // GPT 0 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x600 0x10;
+ interrupts = 1 9 0;
+ gpio-controller;
+ };
+
+ gpt1: ti...@610 { // GPT 1 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x610 0x10;
+ interrupts = 1 10 0;
+ gpio-controller;
+ };
+
+ gpt2: ti...@620 { // GPT 2 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x620 0x10;
+ interrupts = 1 11 0;
+ gpio-controller;
+ };
+
+ gpt3: ti...@630 { // GPT 3 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
On Tuesday 06 October 2009 23:49:04 Grant Likely wrote: However, I've completely devoted to this work for at least the next two months, so there are plenty more patches to follow. Once I've got all the common code merged between Microblaze, PowerPC and Sparc I'll be fix the endian problems and making it easily usable by other architectures like ARM and MIPS. Lots of work to be done. Is there any news on getting QEMU to parse a device tree to figure out what hardware to emulate? (I.E. using the device tree code to let qemu provide configurable board emulations instead of hardwiring them in C code?) Also, what would be involved in getting x86 to (at least have the option to) use the device tree stuff? Rob -- Latency is more important than throughput. It's that simple. - Linus Torvalds ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Grant Likely grant.lik...@secretlab.ca Date: Tue, 6 Oct 2009 22:49:04 -0600 Also, I'd like to take on responsibility for maintaining the cross- architecture device tree code. If there are no objections, I'll write a patch to add a device tree section to MAINTAINERS. Feel free. And also feel free to add my: Acked-by: David S. Miller da...@davemloft.net to your patches. Thanks! ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 03:07:35: Allright, did a bit of reading of doco and code.. hey, this is a super, thanks! Doco isn't totally clear though. At some stage, it -hints- that in case of a TLB error (match on EA/ASID but incorrect protection/valid/changed/...) the offending TLB entry is automatically invalidated. Do you know if that is correct ? Nope, I don't know. I would hope so since we never do anything to remove the invalid entries we write to the TLB when hitting non-present PTEs but then, that may also explain some of our problems... hmm, then a tlbil_va() in do_page_fault for no translation errors would help I guess. Now, a few comments from what I read in the code: - The whole writeback could be avoided in Instruction/Data TLB miss, but for that, you need to make sure that the TLB entry we create has valid set only if -both- present and accessed are set. That would save in the case of CONFIG_SWAP, a store and a read back of TWC I suppose, but you do need to find a way to do that ANDing of ACCESSED and PRESENT. So far I have mapped !ACCESSED pages as No Access instead, maybe that was wrong? I thought it was easier but I will have a look at this too. - I think we can get rid of HWWRITE. We can make CHANGED be the current HWWRITE value, I agree with you, which matches the HW changed bit. We need to be a bit careful of how we setup the PP bits tho. At this stage, I see several approaches: * One is to basically generate the right PP bits based on a combination of _PAGE_USER and _PAGE_RW. That's the simpler approach but probably uses more code in the TLB miss handler. It would look like that, with MxCTR:PPCS=0 _PAGE_USER_PAGE_RW PP (bits 20..27) 00 011C(C is _PAGE_DIRTY) 01 000C 10 110C 11 100C One easy way to do that is to have _PAGE_USER and _PAGE_RW sit next to each other in bit position 28 and 29 (0xc). Load a GPR with something like 011011001000 and rotate it left by PTE 0xc, then move the resulting 3 bits into position, or something along those lines. You can also give up on kernel read-only support and go down to 2 PP bits and never use the extended encoding. yes, I do think the extended encoding is too much work and not worth it. One concern I have is if a user RO mapping also can be a kernel RO mapping? That is, do kernel require RW to a user page mapped RO? * Another one is to use MxCTR:PPCS=1 a mask of 100C1U00 (U is _PAGE_USER) and or in ^_PAGE_RW (it could actually be made reverse-polarity in the PTE but that would mean some changes to non-8xx specific headers, so let's avoid it for now at least). hmm, interesting. Then I will also have set ACCESSED manually in TLB Miss I think. At least that's the best options I can see from my reading of the doco, though it's not totally clear to me what really happens when doing the PPCS trick, will it generate a TLB error on a non-match or will it try to TLB miss, which could be bad. Yes, I don't think anybody has tested this. * Last but not least, it wouldn't be hard to use either of the above encodings, and have the PTE actually contain the right bit combination already. You don't need to have a _PAGE_RW, you don't need to have a _PAGE_USER :-) Look at how I do things for book3e, where I layout the 6 BookE protection bit directly in the PTE. That's a bit harder and maybe will need subtle changes to pte-common.h and such to accomodate it, and so probably something to experiment with as a second step, but it's the most efficient approach in the long run for obvious reasons. - I think we could have more bits pre-set to the right values in the PTE, look how we play with defining some of the constants in pte-common.h, might be worth having a look, but -after- we have something that works :-) - Possible bug: I'm very disturbed by the fact that DataTLBError sets HWWRITE and DIRTY on a non-present PTE. It should not. Just like ACCESSED. That's going to cause trouble and swap corruption, even more as we move DIRTY around. Yes, this is what I fix with the first patch in my series: 8xx: DTLB Error must check for more errors. DataTLBError currently does: if ((err 0x0200) == 0) DSI(); This won't handle a store with no valid translation. Change this to if ((err 0x4800) != 0) DSI(); that is, branch to DSI if either !permission or !translation. - Maybe we can completely remove that mucking around with dirty, setting of accessed etc... from DataTLBError. Just make it go to C code just like InstructionAccess, as we discussed earlier, the generic code will fix it up and we'll speed up page faults. It should be fairly rare to take a fault due to a missing _PAGE_ACCESSED or _PAGE_DIRTY in any case, so
Re: [FTRACE] Enabling function_graph causes OOPS
Steven Rostedt wrote: On Tue, 2009-10-06 at 07:20 +1100, Benjamin Herrenschmidt wrote: On Mon, 2009-10-05 at 09:25 -0400, Steven Rostedt wrote: Sachin, can you give me more details on how you built that kernel ? (or give them again in case I missed them the first time around :-), ie, what toolchain, options, etc... or even better, give me remote access to the build host ? Ok, got access and had a quick look... seems to be a toolchain problem to me. I'll investigate more tomorrow. Hi Ben, Any more word on this issue? Didn't you fix it using a TOC access ? Unless I'm confusing things, I think the problem is the usage of LOAD_REG_IMMEDIATE which generates relocs that we don't support when CONFIG_RELOCATABLE is set. I've merged a patch that post-processes the kernel now, to check for such relocs so at least you should be warned at build time. I thought we had two issues. One was the use of the relocs that did cause issues. But then there was still crashes reported after that. IIRC. I'm still suffering jetlag, so my memory is not that fresh about As Ben suggested, i changed LOAD_REG_IMMEDIATE() to LOAD_REG_ADDR() as follows. - LOAD_REG_IMMEDIATE(r4,ftrace_return_to_handler) + LOAD_REG_ADDR(r4,ftrace_return_to_handler) With this change compile time warnings about bad relocations related to ftrace are gone. Before the change : WARNING: 6 bad relocations c0008f1a R_PPC64_ADDR16_HIGHEST __ksymtab+0x00742110 c0008f1e R_PPC64_ADDR16_HIGHER __ksymtab+0x00742110 c0008f26 R_PPC64_ADDR16_HI __ksymtab+0x00742110 c0008f2a R_PPC64_ADDR16_LO __ksymtab+0x00742110 c085e118 R_PPC64_ADDR64__crc_per_cpu__softirq_work_list c08662d0 R_PPC64_ADDR64__crc_simple_prepare_write After the change : WARNING: 2 bad relocations c085e118 R_PPC64_ADDR64__crc_per_cpu__softirq_work_list c08662d0 R_PPC64_ADDR64__crc_simple_prepare_write But i still run into oops while using ftrace function_graph. Thanks -Sachin -- - Sachin Sant IBM Linux Technology Center India Systems and Technology Labs Bangalore, India - diff -Naurp a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S --- a/arch/powerpc/kernel/entry_64.S 2009-10-06 15:31:29.0 +0530 +++ b/arch/powerpc/kernel/entry_64.S 2009-10-06 15:34:00.0 +0530 @@ -1038,7 +1038,7 @@ _GLOBAL(mod_return_to_handler) * We are in a module using the module's TOC. * Switch to our TOC to run inside the core kernel. */ - LOAD_REG_IMMEDIATE(r4,ftrace_return_to_handler) + LOAD_REG_ADDR(r4,ftrace_return_to_handler) ld r2, 8(r4) bl .ftrace_return_to_handler ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [FTRACE] Enabling function_graph causes OOPS
On Wed, 2009-10-07 at 14:26 +0530, Sachin Sant wrote: As Ben suggested, i changed LOAD_REG_IMMEDIATE() to LOAD_REG_ADDR() as follows. - LOAD_REG_IMMEDIATE(r4,ftrace_return_to_handler) + LOAD_REG_ADDR(r4,ftrace_return_to_handler) With this change compile time warnings about bad relocations related to ftrace are gone. You also need to make sure r2 is properly loaded with the kernel TOC pointer, something like ld r2,PACAKTOC(r13) before the LOAD_REG_ADDR. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/boot/dts: drop obsolete 'fsl5200-clocking'
On Thu, Sep 10, 2009 at 09:05:46AM -0600, Grant Likely wrote: On Thu, Sep 10, 2009 at 8:55 AM, Wolfram Sang w.s...@pengutronix.de wrote: The 'fsl5200-clocking'-property was dropped since 0d1cde235874b00905bce23f659690d060ebf475. Remove all occurences in dts-files. Signed-off-by: Wolfram Sang w.s...@pengutronix.de Cc: Grant Likely grant.lik...@secretlab.ca Looks good to me. I'll pick it up. Ping? :) -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
However, I've completely devoted to this work for at least the next two months, so there are plenty more patches to follow. Once I've \o/ Thanks, Grant! A seperate tree would be great. Patches look good to me: Acked-by: Wolfram Sang w.s...@pengutronix.de -- Pengutronix e.K. | Wolfram Sang| Industrial Linux Solutions | http://www.pengutronix.de/ | signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v3] mpc5200: support for the MAN mpc5200 based board mucmc52
On Wed, Oct 07, 2009 at 08:40:37AM +0200, Heiko Schocher wrote:
- serial Console on PSC1
- 64MB SDRAM
- MTD CFI Flash
- Ethernet FEC
- IDE support
Signed-off-by: Heiko Schocher h...@denx.de
Sorry for finding things incrementally, but I think there is still one issue
left. Once this is sorted out, you could add my:
Reviewed-by: Wolfram Sang w.s...@pengutronix.de
---
- based on:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
- checked with:
$ ./scripts/checkpatch.pl
0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch
total: 0 errors, 0 warnings, 361 lines checked
0002-mpc5200-support-for-the-MAN-mpc5200-based-board-muc.patch has no obvious
style problems and is ready for submission.
$
changes since v1:
- add comments from Grant Likely grant.lik...@secretlab.ca
use mpc5200_defconfig as default configuration, therefore added
SIMPLE_GPIO support in it, because this is not selectable as a
module.
- add comments from Wolfram Sang w.s...@pengutronix.de
- rebase against current next
changes since v2:
- add comment from Wolfram Sang
remove unofficial binding
arch/powerpc/boot/dts/mucmc52.dts| 346
++
arch/powerpc/configs/mpc5200_defconfig |2 +-
arch/powerpc/platforms/52xx/mpc5200_simple.c |1 +
3 files changed, 348 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mucmc52.dts
diff --git a/arch/powerpc/boot/dts/mucmc52.dts
b/arch/powerpc/boot/dts/mucmc52.dts
new file mode 100644
index 000..3924811
--- /dev/null
+++ b/arch/powerpc/boot/dts/mucmc52.dts
@@ -0,0 +1,346 @@
+/*
+ * mucmc52 board Device Tree Source
+ *
+ * Copyright (C) 2009 DENX Software Engineering GmbH
+ * Heiko Schocher h...@denx.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+ model = manroland,mucmc52;
+ compatible = manroland,mucmc52;
+ #address-cells = 1;
+ #size-cells = 1;
+ interrupt-parent = mpc5200_pic;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,5...@0 {
+ device_type = cpu;
+ reg = 0;
+ d-cache-line-size = 32;
+ i-cache-line-size = 32;
+ d-cache-size = 0x4000;// L1, 16K
+ i-cache-size = 0x4000;// L1, 16K
+ timebase-frequency = 0; // from bootloader
+ bus-frequency = 0;// from bootloader
+ clock-frequency = 0; // from bootloader
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x 0x0400; // 64MB
+ };
+
+ soc5...@f000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = fsl,mpc5200-immr,
+ fsl,mpc5200b-immr;
You should decide on the latter one only here.
+ ranges = 0 0xf000 0xc000;
+ reg = 0xf000 0x0100;
+ bus-frequency = 0;// from bootloader
+ system-frequency = 0; // from bootloader
+
+ c...@200 {
+ compatible = fsl,mpc5200b-cdm,fsl,mpc5200-cdm;
+ reg = 0x200 0x38;
+ };
+
+ mpc5200_pic: interrupt-control...@500 {
+ // 5200 interrupts are encoded into two levels;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ compatible = fsl,mpc5200b-pic,fsl,mpc5200-pic;
+ reg = 0x500 0x80;
+ interrupts = 0 0 3;
+ };
+
+ gpt0: ti...@600 { // GPT 0 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x600 0x10;
+ interrupts = 1 9 0;
+ gpio-controller;
+ };
+
+ gpt1: ti...@610 { // GPT 1 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+ #gpio-cells = 2;
+ reg = 0x610 0x10;
+ interrupts = 1 10 0;
+ gpio-controller;
+ };
+
+ gpt2: ti...@620 { // GPT 2 in GPIO mode
+ compatible = fsl,mpc5200b-gpt-gpio,
+ fsl,mpc5200-gpt-gpio;
+
[PATCH 10/16] percpu: make percpu symbols in powerpc unique
This patch updates percpu related symbols in powerpc such that percpu
symbols are unique and don't clash with local symbols. This serves
two purposes of decreasing the possibility of global percpu symbol
collision and allowing dropping per_cpu__ prefix from percpu symbols.
* arch/powerpc/kernel/perf_callchain.c: s/callchain/cpu_perf_callchain/
* arch/powerpc/kernel/setup-common.c: s/pvr/cpu_pvr/
* arch/powerpc/platforms/pseries/dtl.c: s/dtl/cpu_dtl/
* arch/powerpc/platforms/cell/interrupt.c: s/iic/cpu_iic/
Partly based on Rusty Russell's alloc_percpu: rename percpu vars
which cause name clashes patch.
Signed-off-by: Tejun Heo t...@kernel.org
Cc: Rusty Russell ru...@rustcorp.com.au
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: Paul Mackerras pau...@samba.org
Cc: Arnd Bergmann a...@arndb.de
Cc: linuxppc-...@ozlabs.org
---
arch/powerpc/include/asm/smp.h |2 +-
arch/powerpc/kernel/perf_callchain.c|4 ++--
arch/powerpc/kernel/setup-common.c |4 ++--
arch/powerpc/kernel/smp.c |2 +-
arch/powerpc/platforms/cell/interrupt.c | 14 +++---
arch/powerpc/platforms/pseries/dtl.c|4 ++--
6 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index d9ea8d3..1d3b270 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -37,7 +37,7 @@ extern void cpu_die(void);
extern void smp_send_debugger_break(int cpu);
extern void smp_message_recv(int);
-DECLARE_PER_CPU(unsigned int, pvr);
+DECLARE_PER_CPU(unsigned int, cpu_pvr);
#ifdef CONFIG_HOTPLUG_CPU
extern void fixup_irqs(cpumask_t map);
diff --git a/arch/powerpc/kernel/perf_callchain.c
b/arch/powerpc/kernel/perf_callchain.c
index 0a03cf7..fe59c44 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -497,11 +497,11 @@ static void perf_callchain_user_32(struct pt_regs *regs,
* Since we can't get PMU interrupts inside a PMU interrupt handler,
* we don't need separate irq and nmi entries here.
*/
-static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
+static DEFINE_PER_CPU(struct perf_callchain_entry, cpu_perf_callchain);
struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
{
- struct perf_callchain_entry *entry = __get_cpu_var(callchain);
+ struct perf_callchain_entry *entry = __get_cpu_var(cpu_perf_callchain);
entry-nr = 0;
diff --git a/arch/powerpc/kernel/setup-common.c
b/arch/powerpc/kernel/setup-common.c
index 4271f7a..aa5aeb9 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -157,7 +157,7 @@ extern u32 cpu_temp_both(unsigned long cpu);
#endif /* CONFIG_TAU */
#ifdef CONFIG_SMP
-DEFINE_PER_CPU(unsigned int, pvr);
+DEFINE_PER_CPU(unsigned int, cpu_pvr);
#endif
static int show_cpuinfo(struct seq_file *m, void *v)
@@ -209,7 +209,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
}
#ifdef CONFIG_SMP
- pvr = per_cpu(pvr, cpu_id);
+ pvr = per_cpu(cpu_pvr, cpu_id);
#else
pvr = mfspr(SPRN_PVR);
#endif
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 9b86a74..2ebb484 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -232,7 +232,7 @@ struct thread_info *current_set[NR_CPUS];
static void __devinit smp_store_cpu_info(int id)
{
- per_cpu(pvr, id) = mfspr(SPRN_PVR);
+ per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
}
static void __init smp_create_idle(unsigned int cpu)
diff --git a/arch/powerpc/platforms/cell/interrupt.c
b/arch/powerpc/platforms/cell/interrupt.c
index 882e470..54bad90 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -54,7 +54,7 @@ struct iic {
struct device_node *node;
};
-static DEFINE_PER_CPU(struct iic, iic);
+static DEFINE_PER_CPU(struct iic, cpu_iic);
#define IIC_NODE_COUNT 2
static struct irq_host *iic_host;
@@ -82,7 +82,7 @@ static void iic_unmask(unsigned int irq)
static void iic_eoi(unsigned int irq)
{
- struct iic *iic = __get_cpu_var(iic);
+ struct iic *iic = __get_cpu_var(cpu_iic);
out_be64(iic-regs-prio, iic-eoi_stack[--iic-eoi_ptr]);
BUG_ON(iic-eoi_ptr 0);
}
@@ -146,7 +146,7 @@ static unsigned int iic_get_irq(void)
struct iic *iic;
unsigned int virq;
- iic = __get_cpu_var(iic);
+ iic = __get_cpu_var(cpu_iic);
*(unsigned long *) pending =
in_be64((u64 __iomem *) iic-regs-pending_destr);
if (!(pending.flags CBE_IIC_IRQ_VALID))
@@ -161,12 +161,12 @@ static unsigned int iic_get_irq(void)
void iic_setup_cpu(void)
{
- out_be64(__get_cpu_var(iic).regs-prio, 0xff);
+ out_be64(__get_cpu_var(cpu_iic).regs-prio, 0xff);
}
u8 iic_get_target_id(int cpu)
{
- return per_cpu(iic, cpu).target_id;
+ return per_cpu(cpu_iic, cpu).target_id;
}
Re: SMU-base PowerMac and server_mode
On Tue, Oct 6, 2009 at 6:07 PM, Olof Johansson o...@lixom.net wrote: On Tue, Oct 06, 2009 at 09:11:22PM +1100, Benjamin Herrenschmidt wrote: On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote: Hi there, I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard time getting it to boot without a screen attached, but I eventually managed to (yaboot was the culprit). However, this machine is SMU-based, and I couldn't find a way to enable the equivalent of the PMU's server_mode (i.e. automatically reboot after a power failure). Is there any known way to do that ? I'm pretty sure I reverse engineered the necessary command a while back and somebody wrote a userland tool to set it, but I can't find it anymore :-) Yeah, I had one but I have since lost it. I suspect it was on the drive of my second quad that I wiped before I sold it, thinking there was nothing of value on it. :( -Olof Ha, that's too bad. Do you know if it might be online somewhere ? Maybe an idea of the right keywords to google ? Thanks ! - Romain ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7 PATCH 0/7]: cpuidle/x86/POWER: Cleanup idle power management code in x86, cleanup drivers/cpuidle/cpuidle.c and introduce cpuidle to POWER.
* Vaidy sva...@linux.vnet.ibm.com [2009-10-07 16:56:48]: * Peter Zijlstra a.p.zijls...@chello.nl [2009-10-06 20:04:39]: On Tue, 2009-10-06 at 22:05 +0530, Arun R Bharadwaj wrote: Also, the per-cpu nature of registration/unregistration of cpuidle has been maintained as ACPI needs this. Right, so can't we ditch that and have acpi default to the lowest common C-state and warn when various cpus report different C-states? Hi Peter, As Arjan mentioned previously, the per-cpu registration has to stay for x86 for now due to legacy ACPI compatibility. Breaking that may break lot of existing users and we do not have a clean fallback method. As far as powerpc is concerned, we can work with a single global registration. However we would like to have the same interface across different archs. With the new re-factoring (v7), Arun has killed most of the list traversal and linking between various cpu's cpuidle_driver structures. Now we have a per-cpu stack of registered devices and we lookup the structs using online cpumasks. The cpuidle_driver structure has list of idle routing pointers (struct cpuidle_state) and rest of it is statistics that needs to be maintained at a per-cpu level anyway. All that is duplicated here is the array of idle routines (struct cpuidle_state) on each cpu. The objective of the refactoring is to have a single common idle routine management framework (remove pm_idle) and we have it done through cpuidle registration framework. We can incrementally remove the per-cpu registration later easily by splitting the cpuidle_driver structure. Yes, incremental refactoring makes the most sense from the do not break as you refactor point of view. -- Balbir ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [microblaze-uclinux] Re: [RFC PATCH 05/12] of: add common header for flattened device tree representation
Stephen Rothwell wrote: Hi Grant, Just first obvious thing: On Tue, 06 Oct 2009 22:30:59 -0600 Grant Likely grant.lik...@secretlab.ca wrote: diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 64e8b3a..5f461f0 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -17,20 +17,10 @@ #ifndef _ASM_MICROBLAZE_PROM_H #define _ASM_MICROBLAZE_PROM_H #ifdef __KERNEL__ - -/* Definitions used by the flattened device tree */ -#define OF_DT_HEADER0xd00dfeed /* marker */ This is used in arch/microblaze/kernel/head.S, but you move its definition inside #ifndef __ASSEMBLY__ below. You should probably replace the include of asm/prom.h in arch/microblaze/kernel/head.S with linux/of_fdt.h (assuming that the comment in there is correct). yes, Stephen is right here. I created one patch (in attachment) which fixed it. I tested your patches on Microblaze (noMMU and MMU) and I have no problem with compilation and simple boot-up works for both versions too. With that my patch: Acked-by: Michal Simek mon...@monstr.eu Thanks, Michal P.S.: I have my provider - it block my emails - that's why the patch is in attachment. -#define OF_DT_BEGIN_NODE0x1 /* Start of node, full name */ -#define OF_DT_END_NODE 0x2 /* End node */ -#define OF_DT_PROP 0x3 /* Property: name off, size, content */ -#define OF_DT_NOP 0x4 /* nop */ -#define OF_DT_END 0x9 - -#define OF_DT_VERSION 0x10 - #ifndef __ASSEMBLY__ #include linux/types.h +#include linux/of_fdt.h #include linux/proc_fs.h #include linux/platform_device.h #include asm/irq.h -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian From 73b16544fe8410ec8e8e893aa3357093e985 Mon Sep 17 00:00:00 2001 From: Michal Simek mon...@monstr.eu Date: Wed, 7 Oct 2009 14:04:01 +0200 Subject: [PATCH] of: microblaze: of_fdt.h is used in asm code. Microblaze uses OF_DT_HEADER macro to identify DTB. Reported-by: Stephen Rothwell s...@canb.auug.org.au Signed-off-by: Michal Simek mon...@monstr.eu --- arch/microblaze/kernel/head.S |2 +- include/linux/of_fdt.h|3 +++ 2 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S index 697ce30..3091619 100644 --- a/arch/microblaze/kernel/head.S +++ b/arch/microblaze/kernel/head.S @@ -31,7 +31,7 @@ #include linux/linkage.h #include asm/thread_info.h #include asm/page.h -#include asm/prom.h /* for OF_DT_HEADER */ +#include linux/of_fdt.h /* for OF_DT_HEADER */ #ifdef CONFIG_MMU #include asm/setup.h /* COMMAND_LINE_SIZE */ diff --git a/include/linux/of_fdt.h b/include/linux/of_fdt.h index b41bd18..44fecfa 100644 --- a/include/linux/of_fdt.h +++ b/include/linux/of_fdt.h @@ -30,6 +30,7 @@ #define OF_DT_VERSION 0x10 +#ifndef __ASSEMBLY__ /* * This is what gets passed to the kernel by prom_init or kexec * @@ -84,4 +85,6 @@ extern int prom_remove_property(struct device_node *np, struct property *prop); extern int prom_update_property(struct device_node *np, struct property *newprop, struct property *oldprop); +#endif /* __ASSEMBLY__ */ + #endif /* _LINUX_OF_FDT_H */ -- 1.5.5.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7 PATCH 0/7]: cpuidle/x86/POWER: Cleanup idle power management code in x86, cleanup drivers/cpuidle/cpuidle.c and introduce cpuidle to POWER.
On Wed, 2009-10-07 at 16:56 +0530, Vaidyanathan Srinivasan wrote: * Peter Zijlstra a.p.zijls...@chello.nl [2009-10-06 20:04:39]: On Tue, 2009-10-06 at 22:05 +0530, Arun R Bharadwaj wrote: Also, the per-cpu nature of registration/unregistration of cpuidle has been maintained as ACPI needs this. Right, so can't we ditch that and have acpi default to the lowest common C-state and warn when various cpus report different C-states? Hi Peter, As Arjan mentioned previously, the per-cpu registration has to stay for x86 for now due to legacy ACPI compatibility. Breaking that may break lot of existing users and we do not have a clean fallback method. From what I understood some broken ass bioses report different C state availability on different CPUs in the same SMP system. I'm suggesting to work around that by limiting all CPUs to the subset of C states reported on all CPUs, instead of the current mess. I haven't heard anybody tell me why that wouldn't be possible on x86 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [microblaze-uclinux] Re: [RFC PATCH 05/12] of: add common header for flattened device tree representation
On Wed, Oct 7, 2009 at 6:14 AM, Michal Simek mon...@monstr.eu wrote: Stephen Rothwell wrote: Hi Grant, Just first obvious thing: On Tue, 06 Oct 2009 22:30:59 -0600 Grant Likely grant.lik...@secretlab.ca wrote: diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 64e8b3a..5f461f0 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -17,20 +17,10 @@ #ifndef _ASM_MICROBLAZE_PROM_H #define _ASM_MICROBLAZE_PROM_H #ifdef __KERNEL__ - -/* Definitions used by the flattened device tree */ -#define OF_DT_HEADER 0xd00dfeed /* marker */ This is used in arch/microblaze/kernel/head.S, but you move its definition inside #ifndef __ASSEMBLY__ below. You should probably replace the include of asm/prom.h in arch/microblaze/kernel/head.S with linux/of_fdt.h (assuming that the comment in there is correct). yes, Stephen is right here. I created one patch (in attachment) which fixed it. I tested your patches on Microblaze (noMMU and MMU) and I have no problem with compilation and simple boot-up works for both versions too. With that my patch: Acked-by: Michal Simek mon...@monstr.eu Thanks. I'll merge your change with my patch so that bisect isn't broken. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 05/12] of: add common header for flattened device tree representation
On Tue, Oct 6, 2009 at 11:14 PM, Benjamin Herrenschmidt b...@kernel.crashing.org wrote: On Tue, 2009-10-06 at 22:30 -0600, Grant Likely wrote: --- /dev/null +++ b/include/linux/of_fdt.h @@ -0,0 +1,30 @@ +/* + * Definitions for working with the Flattened Device Tree data format + * + * Copyright (C) 1996-2005 Paul Mackerras. + * + * Updates for PPC64 by Peter Bergner David Engebretsen, IBM Corp. + * Updates for SPARC by David S. Miller + * Merged to common code by Grant Likely I think you should prune the above. Make it (c) myself since I wrote the FDT code initially. You can add back (c) of other people as you add more stuff here I suppose. No big deal tho. No problem. What is the exact copyright text that you'd like to see here? I'm not going to guess on other people's copyright notice. :-) g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7 PATCH 7/7]: pSeries: implement pSeries processor idle module.
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 21:05:22]:
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
Please consider this updated PATCH 7/7 instead of the earlier one.
The earlier one had a late_initcall(pseries_processor_idle_init),
which caused a panic when cpuidle_enable_device() was called from
cpuidle_switch_governor(). This is because registration of cpuidle
devices was happening at a later stage. So change this to a
device_initcall() to get rid of the panic.
---
This patch creates arch/powerpc/platforms/pseries/processor_idle.c,
which implements the cpuidle infrastructure for pseries.
It implements a pseries_cpuidle_loop() which would be the main idle loop
called from cpu_idle(). It makes decision of entering either
dedicated_snooze_loop or dedicated_cede_loop for dedicated lpar and
shared_cede_loop for shared lpar processor based on the
decision taken by the cpuidle governor.
Signed-off-by: Arun R Bharadwaj a...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/system.h |1
arch/powerpc/kernel/sysfs.c |2
arch/powerpc/platforms/pseries/Makefile |1
arch/powerpc/platforms/pseries/processor_idle.c | 208
arch/powerpc/platforms/pseries/pseries.h|8
5 files changed, 220 insertions(+)
Index: linux.trees.git/arch/powerpc/platforms/pseries/Makefile
===
--- linux.trees.git.orig/arch/powerpc/platforms/pseries/Makefile
+++ linux.trees.git/arch/powerpc/platforms/pseries/Makefile
@@ -26,3 +26,4 @@ obj-$(CONFIG_HCALL_STATS) += hvCall_inst
obj-$(CONFIG_PHYP_DUMP)+= phyp_dump.o
obj-$(CONFIG_CMM) += cmm.o
obj-$(CONFIG_DTL) += dtl.o
+obj-$(CONFIG_PSERIES_PROCESSOR_IDLE) += processor_idle.o
Index: linux.trees.git/arch/powerpc/platforms/pseries/pseries.h
===
--- linux.trees.git.orig/arch/powerpc/platforms/pseries/pseries.h
+++ linux.trees.git/arch/powerpc/platforms/pseries/pseries.h
@@ -10,6 +10,8 @@
#ifndef _PSERIES_PSERIES_H
#define _PSERIES_PSERIES_H
+#include linux/cpuidle.h
+
extern void __init fw_feature_init(const char *hypertas, unsigned long len);
struct pt_regs;
@@ -40,4 +42,10 @@ extern unsigned long rtas_poweron_auto;
extern void find_udbg_vterm(void);
+DECLARE_PER_CPU(unsigned long, smt_snooze_delay);
+
+#ifdef CONFIG_PSERIES_PROCESSOR_IDLE
+extern struct cpuidle_driver pseries_idle_driver;
+#endif
+
#endif /* _PSERIES_PSERIES_H */
Index: linux.trees.git/arch/powerpc/platforms/pseries/processor_idle.c
===
--- /dev/null
+++ linux.trees.git/arch/powerpc/platforms/pseries/processor_idle.c
@@ -0,0 +1,208 @@
+/*
+ * processor_idle - idle state cpuidle driver.
+ * Adapted from drivers/acpi/processor_idle.c
+ *
+ * Arun R Bharadwaj a...@linux.vnet.ibm.com
+ *
+ * Copyright (C) 2009 IBM Corporation.
+ * ~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~
+ */
+
+#include linux/kernel.h
+#include linux/module.h
+#include linux/init.h
+#include linux/moduleparam.h
+#include linux/cpuidle.h
+
+#include asm/paca.h
+#include asm/reg.h
+#include asm/system.h
+#include asm/machdep.h
+#include asm/firmware.h
+
+#include plpar_wrappers.h
+#include pseries.h
+
+MODULE_AUTHOR(Arun R Bharadwaj);
+MODULE_DESCRIPTION(pSeries Idle State Driver);
+MODULE_LICENSE(GPL);
+
+struct cpuidle_driver pseries_idle_driver = {
+ .name = pseries_idle,
+ .owner =THIS_MODULE,
+};
+
+DEFINE_PER_CPU(struct cpuidle_device, pseries_dev);
+
+#define IDLE_STATE_COUNT 2
+
+/* pSeries Idle state Flags */
+#definePSERIES_DEDICATED_SNOOZE(0x01)
+#definePSERIES_DEDICATED_CEDE (0x02)
+#definePSERIES_SHARED_CEDE (0x03)
+
+static int pseries_idle_init(struct cpuidle_device *dev)
+{
+ return cpuidle_register_device(dev);
+}
+
+static void shared_cede_loop(void)
+{
+ get_lppaca()-idle = 1;
+ cede_processor();
+ get_lppaca()-idle = 0;
+}
+
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
On Wed, Oct 7, 2009 at 1:09 AM, Rob Landley r...@landley.net wrote: On Tuesday 06 October 2009 23:49:04 Grant Likely wrote: However, I've completely devoted to this work for at least the next two months, so there are plenty more patches to follow. Once I've got all the common code merged between Microblaze, PowerPC and Sparc I'll be fix the endian problems and making it easily usable by other architectures like ARM and MIPS. Lots of work to be done. Is there any news on getting QEMU to parse a device tree to figure out what hardware to emulate? (I.E. using the device tree code to let qemu provide configurable board emulations instead of hardwiring them in C code?) Not that I have, but I expect that I will be hacking on QEMU as part of this work. Also, what would be involved in getting x86 to (at least have the option to) use the device tree stuff? It would be very easy once the endian issues are worked out since the device tree is just a data format to be parsed. g. -- Grant Likely, B.Sc., P.Eng. Secret Lab Technologies Ltd. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [microblaze-uclinux] Re: [RFC PATCH 05/12] of: add common header for flattened device tree representation
Grant Likely wrote: On Wed, Oct 7, 2009 at 6:14 AM, Michal Simek mon...@monstr.eu wrote: Stephen Rothwell wrote: Hi Grant, Just first obvious thing: On Tue, 06 Oct 2009 22:30:59 -0600 Grant Likely grant.lik...@secretlab.ca wrote: diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h index 64e8b3a..5f461f0 100644 --- a/arch/microblaze/include/asm/prom.h +++ b/arch/microblaze/include/asm/prom.h @@ -17,20 +17,10 @@ #ifndef _ASM_MICROBLAZE_PROM_H #define _ASM_MICROBLAZE_PROM_H #ifdef __KERNEL__ - -/* Definitions used by the flattened device tree */ -#define OF_DT_HEADER0xd00dfeed /* marker */ This is used in arch/microblaze/kernel/head.S, but you move its definition inside #ifndef __ASSEMBLY__ below. You should probably replace the include of asm/prom.h in arch/microblaze/kernel/head.S with linux/of_fdt.h (assuming that the comment in there is correct). yes, Stephen is right here. I created one patch (in attachment) which fixed it. I tested your patches on Microblaze (noMMU and MMU) and I have no problem with compilation and simple boot-up works for both versions too. With that my patch: Acked-by: Michal Simek mon...@monstr.eu Thanks. I'll merge your change with my patch so that bisect isn't broken. if is possible to do it, please do it. Thanks, Michal g. -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [microblaze-uclinux] Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
Grant Likely wrote: On Wed, Oct 7, 2009 at 1:09 AM, Rob Landley r...@landley.net wrote: On Tuesday 06 October 2009 23:49:04 Grant Likely wrote: However, I've completely devoted to this work for at least the next two months, so there are plenty more patches to follow. Once I've got all the common code merged between Microblaze, PowerPC and Sparc I'll be fix the endian problems and making it easily usable by other architectures like ARM and MIPS. Lots of work to be done. Is there any news on getting QEMU to parse a device tree to figure out what hardware to emulate? (I.E. using the device tree code to let qemu provide configurable board emulations instead of hardwiring them in C code?) Not that I have, but I expect that I will be hacking on QEMU as part of this work. ok great. Just let us know - we will test it. Thanks, Michal Also, what would be involved in getting x86 to (at least have the option to) use the device tree stuff? It would be very easy once the endian issues are worked out since the device tree is just a data format to be parsed. g. -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7 PATCH 3/7]: x86: refactor x86 idle power management code and remove all instances of pm_idle.
On Tue, 2009-10-06 at 21:01 +0530, Arun R Bharadwaj wrote:
+++ linux.trees.git/arch/x86/kernel/process.c
@@ -9,6 +9,7 @@
#include linux/pm.h
#include linux/clockchips.h
#include linux/random.h
+#include linux/cpuidle.h
#include trace/events/power.h
#include asm/system.h
#include asm/apic.h
@@ -244,12 +245,6 @@ int sys_vfork(struct pt_regs *regs)
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);
-/*
- * Powermanagement idle function, if any..
- */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
-
#ifdef CONFIG_X86_32
/*
* This halt magic was a workaround for ancient floppy DMA
@@ -329,17 +324,15 @@ static void do_nothing(void *unused)
}
/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
+ * cpu_idle_wait - Required while changing idle routine handler on SMP
systems.
*
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this
function.
+ * Caller must have changed idle routine to the new value before the call.
Old
+ * value will not be used by any CPU after the return of this function.
*/
void cpu_idle_wait(void)
{
smp_mb();
- /* kick all the CPUs so that they exit out of pm_idle */
+ /* kick all the CPUs so that they exit out of idle loop */
smp_call_function(do_nothing, NULL, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);
@@ -518,15 +511,59 @@ static void c1e_idle(void)
default_idle();
}
+static void (*local_idle)(void);
+DEFINE_PER_CPU(struct cpuidle_device, idle_devices);
+
+struct cpuidle_driver cpuidle_default_driver = {
+ .name = cpuidle_default,
+};
+
+static int local_idle_loop(struct cpuidle_device *dev, struct cpuidle_state
*st)
+{
+ ktime_t t1, t2;
+ s64 diff;
+ int ret;
+
+ t1 = ktime_get();
+ local_idle();
+ t2 = ktime_get();
+
+ diff = ktime_to_us(ktime_sub(t2, t1));
+ if (diff INT_MAX)
+ diff = INT_MAX;
+ ret = (int) diff;
+
+ return ret;
+}
+
+static int setup_cpuidle_simple(void)
+{
+ struct cpuidle_device *dev;
+ int cpu;
+
+ if (!cpuidle_curr_driver)
+ cpuidle_register_driver(cpuidle_default_driver);
+
+ for_each_online_cpu(cpu) {
+ dev = per_cpu(idle_devices, cpu);
+ dev-cpu = cpu;
+ dev-states[0].enter = local_idle_loop;
+ dev-state_count = 1;
+ cpuidle_register_device(dev);
+ }
+ return 0;
+}
+device_initcall(setup_cpuidle_simple);
+
void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
- if (pm_idle == poll_idle smp_num_siblings 1) {
+ if (local_idle == poll_idle smp_num_siblings 1) {
printk(KERN_WARNING WARNING: polling idle and HT enabled,
performance may degrade.\n);
}
#endif
- if (pm_idle)
+ if (local_idle)
return;
if (cpu_has(c, X86_FEATURE_MWAIT) mwait_usable(c)) {
@@ -534,18 +571,20 @@ void __cpuinit select_idle_routine(const
* One CPU supports mwait = All CPUs supports mwait
*/
printk(KERN_INFO using mwait in idle threads.\n);
- pm_idle = mwait_idle;
+ local_idle = mwait_idle;
} else if (check_c1e_idle(c)) {
printk(KERN_INFO using C1E aware idle routine\n);
- pm_idle = c1e_idle;
+ local_idle = c1e_idle;
} else
- pm_idle = default_idle;
+ local_idle = default_idle;
+
+ return;
}
void __init init_c1e_mask(void)
{
/* If we're using c1e_idle, we need to allocate c1e_mask. */
- if (pm_idle == c1e_idle)
+ if (local_idle == c1e_idle)
zalloc_cpumask_var(c1e_mask, GFP_KERNEL);
}
@@ -556,7 +595,7 @@ static int __init idle_setup(char *str)
if (!strcmp(str, poll)) {
printk(using polling idle threads.\n);
- pm_idle = poll_idle;
+ local_idle = poll_idle;
} else if (!strcmp(str, mwait))
force_mwait = 1;
else if (!strcmp(str, halt)) {
@@ -567,7 +606,7 @@ static int __init idle_setup(char *str)
* To continue to load the CPU idle driver, don't touch
* the boot_option_idle_override.
*/
- pm_idle = default_idle;
+ local_idle = default_idle;
idle_halt = 1;
return 0;
} else if (!strcmp(str, nomwait)) {
What guarantees that the cpuidle bits actually select this
Nested function in drivers/of/of_mdio.c
Dear,
I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381
in file drivers/of/of_mdio.c in function of_phy_find_device.
As you see, this function define match() as a nested function. My
compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link
due to this nested definition:
drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device':
/home/jezz/linux-next/drivers/of/of_mdio.c:107:
undefined reference to `__trampoline_setup'
I am sure I could solve problem by rebuilding my toolchain.
Nevertheless, I think nested function definition is not perfectly
supported by all compilers. Also, I suggest to place function match()
outside of scope of of_phy_find_device as in following patch.
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index bacaa53..c7b2e26 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
}
EXPORT_SYMBOL(of_mdiobus_register);
+static int match(struct device *dev, void *phy_np)
+{
+ return dev_archdata_get_node(dev-archdata) == phy_np;
+}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
@@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
- int match(struct device *dev, void *phy_np)
- {
- return dev_archdata_get_node(dev-archdata) == phy_np;
- }
-
if (!phy_np)
return NULL;
What do you think about it?
Best regards,
--
Jérôme Pouiller (jezz AT sysmic DOT org)
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Nested function in drivers/of/of_mdio.c
On Wed, Oct 7, 2009 at 9:15 AM, Jérôme Pouiller j...@sysmic.org wrote:
Dear,
I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381
in file drivers/of/of_mdio.c in function of_phy_find_device.
As you see, this function define match() as a nested function. My
compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link
due to this nested definition:
drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device':
/home/jezz/linux-next/drivers/of/of_mdio.c:107:
undefined reference to `__trampoline_setup'
I am sure I could solve problem by rebuilding my toolchain.
Nevertheless, I think nested function definition is not perfectly
supported by all compilers. Also, I suggest to place function match()
outside of scope of of_phy_find_device as in following patch.
I'm okay with that, but if you're moving code out of the file scope,
then please rename the function to of_phy_match() to avoid global
namespace conflicts.
g.
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index bacaa53..c7b2e26 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
}
EXPORT_SYMBOL(of_mdiobus_register);
+static int match(struct device *dev, void *phy_np)
+{
+ return dev_archdata_get_node(dev-archdata) == phy_np;
+}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
@@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
- int match(struct device *dev, void *phy_np)
- {
- return dev_archdata_get_node(dev-archdata) == phy_np;
- }
-
if (!phy_np)
return NULL;
What do you think about it?
Best regards,
--
Jérôme Pouiller (jezz AT sysmic DOT org)
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: SMU-base PowerMac and server_mode
On Wed, Oct 07, 2009 at 01:25:13PM +0200, Romain Goyet wrote: On Tue, Oct 6, 2009 at 6:07 PM, Olof Johansson o...@lixom.net wrote: Yeah, I had one but I have since lost it. I suspect it was on the drive of my second quad that I wiped before I sold it, thinking there was nothing of value on it. :( Ha, that's too bad. Do you know if it might be online somewhere ? Maybe an idea of the right keywords to google ? I searched for it, couldn't find any trace of it anywhere. I know I based my little tool on some small smu example that came from Ben or possibly Segher. I can't even find that any more. It's been a couple of years since I last touched it. :( -Olof ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Nested function in drivers/of/of_mdio.c
Guys, are there other instances of nested C functions in the codebase
or was this the first attempt?
On Wed, Oct 7, 2009 at 9:11 AM, Grant Likely grant.lik...@secretlab.ca wrote:
On Wed, Oct 7, 2009 at 9:15 AM, Jérôme Pouiller j...@sysmic.org wrote:
Dear,
I have a problem with commit 8bc487d150b939e69830c39322df4ee486efe381
in file drivers/of/of_mdio.c in function of_phy_find_device.
As you see, this function define match() as a nested function. My
compiler (powerpc-e500-linux-gnu-gcc-3.4.1) raise an error during link
due to this nested definition:
drivers/built-in.o(.text+0x5e2a4): In function `of_phy_find_device':
/home/jezz/linux-next/drivers/of/of_mdio.c:107:
undefined reference to `__trampoline_setup'
I am sure I could solve problem by rebuilding my toolchain.
Nevertheless, I think nested function definition is not perfectly
supported by all compilers. Also, I suggest to place function match()
outside of scope of of_phy_find_device as in following patch.
I'm okay with that, but if you're moving code out of the file scope,
then please rename the function to of_phy_match() to avoid global
namespace conflicts.
g.
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index bacaa53..c7b2e26 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -97,6 +97,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
}
EXPORT_SYMBOL(of_mdiobus_register);
+static int match(struct device *dev, void *phy_np)
+{
+ return dev_archdata_get_node(dev-archdata) == phy_np;
+}
/**
* of_phy_find_device - Give a PHY node, find the phy_device
* @phy_np: Pointer to the phy's device tree node
@@ -106,11 +110,6 @@ EXPORT_SYMBOL(of_mdiobus_register);
struct phy_device *of_phy_find_device(struct device_node *phy_np)
{
struct device *d;
- int match(struct device *dev, void *phy_np)
- {
- return dev_archdata_get_node(dev-archdata) == phy_np;
- }
-
if (!phy_np)
return NULL;
What do you think about it?
Best regards,
--
Jérôme Pouiller (jezz AT sysmic DOT org)
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
On Wed, Oct 07, 2009 at 03:18:04PM +1000, Julian Calaby wrote: On Wed, Oct 7, 2009 at 14:49, Grant Likely grant.lik...@secretlab.ca wrote: On Tue, Oct 6, 2009 at 10:29 PM, Grant Likely grant.lik...@secretlab.ca wrote: So here goes. I've begun the work to merge and clean up the OF device tree handling code and this is my first set of patches. Not fully tested yet, but I'm getting them out to the lists so that I can start responding to comments and collecting acks. This first batch isn't anything exciting, just a merge of common code Good work, for what it's worth, this all looks good to me. However, I've completely devoted to this work for at least the next two months, so there are plenty more patches to follow. Once I've got all the common code merged between Microblaze, PowerPC and Sparc I'll be fix the endian problems and making it easily usable by other architectures like ARM and MIPS. Lots of work to be done. On the subject of merging code, I know that the SUN3 code in m68k uses a similar prom interface to the sparc32 code. (and I've also considered unifying that and ... well ... see above) Does anyone know if it has an OpenFirmware interface for it's devices? Is OF on SUN3 even remotely useful? Does Linux on SUN3 even work with modern kernels? Sun3 doesn't have OF, though I've got some dormant patches to add an OF emulation layer to make it easier to reuse Sparc drivers on Sun3... Never finished enough to submit, so it probably shouldn't affect anything you're doing here. As for recent kernels, I think 2.6.19 was the last sun3 I distributed patches for, so modern might be pushing it... -- Sam ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [v7 PATCH 3/7]: x86: refactor x86 idle power management code and remove all instances of pm_idle.
* Peter Zijlstra a.p.zijls...@chello.nl [2009-10-07 16:45:50]:
On Tue, 2009-10-06 at 21:01 +0530, Arun R Bharadwaj wrote:
+++ linux.trees.git/arch/x86/kernel/process.c
@@ -9,6 +9,7 @@
#include linux/pm.h
#include linux/clockchips.h
#include linux/random.h
+#include linux/cpuidle.h
#include trace/events/power.h
#include asm/system.h
#include asm/apic.h
@@ -244,12 +245,6 @@ int sys_vfork(struct pt_regs *regs)
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);
-/*
- * Powermanagement idle function, if any..
- */
-void (*pm_idle)(void);
-EXPORT_SYMBOL(pm_idle);
-
#ifdef CONFIG_X86_32
/*
* This halt magic was a workaround for ancient floppy DMA
@@ -329,17 +324,15 @@ static void do_nothing(void *unused)
}
/*
- * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
- * pm_idle and update to new pm_idle value. Required while changing pm_idle
- * handler on SMP systems.
+ * cpu_idle_wait - Required while changing idle routine handler on SMP
systems.
*
- * Caller must have changed pm_idle to the new value before the call. Old
- * pm_idle value will not be used by any CPU after the return of this
function.
+ * Caller must have changed idle routine to the new value before the call.
Old
+ * value will not be used by any CPU after the return of this function.
*/
void cpu_idle_wait(void)
{
smp_mb();
- /* kick all the CPUs so that they exit out of pm_idle */
+ /* kick all the CPUs so that they exit out of idle loop */
smp_call_function(do_nothing, NULL, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);
@@ -518,15 +511,59 @@ static void c1e_idle(void)
default_idle();
}
+static void (*local_idle)(void);
+DEFINE_PER_CPU(struct cpuidle_device, idle_devices);
+
+struct cpuidle_driver cpuidle_default_driver = {
+ .name = cpuidle_default,
+};
+
+static int local_idle_loop(struct cpuidle_device *dev, struct
cpuidle_state *st)
+{
+ ktime_t t1, t2;
+ s64 diff;
+ int ret;
+
+ t1 = ktime_get();
+ local_idle();
+ t2 = ktime_get();
+
+ diff = ktime_to_us(ktime_sub(t2, t1));
+ if (diff INT_MAX)
+ diff = INT_MAX;
+ ret = (int) diff;
+
+ return ret;
+}
+
+static int setup_cpuidle_simple(void)
+{
+ struct cpuidle_device *dev;
+ int cpu;
+
+ if (!cpuidle_curr_driver)
+ cpuidle_register_driver(cpuidle_default_driver);
+
+ for_each_online_cpu(cpu) {
+ dev = per_cpu(idle_devices, cpu);
+ dev-cpu = cpu;
+ dev-states[0].enter = local_idle_loop;
+ dev-state_count = 1;
+ cpuidle_register_device(dev);
+ }
+ return 0;
+}
+device_initcall(setup_cpuidle_simple);
+
void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
{
#ifdef CONFIG_SMP
- if (pm_idle == poll_idle smp_num_siblings 1) {
+ if (local_idle == poll_idle smp_num_siblings 1) {
printk(KERN_WARNING WARNING: polling idle and HT enabled,
performance may degrade.\n);
}
#endif
- if (pm_idle)
+ if (local_idle)
return;
if (cpu_has(c, X86_FEATURE_MWAIT) mwait_usable(c)) {
@@ -534,18 +571,20 @@ void __cpuinit select_idle_routine(const
* One CPU supports mwait = All CPUs supports mwait
*/
printk(KERN_INFO using mwait in idle threads.\n);
- pm_idle = mwait_idle;
+ local_idle = mwait_idle;
} else if (check_c1e_idle(c)) {
printk(KERN_INFO using C1E aware idle routine\n);
- pm_idle = c1e_idle;
+ local_idle = c1e_idle;
} else
- pm_idle = default_idle;
+ local_idle = default_idle;
+
+ return;
}
void __init init_c1e_mask(void)
{
/* If we're using c1e_idle, we need to allocate c1e_mask. */
- if (pm_idle == c1e_idle)
+ if (local_idle == c1e_idle)
zalloc_cpumask_var(c1e_mask, GFP_KERNEL);
}
@@ -556,7 +595,7 @@ static int __init idle_setup(char *str)
if (!strcmp(str, poll)) {
printk(using polling idle threads.\n);
- pm_idle = poll_idle;
+ local_idle = poll_idle;
} else if (!strcmp(str, mwait))
force_mwait = 1;
else if (!strcmp(str, halt)) {
@@ -567,7 +606,7 @@ static int __init idle_setup(char *str)
* To continue to load the CPU idle driver, don't touch
* the boot_option_idle_override.
*/
- pm_idle = default_idle;
+
RE: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
-Original Message- From: devicetree-discuss-bounces+stephen.neuendorffer=xilinx@lists.ozlabs. org [mailto:devicetree- discuss-bounces+stephen.neuendorffer=xilinx@lists.ozlabs.org] On Behalf Of David Miller Sent: Wednesday, October 07, 2009 12:27 AM To: grant.lik...@secretlab.ca Cc: s...@canb.auug.org.au; devicetree-disc...@lists.ozlabs.org; microblaze-ucli...@itee.uq.edu.au; sparcli...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org Subject: Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code From: Grant Likely grant.lik...@secretlab.ca Date: Tue, 6 Oct 2009 22:49:04 -0600 Also, I'd like to take on responsibility for maintaining the cross- architecture device tree code. If there are no objections, I'll write a patch to add a device tree section to MAINTAINERS. Feel free. And also feel free to add my: Acked-by: David S. Miller da...@davemloft.net to your patches. Thanks for doing this, Grant It's definitely needed. Acked-by: Stephen Neuendorffer stephen.neuendorf...@xilinx.com Steve This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Trouble with canyonlands and PCI-E LSI SAS Controller
Hello, I've got some trouble getting an LSI SAS controller (LSISAS200) to function. It is at least enumerated correctly in a PC running ubuntu, so it seems that it must be something particular to the PCI implementation on the powerpc or the usage of u-boot. If the board is initialized by u-boot, and the BAR0 is written, then the board does not seem to respond to cfgrds when linux probes. And the kernel crashes when the scsi low level are loaded. If u-boot is inhibited and therefore linux sees the card in its reset state then it will boot ok, but an lspci will show the card as disabled. The last issue, is that I am not quite sure exactly which kernel drivers are needed for this device. Here is the output from DEBUG=1 in the pci_probe. The first is without the fusion driver, and the latter is with the fusion driver. Thanks Ayman # dmesg Bus: primary=80, secondary=81, subordinate=bf, sec-latency=0 Using PowerPC 44x Platform machine description Linux version 2.6.31 (b...@lablinux) (gcc version 4.2.2) #61 Tue Oct 6 08:25:39 CDT 2009 Found initrd at 0xdfb09000:0xdfe4cc6eidge: 8010-801f Found legacy serial port 0 for /plb/opb/ser...@ef600300 mem=4ef600300, taddr=4ef600300, irq=0, clk=6451612, speed=0 Found legacy serial port 1 for /plb/opb/ser...@ef600400: Mask- 64bit+ Queue=0/2 Enable- mem=4ef600400, taddr=4ef600400, irq=0, clk=6451612, speed=0 Found legacy serial port 2 for /plb/opb/ser...@ef600500 mem=4ef600500, taddr=4ef600500, irq=0, clk=6451612, speed=0 Found legacy serial port 3 for /plb/opb/ser...@ef600600 mem=4ef600600, taddr=4ef600600, irq=0, clk=6451612, speed=0 Top of RAM: 0x2000, Total RAM: 0x2000 Memory hole size: 0MBevsel, IRQ 18 Zone PFN ranges:s at 1000 [disabled] [size=256] DMA 0x - 0x0002, non-prefetchable) [disabled] [size=16K] Normal 0x0002 - 0x0002, non-prefetchable) [disabled] [size=256K] HighMem 0x0002 - 0x0002e8010 [disabled] [size=512K] Movable zone start PFN for each nodeagement version 3 early_node_map[1] active PFN rangesEndpoint IRQ 0 0: 0x - 0x0002l Product Data On node 0 totalpages: 131072essage Signalled Interrupts: Mask- 64bit+ Queue=0/0 Enable- free_area_init_node: node 0, pgdat c0335654, node_mem_map c0363000 DMA zone: 1024 pages used for memmaprror Reporting DMA zone: 0 pages reservedPower Budgeting DMA zone: 130048 pages, LIFO batch:31 MMU: Allocated 1088 bytes of context maps for 255 contexts Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048 Kernel command line: root=/dev/ram rw mem=128M mem=512M ip=169.254.0.181:169.254.0.100:169.254.0 PID hash table entries: 2048 (order: 11, 8192 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) High memory: 0k Memory: 512512k/524288k available (3168k kernel code, 11356k reserved, 128k data, 132k bss, 160) Kernel virtual memory layout: * 0xfffef000..0xf000 : fixmap * 0xffc0..0xffe0 : highmem PTEs * 0xffa0..0xffc0 : consistent mem * 0xffa0..0xffa0 : early ioremap * 0xe100..0xffa0 : vmalloc ioremap SLUB: Genslabs=11, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 NR_IRQS:512 UIC0 (32 IRQ sources) at DCR 0xc0 UIC1 (32 IRQ sources) at DCR 0xd0 irq: irq 30 on host /interrupt-controller0 mapped to virtual irq 30 UIC2 (32 IRQ sources) at DCR 0xe0 irq: irq 10 on host /interrupt-controller0 mapped to virtual irq 16 UIC3 (32 IRQ sources) at DCR 0xf0 irq: irq 16 on host /interrupt-controller0 mapped to virtual irq 17 time_init: decrementer frequency = 800.10 MHz time_init: processor frequency = 800.10 MHz clocksource: timebase mult[50] shift[22] registered clockevent: decrementer mult[ccf7] shift[32] cpu[0] Mount-cache hash table entries: 512 NET: Registered protocol family 16 irq: irq 23 on host /interrupt-controller2 mapped to virtual irq 23 256k L2-cache enabled PCIE0: Checking link... PCIE0: No device detected. PCI host bridge /plb/pc...@d (primary) ranges: MEM 0x000e..0x000e7fff - 0x8000 IO 0x000f8000..0x000f8000 - 0x 4xx PCI DMA offset set to 0x PCIE0: successfully set as root-complex PCIE1: Checking link... PCIE1: Device detected, waiting for link... PCIE1: link is up ! PCI host bridge /plb/pc...@d2000 (primary) ranges: MEM 0x000e8000..0x000e - 0x8000 IO 0x000f8001..0x000f8001 - 0x 4xx PCI DMA offset set to 0x PCIE1: successfully set as root-complex PCI host bridge /plb/p...@c0ec0 (primary) ranges: MEM 0x000d8000..0x000d - 0x8000 IO 0x000c0800..0x000c0800 - 0x 4xx PCI DMA offset set to 0x PCI: Probing PCI hardware PCI: Scanning bus :40 pci :40:00.0: found [aaa0:bed0] class 000604
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
Sun3 doesn't have OF When I was first developing Open Boot for the SPARCstation-1, I was also simultaneously trying to do it for a Sun-3 system that was being built at the same time. It proved to be too much to do both jobs at the same time, especially in light of all the hardware debugging that is part of a new system bringup. So I gave up on Sun 3 and just focused on SS-1. That particular Sun-3 machine never sold very well, while the SS-1 was very popular. That was Sun's last 680x0 machine. Personally, I think that continuing to support Sun-3 in Linux is not useful in a practical sense. To the extent that supporting long-obsolete platforms and devices makes the job harder for current systems, it is actually harmful. Portability and generality is good in some theoretical rightness sense, but there are practical limits. Code can become so heavily layered that approaching it requires a huge commitment of effort to learn all the artificial layers. Sometimes you have to prune the dead branches so the living ones can get light and air. Taking this one step further, I don't see any real good reason to continue supporting Sun4 going forward. I got rid of my Sun4 systems long ago because it was just too hard to keep them working - after having used them long after most people had moved on. Dropping Sun3 and Sun4 eliminates all vestiges of the sunmon interface and also allows dropping support for OBP version 1, which only shipped on SS1-class machines - the first machines in the Sun4c subclass. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 3/6] 8xx: invalidate non present TLBs
8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. --- arch/powerpc/mm/fault.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 7699394..72941c7 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -39,7 +39,7 @@ #include asm/uaccess.h #include asm/tlbflush.h #include asm/siginfo.h - +#include mm/mmu_decl.h #ifdef CONFIG_KPROBES static inline int notify_page_fault(struct pt_regs *regs) @@ -243,6 +243,12 @@ good_area: goto bad_area; #endif /* CONFIG_6xx */ #if defined(CONFIG_8xx) + /* 8xx sometimes need to load a invalid/non-present TLBs. +* These must be invalidated separately as linux mm don't. +*/ + if (error_code 0x4000) /* no translation? */ + _tlbil_va(address); + /* The MPC8xx seems to always set 0x8000, which is * undefined. Of those that can be set, this is the only * one which seems bad. -- 1.6.4.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 0/6] 8xx TLB fixes.
OK, here is the next try att fixing the MPC8xx MMU problems. Pleas add one(or two) patches at a time and test. Expect some trivial merge conflicts in 8xx header file, sorry about that. Joakim Tjernlund (6): 8xx: DTLB Error must check for more errors. 8xx: get rid of _PAGE_HWWRITE dependency in MMU. 8xx: invalidate non present TLBs 8xx: Tag DAR with 0x00f0 to catch buggy instructions. 8xx: Fixup DAR from buggy dcbX instructions. 8xx: start using dcbX instructions in various copy routines arch/powerpc/include/asm/pte-8xx.h | 13 +- arch/powerpc/kernel/head_8xx.S | 243 +--- arch/powerpc/kernel/misc_32.S | 18 --- arch/powerpc/lib/copy_32.S | 24 arch/powerpc/mm/fault.c|8 +- 5 files changed, 209 insertions(+), 97 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED. Pros: - I/D TLB Miss never needs to write to the linux pte. - _PAGE_ACCESSED is only set on TLB Error fixing accounting - _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly when a page has been made dirty. - Proper RO/RW mapping of user space. - Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?) Cons: - 1 more instructions in I/D TLB Miss, but the since the linux pte is not written anymore, it should still be a big win. --- arch/powerpc/include/asm/pte-8xx.h | 13 +++--- arch/powerpc/kernel/head_8xx.S | 82 2 files changed, 43 insertions(+), 52 deletions(-) diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h index 8c6e312..f23cd15 100644 --- a/arch/powerpc/include/asm/pte-8xx.h +++ b/arch/powerpc/include/asm/pte-8xx.h @@ -32,22 +32,21 @@ #define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */ #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */ #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */ +#define _PAGE_DIRTY0x0100 /* C: page changed */ -/* These five software bits must be masked out when the entry is loaded - * into the TLB. +/* These 3 software bits must be masked out when the entry is loaded + * into the TLB, 2 SW bits left. */ #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ -#define _PAGE_DIRTY0x0020 /* software: page changed */ -#define _PAGE_RW 0x0040 /* software: user write access allowed */ -#define _PAGE_ACCESSED 0x0080 /* software: page referenced */ +#define _PAGE_ACCESSED 0x0020 /* software: page referenced */ /* Setting any bits in the nibble with the follow two controls will * require a TLB exception handler change. It is assumed unused bits * are always zero. */ -#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ -#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER~RW */ +#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */ +#define _PAGE_USER 0x0800 /* msb PP bits */ #define _PMD_PRESENT 0x0001 #define _PMD_BAD 0x0ff0 diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 118bb05..3cf1289 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -333,26 +333,18 @@ InstructionTLBMiss: mfspr r11, SPRN_MD_TWC/* and get the pte address */ lwz r10, 0(r11) /* Get the pte */ -#ifdef CONFIG_SWAP - /* do not set the _PAGE_ACCESSED bit of a non-present page */ - andi. r11, r10, _PAGE_PRESENT - beq 4f - ori r10, r10, _PAGE_ACCESSED - mfspr r11, SPRN_MD_TWC/* get the pte address again */ - stw r10, 0(r11) -4: -#else - ori r10, r10, _PAGE_ACCESSED - stw r10, 0(r11) -#endif + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED + bne-cr0, 2f + /* Dont' bother with PP lsb, bit 21 for now */ /* The Linux PTE won't go exactly into the MMU TLB. -* Software indicator bits 21, 22 and 28 must be clear. +* Software indicator bits 22 and 28 must be clear. * Software indicator bits 24, 25, 26, and 27 must be * set. All other Linux PTE bits control the behavior * of the MMU. */ -2: li r11, 0x00f0 + li r11, 0x00f0 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x2d80, r3) mtspr SPRN_MI_RPN, r10/* Update TLB entry */ @@ -365,6 +357,19 @@ InstructionTLBMiss: lwz r3, 8(r0) #endif rfi +2: + mfspr r11, SRR1 + rlwinm r11, r11, 0, 5, 3 /* clear guarded */ + mtspr SRR1, r11 + + mfspr r10, SPRN_M_TW /* Restore registers */ + lwz r11, 0(r0) + mtcrr11 + lwz r11, 4(r0) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) +#endif + b InstructionAccess . = 0x1200 DataStoreTLBMiss: @@ -409,21 +414,14 @@ DataStoreTLBMiss: DO_8xx_CPU6(0x3b80, r3) mtspr SPRN_MD_TWC, r11 -#ifdef CONFIG_SWAP - /* do not set the _PAGE_ACCESSED bit of a non-present page */ - andi. r11, r10, _PAGE_PRESENT - beq 4f - ori r10, r10, _PAGE_ACCESSED -4: - /* and update pte in table */ -#else - ori r10, r10, _PAGE_ACCESSED -#endif - mfspr r11, SPRN_MD_TWC/* get the pte address again */ - stw r10, 0(r11) + andi. r11, r10, _PAGE_ACCESSED + bne+cr0, 5f /* branch if access allowed */ + rlwinm r10, r10, 0, 21, 19 /* Clear _PAGE_USER */ + ori r10, r10, _PAGE_RW /* Set RW bit for xor below to clear it */ +5: xorir10, r10,
[PATCH 5/6] 8xx: Fixup DAR from buggy dcbX instructions.
This is an assembler version to fixup DAR not being set by dcbX, icbi instructions. There are two versions, one uses selfmodifing code(default), the other uses jump table but is much bigger. --- arch/powerpc/kernel/head_8xx.S | 146 +++- 1 files changed, 145 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 37aa7d0..8c4c416 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -476,7 +476,8 @@ DataTLBError: mfspr r10, SPRN_DAR cmpwi cr0, r10, 0x00f0 - beq-2f /* must be a buggy dcbX, icbi insn. */ + beq-FixDAR /* must be a buggy dcbX, icbi insn. */ +DARFix:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ /* First, make sure this was a store operation. */ @@ -593,6 +594,149 @@ DataTLBError: . = 0x2000 +/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions + * by decoding the registers used by the dcbx instruction and adding them. + * DAR is set to the calculated address and r10 also holds the EA on exit. + */ +//#define NO_SELF_MODIFYING_CODE /* define if you don't want to use self modifying code */ + nop /* A few nops to make the modified_instr: space below cache line aligned */ + nop +139: /* fetch instruction from userspace memory */ + DO_8xx_CPU6(0x3780, r3) + mtspr SPRN_MD_EPN, r10 + mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ + lwz r11, 0(r11) /* Get the level 1 entry */ + tophys (r11, r11) + DO_8xx_CPU6(0x3b80, r3) + mtspr SPRN_MD_TWC, r11/* Load pte table base address */ + mfspr r11, SPRN_MD_TWC/* and get the pte address */ + lwz r11, 0(r11) /* Get the pte */ + /* concat physical page address(r11) and page offset(r10) */ + rlwimi r11, r10, 0, 20, 31 + b 140f +FixDAR:/* Entry point for dcbx workaround. */ + /* fetch instruction from memory. */ + mfspr r10, SPRN_SRR0 + andis. r11, r10, 0x8000 + tophys (r11, r10) + beq-139b/* Branch if user space address */ +140: lwz r11,0(r11) +#ifdef CONFIG_8xx_CPU6 + lwz r3, 8(r0) /* restore r3 from memory */ +#endif +#ifndef NO_SELF_MODIFYING_CODE + andis. r10,r11,0x1f/* test if reg RA is r0 */ + li r10,modified_in...@l + dcbtst r0,r10 /* touch for store */ + rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ + orisr11,r11,640 /* Transform instr. to a add r10,RA,RB */ + ori r11,r11,532 + stw r11,0(r10) /* store add/and instruction */ + dcbf0,r10 /* flush new instr. to memory. */ + icbi0,r10 /* invalidate instr. cache line */ + lwz r11, 4(r0) /* restore r11 from memory */ + mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ + isync /* Wait until new instr is loaded from memory */ +modified_instr: + .space 4 /* this is where the add/and instr. is stored */ + bne+143f + subfr10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ +143: mtdar r10 /* store faulting EA in DAR */ + b DARFix /* Go back to normal TLB handling */ +#else + mfctr r10 + mtdar r10 /* save ctr reg in DAR */ + rlwinm r10, r11, 24, 24, 28/* offset into jump table for reg RB */ + addir10, r10, 1...@l/* add start of table */ + mtctr r10 /* load ctr with jump address */ + xor r10, r10, r10 /* sum starts at zero */ + bctr/* jump into table */ +150: + add r10, r10, r0 + b 151f + add r10, r10, r1 + b 151f + add r10, r10, r2 + b 151f + add r10, r10, r3 + b 151f + add r10, r10, r4 + b 151f + add r10, r10, r5 + b 151f + add r10, r10, r6 + b 151f + add r10, r10, r7 + b 151f + add r10, r10, r8 + b 151f + add r10, r10, r9 + b 151f + add r10, r10, r10 + b 151f + add r10, r10, r11 + b 151f + add r10, r10, r12 + b 151f + add r10, r10, r13 + b 151f + add r10, r10, r14 + b 151f + add r10, r10, r15 + b 151f + add r10, r10, r16 + b 151f + add r10, r10, r17 + b 151f + add r10, r10, r18 + b 151f + add r10, r10, r19 + b 151f + mtctr r11 /* r10 needs special handling */ + b 154f
[PATCH 6/6] 8xx: start using dcbX instructions in various copy routines
Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. --- arch/powerpc/kernel/misc_32.S | 18 -- arch/powerpc/lib/copy_32.S| 24 2 files changed, 0 insertions(+), 42 deletions(-) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 15f28e0..b92095e 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -495,15 +495,7 @@ _GLOBAL(clear_pages) li r0,PAGE_SIZE/L1_CACHE_BYTES slw r0,r0,r4 mtctr r0 -#ifdef CONFIG_8xx - li r4, 0 -1: stw r4, 0(r3) - stw r4, 4(r3) - stw r4, 8(r3) - stw r4, 12(r3) -#else 1: dcbz0,r3 -#endif addir3,r3,L1_CACHE_BYTES bdnz1b blr @@ -528,15 +520,6 @@ _GLOBAL(copy_page) addir3,r3,-4 addir4,r4,-4 -#ifdef CONFIG_8xx - /* don't use prefetch on 8xx */ - li r0,4096/L1_CACHE_BYTES - mtctr r0 -1: COPY_16_BYTES - bdnz1b - blr - -#else /* not 8xx, we can prefetch */ li r5,4 #if MAX_COPY_PREFETCH 1 @@ -577,7 +560,6 @@ _GLOBAL(copy_page) li r0,MAX_COPY_PREFETCH li r11,4 b 2b -#endif /* CONFIG_8xx */ /* * void atomic_clear_mask(atomic_t mask, atomic_t *addr) diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index c657de5..74a7f41 100644 --- a/arch/powerpc/lib/copy_32.S +++ b/arch/powerpc/lib/copy_32.S @@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero) bdnz4b 3: mtctr r9 li r7,4 -#if !defined(CONFIG_8xx) 10:dcbzr7,r6 -#else -10:stw r4, 4(r6) - stw r4, 8(r6) - stw r4, 12(r6) - stw r4, 16(r6) -#if CACHE_LINE_SIZE = 32 - stw r4, 20(r6) - stw r4, 24(r6) - stw r4, 28(r6) - stw r4, 32(r6) -#endif /* CACHE_LINE_SIZE */ -#endif addir6,r6,CACHELINE_BYTES bdnz10b clrlwi r5,r8,32-LG_CACHELINE_BYTES @@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy) mtctr r0 beq 63f 53: -#if !defined(CONFIG_8xx) dcbzr11,r6 -#endif COPY_16_BYTES #if L1_CACHE_BYTES = 32 COPY_16_BYTES @@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user) li r11,4 beq 63f -#ifdef CONFIG_8xx - /* Don't use prefetch on 8xx */ - mtctr r0 - li r0,0 -53:COPY_16_BYTES_WITHEX(0) - bdnz53b - -#else /* not CONFIG_8xx */ /* Here we decide how far ahead to prefetch the source */ li r3,4 cmpwi r0,1 @@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user) li r3,4 li r7,0 bne 114b -#endif /* CONFIG_8xx */ 63:srwi. r0,r5,2 mtctr r0 -- 1.6.4.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). --- arch/powerpc/kernel/head_8xx.S | 19 --- 1 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3cf1289..37aa7d0 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -206,6 +206,8 @@ MachineCheck: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) + li r5,0x00f0 + mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addi r3,r1,STACK_FRAME_OVERHEAD @@ -222,6 +224,8 @@ DataAccess: stw r10,_DSISR(r11) mr r5,r10 mfspr r4,SPRN_DAR + li r10,0x00f0 + mtspr SPRN_DAR,r10/* Tag DAR, to be used in DTLB Error */ EXC_XFER_EE_LITE(0x300, handle_page_fault) /* Instruction access exception. @@ -244,6 +248,8 @@ Alignment: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) + li r5,0x00f0 + mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addir3,r1,STACK_FRAME_OVERHEAD @@ -427,6 +433,7 @@ DataStoreTLBMiss: * of the MMU. */ 2: li r11, 0x00f0 + mtspr SPRN_DAR,r11/* Tag DAR */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10/* Update TLB entry */ @@ -467,10 +474,14 @@ DataTLBError: stw r10, 0(r0) stw r11, 4(r0) + mfspr r10, SPRN_DAR + cmpwi cr0, r10, 0x00f0 + beq-2f /* must be a buggy dcbX, icbi insn. */ + /* First, make sure this was a store operation. */ - mfspr r10, SPRN_DSISR - andis. r11, r10, 0x4000 /* no translation */ + mfspr r11, SPRN_DSISR + andis. r11, r11, 0x4000 /* no translation */ bne 2f /* branch if set */ /* The EA of a data TLB miss is automatically stored in the MD_EPN @@ -489,7 +500,8 @@ DataTLBError: * are initialized in mapin_ram(). This will avoid the problem, * assuming we only use the dcbi instruction on kernel addresses. */ - mfspr r10, SPRN_DAR + + /* DAR is in r10 already */ rlwinm r11, r10, 0, 0, 19 ori r11, r11, MD_EVALID mfspr r10, SPRN_M_CASID @@ -539,6 +551,7 @@ DataTLBError: * of the MMU. */ li r11, 0x00f0 + mtspr SPRN_DAR,r11/* Tag DAR */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10/* Update TLB entry */ -- 1.6.4.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Chris Newport c...@netunix.com Date: Wed, 7 Oct 2009 21:54:34 +0100 (BST) Sun4c has also been broken for a long time and sun4d has never worked properly. Is it time to also prune these ?. That would leave only Sun4m in the 32bit kernel, which still works and has plenty of ongoing user interest. Chris don't over-exaggerate the state. The truth is that the whole sparc32 port is in a state of mild disrepair, and many of the issues apply to all the port rather than just one family of systems. I think someone suitably motivated could get most of the bugs sorted out. There is no reason to drop support for SS1 machines, we already fully build the software device tree and use all of the generic OF infrastructure in the Linux kernel on those systems. It is not a road block at all for the OF genericization work, if that's what you read into wmb's email. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
On Wed, 7 Oct 2009, Mitch Bradley wrote: Taking this one step further, I don't see any real good reason to continue supporting Sun4 going forward. I got rid of my Sun4 systems long ago because it was just too hard to keep them working - after having used them long after most people had moved on. Dropping Sun3 and Sun4 eliminates all vestiges of the sunmon interface and also allows dropping support for OBP version 1, which only shipped on SS1-class machines - the first machines in the Sun4c subclass. Sun4c has also been broken for a long time and sun4d has never worked properly. Is it time to also prune these ?. That would leave only Sun4m in the 32bit kernel, which still works and has plenty of ongoing user interest. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/6] 8xx: invalidate non present TLBs
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: 8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. not sure about the dsisr test here, what is the point ? Cheers, Ben. --- arch/powerpc/mm/fault.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 7699394..72941c7 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -39,7 +39,7 @@ #include asm/uaccess.h #include asm/tlbflush.h #include asm/siginfo.h - +#include mm/mmu_decl.h #ifdef CONFIG_KPROBES static inline int notify_page_fault(struct pt_regs *regs) @@ -243,6 +243,12 @@ good_area: goto bad_area; #endif /* CONFIG_6xx */ #if defined(CONFIG_8xx) + /* 8xx sometimes need to load a invalid/non-present TLBs. + * These must be invalidated separately as linux mm don't. + */ + if (error_code 0x4000) /* no translation? */ + _tlbil_va(address); + /* The MPC8xx seems to always set 0x8000, which is * undefined. Of those that can be set, this is the only * one which seems bad. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Why not -1 ? :-) Ben. --- arch/powerpc/kernel/head_8xx.S | 19 --- 1 files changed, 16 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 3cf1289..37aa7d0 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -206,6 +206,8 @@ MachineCheck: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) + li r5,0x00f0 + mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addi r3,r1,STACK_FRAME_OVERHEAD @@ -222,6 +224,8 @@ DataAccess: stw r10,_DSISR(r11) mr r5,r10 mfspr r4,SPRN_DAR + li r10,0x00f0 + mtspr SPRN_DAR,r10/* Tag DAR, to be used in DTLB Error */ EXC_XFER_EE_LITE(0x300, handle_page_fault) /* Instruction access exception. @@ -244,6 +248,8 @@ Alignment: EXCEPTION_PROLOG mfspr r4,SPRN_DAR stw r4,_DAR(r11) + li r5,0x00f0 + mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ mfspr r5,SPRN_DSISR stw r5,_DSISR(r11) addir3,r1,STACK_FRAME_OVERHEAD @@ -427,6 +433,7 @@ DataStoreTLBMiss: * of the MMU. */ 2: li r11, 0x00f0 + mtspr SPRN_DAR,r11/* Tag DAR */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10/* Update TLB entry */ @@ -467,10 +474,14 @@ DataTLBError: stw r10, 0(r0) stw r11, 4(r0) + mfspr r10, SPRN_DAR + cmpwi cr0, r10, 0x00f0 + beq-2f /* must be a buggy dcbX, icbi insn. */ + /* First, make sure this was a store operation. */ - mfspr r10, SPRN_DSISR - andis. r11, r10, 0x4000 /* no translation */ + mfspr r11, SPRN_DSISR + andis. r11, r11, 0x4000 /* no translation */ bne 2f /* branch if set */ /* The EA of a data TLB miss is automatically stored in the MD_EPN @@ -489,7 +500,8 @@ DataTLBError: * are initialized in mapin_ram(). This will avoid the problem, * assuming we only use the dcbi instruction on kernel addresses. */ - mfspr r10, SPRN_DAR + + /* DAR is in r10 already */ rlwinm r11, r10, 0, 0, 19 ori r11, r11, MD_EVALID mfspr r10, SPRN_M_CASID @@ -539,6 +551,7 @@ DataTLBError: * of the MMU. */ li r11, 0x00f0 + mtspr SPRN_DAR,r11/* Tag DAR */ rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ DO_8xx_CPU6(0x3d80, r3) mtspr SPRN_MD_RPN, r10/* Update TLB entry */ ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/6] 8xx: invalidate non present TLBs
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:18:05: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: 8xx sometimes need to load a invalid/non-present TLBs in it DTLB asm handler. These must be invalidated separaly as linux mm don't. not sure about the dsisr test here, what is the point ? To remove the need to do the same in generic pte code. Then we only need to do it when it counts. Lets see how it works out. Cheers, Ben. --- arch/powerpc/mm/fault.c |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c index 7699394..72941c7 100644 --- a/arch/powerpc/mm/fault.c +++ b/arch/powerpc/mm/fault.c @@ -39,7 +39,7 @@ #include asm/uaccess.h #include asm/tlbflush.h #include asm/siginfo.h - +#include mm/mmu_decl.h #ifdef CONFIG_KPROBES static inline int notify_page_fault(struct pt_regs *regs) @@ -243,6 +243,12 @@ good_area: goto bad_area; #endif /* CONFIG_6xx */ #if defined(CONFIG_8xx) + /* 8xx sometimes need to load a invalid/non-present TLBs. +* These must be invalidated separately as linux mm don't. +*/ + if (error_code 0x4000) /* no translation? */ + _tlbil_va(address); + /* The MPC8xx seems to always set 0x8000, which is * undefined. Of those that can be set, this is the only * one which seems bad. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:18:21: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Why not -1 ? :-) Because 0x00f0 is already in use in the TLB fast path, saves one insn. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
On Thu, 2009-10-08 at 00:08 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:14:52: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED + bne- cr0, 2f Did you mean _PAGE_PRESENT | _PAGE_ACCESSED ? +2: + mfspr r11, SRR1 + rlwinm r11, r11, 0, 5, 3 /* clear guarded */ + mtspr SRR1, r11 What is the above for ? TLB Miss will set that bit unconditionally and that is the same bit as protection error in TLB error. And ? Big deal :-) IE. Once you get to InstructionAccess, it doesn't matter if that bit is set, does it ? Lets start simple, shall we? :) Anyhow, I looked some more at that and I don't the best thing is to use shifts. All bits are correct if you invert RW and add an exception for extended coding. Right, as long as you avoid doing a conditional branch :-) Because if you go to C with a protection fault, you are in trouble. Why ? So deal with it here. Now, I got another idea too that will make this go away if it work out I don't understand your point about protection faults. You should be able to go straight to C with -anything-, that's what I do for all other platforms. Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 3/6] 8xx: invalidate non present TLBs
On Thu, 2009-10-08 at 00:12 +0200, Joakim Tjernlund wrote: not sure about the dsisr test here, what is the point ? To remove the need to do the same in generic pte code. Then we only need to do it when it counts. Lets see how it works out. But I'm not sure I trust that DSISR test. Just do it unconditionally... How much does it cost anyway ? Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
On Thu, 2009-10-08 at 00:13 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:18:21: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Why not -1 ? :-) Because 0x00f0 is already in use in the TLB fast path, saves one insn. But will cause weird things if the user really uses 0xf0 (though granted that's unlikely :-) Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
On Wed, Oct 07, 2009 at 09:52:43AM -0400, Sam Creasey wrote: On Wed, Oct 07, 2009 at 03:18:04PM +1000, Julian Calaby wrote: On the subject of merging code, I know that the SUN3 code in m68k uses a similar prom interface to the sparc32 code. (and I've also considered unifying that and ... well ... see above) Does anyone know if it has an OpenFirmware interface for it's devices? Is OF on SUN3 even remotely useful? Does Linux on SUN3 even work with modern kernels? Sun3 doesn't have OF, though I've got some dormant patches to add an OF emulation layer to make it easier to reuse Sparc drivers on Sun3... Never finished enough to submit, so it probably shouldn't affect anything you're doing here. I was also looking at using the OF code on m68k, but for a different reason. My goal was to get macio_bus working so we can merge a few of the m68k Mac drivers into the ppc Mac drivers. The simplest way to do that seemed to be supporting OF since macio_dev is a wrapper for of_device. It was also a nice way to build up a table of all the onboard devices in memory. Hopefully it would enable better user-space device detection as well. I got the framework built against an older kernel, but it wasn't enough to be useful at that point. This set of patches could help quite a bit. Brad Boyer f...@allandria.com ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/6] 8xx: Tag DAR with 0x00f0 to catch buggy instructions.
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 08/10/2009 00:21:24: On Thu, 2009-10-08 at 00:13 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:18:21: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Why not -1 ? :-) Because 0x00f0 is already in use in the TLB fast path, saves one insn. But will cause weird things if the user really uses 0xf0 (though granted that's unlikely :-) Yeah, you will most likely end up with a segv anyway. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 08/10/2009 00:20:17: On Thu, 2009-10-08 at 00:08 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:14:52: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED + bne- cr0, 2f Did you mean _PAGE_PRESENT | _PAGE_ACCESSED ? YES! cut and paste error, will send a new much improved patch with my new idea. +2: + mfspr r11, SRR1 + rlwinm r11, r11, 0, 5, 3 /* clear guarded */ + mtspr SRR1, r11 What is the above for ? TLB Miss will set that bit unconditionally and that is the same bit as protection error in TLB error. And ? Big deal :-) IE. Once you get to InstructionAccess, it doesn't matter if that bit is set, does it ? Yes it does. If one adds HWEXEC it will fail, right? Also this count as a read and you could easily end up in the protection case(in 2.4 you do) Lets start simple, shall we? :) Anyhow, I looked some more at that and I don't the best thing is to use shifts. All bits are correct if you invert RW and add an exception for extended coding. Right, as long as you avoid doing a conditional branch :-) hey, I think you have to show how then :) I am not good at ppc shift, mask, rotate insn. Because if you go to C with a protection fault, you are in trouble. Why ? In 2.4 you end up in read protection fault an get a SEGV back :) So deal with it here. Now, I got another idea too that will make this go away if it work out I don't understand your point about protection faults. You should be able to go straight to C with -anything-, that's what I do for all other platforms. Well, you don't force a tlb error like I do, however my new version handles this better. Now I only handle DIRTY and the rest in C. Figured it is much faster and really simplie now, stay tuned. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Joakim Tjernlund/Transmode wrote on 08/10/2009 01:11:23: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 08/10/2009 00:20:17: On Thu, 2009-10-08 at 00:08 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 07/10/2009 23:14:52: On Wed, 2009-10-07 at 22:46 +0200, Joakim Tjernlund wrote: + andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED + cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED + bne- cr0, 2f Did you mean _PAGE_PRESENT | _PAGE_ACCESSED ? YES! cut and paste error, will send a new much improved patch with my new idea. So here it is(on top for now), what do you think? diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 8c4c416..fea9f5b 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -339,8 +339,8 @@ InstructionTLBMiss: mfspr r11, SPRN_MD_TWC/* and get the pte address */ lwz r10, 0(r11) /* Get the pte */ - andi. r11, r10, _PAGE_USER | _PAGE_ACCESSED - cmpwi cr0, r11, _PAGE_USER | _PAGE_ACCESSED + andi. r21, r20, _PAGE_ACCESSED | _PAGE_PRESENT + cmpwi cr0, r21, _PAGE_ACCESSED | _PAGE_PRESENT bne-cr0, 2f /* Dont' bother with PP lsb, bit 21 for now */ @@ -365,7 +365,10 @@ InstructionTLBMiss: rfi 2: mfspr r11, SRR1 - rlwinm r11, r11, 0, 5, 3 /* clear guarded */ + /* clear all error bits as TLB Miss +* sets a few unconditionally + */ + rlwinm r21, r21, 0, 0x mtspr SRR1, r11 mfspr r10, SPRN_M_TW /* Restore registers */ @@ -422,8 +425,8 @@ DataStoreTLBMiss: andi. r11, r10, _PAGE_ACCESSED bne+cr0, 5f /* branch if access allowed */ - rlwinm r10, r10, 0, 21, 19 /* Clear _PAGE_USER */ - ori r10, r10, _PAGE_RW /* Set RW bit for xor below to clear it */ + /* Need to know if load/store - force a TLB Error */ + rlwinm r20, r20, 0, 0, 30 /* Clear _PAGE_PRESENT */ 5: xorir10, r10, _PAGE_RW /* invert RW bit */ /* The Linux PTE won't go exactly into the MMU TLB. @@ -482,8 +485,11 @@ DARFix:/* Return from dcbx instruction bug workaround, r10 holds value of DAR * /* First, make sure this was a store operation. */ mfspr r11, SPRN_DSISR - andis. r11, r11, 0x4000 /* no translation */ - bne 2f /* branch if set */ + andis. r21, r21, 0x4800/* !translation or protection */ + bne 2f /* branch if either is set */ + /* Only Change bit left now, do it here as it is faster +* than trapping to the C fault handler. + */ /* The EA of a data TLB miss is automatically stored in the MD_EPN * register. The EA of a data TLB error is automatically stored in @@ -533,16 +539,8 @@ DARFix:/* Return from dcbx instruction bug workaround, r10 holds value of DAR * mfspr r11, SPRN_MD_TWC/* and get the pte address */ lwz r10, 0(r11) /* Get the pte */ - mfspr r11, DSISR - andis. r11, r11, 0x0200/* store */ - beq 5f - andi. r11, r10, _PAGE_RW /* writeable? */ - beq 2f /* nope */ - ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE -5: ori r10, r10, _PAGE_ACCESSED - mfspr r11, MD_TWC /* Get pte address again */ + ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE stw r10, 0(r11) /* and update pte in table */ - xorir10, r10, _PAGE_RW /* RW bit is inverted */ /* The Linux PTE won't go exactly into the MMU TLB. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
Yes it does. If one adds HWEXEC it will fail, right? Why ? We can just filter out DSISR, we don't really care why it failed as long as we know whether it was a store or not. Also this count as a read and you could easily end up in the protection case(in 2.4 you do) I'm not sure what you mean by the protection case Again, the C code shouldn't care. hey, I think you have to show how then :) I am not good at ppc shift, mask, rotate insn. They are so fun ! :-0 Because if you go to C with a protection fault, you are in trouble. Why ? In 2.4 you end up in read protection fault an get a SEGV back :) We probably should ignore the DSISR bits then. So it just goes to generic C code which then fixes up ACCESSED etc... and returns. Now I only handle DIRTY and the rest in C. Figured it is much faster and really simplie now, stay tuned. You should not even have to handle DIRTY at all in asm. At least in 2.6. I can't vouch for what 2.4 generic code does... You should really port your board over :-) Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/6] 8xx: get rid of _PAGE_HWWRITE dependency in MMU.
On Thu, 2009-10-08 at 02:19 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 08/10/2009 02:04:56: Yes it does. If one adds HWEXEC it will fail, right? Why ? We can just filter out DSISR, we don't really care why it failed as long as we know whether it was a store or not. Also this count as a read and you could easily end up in the protection case(in 2.4 you do) I'm not sure what you mean by the protection case Again, the C code shouldn't care. it does, and it should. How else should you know if you try to read a NA space? Generic code should sort it out in handle_mm_fault() (or earlier if it can't find a VMA at all). The DSISR munging is really not necessary I believe. 2.4 and 2.6 have the same handling in asm. Yeah but the C code, especially the generic part, is different. hmm, maybe I should just call C, but 8xx isn't a speed monster so every cycle counts :) But that's a slow path anyways. It works if I trap to C for DIRTY too. Before thinking on porting my old board, I want 2.4 to enjoy the new TLB code too :) Hehehe. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH 00/12] Merge common OpenFirmware device tree code
From: Chris Newport c...@netunix.com Date: Thu, 8 Oct 2009 02:29:25 +0100 (BST) Sun4d has never had SMP support and Wrong. this is apparantly problematic due to Cray interlectual property causing a lack of bus documentation. XBUS documentation is not available, but we fully know how to program the SBUS interrupt controller and whatnot. It's all there in the sun4d interrupt and SMP support and it did work just fine at one point. Amusingly the SBUS interrupt stuff on sun4d is a very close sibling to the IMAP/ICLR scheme used on sun4u. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
