[PATCH] powerpc/fsl: 85xx: add cache-sram support
From: Harninder Rai harninder@freescale.com
It adds cache-sram support in P1/P2 QorIQ platforms as under:
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Drivers can do the following in Kconfig to use these APIs
select FSL_85XX_CACHE_SRAM if MPC85xx
* Required SRAM size and the offset where SRAM should be mapped must be
provided at kernel command line as
cache-sram-size=value
cache-sram-offset=offset
Signed-off-by: Harninder Rai harninder@freescale.com
---
arch/powerpc/include/asm/fsl_85xx_cache_sram.h | 48 +
arch/powerpc/sysdev/Makefile |1 +
arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h | 101 ++
arch/powerpc/sysdev/fsl_85xx_cache_sram.c | 155 +++
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 247
5 files changed, 552 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/include/asm/fsl_85xx_cache_sram.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
create mode 100644 arch/powerpc/sysdev/fsl_85xx_cache_sram.c
create mode 100644 arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
diff --git a/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
new file mode 100644
index 000..2af2bdc
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_85xx_cache_sram.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Cache SRAM handling for QorIQ platform
+ *
+ * Author: Vivek Mahajan vivek.maha...@freescale.com
+
+ * This file is derived from the original work done
+ * by Sylvain Munaut for the Bestcomm SRAM allocator.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
+
+#include asm/rheap.h
+#include linux/spinlock.h
+
+/*
+ * Cache-SRAM
+ */
+
+struct mpc85xx_cache_sram {
+ phys_addr_t base_phys;
+ void *base_virt;
+ unsigned int size;
+ rh_info_t *rh;
+ spinlock_t lock;
+};
+
+extern void mpc85xx_cache_sram_free(void *ptr);
+extern void *mpc85xx_cache_sram_alloc(unsigned int size,
+ phys_addr_t *phys, unsigned int align);
+
+#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5642924..fb60eb1 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_FSL_PMC) += fsl_pmc.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_FSL_GTM) += fsl_gtm.o
obj-$(CONFIG_MPC8xxx_GPIO) += mpc8xxx_gpio.o
+obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o
fsl_85xx_cache_sram.o
obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
obj-$(CONFIG_RAPIDIO) += fsl_rio.o
obj-$(CONFIG_TSI108_BRIDGE)+= tsi108_pci.o tsi108_dev.o
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
new file mode 100644
index 000..62f296e
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc
+ *
+ * QorIQ based Cache Controller Memory Mapped Registers
+ *
+ * Author: Vivek Mahajan vivek.maha...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __FSL_85XX_CACHE_CTLR_H__
+#define __FSL_85XX_CACHE_CTLR_H__
+
+#define L2CR_L2FI 0x4000 /* L2 flash invalidate */
+#define L2CR_L2IO
[PATCH v4 4/5] powerpc/of: add eSPI controller dts bindings and DTS modification
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 ++-
arch/powerpc/boot/dts/mpc8536ds.dts| 52
arch/powerpc/boot/dts/p4080ds.dts | 11 ++---
3 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..777abd7 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -1,7 +1,9 @@
* SPI (Serial Peripheral Interface)
Required properties:
-- cell-index : SPI controller index.
+- cell-index : QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
- compatible : should be fsl,spi.
- mode : the SPI operation mode, it can be cpu or cpu-qe.
- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,mpc8536-espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb..a75c10e 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
};
};
+ s...@7000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x7000 0x1000;
+ interrupts = 59 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+
+ fl...@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000;
+ partit...@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partit...@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partit...@dtb {
+ label = dtb;
+ reg = 0x0060 0x0010;
+ read-only;
+ };
+ partit...@fs {
+ label = file system;
+ reg = 0x0070 0x0090;
+ };
+ };
+ fl...@1 {
+ compatible = spansion,s25sl12801;
+ reg = 1;
+ spi-max-frequency = 4000;
+ };
+ fl...@2 {
+ compatible = spansion,s25sl12801;
+ reg = 2;
+ spi-max-frequency = 4000;
+ };
+ fl...@3 {
+ compatible = spansion,s25sl12801;
+ reg = 3;
+ spi-max-frequency = 4000;
+ };
+ };
+
d...@21300 {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24..5b7fc29 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
};
s...@11 {
-
[PATCH v4 3/5] eSPI: add eSPI controller support
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0x. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Added support to the transaction that the length is grater than 0x.
- Made some changes according to Anton's comments.
drivers/spi/Kconfig|9 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_espi.c | 748
drivers/spi/spi_fsl_lib.h |3 +
4 files changed, 761 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_fsl_espi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 79ad06f..f6888af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -195,6 +195,15 @@ config SPI_FSL_SPI
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
+config SPI_FSL_ESPI
+ tristate Freescale eSPI controller
+ depends on FSL_SOC
+ select SPI_FSL_LIB
+ help
+ This enables using the Freescale eSPI controllers in master mode.
+ From MPC8536, 85xx platform uses the controller, and all P10xx,
+ P20xx, P30xx,P40xx, P50xx uses this controller.
+
config SPI_OMAP_UWIRE
tristate OMAP1 MicroWire
depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7974c21..833d17e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
+obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
new file mode 100644
index 000..e3b4f64
--- /dev/null
+++ b/drivers/spi/spi_fsl_espi.c
@@ -0,0 +1,748 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/module.h
+#include linux/delay.h
+#include linux/irq.h
+#include linux/spi/spi.h
+#include linux/platform_device.h
+#include linux/fsl_devices.h
+#include linux/mm.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include linux/interrupt.h
+#include linux/err.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+/* eSPI Controller registers */
+struct fsl_espi_reg {
+ __be32 mode;/* 0x000 - eSPI mode register */
+ __be32 event; /* 0x004 - eSPI event register */
+ __be32 mask;/* 0x008 - eSPI mask register */
+ __be32 command; /* 0x00c - eSPI command register */
+ __be32 transmit;/* 0x010 - eSPI transmit FIFO access register*/
+ __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
+ u8 res[8]; /* 0x018 - 0x01c
[PATCH v4 2/5] spi/mpc8xxx: refactor the common code for SPI/eSPI controller
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
drivers/spi/Kconfig |5 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_lib.c | 237 +++
drivers/spi/spi_fsl_lib.h | 119 ++
drivers/spi/spi_fsl_spi.c | 552 +
5 files changed, 522 insertions(+), 392 deletions(-)
create mode 100644 drivers/spi/spi_fsl_lib.c
create mode 100644 drivers/spi/spi_fsl_lib.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6af34c6..79ad06f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -182,9 +182,14 @@ config SPI_MPC512x_PSC
This enables using the Freescale MPC5121 Programmable Serial
Controller in SPI master mode.
+config SPI_FSL_LIB
+ tristate
+ depends on FSL_SOC
+
config SPI_FSL_SPI
tristate Freescale SPI controller
depends on FSL_SOC
+ select SPI_FSL_LIB
help
This enables using the Freescale SPI controllers in master mode.
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 770817c..7974c21 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPI_PL022) += amba-pl022.o
obj-$(CONFIG_SPI_MPC512x_PSC) += mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx) += mpc52xx_spi.o
+obj-$(CONFIG_SPI_FSL_LIB) += spi_fsl_lib.o
obj-$(CONFIG_SPI_FSL_SPI) += spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_lib.c b/drivers/spi/spi_fsl_lib.c
new file mode 100644
index 000..5cd741f
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.c
@@ -0,0 +1,237 @@
+/*
+ * Freescale SPI/eSPI controller driver library.
+ *
+ * Maintainer: Kumar Gala
+ *
+ * Copyright (C) 2006 Polycom, Inc.
+ *
+ * CPM SPI and QE buffer descriptors mode support:
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Author: Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/kernel.h
+#include linux/interrupt.h
+#include linux/fsl_devices.h
+#include linux/dma-mapping.h
+#include linux/mm.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+#define MPC8XXX_SPI_RX_BUF(type) \
+void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
+{\
+ type *rx = mpc8xxx_spi-rx; \
+ *rx++ = (type)(data mpc8xxx_spi-rx_shift);\
+ mpc8xxx_spi-rx = rx; \
+}
+
+#define MPC8XXX_SPI_TX_BUF(type) \
+u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
+{ \
+ u32 data; \
+ const type *tx = mpc8xxx_spi-tx; \
+ if (!tx)\
+ return 0; \
+ data = *tx++ mpc8xxx_spi-tx_shift; \
+ mpc8xxx_spi-tx = tx; \
+ return data;\
+}
+
+MPC8XXX_SPI_RX_BUF(u8)
+MPC8XXX_SPI_RX_BUF(u16)
+MPC8XXX_SPI_RX_BUF(u32)
+MPC8XXX_SPI_TX_BUF(u8)
+MPC8XXX_SPI_TX_BUF(u16)
+MPC8XXX_SPI_TX_BUF(u32)
+
+struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data *pdata)
+{
+ return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
+}
+
+void mpc8xxx_spi_work(struct work_struct *work)
+{
+ struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
+ work);
+
+ spin_lock_irq(mpc8xxx_spi-lock);
+ while (!list_empty(mpc8xxx_spi-queue)) {
+ struct spi_message *m = container_of(mpc8xxx_spi-queue.next,
+
[PATCH v4 5/5] mtd: m25p80: add support to parse the partitions by OF node
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Acked-by: Grant Likely grant.lik...@secretlab.ca
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Made changes according to Grant's comments.
drivers/mtd/devices/m25p80.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6f512b5..9d20738 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -924,6 +924,11 @@ static int __devinit m25p_probe(struct spi_device *spi)
nr_parts = data-nr_parts;
}
+ if (nr_parts = 0 spi-dev.of_node) {
+ nr_parts = of_mtd_parse_partitions(spi-dev,
+ spi-dev.of_node, parts);
+ }
+
if (nr_parts 0) {
for (i = 0; i nr_parts; i++) {
DEBUG(MTD_DEBUG_LEVEL2, partitions[%d] =
--
1.6.4
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[PATCH v4 0/5] refactor spi_mpc8xxx.c and add eSPI controller support
This patchset refactor the file spi_mpc8xxx.c to abstract some common code as a lib used by the SPI/eSPI controller driver, move the SPI controller driver code to spi_fsl_spi.c, and add the eSPI controller support with spi_fsl_espi.c. v4 main change: - Update to the latest kernel base(Linux 2.6.36-rc7). - Add support to the transaction that the length is grater than 0x in the eSPI controller's driver. - Some changes according to Grant and Anton's comments. Tested on P4080DS and MPC8536DS board. [PATCH v4 1/5] spi/mpc8xxx: rename spi_mpc8xxx.c to spi_fsl_spi.c [PATCH v4 2/5] spi/mpc8xxx: refactor the common code for SPI/eSPI controller [PATCH v4 3/5] eSPI: add eSPI controller support [PATCH v4 4/5] powerpc/of: add eSPI controller dts bindings and DTS modification [PATCH v4 5/5] mtd: m25p80: add support to parse the partitions by OF node Thanks, Mingkai ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] powerpc/fsl: 85xx: add cache-sram support
On Oct 12, 2010, at 5:25 AM, harninder@freescale.com
harninder@freescale.com wrote:
+static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev,
+ const struct of_device_id *match)
+{
+ long rval;
+ unsigned int rem;
+ unsigned char ways;
+ const unsigned int *prop;
+ unsigned int l2cache_size;
+ struct device_node *np;
+ int i = 0;
+ bool amp = 0;
+ struct sram_parameters sram_params;
+ static char *compatible_list[] = {
+ fsl,MPC85XXRDB-CAMP,
+ fsl,P2020DS-CAMP,
+ NULL
+ };
+
Remove this AMP stuff. We specify the cache-sram-size cache-sram-offset so
for the AMP kernels these can be set as needed.
- k
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Re: [RFC] [PATCH] allow low HZ values?
Thomas Gleixner t...@linutronix.de writes: On Mon, 11 Oct 2010, Tim Pepper wrote: I'm not necessarily wanting to open up the age old question of what is a good HZ, but we were doing some testing on timer tick overheads for HPC applications and this came up... Yeah. This comes always up when the timer tick overhead on HPC is tested. And this patch is again the fundamentally wrong answer. That's a unfair description of the proposal. We have told HPC folks for years that we need a kind of NOHZ mode for HPC where we can transparently switch off the tick when only one user space bound thread is active and switch back to normal once this thing terminates or goes into the kernel via a syscall. Sigh, nothing happened ever except for repeating the same crap patches over and over. Jan Blunck posted a patch for this exactly few months ago. Unfortunately it didn't get the accounting right, but other than that it seemed like a reasonable starting point. -Andi -- a...@linux.intel.com -- Speaking for myself only. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH v2] powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
The new e5500 core is similar to the e500mc core but adds 64-bit
support. We support running it in 32-bit mode as it is identical to the
e500mc.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Updated to remove CONFIG_PPC_E5500 and use E500MC
arch/powerpc/include/asm/reg_booke.h |3 ++-
arch/powerpc/kernel/Makefile |1 +
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 15 +++
arch/powerpc/kernel/cputable.c| 26 +-
arch/powerpc/kernel/traps.c |8 +++-
arch/powerpc/platforms/85xx/Kconfig |4
arch/powerpc/platforms/Kconfig.cputype| 19 ---
7 files changed, 66 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 667a498..5e7ab0c 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -203,7 +203,8 @@
#define PPC47x_MCSR_FPR0x0080 /* FPR parity error */
#define PPC47x_MCSR_IPR0x0040 /* Imprecise Machine Check Exception
*/
-#ifdef CONFIG_E500
+#if defined(CONFIG_E500) || defined(CONFIG_PPC_E500MC) \
+ || defined(CONFIG_PPC_BOOK3E_64)
/* All e500 */
#define MCSR_MCP 0x8000UL /* Machine Check Input Pin */
#define MCSR_ICPERR0x4000UL /* I-Cache Parity Error */
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 1dda701..ac4aadf 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
paca.o nvram_64.o firmware.o
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
obj-$(CONFIG_PPC_BOOK3S_64)+= cpu_setup_ppc970.o cpu_setup_pa6t.o
+obj-$(CONFIG_PPC_BOOK3E_64)+= cpu_setup_fsl_booke.o
obj64-$(CONFIG_RELOCATABLE)+= reloc_64.o
obj-$(CONFIG_PPC_BOOK3E_64)+= exceptions-64e.o idle_book3e.o
obj-$(CONFIG_PPC64)+= vdso64/
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 0adb50a..894e64f 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -51,6 +51,7 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
+#ifdef CONFIG_PPC32
_GLOBAL(__setup_cpu_e200)
/* enable dedicated debug exception handling resources (Debug APU) */
mfspr r3,SPRN_HID0
@@ -72,3 +73,17 @@ _GLOBAL(__setup_cpu_e500mc)
bl __setup_e500mc_ivors
mtlrr4
blr
+#endif
+/* Right now, restore and setup are the same thing */
+_GLOBAL(__restore_cpu_e5500)
+_GLOBAL(__setup_cpu_e5500)
+ mflrr4
+ bl __e500_icache_setup
+ bl __e500_dcache_setup
+#ifdef CONFIG_PPC_BOOK3E_64
+ bl .__setup_base_ivors
+#else
+ bl __setup_e500mc_ivors
+#endif
+ mtlrr4
+ blr
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 1f9123f..f93a061 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -66,6 +66,10 @@ extern void __restore_cpu_ppc970(void);
extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power7(void);
#endif /* CONFIG_PPC64 */
+#if defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_E500)
+extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
+extern void __restore_cpu_e5500(void);
+#endif /* CONFIG_PPC_BOOK3E_64 || CONFIG_E500 */
/* This table only contains desktop CPUs, it need to be filled with embedded
* ones as well...
@@ -1891,6 +1895,27 @@ static struct cpu_spec __initdata cpu_specs[] = {
.platform = ppc5554,
}
#endif /* CONFIG_E200 */
+#endif /* CONFIG_PPC32 */
+#if defined(CONFIG_PPC_BOOK3E_64) || defined(CONFIG_E500)
+ { /* e5500 */
+ .pvr_mask = 0x,
+ .pvr_value = 0x8024,
+ .cpu_name = e5500,
+ .cpu_features = CPU_FTRS_E500MC,
+ .cpu_user_features = COMMON_USER_BOOKE,
+ .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS
|
+ MMU_FTR_USE_TLBILX,
+ .icache_bsize = 64,
+ .dcache_bsize = 64,
+ .num_pmcs = 4,
+ .oprofile_cpu_type = ppc/e500mc,
+ .oprofile_type = PPC_OPROFILE_FSL_EMB,
+ .cpu_setup = __setup_cpu_e5500,
+ .cpu_restore= __restore_cpu_e5500,
+ .machine_check = machine_check_e500mc,
+ .platform = ppce5500,
+ },
+#endif
#ifdef CONFIG_E500
{ /* e500 */
.pvr_mask = 0x,
@@ -1961,7 +1986,6 @@
[PATCH v2] powerpc/fsl-booke: Add p5020 DS board support
The P5020DS is in the same family of boards as the P4080 DS and thus
shares the corenet_ds code.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
* Updated based on removal of CONFIG_PPC_E5500
arch/powerpc/platforms/85xx/Kconfig| 12 ++
arch/powerpc/platforms/85xx/Makefile |1 +
arch/powerpc/platforms/85xx/p5020_ds.c | 69
3 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/85xx/p5020_ds.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig
b/arch/powerpc/platforms/85xx/Kconfig
index ae25527..82d7f33 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -181,6 +181,18 @@ config P4080_DS
endif # PPC32
+config P5020_DS
+ bool Freescale P5020 DS
+ select DEFAULT_UIMAGE
+ select PPC_FSL_BOOK3E
+ select PPC_E500MC
+ select PHYS_64BIT
+ select SWIOTLB
+ select MPC8xxx_GPIO
+ select HAS_RAPIDIO
+ help
+ This option enables support for the P5020 DS board
+
endif # FSL_SOC_BOOKE
config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile
b/arch/powerpc/platforms/85xx/Makefile
index c3ac071..dd70db7 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_P1022_DS)+= p1022_ds.o
obj-$(CONFIG_P3041_DS)+= p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS)+= p4080_ds.o corenet_ds.o
+obj-$(CONFIG_P5020_DS)+= p5020_ds.o corenet_ds.o
obj-$(CONFIG_STX_GP3)+= stx_gp3.o
obj-$(CONFIG_TQM85xx)+= tqm85xx.o
obj-$(CONFIG_SBC8560) += sbc8560.o
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c
b/arch/powerpc/platforms/85xx/p5020_ds.c
new file mode 100644
index 000..7467b71
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -0,0 +1,69 @@
+/*
+ * P5020 DS Setup
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * Copyright 2009-2010 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include linux/kernel.h
+#include linux/pci.h
+#include linux/kdev_t.h
+#include linux/delay.h
+#include linux/interrupt.h
+#include linux/phy.h
+
+#include asm/system.h
+#include asm/time.h
+#include asm/machdep.h
+#include asm/pci-bridge.h
+#include mm/mmu_decl.h
+#include asm/prom.h
+#include asm/udbg.h
+#include asm/mpic.h
+
+#include linux/of_platform.h
+#include sysdev/fsl_soc.h
+#include sysdev/fsl_pci.h
+
+#include corenet_ds.h
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p5020_ds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, fsl,P5020DS);
+}
+
+define_machine(p5020_ds) {
+ .name = P5020 DS,
+ .probe = p5020_ds_probe,
+ .setup_arch = corenet_ds_setup_arch,
+ .init_IRQ = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+ .get_irq= mpic_get_irq,
+#else
+ .get_irq= mpic_get_coreint_irq,
+#endif
+ .restart= fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
+
+machine_device_initcall(p5020_ds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
+#endif
--
1.7.2.3
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Re: [RFC] [PATCH] allow low HZ values?
On Tue, 12 Oct 2010, Andi Kleen wrote: Thomas Gleixner t...@linutronix.de writes: We have told HPC folks for years that we need a kind of NOHZ mode for HPC where we can transparently switch off the tick when only one user space bound thread is active and switch back to normal once this thing terminates or goes into the kernel via a syscall. Sigh, nothing happened ever except for repeating the same crap patches over and over. Jan Blunck posted a patch for this exactly few months ago. Unfortunately it didn't get the accounting right, but other than that it seemed like a reasonable starting point. Unfortunately it did not get a lot of other things right either. Thanks, tglx ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH] powerpc/fsl: 85xx: add cache-sram support
Currently the design is that we divide the sram portion into 2 equal
parts for AMP
That was the part of initial requirement
Do we want to remove that?
Thanks and Regards
Harry++
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, October 12, 2010 7:40 PM
To: Rai Harninder-B01044
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/fsl: 85xx: add cache-sram support
On Oct 12, 2010, at 5:25 AM, harninder@freescale.com
harninder@freescale.com wrote:
+static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device
*dev,
+ const struct of_device_id
*match) {
+ long rval;
+ unsigned int rem;
+ unsigned char ways;
+ const unsigned int *prop;
+ unsigned int l2cache_size;
+ struct device_node *np;
+ int i = 0;
+ bool amp = 0;
+ struct sram_parameters sram_params;
+ static char *compatible_list[] = {
+ fsl,MPC85XXRDB-CAMP,
+ fsl,P2020DS-CAMP,
+ NULL
+ };
+
Remove this AMP stuff. We specify the cache-sram-size cache-sram-
offset so for the AMP kernels these can be set as needed.
- k
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Re: [PATCH] powerpc/fsl: 85xx: add cache-sram support
On Tue, Oct 12, 2010 at 10:02 AM, Rai Harninder-B01044 b01...@freescale.com wrote: Currently the design is that we divide the sram portion into 2 equal parts for AMP That was the part of initial requirement Do we want to remove that? Why wouldn't you just pass different cache-sram-size/offset values to each kernel? -Hollis ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
On Tue, 12 Oct 2010 10:50:52 -0500 Kumar Gala ga...@kernel.crashing.org wrote: The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * Updated to remove CONFIG_PPC_E5500 and use E500MC It still has E500 || E500MC all over the place... If E500MC is not going to imply E500 that should be consistent for both 32 and 64 bit -- though I think it would make more sense that E500MC does imply E500. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/2] v2 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
Josh, Please pull this patch. I just found a bone-headed mistake that makes the whole patch a no-op. I'll need to fix it and put it through a bit of testing before I can re-submit it. The other patch in this series should be okay. Thanks, Shaggy On Mon, 2010-09-27 at 16:56 -0500, Dave Kleikamp wrote: When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 25 + arch/powerpc/mm/tlb_nohash_low.S | 14 +- arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 4 files changed, 68 insertions(+), 1 deletions(-) --- snip --- --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S Not only is this in the wrong place (non-47x initialization) but ... @@ -861,6 +877,15 @@ skpinv: addir4,r4,1 /* Increment */ isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ +BEGIN_MMU_FTR_SECTION + mfspr r3,SPRN_CCR2_476 + /* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ + orisr3,r3,ccr2_476_d...@h + rlwinm r3,r3,0,~CCR2_476_DSTI ^^^ This instruction doesn't belong at all. It clears the bit right after setting it. This one was just introduced removing the config option, but it was in the wrong place all along. + mtspr SPRN_CCR2_476,r3 + isync +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheck); I wasn't diligent enough checking a year-old patch that I got back to work on. The code is very similar in two places and the patch applied to the wrong section. Thanks, Shaggy -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
On Oct 12, 2010, at 12:33 PM, Scott Wood wrote: On Tue, 12 Oct 2010 10:50:52 -0500 Kumar Gala ga...@kernel.crashing.org wrote: The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * Updated to remove CONFIG_PPC_E5500 and use E500MC It still has E500 || E500MC all over the place... If E500MC is not going to imply E500 that should be consistent for both 32 and 64 bit -- though I think it would make more sense that E500MC does imply E500. -Scott I have a problem with Kconfig and getting E500MC option to only exist in the proper cases. - k ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v2] powerpc/fsl-booke: Add support for FSL 64-bit e5500 core
On Tue, 12 Oct 2010 14:55:42 -0500 Kumar Gala ga...@kernel.crashing.org wrote: On Oct 12, 2010, at 12:33 PM, Scott Wood wrote: On Tue, 12 Oct 2010 10:50:52 -0500 Kumar Gala ga...@kernel.crashing.org wrote: The new e5500 core is similar to the e500mc core but adds 64-bit support. We support running it in 32-bit mode as it is identical to the e500mc. Signed-off-by: Kumar Gala ga...@kernel.crashing.org --- * Updated to remove CONFIG_PPC_E5500 and use E500MC It still has E500 || E500MC all over the place... If E500MC is not going to imply E500 that should be consistent for both 32 and 64 bit -- though I think it would make more sense that E500MC does imply E500. -Scott I have a problem with Kconfig and getting E500MC option to only exist in the proper cases. Does having P5020DS (and any future 64-bit-capable board) explicitly select E500 as well as PPC_E500MC avoid the issue? -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Questions on interrupt vector assignment on MPC8641D
There's mpic stuff in the call trace, so the NULL host was OK.
Look in arch/powerpc/platforms/86xx/pic.c. What is the second-to-last
parameter of mpc86xx_init_irq() in your kernel tree? It's 256 in
current upstream -- this is the number of IRQ sources the MPIC driver
will handle.
One, thanks for your help - I do appreciate it.
In the tree I am working from, the call to mpc86xx_init_irq() function is
in a BSP file (ep8641a.c), and the line was
mpic1 = mpic_alloc(np, res.start,
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
16, NR_IRQS-4,
MPIC );
I tried changing that to
mpic1 = mpic_alloc(np, res.start,
MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
16, 256,
MPIC );
With no meaningful changes.
I wonder about the next lines:
mpic_assign_isu(mpic1, 0, res.start + 0x1);
/* 48 Internal Interrupts */
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
mpic_assign_isu(mpic1, 2, res.start + 0x10400);
mpic_assign_isu(mpic1, 3, res.start + 0x10600);
/* 16 External interrupts
* Moving them from [0 - 15] to [64 - 79]
*/
mpic_assign_isu(mpic1, 4, res.start + 0x1);
Looking at the code, and where it appears to be faulting, it looks like
its in kernel/irq/chip.c:
int set_irq_type(unsigned int irq, unsigned int type)
{
struct irq_desc *desc;
unsigned long flags;
int ret = -ENXIO;
if (irq = NR_IRQS) {
printk(KERN_ERR Trying to set irq type for IRQ%d\n, irq);
return -ENODEV;
}
desc = irq_desc + irq;
if (desc-chip-set_type) {
spin_lock_irqsave(desc-lock, flags);
ret = desc-chip-set_type(irq, type);
spin_unlock_irqrestore(desc-lock, flags);
}
return ret;
}
My conjecture is that desc-chip isn't set. Is mpic_assign_isu the
function that does that?
(yes, I know - update your kernel. I am 2 weeks from a delivery, I have to
merge driver changes to sRIO in along with all of this)
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Re: Questions on interrupt vector assignment on MPC8641D
On Tue, 12 Oct 2010 15:55:28 -0500
david.hag...@gmail.com wrote:
I wonder about the next lines:
mpic_assign_isu(mpic1, 0, res.start + 0x1);
/* 48 Internal Interrupts */
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
mpic_assign_isu(mpic1, 2, res.start + 0x10400);
mpic_assign_isu(mpic1, 3, res.start + 0x10600);
/* 16 External interrupts
* Moving them from [0 - 15] to [64 - 79]
*/
mpic_assign_isu(mpic1, 4, res.start + 0x1);
No mainline 86xx boards do that, even in 2.6.26. I suspect you need to
either get rid of the isu stuff altogether, or add a mapping for the
MSI interrupts.
Looking at the code, and where it appears to be faulting, it looks like
its in kernel/irq/chip.c:
int set_irq_type(unsigned int irq, unsigned int type)
{
struct irq_desc *desc;
unsigned long flags;
int ret = -ENXIO;
if (irq = NR_IRQS) {
printk(KERN_ERR Trying to set irq type for IRQ%d\n, irq);
return -ENODEV;
}
desc = irq_desc + irq;
if (desc-chip-set_type) {
spin_lock_irqsave(desc-lock, flags);
ret = desc-chip-set_type(irq, type);
spin_unlock_irqrestore(desc-lock, flags);
}
return ret;
}
My conjecture is that desc-chip isn't set. Is mpic_assign_isu the
function that does that?
That happens in set_irq_chip_and_handler(), called from mpic_host_map()
-- just a few lines before calling set_irq_type().
The crash is happening somewhere in mpic_set_irq_type():
NIP [c0016540] mpic_set_irq_type+0x188/0x1c4
-Scott
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Re: [PATCH 1/2] v2 476: Set CCR2[DSTI] to prevent isync from flushing shadow TLB
On Tue, Oct 12, 2010 at 02:40:13PM -0500, Dave Kleikamp wrote: Josh, Please pull this patch. I just found a bone-headed mistake that makes the whole patch a no-op. I'll need to fix it and put it through a bit of testing before I can re-submit it. OK. I should have looked more closely myself. I did think it odd that it was changing head_44x.S but didn't follow up. Ben, since you haven't pulled my -next branch yet, don't ;). I'll fix this up in my tree and resend a request tomorrow. josh The other patch in this series should be okay. Thanks, Shaggy On Mon, 2010-09-27 at 16:56 -0500, Dave Kleikamp wrote: When the DSTI (Disable Shadow TLB Invalidate) bit is set in the CCR2 register, the isync command does not flush the shadow TLB (iTLB dTLB). However, since the shadow TLB does not contain context information, we want the shadow TLB flushed in situations where we are switching context. In those situations, we explicitly clear the DSTI bit before performing isync, and set it again afterward. We also need to do the same when we perform isync after explicitly flushing the TLB. Signed-off-by: Dave Kleikamp sha...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg_booke.h |4 arch/powerpc/kernel/head_44x.S| 25 + arch/powerpc/mm/tlb_nohash_low.S | 14 +- arch/powerpc/platforms/44x/misc_44x.S | 26 ++ 4 files changed, 68 insertions(+), 1 deletions(-) --- snip --- --- a/arch/powerpc/kernel/head_44x.S +++ b/arch/powerpc/kernel/head_44x.S Not only is this in the wrong place (non-47x initialization) but ... @@ -861,6 +877,15 @@ skpinv: addir4,r4,1 /* Increment */ isync #endif /* CONFIG_PPC_EARLY_DEBUG_44x */ +BEGIN_MMU_FTR_SECTION +mfspr r3,SPRN_CCR2_476 +/* With CCR2(DSTI) set, isync does not invalidate the shadow TLB */ +orisr3,r3,ccr2_476_d...@h +rlwinm r3,r3,0,~CCR2_476_DSTI ^^^ This instruction doesn't belong at all. It clears the bit right after setting it. This one was just introduced removing the config option, but it was in the wrong place all along. +mtspr SPRN_CCR2_476,r3 +isync +END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) + /* Establish the interrupt vector offsets */ SET_IVOR(0, CriticalInput); SET_IVOR(1, MachineCheck); I wasn't diligent enough checking a year-old patch that I got back to work on. The code is very similar in two places and the patch applied to the wrong section. Thanks, Shaggy -- Dave Kleikamp IBM Linux Technology Center ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH] add icswx support v2
In message 1286855108.14049.8.ca...@flin.austin.ibm.com you wrote:
icswx is a PowerPC co-processor instruction to send data to a
co-processor. On Book-S processors the LPAR_ID and process ID (PID) of
the owning process are registered in the window context of the
co-processor at initial time. When the icswx instruction is executed,
the L2 generates a cop-reg transaction on PowerBus. The transaction has
no address and the processor does not perform an MMU access to
authenticate the transaction. The coprocessor compares the LPAR_ID and
the PID included in the transaction and the LPAR_ID and PID held in the
window context to determine if the process is authorized to generate the
transaction.
This patch adds icswx co-processor instruction support.
Can you describe the ABI a bit?
How has this changed from version 1?
Patch has been whitespace munged aswell.
More comments below...
Signed-off-by: Sonny Rao sonny...@linux.vnet.ibm.com
Signed-off-by: Tseng-Hui (Frank) Lin th...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/mmu-hash64.h |5 ++
arch/powerpc/include/asm/mmu_context.h |6 ++
arch/powerpc/include/asm/reg.h | 12
arch/powerpc/include/asm/reg_booke.h |3 -
arch/powerpc/mm/mmu_context_hash64.c | 105
arch/powerpc/platforms/Kconfig.cputype | 16 +
6 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h
b/arch/powerpc/include/asm/mmu-hash64.h
index acac35d..6c1ab90 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -423,6 +423,11 @@ typedef struct {
#ifdef CONFIG_PPC_SUBPAGE_PROT
struct subpage_prot_table spt;
#endif /* CONFIG_PPC_SUBPAGE_PROT */
+#ifdef CONFIG_ICSWX
+ unsigned long acop; /* mask of enabled coprocessor types */
+#define HASH64_MAX_PID (0x)
+ unsigned int acop_pid; /* pid value used with coprocessors */
+#endif /* CONFIG_ICSWX */
} mm_context_t;
diff --git a/arch/powerpc/include/asm/mmu_context.h
b/arch/powerpc/include/asm/mmu_context.h
index 81fb412..88118de 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -80,6 +80,12 @@ static inline void switch_mm(struct mm_struct *prev,
struct mm_struct *next,
#define deactivate_mm(tsk,mm)do { } while (0)
+#ifdef CONFIG_ICSWX
+extern void switch_cop(struct mm_struct *next);
+extern int use_cop(unsigned long acop, struct mm_struct *mm);
+extern void drop_cop(unsigned long acop, struct mm_struct *mm);
+#endif /* CONFIG_ICSWX */
+
/*
* After we have set current-mm to a new value, this activates
* the context for the new mm so we see the new mappings.
diff --git a/arch/powerpc/include/asm/reg.h
b/arch/powerpc/include/asm/reg.h
index ff0005eec..9bbf178 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -170,8 +170,19 @@
#define SPEFSCR_FRMC 0x0003 /* Embedded FP rounding mode co
ntrol
*/
/* Special Purpose Registers (SPRNs)*/
+
+#ifdef CONFIG_40x
+#define SPRN_PID 0x3B1 /* Process ID */
+#else
+#define SPRN_PID0x030 /* Process ID */
+#ifdef CONFIG_BOOKE
+#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
+#endif
+#endif
+
Why are you moving these definitions?
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DSCR0x11
+#define SPRN_ACOP0x1F/* Available Coprocessor Register */
#define SPRN_CTRLF 0x088
#define SPRN_CTRLT 0x098
#define CTRL_CT0xc000 /* current thread */
@@ -879,6 +890,7 @@
#define PV_POWER50x003A
#define PV_POWER5p 0x003B
#define PV_970FX 0x003C
+#define PV_POWER70x003F
#define PV_630 0x0040
#define PV_630p 0x0041
#define PV_970MP 0x0044
diff --git a/arch/powerpc/include/asm/reg_booke.h
b/arch/powerpc/include/asm/reg_booke.h
index 667a498..5b0c781 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -150,8 +150,6 @@
* or IBM 40x.
*/
#ifdef CONFIG_BOOKE
-#define SPRN_PID 0x030 /* Process ID */
-#define SPRN_PID0SPRN_PID/* Process ID Register 0 */
#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
#define SPRN_DEAR0x03D /* Data Error Address Register */
@@ -168,7 +166,6 @@
#define SPRN_TCR 0x154 /* Timer Control Register */
#endif /* Book E */
#ifdef CONFIG_40x
-#define SPRN_PID 0x3B1 /* Process ID */
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
#define SPRN_DEAR0x3D5 /* Data Error Address Register */
diff --git a/arch/powerpc/mm/mmu_context_hash64.c
b/arch/powerpc/mm/mmu_context_hash64.c
index 2535828..8f432b6
Re: Questions on interrupt vector assignment on MPC8641D
On Mon, 2010-10-11 at 09:44 -0500, david.hag...@gmail.com wrote: You should define MSI device nodes on your target dts. And you can refer to the file, mpc8572ds.dts. I see nothing in that file that defines any MSIs. I see code that looks like it maps ROOT COMPLEX MODE interrupts on regular PCI interfaces, which IS NOT WHAT I AM DOING. Since it seems I have been unclear, let me state this as clearly as possible. I AM DOING ENDPOINT MODE. Shouting is not going to make you any friends. cheers signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: Questions on interrupt vector assignment on MPC8641D
Scott Wood wrote:
On Tue, 12 Oct 2010 15:55:28 -0500
david.hag...@gmail.com wrote:
I wonder about the next lines:
mpic_assign_isu(mpic1, 0, res.start + 0x1);
/* 48 Internal Interrupts */
mpic_assign_isu(mpic1, 1, res.start + 0x10200);
mpic_assign_isu(mpic1, 2, res.start + 0x10400);
mpic_assign_isu(mpic1, 3, res.start + 0x10600);
/* 16 External interrupts
* Moving them from [0 - 15] to [64 - 79]
*/
mpic_assign_isu(mpic1, 4, res.start + 0x1);
No mainline 86xx boards do that, even in 2.6.26. I suspect you need to
either get rid of the isu stuff altogether, or add a mapping for the
MSI interrupts.
Looking at the code, and where it appears to be faulting, it looks like
its in kernel/irq/chip.c:
int set_irq_type(unsigned int irq, unsigned int type)
{
struct irq_desc *desc;
unsigned long flags;
int ret = -ENXIO;
if (irq = NR_IRQS) {
printk(KERN_ERR Trying to set irq type for IRQ%d\n, irq);
return -ENODEV;
}
desc = irq_desc + irq;
if (desc-chip-set_type) {
spin_lock_irqsave(desc-lock, flags);
ret = desc-chip-set_type(irq, type);
spin_unlock_irqrestore(desc-lock, flags);
}
return ret;
}
My conjecture is that desc-chip isn't set. Is mpic_assign_isu the
function that does that?
That happens in set_irq_chip_and_handler(), called from mpic_host_map()
-- just a few lines before calling set_irq_type().
The crash is happening somewhere in mpic_set_irq_type():
Agreed. That is just where I pointed out on my email replied for OOPS. To enable
DBG to figure out 'src' and 'mpic-irq_count' from the file,
arch/powerpc/sysdev/mpic.c,.
==
int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
{
..
if (src = mpic-irq_count)
return -EINVAL;
^
I think this OOPS may be from here.
Tiejun
NIP [c0016540] mpic_set_irq_type+0x188/0x1c4
-Scott
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Re: MSI-X vector allocation failure in upstream kernel
On Tue, 2010-10-05 at 10:18 -0700, Anirban Chakraborty wrote: Hi All, I am trying to test qlcnic driver (for 10Gb QLogic network adapter) on a Power 6 system (IBM P 520, System type 8203) with upstream kernel and I do see that the kernel is not able to allocate any MSI-X vectors. The driver requests for 4 vectors in pci_enable_msix, which returns 2. OK, that's the platform code saying it can only support 2, that seems low, but it's possible. The driver again attempts, this time for 2 vectors but the kernel can't allocate and it returns a value of 0xfffd. OK, that's odd. That is -3, which AFAICS we don't return from the linux code. So it must be coming from firmware? In which case it would be parameter error. I upgraded the system FW to 01EL350 (from 01EL340) just to make sure if MSI-X is enabled in the system. Is that the latest FW version? Adding #define DEBUG at the top of arch/powerpc/platforms/pseries/msi.c will give us lots of useful info. Or you can enable CONFIG_DYNAMIC_DEBUG, and enable it that way. cheers signature.asc Description: This is a digitally signed message part ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: ppc405 + MCP23S17
WANG YiFei wrote: Hi, I'm a newbie for linux device driver development. We have a custom ppc405 board which has MCP23S17 (16-Bit I/O Expander with SPI Interface) on it. I noticed that current kernel has MCP23S08 driver support, I'd like to know: 1. if passing platform data to MCP23S08 driver, can it make MCP23S17 work? These chips should be same vendor product so I think 16-bit mcp23s17 may be compatible to 8-bit modes. But you have to check the data sheet to confirm this and track how to configure that as 8-bit mode. After that it's possible to run mcp23s17 with mcp23s08.c. 2. Generally, I'd like to know how to pass platform data to a particular device driver. In my mind, platform data should not be in driver code, right? However, I don't know where is Firstly you should define this on your dts. Then parse that to register corresponding of_platform_device or platform_device when you setup your target on your target.c. When spi_register_driver prober successfully, you can get the platform_data from associated spi device. the suitable place to pass platform data to driver. 3. How to describe this in dts file? You can get more from the file, Documentation/powerpc/dts-bindings/spi-bus.txt. Or refer to those existed spi nodes on other platform dts. Tiejun Thanks in advance, YiFei ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: RTC rtc-cmos.c : Fix warning on PowerPC
I noticed a compilation warning of RTC for powerpc. Found the fix existing for MIPS not for available for PowerPC. Can you please add the waring text here. [1. text/x-patch; 0001-RTC-rtc-cmos.c-Fix-warning-on-PowerPC.patch]... Please inline the patch rather than using an attachment. Mikey ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH v4 2/5] spi/mpc8xxx: refactor the common code for SPI/eSPI controller
On Tue, Oct 12, 2010 at 06:18:31PM +0800, Mingkai Hu wrote:
Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.
Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Applied, thanks.
g.
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
drivers/spi/Kconfig |5 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_lib.c | 237 +++
drivers/spi/spi_fsl_lib.h | 119 ++
drivers/spi/spi_fsl_spi.c | 552
+
5 files changed, 522 insertions(+), 392 deletions(-)
create mode 100644 drivers/spi/spi_fsl_lib.c
create mode 100644 drivers/spi/spi_fsl_lib.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 6af34c6..79ad06f 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -182,9 +182,14 @@ config SPI_MPC512x_PSC
This enables using the Freescale MPC5121 Programmable Serial
Controller in SPI master mode.
+config SPI_FSL_LIB
+ tristate
+ depends on FSL_SOC
+
config SPI_FSL_SPI
tristate Freescale SPI controller
depends on FSL_SOC
+ select SPI_FSL_LIB
help
This enables using the Freescale SPI controllers in master mode.
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 770817c..7974c21 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_SPI_PL022) += amba-pl022.o
obj-$(CONFIG_SPI_MPC512x_PSC)+= mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC)+= mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx)+= mpc52xx_spi.o
+obj-$(CONFIG_SPI_FSL_LIB)+= spi_fsl_lib.o
obj-$(CONFIG_SPI_FSL_SPI)+= spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_lib.c b/drivers/spi/spi_fsl_lib.c
new file mode 100644
index 000..5cd741f
--- /dev/null
+++ b/drivers/spi/spi_fsl_lib.c
@@ -0,0 +1,237 @@
+/*
+ * Freescale SPI/eSPI controller driver library.
+ *
+ * Maintainer: Kumar Gala
+ *
+ * Copyright (C) 2006 Polycom, Inc.
+ *
+ * CPM SPI and QE buffer descriptors mode support:
+ * Copyright (c) 2009 MontaVista Software, Inc.
+ * Author: Anton Vorontsov avoront...@ru.mvista.com
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/kernel.h
+#include linux/interrupt.h
+#include linux/fsl_devices.h
+#include linux/dma-mapping.h
+#include linux/mm.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+#define MPC8XXX_SPI_RX_BUF(type) \
+void mpc8xxx_spi_rx_buf_##type(u32 data, struct mpc8xxx_spi *mpc8xxx_spi) \
+{ \
+ type *rx = mpc8xxx_spi-rx; \
+ *rx++ = (type)(data mpc8xxx_spi-rx_shift);\
+ mpc8xxx_spi-rx = rx; \
+}
+
+#define MPC8XXX_SPI_TX_BUF(type) \
+u32 mpc8xxx_spi_tx_buf_##type(struct mpc8xxx_spi *mpc8xxx_spi) \
+{\
+ u32 data; \
+ const type *tx = mpc8xxx_spi-tx; \
+ if (!tx)\
+ return 0; \
+ data = *tx++ mpc8xxx_spi-tx_shift; \
+ mpc8xxx_spi-tx = tx; \
+ return data;\
+}
+
+MPC8XXX_SPI_RX_BUF(u8)
+MPC8XXX_SPI_RX_BUF(u16)
+MPC8XXX_SPI_RX_BUF(u32)
+MPC8XXX_SPI_TX_BUF(u8)
+MPC8XXX_SPI_TX_BUF(u16)
+MPC8XXX_SPI_TX_BUF(u32)
+
+struct mpc8xxx_spi_probe_info *to_of_pinfo(struct fsl_spi_platform_data
*pdata)
+{
+ return container_of(pdata, struct mpc8xxx_spi_probe_info, pdata);
+}
+
+void mpc8xxx_spi_work(struct work_struct *work)
+{
+ struct mpc8xxx_spi *mpc8xxx_spi = container_of(work, struct mpc8xxx_spi,
+work);
+
+
Re: [PATCH v4 3/5] eSPI: add eSPI controller support
On Tue, Oct 12, 2010 at 06:18:32PM +0800, Mingkai Hu wrote:
Add eSPI controller support based on the library code spi_fsl_lib.c.
The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:
1. Has different register map and different bit definition
So leave the code operated the register to the driver code, not
the common code.
2. Support 4 dedicated chip selects
The software can't controll the chip selects directly, The SPCOM[CS]
field is used to select which chip selects is used, and the
SPCOM[TRANLEN] field is set to tell the controller how long the CS
signal need to be asserted. So the driver doesn't need the chipselect
related function when transfering data, just set corresponding register
fields to controll the chipseclect.
3. Different Transmit/Receive FIFO access register behavior
For SPI controller, the Tx/Rx FIFO access register can hold only
one character regardless of the character length, but for eSPI
controller, the register can hold 4 or 2 characters according to
the character lengths. Access the Tx/Rx FIFO access register of the
eSPI controller will shift out/in 4/2 characters one time. For SPI
subsystem, the command and data are put into different transfers, so
we need to combine all the transfers to one transfer in order to pass
the transfer to eSPI controller.
4. The max transaction length limitation
The max transaction length one time is limitted by the SPCOM[TRANSLEN]
field which is 0x. When used mkfs.ext2 command to create ext2
filesystem on the flash, the read length will exceed the max value of
the SPCOM[TRANSLEN] field.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Applied, thanks.
g.
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Added support to the transaction that the length is grater than 0x.
- Made some changes according to Anton's comments.
drivers/spi/Kconfig|9 +
drivers/spi/Makefile |1 +
drivers/spi/spi_fsl_espi.c | 748
drivers/spi/spi_fsl_lib.h |3 +
4 files changed, 761 insertions(+), 0 deletions(-)
create mode 100644 drivers/spi/spi_fsl_espi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 79ad06f..f6888af 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -195,6 +195,15 @@ config SPI_FSL_SPI
MPC83xx platform uses the controller in cpu mode or CPM/QE mode.
MPC8569 uses the controller in QE mode, MPC8610 in cpu mode.
+config SPI_FSL_ESPI
+ tristate Freescale eSPI controller
+ depends on FSL_SOC
+ select SPI_FSL_LIB
+ help
+ This enables using the Freescale eSPI controllers in master mode.
+ From MPC8536, 85xx platform uses the controller, and all P10xx,
+ P20xx, P30xx,P40xx, P50xx uses this controller.
+
config SPI_OMAP_UWIRE
tristate OMAP1 MicroWire
depends on ARCH_OMAP1
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7974c21..833d17e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) +=
mpc512x_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx_PSC)+= mpc52xx_psc_spi.o
obj-$(CONFIG_SPI_MPC52xx)+= mpc52xx_spi.o
obj-$(CONFIG_SPI_FSL_LIB)+= spi_fsl_lib.o
+obj-$(CONFIG_SPI_FSL_ESPI) += spi_fsl_espi.o
obj-$(CONFIG_SPI_FSL_SPI)+= spi_fsl_spi.o
obj-$(CONFIG_SPI_PPC4xx) += spi_ppc4xx.o
obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c
new file mode 100644
index 000..e3b4f64
--- /dev/null
+++ b/drivers/spi/spi_fsl_espi.c
@@ -0,0 +1,748 @@
+/*
+ * Freescale eSPI controller driver.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include linux/module.h
+#include linux/delay.h
+#include linux/irq.h
+#include linux/spi/spi.h
+#include linux/platform_device.h
+#include linux/fsl_devices.h
+#include linux/mm.h
+#include linux/of.h
+#include linux/of_platform.h
+#include linux/of_spi.h
+#include linux/interrupt.h
+#include linux/err.h
+#include sysdev/fsl_soc.h
+
+#include spi_fsl_lib.h
+
+/* eSPI Controller registers */
+struct fsl_espi_reg {
+ __be32 mode;/* 0x000 - eSPI mode register */
+ __be32 event; /* 0x004 - eSPI event register */
+ __be32 mask;/* 0x008 - eSPI mask register */
+ __be32 command; /* 0x00c - eSPI command register */
+ __be32 transmit;/*
Re: [PATCH v4 4/5] powerpc/of: add eSPI controller dts bindings and DTS modification
On Tue, Oct 12, 2010 at 06:18:33PM +0800, Mingkai Hu wrote:
Also modifiy the document of cell-index in SPI controller. Add the
SPI flash(s25fl128p01) support on p4080ds and mpc8536ds board.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Applied, thanks.
g.
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
Documentation/powerpc/dts-bindings/fsl/spi.txt | 24 ++-
arch/powerpc/boot/dts/mpc8536ds.dts| 52
arch/powerpc/boot/dts/p4080ds.dts | 11 ++---
3 files changed, 79 insertions(+), 8 deletions(-)
diff --git a/Documentation/powerpc/dts-bindings/fsl/spi.txt
b/Documentation/powerpc/dts-bindings/fsl/spi.txt
index 80510c0..777abd7 100644
--- a/Documentation/powerpc/dts-bindings/fsl/spi.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/spi.txt
@@ -1,7 +1,9 @@
* SPI (Serial Peripheral Interface)
Required properties:
-- cell-index : SPI controller index.
+- cell-index : QE SPI subblock index.
+ 0: QE subblock SPI1
+ 1: QE subblock SPI2
- compatible : should be fsl,spi.
- mode : the SPI operation mode, it can be cpu or cpu-qe.
- reg : Offset and length of the register set for the device
@@ -29,3 +31,23 @@ Example:
gpios = gpio 18 1 // device reg=0
gpio 19 1; // device reg=1
};
+
+
+* eSPI (Enhanced Serial Peripheral Interface)
+
+Required properties:
+- compatible : should be fsl,mpc8536-espi.
+- reg : Offset and length of the register set for the device.
+- interrupts : should contain eSPI interrupt, the device has one interrupt.
+- fsl,espi-num-chipselects : the number of the chipselect signals.
+
+Example:
+ s...@11 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x11 0x1000;
+ interrupts = 53 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+ };
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts
b/arch/powerpc/boot/dts/mpc8536ds.dts
index 815cebb..a75c10e 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -108,6 +108,58 @@
};
};
+ s...@7000 {
+ #address-cells = 1;
+ #size-cells = 0;
+ compatible = fsl,mpc8536-espi;
+ reg = 0x7000 0x1000;
+ interrupts = 59 0x2;
+ interrupt-parent = mpic;
+ fsl,espi-num-chipselects = 4;
+
+ fl...@0 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = spansion,s25sl12801;
+ reg = 0;
+ spi-max-frequency = 4000;
+ partit...@u-boot {
+ label = u-boot;
+ reg = 0x 0x0010;
+ read-only;
+ };
+ partit...@kernel {
+ label = kernel;
+ reg = 0x0010 0x0050;
+ read-only;
+ };
+ partit...@dtb {
+ label = dtb;
+ reg = 0x0060 0x0010;
+ read-only;
+ };
+ partit...@fs {
+ label = file system;
+ reg = 0x0070 0x0090;
+ };
+ };
+ fl...@1 {
+ compatible = spansion,s25sl12801;
+ reg = 1;
+ spi-max-frequency = 4000;
+ };
+ fl...@2 {
+ compatible = spansion,s25sl12801;
+ reg = 2;
+ spi-max-frequency = 4000;
+ };
+ fl...@3 {
+ compatible = spansion,s25sl12801;
+ reg = 3;
+ spi-max-frequency = 4000;
+ };
+ };
+
d...@21300 {
#address-cells = 1;
#size-cells = 1;
diff --git a/arch/powerpc/boot/dts/p4080ds.dts
b/arch/powerpc/boot/dts/p4080ds.dts
index 2f0de24..5b7fc29 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -236,22 +236,19 @@
Re: [PATCH v4 5/5] mtd: m25p80: add support to parse the partitions by OF node
On Tue, Oct 12, 2010 at 06:18:34PM +0800, Mingkai Hu wrote:
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Acked-by: Grant Likely grant.lik...@secretlab.ca
dwmw2: what are your thoughts on this one?
g.
---
v4:
- Updated to latest kernel base(Linux 2.6.36-rc7).
- Made changes according to Grant's comments.
drivers/mtd/devices/m25p80.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 6f512b5..9d20738 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -924,6 +924,11 @@ static int __devinit m25p_probe(struct spi_device *spi)
nr_parts = data-nr_parts;
}
+ if (nr_parts = 0 spi-dev.of_node) {
+ nr_parts = of_mtd_parse_partitions(spi-dev,
+ spi-dev.of_node, parts);
+ }
+
if (nr_parts 0) {
for (i = 0; i nr_parts; i++) {
DEBUG(MTD_DEBUG_LEVEL2, partitions[%d] =
--
1.6.4
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Re: [PATCH 09/15] ppc/vio: use dma ops helpers
On Wed, 2010-09-15 at 12:33 -0600, Grant Likely wrote:
On Wed, Sep 15, 2010 at 12:05 PM, Nishanth Aravamudan n...@us.ibm.com wrote:
Use the set_dma_ops helper. Instead of modifying vio_dma_mapping_ops,
just create a trivial wrapper for dma_supported.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Nishanth Aravamudan n...@us.ibm.com
Looks right to me.
I never saw 8/15 btw ... I'm applying up to 7, please resend the rest.
Cheers,
Ben.
---
arch/powerpc/kernel/vio.c | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index d692989..3c3083f 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -602,6 +602,11 @@ static void vio_dma_iommu_unmap_sg(struct device *dev,
vio_cmo_dealloc(viodev, alloc_size);
}
+static int vio_dma_iommu_dma_supported(struct device *dev, u64 mask)
+{
+return dma_iommu_ops.dma_supported(dev, mask);
+}
+
struct dma_map_ops vio_dma_mapping_ops = {
.alloc_coherent = vio_dma_iommu_alloc_coherent,
.free_coherent = vio_dma_iommu_free_coherent,
@@ -609,6 +614,7 @@ struct dma_map_ops vio_dma_mapping_ops = {
.unmap_sg = vio_dma_iommu_unmap_sg,
.map_page = vio_dma_iommu_map_page,
.unmap_page = vio_dma_iommu_unmap_page,
+ .dma_supported = vio_dma_iommu_dma_supported,
};
@@ -860,8 +866,7 @@ static void vio_cmo_bus_remove(struct vio_dev *viodev)
static void vio_cmo_set_dma_ops(struct vio_dev *viodev)
{
- vio_dma_mapping_ops.dma_supported = dma_iommu_ops.dma_supported;
- viodev-dev.archdata.dma_ops = vio_dma_mapping_ops;
+ set_dma_ops(viodev-dev, vio_dma_mapping_ops);
}
/**
@@ -1246,7 +1251,7 @@ struct vio_dev *vio_register_device_node(struct
device_node *of_node)
if (firmware_has_feature(FW_FEATURE_CMO))
vio_cmo_set_dma_ops(viodev);
else
- viodev-dev.archdata.dma_ops = dma_iommu_ops;
+ set_dma_ops(viodev-dev, dma_iommu_ops);
set_iommu_table_base(viodev-dev, vio_build_iommu_table(viodev));
set_dev_node(viodev-dev, of_node_to_nid(of_node));
--
1.7.0.4
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Re: [git pull] Please pull powerpc.git merge branch
On Fri, 2010-10-08 at 11:04 -0500, Kumar Gala wrote: Ben, This isn't critical, but it does fix having the ppc64e_defconfig build cleanly. Doesn't matter, I'm putting it in -next. When is your -next branch btw ? It's overdue by 3 or 4 rc's already :-) Cheers, Ben. - k The following changes since commit 6b0cd00bc396daf5c2dcf17a8d82055335341f46: Merge branch 'hwpoison-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux-mce-2.6 (2010-10-07 13:59:32 -0700) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git merge Kumar Gala (1): powerpc/ppc64e: Fix link problem when building ppc64e_defconfig arch/powerpc/platforms/85xx/smp.c |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
